task_id
stringlengths 16
24
| shuttle_name
stringclasses 7
values | project_name
stringlengths 12
79
| task_name
stringlengths 7
59
| top_module_name
stringlengths 9
54
| system_message
stringclasses 1
value | prompt
stringlengths 724
368k
| golden_module
stringlengths 66
320k
|
|---|---|---|---|---|---|---|---|
tt06-finale_0001
|
tt06-finale
|
CEJMU-tt06_tinyrv1
|
task_alu
|
tt_um_cejmu_riscv
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/* Generated by Yosys 0.39+165 (git sha1 22c5ab90d, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */
module alu(clk, reset, a, b, instruction, rd);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module control(clk, reset, iword, data_valid, imm, control_flags_out, wbflag, memflag, pcflag, fetchflag, mem_req);
wire _000_;
wire _001_;
wire _002_;
wire [2:0] _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire [2:0] _012_;
wire _013_;
wire [2:0] _014_;
wire [2:0] _015_;
wire [2:0] _016_;
wire [2:0] _017_;
wire [2:0] _018_;
wire [2:0] _019_;
wire [2:0] _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire [31:0] _066_;
wire _067_;
wire [31:0] _068_;
wire _069_;
wire [31:0] _070_;
wire _071_;
wire [31:0] _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
reg [2:0] _109_;
input clk;
wire clk;
wire [6:0] control_flags;
output [6:0] control_flags_out;
wire [6:0] control_flags_out;
wire [2:0] currstate;
input data_valid;
wire data_valid;
output fetchflag;
wire fetchflag;
output [31:0] imm;
wire [31:0] imm;
input [31:0] iword;
wire [31:0] iword;
output mem_req;
wire mem_req;
output memflag;
wire memflag;
output pcflag;
wire pcflag;
input reset;
wire reset;
wire [20:0] w31_to_w11;
output wbflag;
wire wbflag;
assign _000_ = currstate == 3'h0;
assign _001_ = currstate == 3'h5;
assign _002_ = currstate == 3'h1;
assign _003_ = data_valid ? 3'h6 : currstate;
assign _004_ = currstate == 3'h6;
assign _005_ = currstate == 3'h2;
assign _006_ = currstate == 3'h3;
assign _007_ = control_flags[0] & _006_;
assign _008_ = currstate == 3'h3;
assign _009_ = ~ control_flags[0];
assign _010_ = _009_ & _008_;
assign _011_ = currstate == 3'h4;
assign _012_ = _013_ ? 3'h5 : currstate;
assign _013_ = data_valid & _011_;
assign _014_ = _010_ ? 3'h5 : _012_;
assign _015_ = _007_ ? 3'h4 : _014_;
assign _016_ = _005_ ? 3'h3 : _015_;
assign _017_ = _004_ ? 3'h2 : _016_;
assign _018_ = _002_ ? _003_ : _017_;
assign _019_ = _001_ ? 3'h1 : _018_;
assign _020_ = _000_ ? 3'h1 : _019_;
assign _021_ = currstate == 3'h1;
assign _022_ = currstate == 3'h4;
assign _023_ = _021_ | _022_;
assign _024_ = ~ data_valid;
assign _025_ = _024_ & _023_;
assign _026_ = _025_ ? 1'h0 : 1'h1;
assign _027_ = currstate == 3'h3;
assign _028_ = ~ control_flags[0];
assign _029_ = _028_ & _027_;
assign _030_ = currstate == 3'h4;
assign _031_ = data_valid & _030_;
assign _032_ = _029_ | _031_;
assign _033_ = _032_ ? 1'h1 : 1'h0;
assign _034_ = currstate == 3'h3;
assign _035_ = control_flags[0] & _034_;
assign _036_ = control_flags[1] & _035_;
assign _037_ = currstate == 3'h4;
assign _038_ = control_flags[1] & _037_;
assign _039_ = _036_ | _038_;
assign _040_ = _039_ ? 1'h1 : 1'h0;
assign _041_ = currstate == 3'h4;
assign _042_ = control_flags[2] & _041_;
assign _043_ = data_valid & _042_;
assign _044_ = currstate == 3'h3;
assign _045_ = control_flags[2] & _044_;
assign _046_ = ~ control_flags[0];
assign _047_ = _046_ & _045_;
assign _048_ = _043_ | _047_;
assign _049_ = _048_ ? 1'h1 : 1'h0;
assign _050_ = currstate == 3'h1;
assign _051_ = data_valid & _050_;
assign _052_ = _051_ ? 1'h1 : 1'h0;
assign _053_ = currstate == 3'h1;
assign _054_ = currstate == 3'h0;
assign _055_ = _053_ | _054_;
assign _056_ = currstate == 3'h5;
assign _057_ = _055_ | _056_;
assign _058_ = _057_ ? 1'h1 : 1'h0;
assign _059_ = iword[6:0] == 7'h67;
assign _060_ = _059_ ? 1'h1 : 1'h0;
assign _061_ = iword[6:0] == 7'h03;
assign _062_ = iword[6:0] == 7'h13;
assign _063_ = _061_ | _062_;
assign _064_ = iword[6:0] == 7'h67;
assign _065_ = _063_ | _064_;
assign _066_ = _065_ ? { w31_to_w11, iword[30:20] } : _068_;
assign _067_ = iword[6:0] == 7'h23;
assign _068_ = _067_ ? { w31_to_w11, iword[30:25], iword[11:7] } : _070_;
assign _069_ = iword[6:0] == 7'h63;
assign _070_ = _069_ ? { w31_to_w11[20:1], iword[7], iword[30:25], iword[11:8], 1'h0 } : _072_;
assign _071_ = iword[6:0] == 7'h6f;
assign _072_ = _071_ ? { w31_to_w11[11:0], iword[19:12], iword[20], iword[30:21], 1'h0 } : 32'd0;
assign _073_ = iword[6:0] == 7'h03;
assign _074_ = iword[6:0] == 7'h23;
assign _075_ = _073_ | _074_;
assign _076_ = iword[14:12] == 3'h2;
assign _077_ = _076_ & _075_;
assign _078_ = _077_ ? 1'h1 : 1'h0;
assign _079_ = iword[6:0] == 7'h23;
assign _080_ = iword[14:12] == 3'h2;
assign _081_ = _080_ & _079_;
assign _082_ = _081_ ? 1'h1 : 1'h0;
assign _083_ = iword[6:0] == 7'h63;
assign _084_ = _083_ ? 1'h0 : 1'h1;
assign _085_ = iword[6:0] == 7'h13;
assign _086_ = iword[6:0] == 7'h37;
assign _087_ = _085_ | _086_;
assign _088_ = iword[6:0] == 7'h17;
assign _089_ = _087_ | _088_;
assign _090_ = iword[6:0] == 7'h03;
assign _091_ = iword[6:0] == 7'h23;
assign _092_ = _090_ | _091_;
assign _093_ = iword[14:12] == 3'h2;
assign _094_ = _093_ & _092_;
assign _095_ = _089_ | _094_;
assign _096_ = iword[6:0] == 7'h6f;
assign _097_ = _095_ | _096_;
assign _098_ = iword[6:0] == 7'h67;
assign _099_ = _097_ | _098_;
assign _100_ = _099_ ? 1'h1 : 1'h0;
assign _101_ = iword[6:0] == 7'h63;
assign _102_ = iword[6:0] == 7'h6f;
assign _103_ = _101_ | _102_;
assign _104_ = iword[6:0] == 7'h67;
assign _105_ = _103_ | _104_;
assign _106_ = iword[6:0] == 7'h67;
assign _107_ = _105_ | _106_;
assign _108_ = _107_ ? 1'h1 : 1'h0;
always @(posedge clk, posedge reset)
if (reset) _109_ <= 3'h0;
else _109_ <= _020_;
assign currstate = _109_;
assign control_flags = { _060_, _058_, _108_, _100_, _084_, _082_, _078_ };
assign w31_to_w11 = { iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31] };
assign imm = _066_;
assign control_flags_out = control_flags;
assign wbflag = _049_;
assign memflag = _040_;
assign pcflag = _033_;
assign fetchflag = _052_;
assign mem_req = _026_;
endmodule
module cpu(clk, reset, data_in, data_valid, data_out, addr_out, write_en, mem_req, x1);
wire [31:0] _00_;
wire [31:0] _01_;
wire [12:0] _02_;
wire [31:0] _03_;
wire [31:0] _04_;
wire [6:0] _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire [31:0] _11_;
wire [31:0] _12_;
wire [31:0] _13_;
wire _14_;
wire _15_;
wire [15:0] _16_;
wire [15:0] _17_;
wire [15:0] _18_;
wire [13:0] _19_;
wire [31:0] _20_;
reg [31:0] _21_;
output [13:0] addr_out;
wire [13:0] addr_out;
wire [31:0] b;
input clk;
wire clk;
wire [6:0] control_flags_out;
input [31:0] data_in;
wire [31:0] data_in;
output [31:0] data_out;
wire [31:0] data_out;
input data_valid;
wire data_valid;
wire fetchflag;
wire [31:0] imm;
wire [16:0] instruction;
wire [31:0] iword_reg;
output mem_req;
wire mem_req;
wire memflag;
wire [15:0] pc_inc;
wire [15:0] pc_offset;
wire [15:0] pc_out;
wire pcflag;
wire [31:0] rd;
wire [31:0] rdalu;
input reset;
wire reset;
wire [31:0] rs1;
wire [31:0] rs2;
wire s0;
wire s1;
wire wbflag;
output write_en;
wire write_en;
output [12:0] x1;
wire [12:0] x1;
assign _11_ = control_flags_out[3] ? imm : rs2;
assign _12_ = control_flags_out[4] ? { 16'h0000, pc_inc } : _13_;
assign _13_ = control_flags_out[0] ? data_in : rdalu;
assign _14_ = control_flags_out[4] ? rdalu[16] : 1'h0;
assign _15_ = control_flags_out[4] ? rdalu[17] : 1'h1;
assign _18_ = control_flags_out[6] ? rs1[15:0] : imm[15:0];
assign _19_ = control_flags_out[5] ? pc_out[15:2] : rdalu[13:0];
assign _20_ = fetchflag ? data_in : iword_reg;
always @(posedge clk, posedge reset)
if (reset) _21_ <= 32'd0;
else _21_ <= _20_;
alu alu_inst (
.a(rs1),
.b(b),
.clk(clk),
.instruction(instruction),
.rd(_03_),
.reset(reset)
);
control control_inst (
.clk(clk),
.control_flags_out(_05_),
.data_valid(data_valid),
.fetchflag(_09_),
.imm(_04_),
.iword(iword_reg),
.mem_req(_10_),
.memflag(_07_),
.pcflag(_08_),
.reset(reset),
.wbflag(_06_)
);
instructioncounter instruction_inst (
.clk(clk),
.pc_inc(_16_),
.pc_new(_17_),
.pc_offset(pc_offset),
.pcflag(pcflag),
.reset(reset),
.s0(s0),
.s1(s1)
);
regs regs_inst (
.clk(clk),
.rd(rd),
.rdadr(iword_reg[11:7]),
.regwrite(wbflag),
.reset(reset),
.rs1(_00_),
.rs1adr(iword_reg[19:15]),
.rs2(_01_),
.rs2adr(iword_reg[24:20]),
.x1(_02_)
);
assign s0 = _14_;
assign s1 = _15_;
assign imm = _04_;
assign control_flags_out = _05_;
assign rs1 = _00_;
assign rs2 = _01_;
assign b = _11_;
assign rdalu = _03_;
assign rd = _12_;
assign wbflag = _06_;
assign memflag = _07_;
assign pcflag = _08_;
assign fetchflag = _09_;
assign instruction = { iword_reg[31:25], iword_reg[14:12], iword_reg[6:0] };
assign iword_reg = _21_;
assign pc_inc = _16_;
assign pc_out = _17_;
assign pc_offset = _18_;
assign data_out = rs2;
assign addr_out = _19_;
assign write_en = memflag;
assign mem_req = _10_;
assign x1 = _02_;
endmodule
module instructioncounter(clk, reset, pcflag, s0, s1, pc_offset, pc_inc, pc_new);
wire [15:0] _00_;
wire [15:0] _01_;
wire _02_;
wire [15:0] _03_;
wire _04_;
wire _05_;
wire [15:0] _06_;
wire [15:0] _07_;
wire [15:0] _08_;
reg [15:0] _09_ = 16'h0000;
reg [15:0] _10_;
input clk;
wire clk;
output [15:0] pc_inc;
wire [15:0] pc_inc;
output [15:0] pc_new;
wire [15:0] pc_new;
input [15:0] pc_offset;
wire [15:0] pc_offset;
input pcflag;
wire pcflag;
wire [15:0] \reg ;
input reset;
wire reset;
input s0;
wire s0;
input s1;
wire s1;
wire [1:0] s1s0;
assign _00_ = \reg + 16'h0004;
assign _01_ = pc_offset + \reg ;
assign _02_ = s1s0 == 2'h0;
assign _03_ = \reg + 16'h0004;
assign _04_ = s1s0 == 2'h2;
assign _05_ = s1s0 == 2'h1;
function [15:0] \1383 ;
input [15:0] a;
input [47:0] b;
input [2:0] s;
(* parallel_case *)
casez (s)
3'b??1:
\1383 = b[15:0];
3'b?1?:
\1383 = b[31:16];
3'b1??:
\1383 = b[47:32];
default:
\1383 = a;
endcase
endfunction
assign _06_ = \1383 (16'h0000, { pc_offset, _03_, _01_ }, { _05_, _04_, _02_ });
assign _07_ = pcflag ? _06_ : \reg ;
assign _08_ = reset ? 16'h0000 : _07_;
always @(posedge clk)
_09_ <= _08_;
always @(posedge clk)
_10_ <= _00_;
assign s1s0 = { s1, s0 };
assign \reg = _09_;
assign pc_inc = _10_;
assign pc_new = \reg ;
endmodule
module regs(clk, reset, rs1adr, rs2adr, rdadr, rd, regwrite, rs1, rs2, x1);
wire [31:0] _000_;
wire [31:0] _001_;
wire [31:0] _002_;
wire [31:0] _003_;
wire [31:0] _004_;
wire [31:0] _005_;
wire [31:0] _006_;
wire [31:0] _007_;
wire [31:0] _008_;
wire [31:0] _009_;
wire [31:0] _010_;
wire [31:0] _011_;
wire [31:0] _012_;
wire [31:0] _013_;
wire [31:0] _014_;
wire [31:0] _015_;
wire [31:0] _016_;
wire [31:0] _017_;
wire [31:0] _018_;
wire [31:0] _019_;
wire [31:0] _020_;
wire [31:0] _021_;
wire [31:0] _022_;
wire [31:0] _023_;
wire [31:0] _024_;
wire [31:0] _025_;
wire [31:0] _026_;
wire [31:0] _027_;
wire [31:0] _028_;
wire [31:0] _029_;
wire [31:0] _030_;
wire [31:0] _031_;
wire [31:0] _032_;
wire [31:0] _033_;
wire [31:0] _034_;
wire [31:0] _035_;
wire [31:0] _036_;
wire [31:0] _037_;
wire [31:0] _038_;
wire [31:0] _039_;
wire _040_;
wire _041_;
wire [4:0] _042_;
wire [4:0] _043_;
wire [4:0] _044_;
wire [1023:0] _045_;
reg [1023:0] _046_;
reg [31:0] _047_;
reg [31:0] _048_;
wire _049_;
wire [12:0] _050_;
reg [12:0] _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire [31:0] _117_;
wire [31:0] _118_;
wire [31:0] _119_;
wire [31:0] _120_;
wire [31:0] _121_;
wire [31:0] _122_;
wire [31:0] _123_;
wire [31:0] _124_;
wire [31:0] _125_;
wire [31:0] _126_;
wire [31:0] _127_;
wire [31:0] _128_;
wire [31:0] _129_;
wire [31:0] _130_;
wire [31:0] _131_;
wire [31:0] _132_;
wire [31:0] _133_;
wire [31:0] _134_;
wire [31:0] _135_;
wire [31:0] _136_;
wire [31:0] _137_;
wire [31:0] _138_;
wire [31:0] _139_;
wire [31:0] _140_;
wire [31:0] _141_;
wire [31:0] _142_;
wire [31:0] _143_;
wire [31:0] _144_;
wire [31:0] _145_;
wire [31:0] _146_;
wire [31:0] _147_;
wire [31:0] _148_;
wire [31:0] _149_;
wire [31:0] _150_;
wire [31:0] _151_;
wire [31:0] _152_;
wire [31:0] _153_;
wire [31:0] _154_;
wire [31:0] _155_;
wire [31:0] _156_;
wire [31:0] _157_;
wire [31:0] _158_;
wire [31:0] _159_;
wire [31:0] _160_;
wire [31:0] _161_;
wire [31:0] _162_;
wire [31:0] _163_;
wire [31:0] _164_;
wire [31:0] _165_;
wire [31:0] _166_;
wire [31:0] _167_;
wire [31:0] _168_;
wire [31:0] _169_;
wire [31:0] _170_;
input clk;
wire clk;
input [31:0] rd;
wire [31:0] rd;
input [4:0] rdadr;
wire [4:0] rdadr;
wire [1023:0] registers;
input regwrite;
wire regwrite;
input reset;
wire reset;
output [31:0] rs1;
wire [31:0] rs1;
input [4:0] rs1adr;
wire [4:0] rs1adr;
output [31:0] rs2;
wire [31:0] rs2;
input [4:0] rs2adr;
wire [4:0] rs2adr;
output [12:0] x1;
wire [12:0] x1;
assign _000_ = _043_[0] ? registers[63:32] : registers[31:0];
assign _001_ = _043_[0] ? registers[191:160] : registers[159:128];
assign _002_ = _043_[0] ? registers[319:288] : registers[287:256];
assign _003_ = _043_[0] ? registers[447:416] : registers[415:384];
assign _004_ = _043_[0] ? registers[575:544] : registers[543:512];
assign _005_ = _043_[0] ? registers[703:672] : registers[671:640];
assign _006_ = _043_[0] ? registers[831:800] : registers[799:768];
assign _007_ = _043_[0] ? registers[959:928] : registers[927:896];
assign _008_ = _043_[2] ? _150_ : _149_;
assign _009_ = _043_[2] ? _154_ : _153_;
assign _010_ = _044_[0] ? registers[63:32] : registers[31:0];
assign _011_ = _044_[0] ? registers[191:160] : registers[159:128];
assign _012_ = _044_[0] ? registers[319:288] : registers[287:256];
assign _013_ = _044_[0] ? registers[447:416] : registers[415:384];
assign _014_ = _044_[0] ? registers[575:544] : registers[543:512];
assign _015_ = _044_[0] ? registers[703:672] : registers[671:640];
assign _016_ = _044_[0] ? registers[831:800] : registers[799:768];
assign _017_ = _044_[0] ? registers[959:928] : registers[927:896];
assign _018_ = _044_[2] ? _161_ : _160_;
assign _019_ = _044_[2] ? _165_ : _164_;
assign _020_ = _043_[0] ? registers[127:96] : registers[95:64];
assign _021_ = _043_[0] ? registers[255:224] : registers[223:192];
assign _022_ = _043_[0] ? registers[383:352] : registers[351:320];
assign _023_ = _043_[0] ? registers[511:480] : registers[479:448];
assign _024_ = _043_[0] ? registers[639:608] : registers[607:576];
assign _025_ = _043_[0] ? registers[767:736] : registers[735:704];
assign _026_ = _043_[0] ? registers[895:864] : registers[863:832];
assign _027_ = _043_[0] ? registers[1023:992] : registers[991:960];
assign _028_ = _043_[2] ? _152_ : _151_;
assign _029_ = _043_[2] ? _156_ : _155_;
assign _030_ = _044_[0] ? registers[127:96] : registers[95:64];
assign _031_ = _044_[0] ? registers[255:224] : registers[223:192];
assign _032_ = _044_[0] ? registers[383:352] : registers[351:320];
assign _033_ = _044_[0] ? registers[511:480] : registers[479:448];
assign _034_ = _044_[0] ? registers[639:608] : registers[607:576];
assign _035_ = _044_[0] ? registers[767:736] : registers[735:704];
assign _036_ = _044_[0] ? registers[895:864] : registers[863:832];
assign _037_ = _044_[0] ? registers[1023:992] : registers[991:960];
assign _038_ = _044_[2] ? _163_ : _162_;
assign _039_ = _044_[2] ? _167_ : _166_;
assign _149_ = _043_[1] ? _020_ : _000_;
assign _150_ = _043_[1] ? _021_ : _001_;
assign _151_ = _043_[1] ? _022_ : _002_;
assign _152_ = _043_[1] ? _023_ : _003_;
assign _153_ = _043_[1] ? _024_ : _004_;
assign _154_ = _043_[1] ? _025_ : _005_;
assign _155_ = _043_[1] ? _026_ : _006_;
assign _156_ = _043_[1] ? _027_ : _007_;
assign _157_ = _043_[3] ? _028_ : _008_;
assign _158_ = _043_[3] ? _029_ : _009_;
assign _160_ = _044_[1] ? _030_ : _010_;
assign _161_ = _044_[1] ? _031_ : _011_;
assign _162_ = _044_[1] ? _032_ : _012_;
assign _163_ = _044_[1] ? _033_ : _013_;
assign _164_ = _044_[1] ? _034_ : _014_;
assign _165_ = _044_[1] ? _035_ : _015_;
assign _166_ = _044_[1] ? _036_ : _016_;
assign _167_ = _044_[1] ? _037_ : _017_;
assign _168_ = _044_[3] ? _038_ : _018_;
assign _169_ = _044_[3] ? _039_ : _019_;
assign _170_ = _044_[4] ? _169_ : _168_;
assign _040_ = rdadr != 5'h00;
assign _041_ = _040_ & regwrite;
assign _042_ = 5'h1f - rdadr;
assign _043_ = 5'h1f - rs1adr;
assign _044_ = 5'h1f - rs2adr;
assign _045_ = _041_ ? { _148_, _147_, _146_, _145_, _144_, _143_, _142_, _141_, _140_, _139_, _138_, _137_, _136_, _135_, _134_, _133_, _132_, _131_, _130_, _129_, _128_, _127_, _126_, _125_, _124_, _123_, _122_, _121_, _120_, _119_, _118_, _117_ } : registers;
always @(posedge clk, posedge reset)
if (reset) _046_ <= 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
else _046_ <= _045_;
always @(posedge clk, posedge reset)
if (reset) _047_ <= 32'd0;
else _047_ <= _159_;
always @(posedge clk, posedge reset)
if (reset) _048_ <= 32'd0;
else _048_ <= _170_;
assign _049_ = ~ reset;
assign _050_ = _049_ ? registers[972:960] : _051_;
always @(posedge clk)
_051_ <= _050_;
assign _052_ = ~ _042_[4];
assign _053_ = ~ _042_[3];
assign _054_ = _052_ & _053_;
assign _055_ = _052_ & _042_[3];
assign _056_ = _042_[4] & _053_;
assign _057_ = _042_[4] & _042_[3];
assign _058_ = ~ _042_[2];
assign _059_ = _054_ & _058_;
assign _060_ = _054_ & _042_[2];
assign _061_ = _055_ & _058_;
assign _062_ = _055_ & _042_[2];
assign _063_ = _056_ & _058_;
assign _064_ = _056_ & _042_[2];
assign _065_ = _057_ & _058_;
assign _066_ = _057_ & _042_[2];
assign _067_ = ~ _042_[1];
assign _068_ = _059_ & _067_;
assign _069_ = _059_ & _042_[1];
assign _070_ = _060_ & _067_;
assign _071_ = _060_ & _042_[1];
assign _072_ = _061_ & _067_;
assign _073_ = _061_ & _042_[1];
assign _074_ = _062_ & _067_;
assign _075_ = _062_ & _042_[1];
assign _076_ = _063_ & _067_;
assign _077_ = _063_ & _042_[1];
assign _078_ = _064_ & _067_;
assign _079_ = _064_ & _042_[1];
assign _080_ = _065_ & _067_;
assign _081_ = _065_ & _042_[1];
assign _082_ = _066_ & _067_;
assign _083_ = _066_ & _042_[1];
assign _084_ = ~ _042_[0];
assign _085_ = _068_ & _084_;
assign _086_ = _068_ & _042_[0];
assign _087_ = _069_ & _084_;
assign _088_ = _069_ & _042_[0];
assign _089_ = _070_ & _084_;
assign _090_ = _070_ & _042_[0];
assign _091_ = _071_ & _084_;
assign _092_ = _071_ & _042_[0];
assign _093_ = _072_ & _084_;
assign _094_ = _072_ & _042_[0];
assign _095_ = _073_ & _084_;
assign _096_ = _073_ & _042_[0];
assign _097_ = _074_ & _084_;
assign _098_ = _074_ & _042_[0];
assign _099_ = _075_ & _084_;
assign _100_ = _075_ & _042_[0];
assign _101_ = _076_ & _084_;
assign _102_ = _076_ & _042_[0];
assign _103_ = _077_ & _084_;
assign _104_ = _077_ & _042_[0];
assign _105_ = _078_ & _084_;
assign _106_ = _078_ & _042_[0];
assign _107_ = _079_ & _084_;
assign _108_ = _079_ & _042_[0];
assign _109_ = _080_ & _084_;
assign _110_ = _080_ & _042_[0];
assign _111_ = _081_ & _084_;
assign _112_ = _081_ & _042_[0];
assign _113_ = _082_ & _084_;
assign _114_ = _082_ & _042_[0];
assign _115_ = _083_ & _084_;
assign _116_ = _083_ & _042_[0];
assign _117_ = _085_ ? rd : registers[31:0];
assign _118_ = _086_ ? rd : registers[63:32];
assign _119_ = _087_ ? rd : registers[95:64];
assign _120_ = _088_ ? rd : registers[127:96];
assign _121_ = _089_ ? rd : registers[159:128];
assign _122_ = _090_ ? rd : registers[191:160];
assign _123_ = _091_ ? rd : registers[223:192];
assign _124_ = _092_ ? rd : registers[255:224];
assign _125_ = _093_ ? rd : registers[287:256];
assign _126_ = _094_ ? rd : registers[319:288];
assign _127_ = _095_ ? rd : registers[351:320];
assign _128_ = _096_ ? rd : registers[383:352];
assign _129_ = _097_ ? rd : registers[415:384];
assign _130_ = _098_ ? rd : registers[447:416];
assign _131_ = _099_ ? rd : registers[479:448];
assign _132_ = _100_ ? rd : registers[511:480];
assign _133_ = _101_ ? rd : registers[543:512];
assign _134_ = _102_ ? rd : registers[575:544];
assign _135_ = _103_ ? rd : registers[607:576];
assign _136_ = _104_ ? rd : registers[639:608];
assign _137_ = _105_ ? rd : registers[671:640];
assign _138_ = _106_ ? rd : registers[703:672];
assign _139_ = _107_ ? rd : registers[735:704];
assign _140_ = _108_ ? rd : registers[767:736];
assign _141_ = _109_ ? rd : registers[799:768];
assign _142_ = _110_ ? rd : registers[831:800];
assign _143_ = _111_ ? rd : registers[863:832];
assign _144_ = _112_ ? rd : registers[895:864];
assign _145_ = _113_ ? rd : registers[927:896];
assign _146_ = _114_ ? rd : registers[959:928];
assign _147_ = _115_ ? rd : registers[991:960];
assign _148_ = _116_ ? rd : registers[1023:992];
assign _159_ = _043_[4] ? _158_ : _157_;
assign registers = _046_;
assign rs1 = _047_;
assign rs2 = _048_;
assign x1 = _051_;
endmodule
module spi_master(clk, mode_select, reset, miso, cs, data_in, addr, sclk, mosi, data_out, data_valid);
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire [31:0] _060_;
wire [31:0] _061_;
wire [31:0] _062_;
wire [2:0] _063_;
wire _064_;
wire [31:0] _065_;
reg [31:0] _066_;
wire _067_;
wire _068_;
wire _069_;
reg _070_;
wire _071_;
wire [31:0] _072_;
reg [31:0] _073_ = 32'd16;
wire _074_;
wire [31:0] _075_;
reg [31:0] _076_ = 32'd33;
reg [2:0] _077_;
wire _078_;
wire _079_;
reg _080_;
wire _081_;
wire [31:0] _082_;
reg [31:0] _083_;
wire _084_;
wire _085_;
reg _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
wire _203_;
wire _204_;
wire _205_;
wire _206_;
wire _207_;
wire _208_;
wire _209_;
wire _210_;
wire _211_;
wire _212_;
wire _213_;
wire _214_;
wire _215_;
wire _216_;
wire _217_;
wire _218_;
wire _219_;
wire _220_;
wire _221_;
wire _222_;
wire _223_;
wire _224_;
wire _225_;
wire _226_;
wire _227_;
wire _228_;
wire _229_;
wire _230_;
wire _231_;
wire _232_;
wire _233_;
wire _234_;
wire _235_;
wire _236_;
wire _237_;
wire _238_;
wire _239_;
wire _240_;
wire _241_;
wire _242_;
wire _243_;
wire _244_;
wire _245_;
wire _246_;
wire _247_;
wire _248_;
wire _249_;
wire _250_;
wire _251_;
wire _252_;
wire _253_;
wire _254_;
wire _255_;
wire _256_;
wire _257_;
wire _258_;
wire _259_;
wire _260_;
wire _261_;
wire _262_;
wire _263_;
wire _264_;
wire _265_;
wire _266_;
wire _267_;
wire _268_;
wire _269_;
wire _270_;
wire _271_;
wire _272_;
wire _273_;
wire _274_;
wire _275_;
wire _276_;
wire _277_;
wire _278_;
wire _279_;
wire _280_;
wire _281_;
wire _282_;
wire _283_;
wire _284_;
wire _285_;
wire _286_;
wire _287_;
wire _288_;
wire _289_;
wire _290_;
wire _291_;
wire _292_;
wire _293_;
wire _294_;
wire _295_;
wire _296_;
wire _297_;
wire _298_;
wire _299_;
wire _300_;
wire _301_;
wire _302_;
wire _303_;
wire _304_;
wire _305_;
wire _306_;
wire _307_;
wire _308_;
wire _309_;
wire _310_;
wire _311_;
wire _312_;
wire _313_;
wire _314_;
wire _315_;
wire [2:0] _316_;
wire _317_;
wire _318_;
wire [31:0] _319_;
wire _320_;
wire _321_;
wire _322_;
wire [31:0] _323_;
wire _324_;
wire [2:0] _325_;
wire [2:0] _326_;
wire _327_;
wire [31:0] _328_;
wire [2:0] _329_;
wire _330_;
wire [31:0] _331_;
wire [2:0] _332_;
wire _333_;
wire _334_;
wire [31:0] _335_;
wire _336_;
wire [31:0] _337_;
wire [31:0] _338_;
wire [31:0] _339_;
wire [2:0] _340_;
wire [31:0] _341_;
wire [31:0] _342_;
wire [2:0] _343_;
wire _344_;
wire _345_;
wire [31:0] _346_;
wire _347_;
wire [31:0] _348_;
wire _349_;
wire [31:0] _350_;
wire [2:0] _351_;
wire _352_;
wire [31:0] _353_;
wire [2:0] _354_;
wire _355_;
wire [31:0] _356_;
wire _357_;
wire [2:0] _358_;
wire _359_;
wire [31:0] _360_;
wire _361_;
wire [31:0] _362_;
wire [2:0] _363_;
wire _364_;
wire [31:0] _365_;
wire _366_;
wire [31:0] _367_;
wire [31:0] _368_;
wire [2:0] _369_;
wire _370_;
wire [31:0] _371_;
wire _372_;
wire [31:0] _373_;
wire [31:0] _374_;
wire [31:0] _375_;
wire [2:0] _376_;
wire _377_;
wire [31:0] _378_;
wire _379_;
input [15:0] addr;
wire [15:0] addr;
input clk;
wire clk;
input cs;
wire cs;
wire [2:0] currstate;
input [31:0] data_in;
wire [31:0] data_in;
output [31:0] data_out;
wire [31:0] data_out;
wire [31:0] data_reg;
output data_valid;
wire data_valid;
input miso;
wire miso;
input mode_select;
wire mode_select;
wire mode_select_zw;
output mosi;
wire mosi;
wire [31:0] read_adress_counter;
input reset;
wire reset;
output sclk;
wire sclk;
wire [31:0] write_adress_counter;
assign _000_ = write_adress_counter[0] ? addr[1] : addr[0];
assign _001_ = write_adress_counter[0] ? addr[5] : addr[4];
assign _002_ = write_adress_counter[0] ? addr[9] : addr[8];
assign _003_ = write_adress_counter[0] ? addr[13] : addr[12];
assign _004_ = write_adress_counter[2] ? _088_ : _087_;
assign _005_ = write_adress_counter[0] ? addr[1] : addr[0];
assign _006_ = write_adress_counter[0] ? addr[5] : addr[4];
assign _007_ = write_adress_counter[0] ? addr[9] : addr[8];
assign _008_ = write_adress_counter[0] ? addr[13] : addr[12];
assign _009_ = write_adress_counter[2] ? _093_ : _092_;
assign _010_ = read_adress_counter[0] ? data_in[1] : data_in[0];
assign _011_ = read_adress_counter[0] ? data_in[5] : data_in[4];
assign _012_ = read_adress_counter[0] ? data_in[9] : data_in[8];
assign _013_ = read_adress_counter[0] ? data_in[13] : data_in[12];
assign _014_ = read_adress_counter[0] ? data_in[17] : data_in[16];
assign _015_ = read_adress_counter[0] ? data_in[21] : data_in[20];
assign _016_ = read_adress_counter[0] ? data_in[25] : data_in[24];
assign _017_ = read_adress_counter[0] ? data_in[29] : data_in[28];
assign _018_ = read_adress_counter[2] ? _293_ : _292_;
assign _019_ = read_adress_counter[2] ? _297_ : _296_;
assign _020_ = read_adress_counter[0] ? data_in[1] : data_in[0];
assign _021_ = read_adress_counter[0] ? data_in[5] : data_in[4];
assign _022_ = read_adress_counter[0] ? data_in[9] : data_in[8];
assign _023_ = read_adress_counter[0] ? data_in[13] : data_in[12];
assign _024_ = read_adress_counter[0] ? data_in[17] : data_in[16];
assign _025_ = read_adress_counter[0] ? data_in[21] : data_in[20];
assign _026_ = read_adress_counter[0] ? data_in[25] : data_in[24];
assign _027_ = read_adress_counter[0] ? data_in[29] : data_in[28];
assign _028_ = read_adress_counter[2] ? _305_ : _304_;
assign _029_ = read_adress_counter[2] ? _309_ : _308_;
assign _030_ = write_adress_counter[0] ? addr[3] : addr[2];
assign _031_ = write_adress_counter[0] ? addr[7] : addr[6];
assign _032_ = write_adress_counter[0] ? addr[11] : addr[10];
assign _033_ = write_adress_counter[0] ? addr[15] : addr[14];
assign _034_ = write_adress_counter[2] ? _090_ : _089_;
assign _035_ = write_adress_counter[0] ? addr[3] : addr[2];
assign _036_ = write_adress_counter[0] ? addr[7] : addr[6];
assign _037_ = write_adress_counter[0] ? addr[11] : addr[10];
assign _038_ = write_adress_counter[0] ? addr[15] : addr[14];
assign _039_ = write_adress_counter[2] ? _095_ : _094_;
assign _040_ = read_adress_counter[0] ? data_in[3] : data_in[2];
assign _041_ = read_adress_counter[0] ? data_in[7] : data_in[6];
assign _042_ = read_adress_counter[0] ? data_in[11] : data_in[10];
assign _043_ = read_adress_counter[0] ? data_in[15] : data_in[14];
assign _044_ = read_adress_counter[0] ? data_in[19] : data_in[18];
assign _045_ = read_adress_counter[0] ? data_in[23] : data_in[22];
assign _046_ = read_adress_counter[0] ? data_in[27] : data_in[26];
assign _047_ = read_adress_counter[0] ? data_in[31] : data_in[30];
assign _048_ = read_adress_counter[2] ? _295_ : _294_;
assign _049_ = read_adress_counter[2] ? _299_ : _298_;
assign _050_ = read_adress_counter[0] ? data_in[3] : data_in[2];
assign _051_ = read_adress_counter[0] ? data_in[7] : data_in[6];
assign _052_ = read_adress_counter[0] ? data_in[11] : data_in[10];
assign _053_ = read_adress_counter[0] ? data_in[15] : data_in[14];
assign _054_ = read_adress_counter[0] ? data_in[19] : data_in[18];
assign _055_ = read_adress_counter[0] ? data_in[23] : data_in[22];
assign _056_ = read_adress_counter[0] ? data_in[27] : data_in[26];
assign _057_ = read_adress_counter[0] ? data_in[31] : data_in[30];
assign _058_ = read_adress_counter[2] ? _307_ : _306_;
assign _059_ = read_adress_counter[2] ? _311_ : _310_;
assign _087_ = write_adress_counter[1] ? _030_ : _000_;
assign _088_ = write_adress_counter[1] ? _031_ : _001_;
assign _089_ = write_adress_counter[1] ? _032_ : _002_;
assign _090_ = write_adress_counter[1] ? _033_ : _003_;
assign _091_ = write_adress_counter[3] ? _034_ : _004_;
assign _092_ = write_adress_counter[1] ? _035_ : _005_;
assign _093_ = write_adress_counter[1] ? _036_ : _006_;
assign _094_ = write_adress_counter[1] ? _037_ : _007_;
assign _095_ = write_adress_counter[1] ? _038_ : _008_;
assign _096_ = write_adress_counter[3] ? _039_ : _009_;
assign _292_ = read_adress_counter[1] ? _040_ : _010_;
assign _293_ = read_adress_counter[1] ? _041_ : _011_;
assign _294_ = read_adress_counter[1] ? _042_ : _012_;
assign _295_ = read_adress_counter[1] ? _043_ : _013_;
assign _296_ = read_adress_counter[1] ? _044_ : _014_;
assign _297_ = read_adress_counter[1] ? _045_ : _015_;
assign _298_ = read_adress_counter[1] ? _046_ : _016_;
assign _299_ = read_adress_counter[1] ? _047_ : _017_;
assign _300_ = read_adress_counter[3] ? _048_ : _018_;
assign _302_ = read_adress_counter[3] ? _049_ : _019_;
assign _304_ = read_adress_counter[1] ? _050_ : _020_;
assign _305_ = read_adress_counter[1] ? _051_ : _021_;
assign _306_ = read_adress_counter[1] ? _052_ : _022_;
assign _307_ = read_adress_counter[1] ? _053_ : _023_;
assign _308_ = read_adress_counter[1] ? _054_ : _024_;
assign _309_ = read_adress_counter[1] ? _055_ : _025_;
assign _310_ = read_adress_counter[1] ? _056_ : _026_;
assign _311_ = read_adress_counter[1] ? _057_ : _027_;
assign _313_ = read_adress_counter[3] ? _058_ : _028_;
assign _314_ = read_adress_counter[3] ? _059_ : _029_;
assign _316_ = _301_ ? 3'h1 : currstate;
assign _317_ = currstate == 3'h1;
assign _318_ = write_adress_counter == 32'd16;
assign _319_ = write_adress_counter - 32'd1;
assign _320_ = $signed(write_adress_counter) > $signed(32'd0);
assign _321_ = $signed(write_adress_counter) <= $signed(32'd15);
assign _322_ = _321_ & _320_;
assign _323_ = write_adress_counter - 32'd1;
assign _324_ = ~ mode_select_zw;
assign _325_ = mode_select_zw ? 3'h2 : currstate;
assign _326_ = _324_ ? 3'h3 : _325_;
assign _327_ = _322_ ? _091_ : _096_;
assign _328_ = _322_ ? _323_ : write_adress_counter;
assign _329_ = _322_ ? currstate : _326_;
assign _330_ = _318_ ? mode_select_zw : _327_;
assign _331_ = _318_ ? _319_ : _328_;
assign _332_ = _318_ ? currstate : _329_;
assign _333_ = currstate == 3'h3;
assign _334_ = $signed(read_adress_counter) >= $signed(32'd32);
assign _335_ = read_adress_counter - 32'd1;
assign _336_ = $signed(read_adress_counter) > $signed(32'd0);
assign _337_ = read_adress_counter - 32'd1;
assign _338_ = _336_ ? { _193_, _192_, _191_, _190_, _189_, _188_, _187_, _186_, _185_, _184_, _183_, _182_, _181_, _180_, _179_, _178_, _177_, _176_, _175_, _174_, _173_, _172_, _171_, _170_, _169_, _168_, _167_, _166_, _165_, _164_, _163_, _162_ } : { _291_, _289_, _288_, _287_, _286_, _285_, _284_, _283_, _282_, _281_, _280_, _279_, _278_, _277_, _276_, _275_, _274_, _273_, _272_, _271_, _270_, _269_, _268_, _267_, _266_, _265_, _264_, _263_, _262_, _261_, _260_, _259_ };
assign _339_ = _336_ ? _337_ : read_adress_counter;
assign _340_ = _336_ ? currstate : 3'h4;
assign _341_ = _334_ ? data_reg : _338_;
assign _342_ = _334_ ? _335_ : _339_;
assign _343_ = _334_ ? currstate : _340_;
assign _344_ = currstate == 3'h2;
assign _345_ = $signed(read_adress_counter) >= $signed(32'd32);
assign _346_ = read_adress_counter - 32'd1;
assign _347_ = $signed(read_adress_counter) > $signed(32'd0);
assign _348_ = read_adress_counter - 32'd1;
assign _349_ = _347_ ? _303_ : _315_;
assign _350_ = _347_ ? _348_ : read_adress_counter;
assign _351_ = _347_ ? currstate : 3'h4;
assign _352_ = _345_ ? _080_ : _349_;
assign _353_ = _345_ ? _346_ : _350_;
assign _354_ = _345_ ? currstate : _351_;
assign _355_ = currstate == 3'h4;
assign _356_ = _355_ ? data_reg : _083_;
assign _357_ = _355_ ? 1'h1 : _086_;
assign _358_ = _355_ ? 3'h0 : currstate;
assign _359_ = _344_ ? _352_ : _080_;
assign _360_ = _344_ ? _083_ : _356_;
assign _361_ = _344_ ? _086_ : _357_;
assign _362_ = _344_ ? _353_ : read_adress_counter;
assign _363_ = _344_ ? _354_ : _358_;
assign _364_ = _333_ ? _080_ : _359_;
assign _365_ = _333_ ? _083_ : _360_;
assign _366_ = _333_ ? _086_ : _361_;
assign _367_ = _333_ ? _341_ : data_reg;
assign _368_ = _333_ ? _342_ : _362_;
assign _369_ = _333_ ? _343_ : _363_;
assign _370_ = _317_ ? _330_ : _364_;
assign _371_ = _317_ ? _083_ : _365_;
assign _372_ = _317_ ? _086_ : _366_;
assign _373_ = _317_ ? data_reg : _367_;
assign _374_ = _317_ ? _331_ : write_adress_counter;
assign _375_ = _317_ ? read_adress_counter : _368_;
assign _376_ = _317_ ? _332_ : _369_;
assign _377_ = _290_ ? 1'h0 : _370_;
assign _378_ = _290_ ? 32'd0 : _371_;
assign _379_ = _290_ ? 1'h0 : _372_;
assign _060_ = _290_ ? 32'd0 : _373_;
assign _061_ = _290_ ? 32'd16 : _374_;
assign _062_ = _290_ ? 32'd33 : _375_;
assign _063_ = _290_ ? _316_ : _376_;
assign _064_ = ~ reset;
assign _065_ = _064_ ? _060_ : data_reg;
always @(posedge clk)
_066_ <= _065_;
assign _067_ = ~ reset;
assign _068_ = _290_ & _067_;
assign _069_ = _068_ ? _312_ : mode_select_zw;
always @(posedge clk)
_070_ <= _069_;
assign _071_ = ~ reset;
assign _072_ = _071_ ? _061_ : write_adress_counter;
always @(posedge clk)
_073_ <= _072_;
assign _074_ = ~ reset;
assign _075_ = _074_ ? _062_ : read_adress_counter;
always @(posedge clk)
_076_ <= _075_;
always @(posedge clk, posedge reset)
if (reset) _077_ <= 3'h0;
else _077_ <= _063_;
assign _078_ = ~ reset;
assign _079_ = _078_ ? _377_ : _080_;
always @(posedge clk)
_080_ <= _079_;
assign _081_ = ~ reset;
assign _082_ = _081_ ? _378_ : _083_;
always @(posedge clk)
_083_ <= _082_;
assign _084_ = ~ reset;
assign _085_ = _084_ ? _379_ : _086_;
always @(posedge clk)
_086_ <= _085_;
assign _097_ = ~ read_adress_counter[4];
assign _098_ = ~ read_adress_counter[3];
assign _099_ = _097_ & _098_;
assign _100_ = _097_ & read_adress_counter[3];
assign _101_ = read_adress_counter[4] & _098_;
assign _102_ = read_adress_counter[4] & read_adress_counter[3];
assign _103_ = ~ read_adress_counter[2];
assign _104_ = _099_ & _103_;
assign _105_ = _099_ & read_adress_counter[2];
assign _106_ = _100_ & _103_;
assign _107_ = _100_ & read_adress_counter[2];
assign _108_ = _101_ & _103_;
assign _109_ = _101_ & read_adress_counter[2];
assign _110_ = _102_ & _103_;
assign _111_ = _102_ & read_adress_counter[2];
assign _112_ = ~ read_adress_counter[1];
assign _113_ = _104_ & _112_;
assign _114_ = _104_ & read_adress_counter[1];
assign _115_ = _105_ & _112_;
assign _116_ = _105_ & read_adress_counter[1];
assign _117_ = _106_ & _112_;
assign _118_ = _106_ & read_adress_counter[1];
assign _119_ = _107_ & _112_;
assign _120_ = _107_ & read_adress_counter[1];
assign _121_ = _108_ & _112_;
assign _122_ = _108_ & read_adress_counter[1];
assign _123_ = _109_ & _112_;
assign _124_ = _109_ & read_adress_counter[1];
assign _125_ = _110_ & _112_;
assign _126_ = _110_ & read_adress_counter[1];
assign _127_ = _111_ & _112_;
assign _128_ = _111_ & read_adress_counter[1];
assign _129_ = ~ read_adress_counter[0];
assign _130_ = _113_ & _129_;
assign _131_ = _113_ & read_adress_counter[0];
assign _132_ = _114_ & _129_;
assign _133_ = _114_ & read_adress_counter[0];
assign _134_ = _115_ & _129_;
assign _135_ = _115_ & read_adress_counter[0];
assign _136_ = _116_ & _129_;
assign _137_ = _116_ & read_adress_counter[0];
assign _138_ = _117_ & _129_;
assign _139_ = _117_ & read_adress_counter[0];
assign _140_ = _118_ & _129_;
assign _141_ = _118_ & read_adress_counter[0];
assign _142_ = _119_ & _129_;
assign _143_ = _119_ & read_adress_counter[0];
assign _144_ = _120_ & _129_;
assign _145_ = _120_ & read_adress_counter[0];
assign _146_ = _121_ & _129_;
assign _147_ = _121_ & read_adress_counter[0];
assign _148_ = _122_ & _129_;
assign _149_ = _122_ & read_adress_counter[0];
assign _150_ = _123_ & _129_;
assign _151_ = _123_ & read_adress_counter[0];
assign _152_ = _124_ & _129_;
assign _153_ = _124_ & read_adress_counter[0];
assign _154_ = _125_ & _129_;
assign _155_ = _125_ & read_adress_counter[0];
assign _156_ = _126_ & _129_;
assign _157_ = _126_ & read_adress_counter[0];
assign _158_ = _127_ & _129_;
assign _159_ = _127_ & read_adress_counter[0];
assign _160_ = _128_ & _129_;
assign _161_ = _128_ & read_adress_counter[0];
assign _162_ = _130_ ? miso : data_reg[0];
assign _163_ = _131_ ? miso : data_reg[1];
assign _164_ = _132_ ? miso : data_reg[2];
assign _165_ = _133_ ? miso : data_reg[3];
assign _166_ = _134_ ? miso : data_reg[4];
assign _167_ = _135_ ? miso : data_reg[5];
assign _168_ = _136_ ? miso : data_reg[6];
assign _169_ = _137_ ? miso : data_reg[7];
assign _170_ = _138_ ? miso : data_reg[8];
assign _171_ = _139_ ? miso : data_reg[9];
assign _172_ = _140_ ? miso : data_reg[10];
assign _173_ = _141_ ? miso : data_reg[11];
assign _174_ = _142_ ? miso : data_reg[12];
assign _175_ = _143_ ? miso : data_reg[13];
assign _176_ = _144_ ? miso : data_reg[14];
assign _177_ = _145_ ? miso : data_reg[15];
assign _178_ = _146_ ? miso : data_reg[16];
assign _179_ = _147_ ? miso : data_reg[17];
assign _180_ = _148_ ? miso : data_reg[18];
assign _181_ = _149_ ? miso : data_reg[19];
assign _182_ = _150_ ? miso : data_reg[20];
assign _183_ = _151_ ? miso : data_reg[21];
assign _184_ = _152_ ? miso : data_reg[22];
assign _185_ = _153_ ? miso : data_reg[23];
assign _186_ = _154_ ? miso : data_reg[24];
assign _187_ = _155_ ? miso : data_reg[25];
assign _188_ = _156_ ? miso : data_reg[26];
assign _189_ = _157_ ? miso : data_reg[27];
assign _190_ = _158_ ? miso : data_reg[28];
assign _191_ = _159_ ? miso : data_reg[29];
assign _192_ = _160_ ? miso : data_reg[30];
assign _193_ = _161_ ? miso : data_reg[31];
assign _194_ = ~ read_adress_counter[4];
assign _195_ = ~ read_adress_counter[3];
assign _196_ = _194_ & _195_;
assign _197_ = _194_ & read_adress_counter[3];
assign _198_ = read_adress_counter[4] & _195_;
assign _199_ = read_adress_counter[4] & read_adress_counter[3];
assign _200_ = ~ read_adress_counter[2];
assign _201_ = _196_ & _200_;
assign _202_ = _196_ & read_adress_counter[2];
assign _203_ = _197_ & _200_;
assign _204_ = _197_ & read_adress_counter[2];
assign _205_ = _198_ & _200_;
assign _206_ = _198_ & read_adress_counter[2];
assign _207_ = _199_ & _200_;
assign _208_ = _199_ & read_adress_counter[2];
assign _209_ = ~ read_adress_counter[1];
assign _210_ = _201_ & _209_;
assign _211_ = _201_ & read_adress_counter[1];
assign _212_ = _202_ & _209_;
assign _213_ = _202_ & read_adress_counter[1];
assign _214_ = _203_ & _209_;
assign _215_ = _203_ & read_adress_counter[1];
assign _216_ = _204_ & _209_;
assign _217_ = _204_ & read_adress_counter[1];
assign _218_ = _205_ & _209_;
assign _219_ = _205_ & read_adress_counter[1];
assign _220_ = _206_ & _209_;
assign _221_ = _206_ & read_adress_counter[1];
assign _222_ = _207_ & _209_;
assign _223_ = _207_ & read_adress_counter[1];
assign _224_ = _208_ & _209_;
assign _225_ = _208_ & read_adress_counter[1];
assign _226_ = ~ read_adress_counter[0];
assign _227_ = _210_ & _226_;
assign _228_ = _210_ & read_adress_counter[0];
assign _229_ = _211_ & _226_;
assign _230_ = _211_ & read_adress_counter[0];
assign _231_ = _212_ & _226_;
assign _232_ = _212_ & read_adress_counter[0];
assign _233_ = _213_ & _226_;
assign _234_ = _213_ & read_adress_counter[0];
assign _235_ = _214_ & _226_;
assign _236_ = _214_ & read_adress_counter[0];
assign _237_ = _215_ & _226_;
assign _238_ = _215_ & read_adress_counter[0];
assign _239_ = _216_ & _226_;
assign _240_ = _216_ & read_adress_counter[0];
assign _241_ = _217_ & _226_;
assign _242_ = _217_ & read_adress_counter[0];
assign _243_ = _218_ & _226_;
assign _244_ = _218_ & read_adress_counter[0];
assign _245_ = _219_ & _226_;
assign _246_ = _219_ & read_adress_counter[0];
assign _247_ = _220_ & _226_;
assign _248_ = _220_ & read_adress_counter[0];
assign _249_ = _221_ & _226_;
assign _250_ = _221_ & read_adress_counter[0];
assign _251_ = _222_ & _226_;
assign _252_ = _222_ & read_adress_counter[0];
assign _253_ = _223_ & _226_;
assign _254_ = _223_ & read_adress_counter[0];
assign _255_ = _224_ & _226_;
assign _256_ = _224_ & read_adress_counter[0];
assign _257_ = _225_ & _226_;
assign _258_ = _225_ & read_adress_counter[0];
assign _259_ = _227_ ? miso : data_reg[0];
assign _260_ = _228_ ? miso : data_reg[1];
assign _261_ = _229_ ? miso : data_reg[2];
assign _262_ = _230_ ? miso : data_reg[3];
assign _263_ = _231_ ? miso : data_reg[4];
assign _264_ = _232_ ? miso : data_reg[5];
assign _265_ = _233_ ? miso : data_reg[6];
assign _266_ = _234_ ? miso : data_reg[7];
assign _267_ = _235_ ? miso : data_reg[8];
assign _268_ = _236_ ? miso : data_reg[9];
assign _269_ = _237_ ? miso : data_reg[10];
assign _270_ = _238_ ? miso : data_reg[11];
assign _271_ = _239_ ? miso : data_reg[12];
assign _272_ = _240_ ? miso : data_reg[13];
assign _273_ = _241_ ? miso : data_reg[14];
assign _274_ = _242_ ? miso : data_reg[15];
assign _275_ = _243_ ? miso : data_reg[16];
assign _276_ = _244_ ? miso : data_reg[17];
assign _277_ = _245_ ? miso : data_reg[18];
assign _278_ = _246_ ? miso : data_reg[19];
assign _279_ = _247_ ? miso : data_reg[20];
assign _280_ = _248_ ? miso : data_reg[21];
assign _281_ = _249_ ? miso : data_reg[22];
assign _282_ = _250_ ? miso : data_reg[23];
assign _283_ = _251_ ? miso : data_reg[24];
assign _284_ = _252_ ? miso : data_reg[25];
assign _285_ = _253_ ? miso : data_reg[26];
assign _286_ = _254_ ? miso : data_reg[27];
assign _287_ = _255_ ? miso : data_reg[28];
assign _288_ = _256_ ? miso : data_reg[29];
assign _289_ = _257_ ? miso : data_reg[30];
assign _291_ = _258_ ? miso : data_reg[31];
assign _303_ = read_adress_counter[4] ? _302_ : _300_;
assign _315_ = read_adress_counter[4] ? _314_ : _313_;
assign _290_ = currstate == 3'h0;
assign _301_ = ~ cs;
assign _312_ = _301_ ? mode_select : 1'h0;
assign data_reg = _066_;
assign mode_select_zw = _070_;
assign write_adress_counter = _073_;
assign read_adress_counter = _076_;
assign currstate = _077_;
assign sclk = clk;
assign mosi = _080_;
assign data_out = _083_;
assign data_valid = _086_;
endmodule
module tt_um_cejmu_riscv(clk, ena, rst_n, ui_in, uio_in, uo_out, uio_out, uio_oe);
wire _0_;
wire _1_;
wire [31:0] _2_;
wire [13:0] _3_;
wire _4_;
wire _5_;
wire [12:0] _6_;
wire _7_;
wire _8_;
wire [31:0] _9_;
input clk;
wire clk;
wire [13:0] cpu_addr_out;
wire data_valid;
input ena;
wire ena;
wire mem_req;
wire reset;
input rst_n;
wire rst_n;
wire [15:0] spi_addr_in;
wire [31:0] spi_data_in;
wire [31:0] spi_data_out;
input [7:0] ui_in;
wire [7:0] ui_in;
input [7:0] uio_in;
wire [7:0] uio_in;
output [7:0] uio_oe;
wire [7:0] uio_oe;
output [7:0] uio_out;
wire [7:0] uio_out;
output [7:0] uo_out;
wire [7:0] uo_out;
wire write_enable;
wire [12:0] x1;
assign _0_ = ~ rst_n;
cpu cpu_inst (
.addr_out(_3_),
.clk(clk),
.data_in(spi_data_out),
.data_out(_2_),
.data_valid(data_valid),
.mem_req(_5_),
.reset(reset),
.write_en(_4_),
.x1(_6_)
);
spi_master spi_master_inst (
.addr(spi_addr_in),
.clk(clk),
.cs(mem_req),
.data_in(spi_data_in),
.data_out(_9_),
.data_valid(_1_),
.miso(ui_in[0]),
.mode_select(write_enable),
.mosi(_8_),
.reset(reset),
.sclk(_7_)
);
assign write_enable = _4_;
assign cpu_addr_out = _3_;
assign spi_addr_in = { 2'h0, cpu_addr_out };
assign spi_data_out = _9_;
assign spi_data_in = _2_;
assign mem_req = _5_;
assign data_valid = _1_;
assign reset = _0_;
assign x1 = _6_;
assign uo_out = { x1[4:0], mem_req, _7_, _8_ };
assign uio_out = x1[12:5];
assign uio_oe = 8'hff;
endmodule
|
module alu(clk, reset, a, b, instruction, rd);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire [31:0] _15_;
wire _16_;
wire _17_;
wire _18_;
wire _19_;
wire _20_;
wire [31:0] _21_;
wire _22_;
wire _23_;
wire _24_;
wire _25_;
wire _26_;
wire [31:0] _27_;
wire _28_;
wire _29_;
wire _30_;
wire _31_;
wire _32_;
wire _33_;
wire [1:0] _34_;
wire [31:0] _35_;
wire [31:0] _36_;
wire [31:0] _37_;
wire [31:0] _38_;
wire [31:0] _39_;
wire [31:0] _40_;
wire [31:0] _41_;
reg [31:0] _42_;
input [31:0] a;
wire [31:0] a;
input [31:0] b;
wire [31:0] b;
input clk;
wire clk;
input [16:0] instruction;
wire [16:0] instruction;
output [31:0] rd;
wire [31:0] rd;
input reset;
wire reset;
assign _00_ = instruction[16:10] == 7'h00;
assign _01_ = instruction[9:7] == 3'h0;
assign _02_ = _01_ & _00_;
assign _03_ = instruction[6:0] == 7'h33;
assign _04_ = _03_ & _02_;
assign _05_ = instruction[9:7] == 3'h0;
assign _06_ = instruction[6:0] == 7'h13;
assign _07_ = _06_ & _05_;
assign _08_ = _04_ | _07_;
assign _09_ = instruction[6:0] == 7'h23;
assign _10_ = instruction[6:0] == 7'h03;
assign _11_ = _09_ | _10_;
assign _12_ = instruction[9:7] == 3'h2;
assign _13_ = _12_ & _11_;
assign _14_ = _08_ | _13_;
assign _15_ = a + b;
assign _16_ = instruction[16:10] == 7'h00;
assign _17_ = instruction[9:7] == 3'h7;
assign _18_ = _17_ & _16_;
assign _19_ = instruction[6:0] == 7'h33;
assign _20_ = _19_ & _18_;
assign _21_ = a & b;
assign _22_ = instruction[16:10] == 7'h00;
assign _23_ = instruction[9:7] == 3'h4;
assign _24_ = _23_ & _22_;
assign _25_ = instruction[6:0] == 7'h33;
assign _26_ = _25_ & _24_;
assign _27_ = a ^ b;
assign _28_ = instruction[6:0] == 7'h6f;
assign _29_ = instruction[6:0] == 7'h67;
assign _30_ = instruction[6:0] == 7'h63;
assign _31_ = instruction[9:7] == 3'h1;
assign _32_ = _31_ & _30_;
assign _33_ = a == b;
assign _34_ = _33_ ? 2'h2 : 2'h0;
assign _35_ = _32_ ? { 14'h0000, _34_, 16'h0000 } : 32'd0;
assign _36_ = _29_ ? 32'd65536 : _35_;
assign _37_ = _28_ ? 32'd0 : _36_;
assign _38_ = _26_ ? _27_ : _37_;
assign _39_ = _20_ ? _21_ : _38_;
assign _40_ = _14_ ? _15_ : _39_;
assign _41_ = reset ? 32'd0 : _40_;
always @(posedge clk)
_42_ <= _41_;
assign rd = _42_;
endmodule
|
tt06-finale_0002
|
tt06-finale
|
CEJMU-tt06_tinyrv1
|
task_control
|
tt_um_cejmu_riscv
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/* Generated by Yosys 0.39+165 (git sha1 22c5ab90d, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */
module alu(clk, reset, a, b, instruction, rd);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire [31:0] _15_;
wire _16_;
wire _17_;
wire _18_;
wire _19_;
wire _20_;
wire [31:0] _21_;
wire _22_;
wire _23_;
wire _24_;
wire _25_;
wire _26_;
wire [31:0] _27_;
wire _28_;
wire _29_;
wire _30_;
wire _31_;
wire _32_;
wire _33_;
wire [1:0] _34_;
wire [31:0] _35_;
wire [31:0] _36_;
wire [31:0] _37_;
wire [31:0] _38_;
wire [31:0] _39_;
wire [31:0] _40_;
wire [31:0] _41_;
reg [31:0] _42_;
input [31:0] a;
wire [31:0] a;
input [31:0] b;
wire [31:0] b;
input clk;
wire clk;
input [16:0] instruction;
wire [16:0] instruction;
output [31:0] rd;
wire [31:0] rd;
input reset;
wire reset;
assign _00_ = instruction[16:10] == 7'h00;
assign _01_ = instruction[9:7] == 3'h0;
assign _02_ = _01_ & _00_;
assign _03_ = instruction[6:0] == 7'h33;
assign _04_ = _03_ & _02_;
assign _05_ = instruction[9:7] == 3'h0;
assign _06_ = instruction[6:0] == 7'h13;
assign _07_ = _06_ & _05_;
assign _08_ = _04_ | _07_;
assign _09_ = instruction[6:0] == 7'h23;
assign _10_ = instruction[6:0] == 7'h03;
assign _11_ = _09_ | _10_;
assign _12_ = instruction[9:7] == 3'h2;
assign _13_ = _12_ & _11_;
assign _14_ = _08_ | _13_;
assign _15_ = a + b;
assign _16_ = instruction[16:10] == 7'h00;
assign _17_ = instruction[9:7] == 3'h7;
assign _18_ = _17_ & _16_;
assign _19_ = instruction[6:0] == 7'h33;
assign _20_ = _19_ & _18_;
assign _21_ = a & b;
assign _22_ = instruction[16:10] == 7'h00;
assign _23_ = instruction[9:7] == 3'h4;
assign _24_ = _23_ & _22_;
assign _25_ = instruction[6:0] == 7'h33;
assign _26_ = _25_ & _24_;
assign _27_ = a ^ b;
assign _28_ = instruction[6:0] == 7'h6f;
assign _29_ = instruction[6:0] == 7'h67;
assign _30_ = instruction[6:0] == 7'h63;
assign _31_ = instruction[9:7] == 3'h1;
assign _32_ = _31_ & _30_;
assign _33_ = a == b;
assign _34_ = _33_ ? 2'h2 : 2'h0;
assign _35_ = _32_ ? { 14'h0000, _34_, 16'h0000 } : 32'd0;
assign _36_ = _29_ ? 32'd65536 : _35_;
assign _37_ = _28_ ? 32'd0 : _36_;
assign _38_ = _26_ ? _27_ : _37_;
assign _39_ = _20_ ? _21_ : _38_;
assign _40_ = _14_ ? _15_ : _39_;
assign _41_ = reset ? 32'd0 : _40_;
always @(posedge clk)
_42_ <= _41_;
assign rd = _42_;
endmodule
module control(clk, reset, iword, data_valid, imm, control_flags_out, wbflag, memflag, pcflag, fetchflag, mem_req);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module cpu(clk, reset, data_in, data_valid, data_out, addr_out, write_en, mem_req, x1);
wire [31:0] _00_;
wire [31:0] _01_;
wire [12:0] _02_;
wire [31:0] _03_;
wire [31:0] _04_;
wire [6:0] _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire [31:0] _11_;
wire [31:0] _12_;
wire [31:0] _13_;
wire _14_;
wire _15_;
wire [15:0] _16_;
wire [15:0] _17_;
wire [15:0] _18_;
wire [13:0] _19_;
wire [31:0] _20_;
reg [31:0] _21_;
output [13:0] addr_out;
wire [13:0] addr_out;
wire [31:0] b;
input clk;
wire clk;
wire [6:0] control_flags_out;
input [31:0] data_in;
wire [31:0] data_in;
output [31:0] data_out;
wire [31:0] data_out;
input data_valid;
wire data_valid;
wire fetchflag;
wire [31:0] imm;
wire [16:0] instruction;
wire [31:0] iword_reg;
output mem_req;
wire mem_req;
wire memflag;
wire [15:0] pc_inc;
wire [15:0] pc_offset;
wire [15:0] pc_out;
wire pcflag;
wire [31:0] rd;
wire [31:0] rdalu;
input reset;
wire reset;
wire [31:0] rs1;
wire [31:0] rs2;
wire s0;
wire s1;
wire wbflag;
output write_en;
wire write_en;
output [12:0] x1;
wire [12:0] x1;
assign _11_ = control_flags_out[3] ? imm : rs2;
assign _12_ = control_flags_out[4] ? { 16'h0000, pc_inc } : _13_;
assign _13_ = control_flags_out[0] ? data_in : rdalu;
assign _14_ = control_flags_out[4] ? rdalu[16] : 1'h0;
assign _15_ = control_flags_out[4] ? rdalu[17] : 1'h1;
assign _18_ = control_flags_out[6] ? rs1[15:0] : imm[15:0];
assign _19_ = control_flags_out[5] ? pc_out[15:2] : rdalu[13:0];
assign _20_ = fetchflag ? data_in : iword_reg;
always @(posedge clk, posedge reset)
if (reset) _21_ <= 32'd0;
else _21_ <= _20_;
alu alu_inst (
.a(rs1),
.b(b),
.clk(clk),
.instruction(instruction),
.rd(_03_),
.reset(reset)
);
control control_inst (
.clk(clk),
.control_flags_out(_05_),
.data_valid(data_valid),
.fetchflag(_09_),
.imm(_04_),
.iword(iword_reg),
.mem_req(_10_),
.memflag(_07_),
.pcflag(_08_),
.reset(reset),
.wbflag(_06_)
);
instructioncounter instruction_inst (
.clk(clk),
.pc_inc(_16_),
.pc_new(_17_),
.pc_offset(pc_offset),
.pcflag(pcflag),
.reset(reset),
.s0(s0),
.s1(s1)
);
regs regs_inst (
.clk(clk),
.rd(rd),
.rdadr(iword_reg[11:7]),
.regwrite(wbflag),
.reset(reset),
.rs1(_00_),
.rs1adr(iword_reg[19:15]),
.rs2(_01_),
.rs2adr(iword_reg[24:20]),
.x1(_02_)
);
assign s0 = _14_;
assign s1 = _15_;
assign imm = _04_;
assign control_flags_out = _05_;
assign rs1 = _00_;
assign rs2 = _01_;
assign b = _11_;
assign rdalu = _03_;
assign rd = _12_;
assign wbflag = _06_;
assign memflag = _07_;
assign pcflag = _08_;
assign fetchflag = _09_;
assign instruction = { iword_reg[31:25], iword_reg[14:12], iword_reg[6:0] };
assign iword_reg = _21_;
assign pc_inc = _16_;
assign pc_out = _17_;
assign pc_offset = _18_;
assign data_out = rs2;
assign addr_out = _19_;
assign write_en = memflag;
assign mem_req = _10_;
assign x1 = _02_;
endmodule
module instructioncounter(clk, reset, pcflag, s0, s1, pc_offset, pc_inc, pc_new);
wire [15:0] _00_;
wire [15:0] _01_;
wire _02_;
wire [15:0] _03_;
wire _04_;
wire _05_;
wire [15:0] _06_;
wire [15:0] _07_;
wire [15:0] _08_;
reg [15:0] _09_ = 16'h0000;
reg [15:0] _10_;
input clk;
wire clk;
output [15:0] pc_inc;
wire [15:0] pc_inc;
output [15:0] pc_new;
wire [15:0] pc_new;
input [15:0] pc_offset;
wire [15:0] pc_offset;
input pcflag;
wire pcflag;
wire [15:0] \reg ;
input reset;
wire reset;
input s0;
wire s0;
input s1;
wire s1;
wire [1:0] s1s0;
assign _00_ = \reg + 16'h0004;
assign _01_ = pc_offset + \reg ;
assign _02_ = s1s0 == 2'h0;
assign _03_ = \reg + 16'h0004;
assign _04_ = s1s0 == 2'h2;
assign _05_ = s1s0 == 2'h1;
function [15:0] \1383 ;
input [15:0] a;
input [47:0] b;
input [2:0] s;
(* parallel_case *)
casez (s)
3'b??1:
\1383 = b[15:0];
3'b?1?:
\1383 = b[31:16];
3'b1??:
\1383 = b[47:32];
default:
\1383 = a;
endcase
endfunction
assign _06_ = \1383 (16'h0000, { pc_offset, _03_, _01_ }, { _05_, _04_, _02_ });
assign _07_ = pcflag ? _06_ : \reg ;
assign _08_ = reset ? 16'h0000 : _07_;
always @(posedge clk)
_09_ <= _08_;
always @(posedge clk)
_10_ <= _00_;
assign s1s0 = { s1, s0 };
assign \reg = _09_;
assign pc_inc = _10_;
assign pc_new = \reg ;
endmodule
module regs(clk, reset, rs1adr, rs2adr, rdadr, rd, regwrite, rs1, rs2, x1);
wire [31:0] _000_;
wire [31:0] _001_;
wire [31:0] _002_;
wire [31:0] _003_;
wire [31:0] _004_;
wire [31:0] _005_;
wire [31:0] _006_;
wire [31:0] _007_;
wire [31:0] _008_;
wire [31:0] _009_;
wire [31:0] _010_;
wire [31:0] _011_;
wire [31:0] _012_;
wire [31:0] _013_;
wire [31:0] _014_;
wire [31:0] _015_;
wire [31:0] _016_;
wire [31:0] _017_;
wire [31:0] _018_;
wire [31:0] _019_;
wire [31:0] _020_;
wire [31:0] _021_;
wire [31:0] _022_;
wire [31:0] _023_;
wire [31:0] _024_;
wire [31:0] _025_;
wire [31:0] _026_;
wire [31:0] _027_;
wire [31:0] _028_;
wire [31:0] _029_;
wire [31:0] _030_;
wire [31:0] _031_;
wire [31:0] _032_;
wire [31:0] _033_;
wire [31:0] _034_;
wire [31:0] _035_;
wire [31:0] _036_;
wire [31:0] _037_;
wire [31:0] _038_;
wire [31:0] _039_;
wire _040_;
wire _041_;
wire [4:0] _042_;
wire [4:0] _043_;
wire [4:0] _044_;
wire [1023:0] _045_;
reg [1023:0] _046_;
reg [31:0] _047_;
reg [31:0] _048_;
wire _049_;
wire [12:0] _050_;
reg [12:0] _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire [31:0] _117_;
wire [31:0] _118_;
wire [31:0] _119_;
wire [31:0] _120_;
wire [31:0] _121_;
wire [31:0] _122_;
wire [31:0] _123_;
wire [31:0] _124_;
wire [31:0] _125_;
wire [31:0] _126_;
wire [31:0] _127_;
wire [31:0] _128_;
wire [31:0] _129_;
wire [31:0] _130_;
wire [31:0] _131_;
wire [31:0] _132_;
wire [31:0] _133_;
wire [31:0] _134_;
wire [31:0] _135_;
wire [31:0] _136_;
wire [31:0] _137_;
wire [31:0] _138_;
wire [31:0] _139_;
wire [31:0] _140_;
wire [31:0] _141_;
wire [31:0] _142_;
wire [31:0] _143_;
wire [31:0] _144_;
wire [31:0] _145_;
wire [31:0] _146_;
wire [31:0] _147_;
wire [31:0] _148_;
wire [31:0] _149_;
wire [31:0] _150_;
wire [31:0] _151_;
wire [31:0] _152_;
wire [31:0] _153_;
wire [31:0] _154_;
wire [31:0] _155_;
wire [31:0] _156_;
wire [31:0] _157_;
wire [31:0] _158_;
wire [31:0] _159_;
wire [31:0] _160_;
wire [31:0] _161_;
wire [31:0] _162_;
wire [31:0] _163_;
wire [31:0] _164_;
wire [31:0] _165_;
wire [31:0] _166_;
wire [31:0] _167_;
wire [31:0] _168_;
wire [31:0] _169_;
wire [31:0] _170_;
input clk;
wire clk;
input [31:0] rd;
wire [31:0] rd;
input [4:0] rdadr;
wire [4:0] rdadr;
wire [1023:0] registers;
input regwrite;
wire regwrite;
input reset;
wire reset;
output [31:0] rs1;
wire [31:0] rs1;
input [4:0] rs1adr;
wire [4:0] rs1adr;
output [31:0] rs2;
wire [31:0] rs2;
input [4:0] rs2adr;
wire [4:0] rs2adr;
output [12:0] x1;
wire [12:0] x1;
assign _000_ = _043_[0] ? registers[63:32] : registers[31:0];
assign _001_ = _043_[0] ? registers[191:160] : registers[159:128];
assign _002_ = _043_[0] ? registers[319:288] : registers[287:256];
assign _003_ = _043_[0] ? registers[447:416] : registers[415:384];
assign _004_ = _043_[0] ? registers[575:544] : registers[543:512];
assign _005_ = _043_[0] ? registers[703:672] : registers[671:640];
assign _006_ = _043_[0] ? registers[831:800] : registers[799:768];
assign _007_ = _043_[0] ? registers[959:928] : registers[927:896];
assign _008_ = _043_[2] ? _150_ : _149_;
assign _009_ = _043_[2] ? _154_ : _153_;
assign _010_ = _044_[0] ? registers[63:32] : registers[31:0];
assign _011_ = _044_[0] ? registers[191:160] : registers[159:128];
assign _012_ = _044_[0] ? registers[319:288] : registers[287:256];
assign _013_ = _044_[0] ? registers[447:416] : registers[415:384];
assign _014_ = _044_[0] ? registers[575:544] : registers[543:512];
assign _015_ = _044_[0] ? registers[703:672] : registers[671:640];
assign _016_ = _044_[0] ? registers[831:800] : registers[799:768];
assign _017_ = _044_[0] ? registers[959:928] : registers[927:896];
assign _018_ = _044_[2] ? _161_ : _160_;
assign _019_ = _044_[2] ? _165_ : _164_;
assign _020_ = _043_[0] ? registers[127:96] : registers[95:64];
assign _021_ = _043_[0] ? registers[255:224] : registers[223:192];
assign _022_ = _043_[0] ? registers[383:352] : registers[351:320];
assign _023_ = _043_[0] ? registers[511:480] : registers[479:448];
assign _024_ = _043_[0] ? registers[639:608] : registers[607:576];
assign _025_ = _043_[0] ? registers[767:736] : registers[735:704];
assign _026_ = _043_[0] ? registers[895:864] : registers[863:832];
assign _027_ = _043_[0] ? registers[1023:992] : registers[991:960];
assign _028_ = _043_[2] ? _152_ : _151_;
assign _029_ = _043_[2] ? _156_ : _155_;
assign _030_ = _044_[0] ? registers[127:96] : registers[95:64];
assign _031_ = _044_[0] ? registers[255:224] : registers[223:192];
assign _032_ = _044_[0] ? registers[383:352] : registers[351:320];
assign _033_ = _044_[0] ? registers[511:480] : registers[479:448];
assign _034_ = _044_[0] ? registers[639:608] : registers[607:576];
assign _035_ = _044_[0] ? registers[767:736] : registers[735:704];
assign _036_ = _044_[0] ? registers[895:864] : registers[863:832];
assign _037_ = _044_[0] ? registers[1023:992] : registers[991:960];
assign _038_ = _044_[2] ? _163_ : _162_;
assign _039_ = _044_[2] ? _167_ : _166_;
assign _149_ = _043_[1] ? _020_ : _000_;
assign _150_ = _043_[1] ? _021_ : _001_;
assign _151_ = _043_[1] ? _022_ : _002_;
assign _152_ = _043_[1] ? _023_ : _003_;
assign _153_ = _043_[1] ? _024_ : _004_;
assign _154_ = _043_[1] ? _025_ : _005_;
assign _155_ = _043_[1] ? _026_ : _006_;
assign _156_ = _043_[1] ? _027_ : _007_;
assign _157_ = _043_[3] ? _028_ : _008_;
assign _158_ = _043_[3] ? _029_ : _009_;
assign _160_ = _044_[1] ? _030_ : _010_;
assign _161_ = _044_[1] ? _031_ : _011_;
assign _162_ = _044_[1] ? _032_ : _012_;
assign _163_ = _044_[1] ? _033_ : _013_;
assign _164_ = _044_[1] ? _034_ : _014_;
assign _165_ = _044_[1] ? _035_ : _015_;
assign _166_ = _044_[1] ? _036_ : _016_;
assign _167_ = _044_[1] ? _037_ : _017_;
assign _168_ = _044_[3] ? _038_ : _018_;
assign _169_ = _044_[3] ? _039_ : _019_;
assign _170_ = _044_[4] ? _169_ : _168_;
assign _040_ = rdadr != 5'h00;
assign _041_ = _040_ & regwrite;
assign _042_ = 5'h1f - rdadr;
assign _043_ = 5'h1f - rs1adr;
assign _044_ = 5'h1f - rs2adr;
assign _045_ = _041_ ? { _148_, _147_, _146_, _145_, _144_, _143_, _142_, _141_, _140_, _139_, _138_, _137_, _136_, _135_, _134_, _133_, _132_, _131_, _130_, _129_, _128_, _127_, _126_, _125_, _124_, _123_, _122_, _121_, _120_, _119_, _118_, _117_ } : registers;
always @(posedge clk, posedge reset)
if (reset) _046_ <= 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
else _046_ <= _045_;
always @(posedge clk, posedge reset)
if (reset) _047_ <= 32'd0;
else _047_ <= _159_;
always @(posedge clk, posedge reset)
if (reset) _048_ <= 32'd0;
else _048_ <= _170_;
assign _049_ = ~ reset;
assign _050_ = _049_ ? registers[972:960] : _051_;
always @(posedge clk)
_051_ <= _050_;
assign _052_ = ~ _042_[4];
assign _053_ = ~ _042_[3];
assign _054_ = _052_ & _053_;
assign _055_ = _052_ & _042_[3];
assign _056_ = _042_[4] & _053_;
assign _057_ = _042_[4] & _042_[3];
assign _058_ = ~ _042_[2];
assign _059_ = _054_ & _058_;
assign _060_ = _054_ & _042_[2];
assign _061_ = _055_ & _058_;
assign _062_ = _055_ & _042_[2];
assign _063_ = _056_ & _058_;
assign _064_ = _056_ & _042_[2];
assign _065_ = _057_ & _058_;
assign _066_ = _057_ & _042_[2];
assign _067_ = ~ _042_[1];
assign _068_ = _059_ & _067_;
assign _069_ = _059_ & _042_[1];
assign _070_ = _060_ & _067_;
assign _071_ = _060_ & _042_[1];
assign _072_ = _061_ & _067_;
assign _073_ = _061_ & _042_[1];
assign _074_ = _062_ & _067_;
assign _075_ = _062_ & _042_[1];
assign _076_ = _063_ & _067_;
assign _077_ = _063_ & _042_[1];
assign _078_ = _064_ & _067_;
assign _079_ = _064_ & _042_[1];
assign _080_ = _065_ & _067_;
assign _081_ = _065_ & _042_[1];
assign _082_ = _066_ & _067_;
assign _083_ = _066_ & _042_[1];
assign _084_ = ~ _042_[0];
assign _085_ = _068_ & _084_;
assign _086_ = _068_ & _042_[0];
assign _087_ = _069_ & _084_;
assign _088_ = _069_ & _042_[0];
assign _089_ = _070_ & _084_;
assign _090_ = _070_ & _042_[0];
assign _091_ = _071_ & _084_;
assign _092_ = _071_ & _042_[0];
assign _093_ = _072_ & _084_;
assign _094_ = _072_ & _042_[0];
assign _095_ = _073_ & _084_;
assign _096_ = _073_ & _042_[0];
assign _097_ = _074_ & _084_;
assign _098_ = _074_ & _042_[0];
assign _099_ = _075_ & _084_;
assign _100_ = _075_ & _042_[0];
assign _101_ = _076_ & _084_;
assign _102_ = _076_ & _042_[0];
assign _103_ = _077_ & _084_;
assign _104_ = _077_ & _042_[0];
assign _105_ = _078_ & _084_;
assign _106_ = _078_ & _042_[0];
assign _107_ = _079_ & _084_;
assign _108_ = _079_ & _042_[0];
assign _109_ = _080_ & _084_;
assign _110_ = _080_ & _042_[0];
assign _111_ = _081_ & _084_;
assign _112_ = _081_ & _042_[0];
assign _113_ = _082_ & _084_;
assign _114_ = _082_ & _042_[0];
assign _115_ = _083_ & _084_;
assign _116_ = _083_ & _042_[0];
assign _117_ = _085_ ? rd : registers[31:0];
assign _118_ = _086_ ? rd : registers[63:32];
assign _119_ = _087_ ? rd : registers[95:64];
assign _120_ = _088_ ? rd : registers[127:96];
assign _121_ = _089_ ? rd : registers[159:128];
assign _122_ = _090_ ? rd : registers[191:160];
assign _123_ = _091_ ? rd : registers[223:192];
assign _124_ = _092_ ? rd : registers[255:224];
assign _125_ = _093_ ? rd : registers[287:256];
assign _126_ = _094_ ? rd : registers[319:288];
assign _127_ = _095_ ? rd : registers[351:320];
assign _128_ = _096_ ? rd : registers[383:352];
assign _129_ = _097_ ? rd : registers[415:384];
assign _130_ = _098_ ? rd : registers[447:416];
assign _131_ = _099_ ? rd : registers[479:448];
assign _132_ = _100_ ? rd : registers[511:480];
assign _133_ = _101_ ? rd : registers[543:512];
assign _134_ = _102_ ? rd : registers[575:544];
assign _135_ = _103_ ? rd : registers[607:576];
assign _136_ = _104_ ? rd : registers[639:608];
assign _137_ = _105_ ? rd : registers[671:640];
assign _138_ = _106_ ? rd : registers[703:672];
assign _139_ = _107_ ? rd : registers[735:704];
assign _140_ = _108_ ? rd : registers[767:736];
assign _141_ = _109_ ? rd : registers[799:768];
assign _142_ = _110_ ? rd : registers[831:800];
assign _143_ = _111_ ? rd : registers[863:832];
assign _144_ = _112_ ? rd : registers[895:864];
assign _145_ = _113_ ? rd : registers[927:896];
assign _146_ = _114_ ? rd : registers[959:928];
assign _147_ = _115_ ? rd : registers[991:960];
assign _148_ = _116_ ? rd : registers[1023:992];
assign _159_ = _043_[4] ? _158_ : _157_;
assign registers = _046_;
assign rs1 = _047_;
assign rs2 = _048_;
assign x1 = _051_;
endmodule
module spi_master(clk, mode_select, reset, miso, cs, data_in, addr, sclk, mosi, data_out, data_valid);
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire [31:0] _060_;
wire [31:0] _061_;
wire [31:0] _062_;
wire [2:0] _063_;
wire _064_;
wire [31:0] _065_;
reg [31:0] _066_;
wire _067_;
wire _068_;
wire _069_;
reg _070_;
wire _071_;
wire [31:0] _072_;
reg [31:0] _073_ = 32'd16;
wire _074_;
wire [31:0] _075_;
reg [31:0] _076_ = 32'd33;
reg [2:0] _077_;
wire _078_;
wire _079_;
reg _080_;
wire _081_;
wire [31:0] _082_;
reg [31:0] _083_;
wire _084_;
wire _085_;
reg _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
wire _203_;
wire _204_;
wire _205_;
wire _206_;
wire _207_;
wire _208_;
wire _209_;
wire _210_;
wire _211_;
wire _212_;
wire _213_;
wire _214_;
wire _215_;
wire _216_;
wire _217_;
wire _218_;
wire _219_;
wire _220_;
wire _221_;
wire _222_;
wire _223_;
wire _224_;
wire _225_;
wire _226_;
wire _227_;
wire _228_;
wire _229_;
wire _230_;
wire _231_;
wire _232_;
wire _233_;
wire _234_;
wire _235_;
wire _236_;
wire _237_;
wire _238_;
wire _239_;
wire _240_;
wire _241_;
wire _242_;
wire _243_;
wire _244_;
wire _245_;
wire _246_;
wire _247_;
wire _248_;
wire _249_;
wire _250_;
wire _251_;
wire _252_;
wire _253_;
wire _254_;
wire _255_;
wire _256_;
wire _257_;
wire _258_;
wire _259_;
wire _260_;
wire _261_;
wire _262_;
wire _263_;
wire _264_;
wire _265_;
wire _266_;
wire _267_;
wire _268_;
wire _269_;
wire _270_;
wire _271_;
wire _272_;
wire _273_;
wire _274_;
wire _275_;
wire _276_;
wire _277_;
wire _278_;
wire _279_;
wire _280_;
wire _281_;
wire _282_;
wire _283_;
wire _284_;
wire _285_;
wire _286_;
wire _287_;
wire _288_;
wire _289_;
wire _290_;
wire _291_;
wire _292_;
wire _293_;
wire _294_;
wire _295_;
wire _296_;
wire _297_;
wire _298_;
wire _299_;
wire _300_;
wire _301_;
wire _302_;
wire _303_;
wire _304_;
wire _305_;
wire _306_;
wire _307_;
wire _308_;
wire _309_;
wire _310_;
wire _311_;
wire _312_;
wire _313_;
wire _314_;
wire _315_;
wire [2:0] _316_;
wire _317_;
wire _318_;
wire [31:0] _319_;
wire _320_;
wire _321_;
wire _322_;
wire [31:0] _323_;
wire _324_;
wire [2:0] _325_;
wire [2:0] _326_;
wire _327_;
wire [31:0] _328_;
wire [2:0] _329_;
wire _330_;
wire [31:0] _331_;
wire [2:0] _332_;
wire _333_;
wire _334_;
wire [31:0] _335_;
wire _336_;
wire [31:0] _337_;
wire [31:0] _338_;
wire [31:0] _339_;
wire [2:0] _340_;
wire [31:0] _341_;
wire [31:0] _342_;
wire [2:0] _343_;
wire _344_;
wire _345_;
wire [31:0] _346_;
wire _347_;
wire [31:0] _348_;
wire _349_;
wire [31:0] _350_;
wire [2:0] _351_;
wire _352_;
wire [31:0] _353_;
wire [2:0] _354_;
wire _355_;
wire [31:0] _356_;
wire _357_;
wire [2:0] _358_;
wire _359_;
wire [31:0] _360_;
wire _361_;
wire [31:0] _362_;
wire [2:0] _363_;
wire _364_;
wire [31:0] _365_;
wire _366_;
wire [31:0] _367_;
wire [31:0] _368_;
wire [2:0] _369_;
wire _370_;
wire [31:0] _371_;
wire _372_;
wire [31:0] _373_;
wire [31:0] _374_;
wire [31:0] _375_;
wire [2:0] _376_;
wire _377_;
wire [31:0] _378_;
wire _379_;
input [15:0] addr;
wire [15:0] addr;
input clk;
wire clk;
input cs;
wire cs;
wire [2:0] currstate;
input [31:0] data_in;
wire [31:0] data_in;
output [31:0] data_out;
wire [31:0] data_out;
wire [31:0] data_reg;
output data_valid;
wire data_valid;
input miso;
wire miso;
input mode_select;
wire mode_select;
wire mode_select_zw;
output mosi;
wire mosi;
wire [31:0] read_adress_counter;
input reset;
wire reset;
output sclk;
wire sclk;
wire [31:0] write_adress_counter;
assign _000_ = write_adress_counter[0] ? addr[1] : addr[0];
assign _001_ = write_adress_counter[0] ? addr[5] : addr[4];
assign _002_ = write_adress_counter[0] ? addr[9] : addr[8];
assign _003_ = write_adress_counter[0] ? addr[13] : addr[12];
assign _004_ = write_adress_counter[2] ? _088_ : _087_;
assign _005_ = write_adress_counter[0] ? addr[1] : addr[0];
assign _006_ = write_adress_counter[0] ? addr[5] : addr[4];
assign _007_ = write_adress_counter[0] ? addr[9] : addr[8];
assign _008_ = write_adress_counter[0] ? addr[13] : addr[12];
assign _009_ = write_adress_counter[2] ? _093_ : _092_;
assign _010_ = read_adress_counter[0] ? data_in[1] : data_in[0];
assign _011_ = read_adress_counter[0] ? data_in[5] : data_in[4];
assign _012_ = read_adress_counter[0] ? data_in[9] : data_in[8];
assign _013_ = read_adress_counter[0] ? data_in[13] : data_in[12];
assign _014_ = read_adress_counter[0] ? data_in[17] : data_in[16];
assign _015_ = read_adress_counter[0] ? data_in[21] : data_in[20];
assign _016_ = read_adress_counter[0] ? data_in[25] : data_in[24];
assign _017_ = read_adress_counter[0] ? data_in[29] : data_in[28];
assign _018_ = read_adress_counter[2] ? _293_ : _292_;
assign _019_ = read_adress_counter[2] ? _297_ : _296_;
assign _020_ = read_adress_counter[0] ? data_in[1] : data_in[0];
assign _021_ = read_adress_counter[0] ? data_in[5] : data_in[4];
assign _022_ = read_adress_counter[0] ? data_in[9] : data_in[8];
assign _023_ = read_adress_counter[0] ? data_in[13] : data_in[12];
assign _024_ = read_adress_counter[0] ? data_in[17] : data_in[16];
assign _025_ = read_adress_counter[0] ? data_in[21] : data_in[20];
assign _026_ = read_adress_counter[0] ? data_in[25] : data_in[24];
assign _027_ = read_adress_counter[0] ? data_in[29] : data_in[28];
assign _028_ = read_adress_counter[2] ? _305_ : _304_;
assign _029_ = read_adress_counter[2] ? _309_ : _308_;
assign _030_ = write_adress_counter[0] ? addr[3] : addr[2];
assign _031_ = write_adress_counter[0] ? addr[7] : addr[6];
assign _032_ = write_adress_counter[0] ? addr[11] : addr[10];
assign _033_ = write_adress_counter[0] ? addr[15] : addr[14];
assign _034_ = write_adress_counter[2] ? _090_ : _089_;
assign _035_ = write_adress_counter[0] ? addr[3] : addr[2];
assign _036_ = write_adress_counter[0] ? addr[7] : addr[6];
assign _037_ = write_adress_counter[0] ? addr[11] : addr[10];
assign _038_ = write_adress_counter[0] ? addr[15] : addr[14];
assign _039_ = write_adress_counter[2] ? _095_ : _094_;
assign _040_ = read_adress_counter[0] ? data_in[3] : data_in[2];
assign _041_ = read_adress_counter[0] ? data_in[7] : data_in[6];
assign _042_ = read_adress_counter[0] ? data_in[11] : data_in[10];
assign _043_ = read_adress_counter[0] ? data_in[15] : data_in[14];
assign _044_ = read_adress_counter[0] ? data_in[19] : data_in[18];
assign _045_ = read_adress_counter[0] ? data_in[23] : data_in[22];
assign _046_ = read_adress_counter[0] ? data_in[27] : data_in[26];
assign _047_ = read_adress_counter[0] ? data_in[31] : data_in[30];
assign _048_ = read_adress_counter[2] ? _295_ : _294_;
assign _049_ = read_adress_counter[2] ? _299_ : _298_;
assign _050_ = read_adress_counter[0] ? data_in[3] : data_in[2];
assign _051_ = read_adress_counter[0] ? data_in[7] : data_in[6];
assign _052_ = read_adress_counter[0] ? data_in[11] : data_in[10];
assign _053_ = read_adress_counter[0] ? data_in[15] : data_in[14];
assign _054_ = read_adress_counter[0] ? data_in[19] : data_in[18];
assign _055_ = read_adress_counter[0] ? data_in[23] : data_in[22];
assign _056_ = read_adress_counter[0] ? data_in[27] : data_in[26];
assign _057_ = read_adress_counter[0] ? data_in[31] : data_in[30];
assign _058_ = read_adress_counter[2] ? _307_ : _306_;
assign _059_ = read_adress_counter[2] ? _311_ : _310_;
assign _087_ = write_adress_counter[1] ? _030_ : _000_;
assign _088_ = write_adress_counter[1] ? _031_ : _001_;
assign _089_ = write_adress_counter[1] ? _032_ : _002_;
assign _090_ = write_adress_counter[1] ? _033_ : _003_;
assign _091_ = write_adress_counter[3] ? _034_ : _004_;
assign _092_ = write_adress_counter[1] ? _035_ : _005_;
assign _093_ = write_adress_counter[1] ? _036_ : _006_;
assign _094_ = write_adress_counter[1] ? _037_ : _007_;
assign _095_ = write_adress_counter[1] ? _038_ : _008_;
assign _096_ = write_adress_counter[3] ? _039_ : _009_;
assign _292_ = read_adress_counter[1] ? _040_ : _010_;
assign _293_ = read_adress_counter[1] ? _041_ : _011_;
assign _294_ = read_adress_counter[1] ? _042_ : _012_;
assign _295_ = read_adress_counter[1] ? _043_ : _013_;
assign _296_ = read_adress_counter[1] ? _044_ : _014_;
assign _297_ = read_adress_counter[1] ? _045_ : _015_;
assign _298_ = read_adress_counter[1] ? _046_ : _016_;
assign _299_ = read_adress_counter[1] ? _047_ : _017_;
assign _300_ = read_adress_counter[3] ? _048_ : _018_;
assign _302_ = read_adress_counter[3] ? _049_ : _019_;
assign _304_ = read_adress_counter[1] ? _050_ : _020_;
assign _305_ = read_adress_counter[1] ? _051_ : _021_;
assign _306_ = read_adress_counter[1] ? _052_ : _022_;
assign _307_ = read_adress_counter[1] ? _053_ : _023_;
assign _308_ = read_adress_counter[1] ? _054_ : _024_;
assign _309_ = read_adress_counter[1] ? _055_ : _025_;
assign _310_ = read_adress_counter[1] ? _056_ : _026_;
assign _311_ = read_adress_counter[1] ? _057_ : _027_;
assign _313_ = read_adress_counter[3] ? _058_ : _028_;
assign _314_ = read_adress_counter[3] ? _059_ : _029_;
assign _316_ = _301_ ? 3'h1 : currstate;
assign _317_ = currstate == 3'h1;
assign _318_ = write_adress_counter == 32'd16;
assign _319_ = write_adress_counter - 32'd1;
assign _320_ = $signed(write_adress_counter) > $signed(32'd0);
assign _321_ = $signed(write_adress_counter) <= $signed(32'd15);
assign _322_ = _321_ & _320_;
assign _323_ = write_adress_counter - 32'd1;
assign _324_ = ~ mode_select_zw;
assign _325_ = mode_select_zw ? 3'h2 : currstate;
assign _326_ = _324_ ? 3'h3 : _325_;
assign _327_ = _322_ ? _091_ : _096_;
assign _328_ = _322_ ? _323_ : write_adress_counter;
assign _329_ = _322_ ? currstate : _326_;
assign _330_ = _318_ ? mode_select_zw : _327_;
assign _331_ = _318_ ? _319_ : _328_;
assign _332_ = _318_ ? currstate : _329_;
assign _333_ = currstate == 3'h3;
assign _334_ = $signed(read_adress_counter) >= $signed(32'd32);
assign _335_ = read_adress_counter - 32'd1;
assign _336_ = $signed(read_adress_counter) > $signed(32'd0);
assign _337_ = read_adress_counter - 32'd1;
assign _338_ = _336_ ? { _193_, _192_, _191_, _190_, _189_, _188_, _187_, _186_, _185_, _184_, _183_, _182_, _181_, _180_, _179_, _178_, _177_, _176_, _175_, _174_, _173_, _172_, _171_, _170_, _169_, _168_, _167_, _166_, _165_, _164_, _163_, _162_ } : { _291_, _289_, _288_, _287_, _286_, _285_, _284_, _283_, _282_, _281_, _280_, _279_, _278_, _277_, _276_, _275_, _274_, _273_, _272_, _271_, _270_, _269_, _268_, _267_, _266_, _265_, _264_, _263_, _262_, _261_, _260_, _259_ };
assign _339_ = _336_ ? _337_ : read_adress_counter;
assign _340_ = _336_ ? currstate : 3'h4;
assign _341_ = _334_ ? data_reg : _338_;
assign _342_ = _334_ ? _335_ : _339_;
assign _343_ = _334_ ? currstate : _340_;
assign _344_ = currstate == 3'h2;
assign _345_ = $signed(read_adress_counter) >= $signed(32'd32);
assign _346_ = read_adress_counter - 32'd1;
assign _347_ = $signed(read_adress_counter) > $signed(32'd0);
assign _348_ = read_adress_counter - 32'd1;
assign _349_ = _347_ ? _303_ : _315_;
assign _350_ = _347_ ? _348_ : read_adress_counter;
assign _351_ = _347_ ? currstate : 3'h4;
assign _352_ = _345_ ? _080_ : _349_;
assign _353_ = _345_ ? _346_ : _350_;
assign _354_ = _345_ ? currstate : _351_;
assign _355_ = currstate == 3'h4;
assign _356_ = _355_ ? data_reg : _083_;
assign _357_ = _355_ ? 1'h1 : _086_;
assign _358_ = _355_ ? 3'h0 : currstate;
assign _359_ = _344_ ? _352_ : _080_;
assign _360_ = _344_ ? _083_ : _356_;
assign _361_ = _344_ ? _086_ : _357_;
assign _362_ = _344_ ? _353_ : read_adress_counter;
assign _363_ = _344_ ? _354_ : _358_;
assign _364_ = _333_ ? _080_ : _359_;
assign _365_ = _333_ ? _083_ : _360_;
assign _366_ = _333_ ? _086_ : _361_;
assign _367_ = _333_ ? _341_ : data_reg;
assign _368_ = _333_ ? _342_ : _362_;
assign _369_ = _333_ ? _343_ : _363_;
assign _370_ = _317_ ? _330_ : _364_;
assign _371_ = _317_ ? _083_ : _365_;
assign _372_ = _317_ ? _086_ : _366_;
assign _373_ = _317_ ? data_reg : _367_;
assign _374_ = _317_ ? _331_ : write_adress_counter;
assign _375_ = _317_ ? read_adress_counter : _368_;
assign _376_ = _317_ ? _332_ : _369_;
assign _377_ = _290_ ? 1'h0 : _370_;
assign _378_ = _290_ ? 32'd0 : _371_;
assign _379_ = _290_ ? 1'h0 : _372_;
assign _060_ = _290_ ? 32'd0 : _373_;
assign _061_ = _290_ ? 32'd16 : _374_;
assign _062_ = _290_ ? 32'd33 : _375_;
assign _063_ = _290_ ? _316_ : _376_;
assign _064_ = ~ reset;
assign _065_ = _064_ ? _060_ : data_reg;
always @(posedge clk)
_066_ <= _065_;
assign _067_ = ~ reset;
assign _068_ = _290_ & _067_;
assign _069_ = _068_ ? _312_ : mode_select_zw;
always @(posedge clk)
_070_ <= _069_;
assign _071_ = ~ reset;
assign _072_ = _071_ ? _061_ : write_adress_counter;
always @(posedge clk)
_073_ <= _072_;
assign _074_ = ~ reset;
assign _075_ = _074_ ? _062_ : read_adress_counter;
always @(posedge clk)
_076_ <= _075_;
always @(posedge clk, posedge reset)
if (reset) _077_ <= 3'h0;
else _077_ <= _063_;
assign _078_ = ~ reset;
assign _079_ = _078_ ? _377_ : _080_;
always @(posedge clk)
_080_ <= _079_;
assign _081_ = ~ reset;
assign _082_ = _081_ ? _378_ : _083_;
always @(posedge clk)
_083_ <= _082_;
assign _084_ = ~ reset;
assign _085_ = _084_ ? _379_ : _086_;
always @(posedge clk)
_086_ <= _085_;
assign _097_ = ~ read_adress_counter[4];
assign _098_ = ~ read_adress_counter[3];
assign _099_ = _097_ & _098_;
assign _100_ = _097_ & read_adress_counter[3];
assign _101_ = read_adress_counter[4] & _098_;
assign _102_ = read_adress_counter[4] & read_adress_counter[3];
assign _103_ = ~ read_adress_counter[2];
assign _104_ = _099_ & _103_;
assign _105_ = _099_ & read_adress_counter[2];
assign _106_ = _100_ & _103_;
assign _107_ = _100_ & read_adress_counter[2];
assign _108_ = _101_ & _103_;
assign _109_ = _101_ & read_adress_counter[2];
assign _110_ = _102_ & _103_;
assign _111_ = _102_ & read_adress_counter[2];
assign _112_ = ~ read_adress_counter[1];
assign _113_ = _104_ & _112_;
assign _114_ = _104_ & read_adress_counter[1];
assign _115_ = _105_ & _112_;
assign _116_ = _105_ & read_adress_counter[1];
assign _117_ = _106_ & _112_;
assign _118_ = _106_ & read_adress_counter[1];
assign _119_ = _107_ & _112_;
assign _120_ = _107_ & read_adress_counter[1];
assign _121_ = _108_ & _112_;
assign _122_ = _108_ & read_adress_counter[1];
assign _123_ = _109_ & _112_;
assign _124_ = _109_ & read_adress_counter[1];
assign _125_ = _110_ & _112_;
assign _126_ = _110_ & read_adress_counter[1];
assign _127_ = _111_ & _112_;
assign _128_ = _111_ & read_adress_counter[1];
assign _129_ = ~ read_adress_counter[0];
assign _130_ = _113_ & _129_;
assign _131_ = _113_ & read_adress_counter[0];
assign _132_ = _114_ & _129_;
assign _133_ = _114_ & read_adress_counter[0];
assign _134_ = _115_ & _129_;
assign _135_ = _115_ & read_adress_counter[0];
assign _136_ = _116_ & _129_;
assign _137_ = _116_ & read_adress_counter[0];
assign _138_ = _117_ & _129_;
assign _139_ = _117_ & read_adress_counter[0];
assign _140_ = _118_ & _129_;
assign _141_ = _118_ & read_adress_counter[0];
assign _142_ = _119_ & _129_;
assign _143_ = _119_ & read_adress_counter[0];
assign _144_ = _120_ & _129_;
assign _145_ = _120_ & read_adress_counter[0];
assign _146_ = _121_ & _129_;
assign _147_ = _121_ & read_adress_counter[0];
assign _148_ = _122_ & _129_;
assign _149_ = _122_ & read_adress_counter[0];
assign _150_ = _123_ & _129_;
assign _151_ = _123_ & read_adress_counter[0];
assign _152_ = _124_ & _129_;
assign _153_ = _124_ & read_adress_counter[0];
assign _154_ = _125_ & _129_;
assign _155_ = _125_ & read_adress_counter[0];
assign _156_ = _126_ & _129_;
assign _157_ = _126_ & read_adress_counter[0];
assign _158_ = _127_ & _129_;
assign _159_ = _127_ & read_adress_counter[0];
assign _160_ = _128_ & _129_;
assign _161_ = _128_ & read_adress_counter[0];
assign _162_ = _130_ ? miso : data_reg[0];
assign _163_ = _131_ ? miso : data_reg[1];
assign _164_ = _132_ ? miso : data_reg[2];
assign _165_ = _133_ ? miso : data_reg[3];
assign _166_ = _134_ ? miso : data_reg[4];
assign _167_ = _135_ ? miso : data_reg[5];
assign _168_ = _136_ ? miso : data_reg[6];
assign _169_ = _137_ ? miso : data_reg[7];
assign _170_ = _138_ ? miso : data_reg[8];
assign _171_ = _139_ ? miso : data_reg[9];
assign _172_ = _140_ ? miso : data_reg[10];
assign _173_ = _141_ ? miso : data_reg[11];
assign _174_ = _142_ ? miso : data_reg[12];
assign _175_ = _143_ ? miso : data_reg[13];
assign _176_ = _144_ ? miso : data_reg[14];
assign _177_ = _145_ ? miso : data_reg[15];
assign _178_ = _146_ ? miso : data_reg[16];
assign _179_ = _147_ ? miso : data_reg[17];
assign _180_ = _148_ ? miso : data_reg[18];
assign _181_ = _149_ ? miso : data_reg[19];
assign _182_ = _150_ ? miso : data_reg[20];
assign _183_ = _151_ ? miso : data_reg[21];
assign _184_ = _152_ ? miso : data_reg[22];
assign _185_ = _153_ ? miso : data_reg[23];
assign _186_ = _154_ ? miso : data_reg[24];
assign _187_ = _155_ ? miso : data_reg[25];
assign _188_ = _156_ ? miso : data_reg[26];
assign _189_ = _157_ ? miso : data_reg[27];
assign _190_ = _158_ ? miso : data_reg[28];
assign _191_ = _159_ ? miso : data_reg[29];
assign _192_ = _160_ ? miso : data_reg[30];
assign _193_ = _161_ ? miso : data_reg[31];
assign _194_ = ~ read_adress_counter[4];
assign _195_ = ~ read_adress_counter[3];
assign _196_ = _194_ & _195_;
assign _197_ = _194_ & read_adress_counter[3];
assign _198_ = read_adress_counter[4] & _195_;
assign _199_ = read_adress_counter[4] & read_adress_counter[3];
assign _200_ = ~ read_adress_counter[2];
assign _201_ = _196_ & _200_;
assign _202_ = _196_ & read_adress_counter[2];
assign _203_ = _197_ & _200_;
assign _204_ = _197_ & read_adress_counter[2];
assign _205_ = _198_ & _200_;
assign _206_ = _198_ & read_adress_counter[2];
assign _207_ = _199_ & _200_;
assign _208_ = _199_ & read_adress_counter[2];
assign _209_ = ~ read_adress_counter[1];
assign _210_ = _201_ & _209_;
assign _211_ = _201_ & read_adress_counter[1];
assign _212_ = _202_ & _209_;
assign _213_ = _202_ & read_adress_counter[1];
assign _214_ = _203_ & _209_;
assign _215_ = _203_ & read_adress_counter[1];
assign _216_ = _204_ & _209_;
assign _217_ = _204_ & read_adress_counter[1];
assign _218_ = _205_ & _209_;
assign _219_ = _205_ & read_adress_counter[1];
assign _220_ = _206_ & _209_;
assign _221_ = _206_ & read_adress_counter[1];
assign _222_ = _207_ & _209_;
assign _223_ = _207_ & read_adress_counter[1];
assign _224_ = _208_ & _209_;
assign _225_ = _208_ & read_adress_counter[1];
assign _226_ = ~ read_adress_counter[0];
assign _227_ = _210_ & _226_;
assign _228_ = _210_ & read_adress_counter[0];
assign _229_ = _211_ & _226_;
assign _230_ = _211_ & read_adress_counter[0];
assign _231_ = _212_ & _226_;
assign _232_ = _212_ & read_adress_counter[0];
assign _233_ = _213_ & _226_;
assign _234_ = _213_ & read_adress_counter[0];
assign _235_ = _214_ & _226_;
assign _236_ = _214_ & read_adress_counter[0];
assign _237_ = _215_ & _226_;
assign _238_ = _215_ & read_adress_counter[0];
assign _239_ = _216_ & _226_;
assign _240_ = _216_ & read_adress_counter[0];
assign _241_ = _217_ & _226_;
assign _242_ = _217_ & read_adress_counter[0];
assign _243_ = _218_ & _226_;
assign _244_ = _218_ & read_adress_counter[0];
assign _245_ = _219_ & _226_;
assign _246_ = _219_ & read_adress_counter[0];
assign _247_ = _220_ & _226_;
assign _248_ = _220_ & read_adress_counter[0];
assign _249_ = _221_ & _226_;
assign _250_ = _221_ & read_adress_counter[0];
assign _251_ = _222_ & _226_;
assign _252_ = _222_ & read_adress_counter[0];
assign _253_ = _223_ & _226_;
assign _254_ = _223_ & read_adress_counter[0];
assign _255_ = _224_ & _226_;
assign _256_ = _224_ & read_adress_counter[0];
assign _257_ = _225_ & _226_;
assign _258_ = _225_ & read_adress_counter[0];
assign _259_ = _227_ ? miso : data_reg[0];
assign _260_ = _228_ ? miso : data_reg[1];
assign _261_ = _229_ ? miso : data_reg[2];
assign _262_ = _230_ ? miso : data_reg[3];
assign _263_ = _231_ ? miso : data_reg[4];
assign _264_ = _232_ ? miso : data_reg[5];
assign _265_ = _233_ ? miso : data_reg[6];
assign _266_ = _234_ ? miso : data_reg[7];
assign _267_ = _235_ ? miso : data_reg[8];
assign _268_ = _236_ ? miso : data_reg[9];
assign _269_ = _237_ ? miso : data_reg[10];
assign _270_ = _238_ ? miso : data_reg[11];
assign _271_ = _239_ ? miso : data_reg[12];
assign _272_ = _240_ ? miso : data_reg[13];
assign _273_ = _241_ ? miso : data_reg[14];
assign _274_ = _242_ ? miso : data_reg[15];
assign _275_ = _243_ ? miso : data_reg[16];
assign _276_ = _244_ ? miso : data_reg[17];
assign _277_ = _245_ ? miso : data_reg[18];
assign _278_ = _246_ ? miso : data_reg[19];
assign _279_ = _247_ ? miso : data_reg[20];
assign _280_ = _248_ ? miso : data_reg[21];
assign _281_ = _249_ ? miso : data_reg[22];
assign _282_ = _250_ ? miso : data_reg[23];
assign _283_ = _251_ ? miso : data_reg[24];
assign _284_ = _252_ ? miso : data_reg[25];
assign _285_ = _253_ ? miso : data_reg[26];
assign _286_ = _254_ ? miso : data_reg[27];
assign _287_ = _255_ ? miso : data_reg[28];
assign _288_ = _256_ ? miso : data_reg[29];
assign _289_ = _257_ ? miso : data_reg[30];
assign _291_ = _258_ ? miso : data_reg[31];
assign _303_ = read_adress_counter[4] ? _302_ : _300_;
assign _315_ = read_adress_counter[4] ? _314_ : _313_;
assign _290_ = currstate == 3'h0;
assign _301_ = ~ cs;
assign _312_ = _301_ ? mode_select : 1'h0;
assign data_reg = _066_;
assign mode_select_zw = _070_;
assign write_adress_counter = _073_;
assign read_adress_counter = _076_;
assign currstate = _077_;
assign sclk = clk;
assign mosi = _080_;
assign data_out = _083_;
assign data_valid = _086_;
endmodule
module tt_um_cejmu_riscv(clk, ena, rst_n, ui_in, uio_in, uo_out, uio_out, uio_oe);
wire _0_;
wire _1_;
wire [31:0] _2_;
wire [13:0] _3_;
wire _4_;
wire _5_;
wire [12:0] _6_;
wire _7_;
wire _8_;
wire [31:0] _9_;
input clk;
wire clk;
wire [13:0] cpu_addr_out;
wire data_valid;
input ena;
wire ena;
wire mem_req;
wire reset;
input rst_n;
wire rst_n;
wire [15:0] spi_addr_in;
wire [31:0] spi_data_in;
wire [31:0] spi_data_out;
input [7:0] ui_in;
wire [7:0] ui_in;
input [7:0] uio_in;
wire [7:0] uio_in;
output [7:0] uio_oe;
wire [7:0] uio_oe;
output [7:0] uio_out;
wire [7:0] uio_out;
output [7:0] uo_out;
wire [7:0] uo_out;
wire write_enable;
wire [12:0] x1;
assign _0_ = ~ rst_n;
cpu cpu_inst (
.addr_out(_3_),
.clk(clk),
.data_in(spi_data_out),
.data_out(_2_),
.data_valid(data_valid),
.mem_req(_5_),
.reset(reset),
.write_en(_4_),
.x1(_6_)
);
spi_master spi_master_inst (
.addr(spi_addr_in),
.clk(clk),
.cs(mem_req),
.data_in(spi_data_in),
.data_out(_9_),
.data_valid(_1_),
.miso(ui_in[0]),
.mode_select(write_enable),
.mosi(_8_),
.reset(reset),
.sclk(_7_)
);
assign write_enable = _4_;
assign cpu_addr_out = _3_;
assign spi_addr_in = { 2'h0, cpu_addr_out };
assign spi_data_out = _9_;
assign spi_data_in = _2_;
assign mem_req = _5_;
assign data_valid = _1_;
assign reset = _0_;
assign x1 = _6_;
assign uo_out = { x1[4:0], mem_req, _7_, _8_ };
assign uio_out = x1[12:5];
assign uio_oe = 8'hff;
endmodule
|
module control(clk, reset, iword, data_valid, imm, control_flags_out, wbflag, memflag, pcflag, fetchflag, mem_req);
wire _000_;
wire _001_;
wire _002_;
wire [2:0] _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire [2:0] _012_;
wire _013_;
wire [2:0] _014_;
wire [2:0] _015_;
wire [2:0] _016_;
wire [2:0] _017_;
wire [2:0] _018_;
wire [2:0] _019_;
wire [2:0] _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire [31:0] _066_;
wire _067_;
wire [31:0] _068_;
wire _069_;
wire [31:0] _070_;
wire _071_;
wire [31:0] _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
reg [2:0] _109_;
input clk;
wire clk;
wire [6:0] control_flags;
output [6:0] control_flags_out;
wire [6:0] control_flags_out;
wire [2:0] currstate;
input data_valid;
wire data_valid;
output fetchflag;
wire fetchflag;
output [31:0] imm;
wire [31:0] imm;
input [31:0] iword;
wire [31:0] iword;
output mem_req;
wire mem_req;
output memflag;
wire memflag;
output pcflag;
wire pcflag;
input reset;
wire reset;
wire [20:0] w31_to_w11;
output wbflag;
wire wbflag;
assign _000_ = currstate == 3'h0;
assign _001_ = currstate == 3'h5;
assign _002_ = currstate == 3'h1;
assign _003_ = data_valid ? 3'h6 : currstate;
assign _004_ = currstate == 3'h6;
assign _005_ = currstate == 3'h2;
assign _006_ = currstate == 3'h3;
assign _007_ = control_flags[0] & _006_;
assign _008_ = currstate == 3'h3;
assign _009_ = ~ control_flags[0];
assign _010_ = _009_ & _008_;
assign _011_ = currstate == 3'h4;
assign _012_ = _013_ ? 3'h5 : currstate;
assign _013_ = data_valid & _011_;
assign _014_ = _010_ ? 3'h5 : _012_;
assign _015_ = _007_ ? 3'h4 : _014_;
assign _016_ = _005_ ? 3'h3 : _015_;
assign _017_ = _004_ ? 3'h2 : _016_;
assign _018_ = _002_ ? _003_ : _017_;
assign _019_ = _001_ ? 3'h1 : _018_;
assign _020_ = _000_ ? 3'h1 : _019_;
assign _021_ = currstate == 3'h1;
assign _022_ = currstate == 3'h4;
assign _023_ = _021_ | _022_;
assign _024_ = ~ data_valid;
assign _025_ = _024_ & _023_;
assign _026_ = _025_ ? 1'h0 : 1'h1;
assign _027_ = currstate == 3'h3;
assign _028_ = ~ control_flags[0];
assign _029_ = _028_ & _027_;
assign _030_ = currstate == 3'h4;
assign _031_ = data_valid & _030_;
assign _032_ = _029_ | _031_;
assign _033_ = _032_ ? 1'h1 : 1'h0;
assign _034_ = currstate == 3'h3;
assign _035_ = control_flags[0] & _034_;
assign _036_ = control_flags[1] & _035_;
assign _037_ = currstate == 3'h4;
assign _038_ = control_flags[1] & _037_;
assign _039_ = _036_ | _038_;
assign _040_ = _039_ ? 1'h1 : 1'h0;
assign _041_ = currstate == 3'h4;
assign _042_ = control_flags[2] & _041_;
assign _043_ = data_valid & _042_;
assign _044_ = currstate == 3'h3;
assign _045_ = control_flags[2] & _044_;
assign _046_ = ~ control_flags[0];
assign _047_ = _046_ & _045_;
assign _048_ = _043_ | _047_;
assign _049_ = _048_ ? 1'h1 : 1'h0;
assign _050_ = currstate == 3'h1;
assign _051_ = data_valid & _050_;
assign _052_ = _051_ ? 1'h1 : 1'h0;
assign _053_ = currstate == 3'h1;
assign _054_ = currstate == 3'h0;
assign _055_ = _053_ | _054_;
assign _056_ = currstate == 3'h5;
assign _057_ = _055_ | _056_;
assign _058_ = _057_ ? 1'h1 : 1'h0;
assign _059_ = iword[6:0] == 7'h67;
assign _060_ = _059_ ? 1'h1 : 1'h0;
assign _061_ = iword[6:0] == 7'h03;
assign _062_ = iword[6:0] == 7'h13;
assign _063_ = _061_ | _062_;
assign _064_ = iword[6:0] == 7'h67;
assign _065_ = _063_ | _064_;
assign _066_ = _065_ ? { w31_to_w11, iword[30:20] } : _068_;
assign _067_ = iword[6:0] == 7'h23;
assign _068_ = _067_ ? { w31_to_w11, iword[30:25], iword[11:7] } : _070_;
assign _069_ = iword[6:0] == 7'h63;
assign _070_ = _069_ ? { w31_to_w11[20:1], iword[7], iword[30:25], iword[11:8], 1'h0 } : _072_;
assign _071_ = iword[6:0] == 7'h6f;
assign _072_ = _071_ ? { w31_to_w11[11:0], iword[19:12], iword[20], iword[30:21], 1'h0 } : 32'd0;
assign _073_ = iword[6:0] == 7'h03;
assign _074_ = iword[6:0] == 7'h23;
assign _075_ = _073_ | _074_;
assign _076_ = iword[14:12] == 3'h2;
assign _077_ = _076_ & _075_;
assign _078_ = _077_ ? 1'h1 : 1'h0;
assign _079_ = iword[6:0] == 7'h23;
assign _080_ = iword[14:12] == 3'h2;
assign _081_ = _080_ & _079_;
assign _082_ = _081_ ? 1'h1 : 1'h0;
assign _083_ = iword[6:0] == 7'h63;
assign _084_ = _083_ ? 1'h0 : 1'h1;
assign _085_ = iword[6:0] == 7'h13;
assign _086_ = iword[6:0] == 7'h37;
assign _087_ = _085_ | _086_;
assign _088_ = iword[6:0] == 7'h17;
assign _089_ = _087_ | _088_;
assign _090_ = iword[6:0] == 7'h03;
assign _091_ = iword[6:0] == 7'h23;
assign _092_ = _090_ | _091_;
assign _093_ = iword[14:12] == 3'h2;
assign _094_ = _093_ & _092_;
assign _095_ = _089_ | _094_;
assign _096_ = iword[6:0] == 7'h6f;
assign _097_ = _095_ | _096_;
assign _098_ = iword[6:0] == 7'h67;
assign _099_ = _097_ | _098_;
assign _100_ = _099_ ? 1'h1 : 1'h0;
assign _101_ = iword[6:0] == 7'h63;
assign _102_ = iword[6:0] == 7'h6f;
assign _103_ = _101_ | _102_;
assign _104_ = iword[6:0] == 7'h67;
assign _105_ = _103_ | _104_;
assign _106_ = iword[6:0] == 7'h67;
assign _107_ = _105_ | _106_;
assign _108_ = _107_ ? 1'h1 : 1'h0;
always @(posedge clk, posedge reset)
if (reset) _109_ <= 3'h0;
else _109_ <= _020_;
assign currstate = _109_;
assign control_flags = { _060_, _058_, _108_, _100_, _084_, _082_, _078_ };
assign w31_to_w11 = { iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31] };
assign imm = _066_;
assign control_flags_out = control_flags;
assign wbflag = _049_;
assign memflag = _040_;
assign pcflag = _033_;
assign fetchflag = _052_;
assign mem_req = _026_;
endmodule
|
tt06-finale_0003
|
tt06-finale
|
CEJMU-tt06_tinyrv1
|
task_cpu
|
tt_um_cejmu_riscv
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/* Generated by Yosys 0.39+165 (git sha1 22c5ab90d, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */
module alu(clk, reset, a, b, instruction, rd);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire [31:0] _15_;
wire _16_;
wire _17_;
wire _18_;
wire _19_;
wire _20_;
wire [31:0] _21_;
wire _22_;
wire _23_;
wire _24_;
wire _25_;
wire _26_;
wire [31:0] _27_;
wire _28_;
wire _29_;
wire _30_;
wire _31_;
wire _32_;
wire _33_;
wire [1:0] _34_;
wire [31:0] _35_;
wire [31:0] _36_;
wire [31:0] _37_;
wire [31:0] _38_;
wire [31:0] _39_;
wire [31:0] _40_;
wire [31:0] _41_;
reg [31:0] _42_;
input [31:0] a;
wire [31:0] a;
input [31:0] b;
wire [31:0] b;
input clk;
wire clk;
input [16:0] instruction;
wire [16:0] instruction;
output [31:0] rd;
wire [31:0] rd;
input reset;
wire reset;
assign _00_ = instruction[16:10] == 7'h00;
assign _01_ = instruction[9:7] == 3'h0;
assign _02_ = _01_ & _00_;
assign _03_ = instruction[6:0] == 7'h33;
assign _04_ = _03_ & _02_;
assign _05_ = instruction[9:7] == 3'h0;
assign _06_ = instruction[6:0] == 7'h13;
assign _07_ = _06_ & _05_;
assign _08_ = _04_ | _07_;
assign _09_ = instruction[6:0] == 7'h23;
assign _10_ = instruction[6:0] == 7'h03;
assign _11_ = _09_ | _10_;
assign _12_ = instruction[9:7] == 3'h2;
assign _13_ = _12_ & _11_;
assign _14_ = _08_ | _13_;
assign _15_ = a + b;
assign _16_ = instruction[16:10] == 7'h00;
assign _17_ = instruction[9:7] == 3'h7;
assign _18_ = _17_ & _16_;
assign _19_ = instruction[6:0] == 7'h33;
assign _20_ = _19_ & _18_;
assign _21_ = a & b;
assign _22_ = instruction[16:10] == 7'h00;
assign _23_ = instruction[9:7] == 3'h4;
assign _24_ = _23_ & _22_;
assign _25_ = instruction[6:0] == 7'h33;
assign _26_ = _25_ & _24_;
assign _27_ = a ^ b;
assign _28_ = instruction[6:0] == 7'h6f;
assign _29_ = instruction[6:0] == 7'h67;
assign _30_ = instruction[6:0] == 7'h63;
assign _31_ = instruction[9:7] == 3'h1;
assign _32_ = _31_ & _30_;
assign _33_ = a == b;
assign _34_ = _33_ ? 2'h2 : 2'h0;
assign _35_ = _32_ ? { 14'h0000, _34_, 16'h0000 } : 32'd0;
assign _36_ = _29_ ? 32'd65536 : _35_;
assign _37_ = _28_ ? 32'd0 : _36_;
assign _38_ = _26_ ? _27_ : _37_;
assign _39_ = _20_ ? _21_ : _38_;
assign _40_ = _14_ ? _15_ : _39_;
assign _41_ = reset ? 32'd0 : _40_;
always @(posedge clk)
_42_ <= _41_;
assign rd = _42_;
endmodule
module control(clk, reset, iword, data_valid, imm, control_flags_out, wbflag, memflag, pcflag, fetchflag, mem_req);
wire _000_;
wire _001_;
wire _002_;
wire [2:0] _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire [2:0] _012_;
wire _013_;
wire [2:0] _014_;
wire [2:0] _015_;
wire [2:0] _016_;
wire [2:0] _017_;
wire [2:0] _018_;
wire [2:0] _019_;
wire [2:0] _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire [31:0] _066_;
wire _067_;
wire [31:0] _068_;
wire _069_;
wire [31:0] _070_;
wire _071_;
wire [31:0] _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
reg [2:0] _109_;
input clk;
wire clk;
wire [6:0] control_flags;
output [6:0] control_flags_out;
wire [6:0] control_flags_out;
wire [2:0] currstate;
input data_valid;
wire data_valid;
output fetchflag;
wire fetchflag;
output [31:0] imm;
wire [31:0] imm;
input [31:0] iword;
wire [31:0] iword;
output mem_req;
wire mem_req;
output memflag;
wire memflag;
output pcflag;
wire pcflag;
input reset;
wire reset;
wire [20:0] w31_to_w11;
output wbflag;
wire wbflag;
assign _000_ = currstate == 3'h0;
assign _001_ = currstate == 3'h5;
assign _002_ = currstate == 3'h1;
assign _003_ = data_valid ? 3'h6 : currstate;
assign _004_ = currstate == 3'h6;
assign _005_ = currstate == 3'h2;
assign _006_ = currstate == 3'h3;
assign _007_ = control_flags[0] & _006_;
assign _008_ = currstate == 3'h3;
assign _009_ = ~ control_flags[0];
assign _010_ = _009_ & _008_;
assign _011_ = currstate == 3'h4;
assign _012_ = _013_ ? 3'h5 : currstate;
assign _013_ = data_valid & _011_;
assign _014_ = _010_ ? 3'h5 : _012_;
assign _015_ = _007_ ? 3'h4 : _014_;
assign _016_ = _005_ ? 3'h3 : _015_;
assign _017_ = _004_ ? 3'h2 : _016_;
assign _018_ = _002_ ? _003_ : _017_;
assign _019_ = _001_ ? 3'h1 : _018_;
assign _020_ = _000_ ? 3'h1 : _019_;
assign _021_ = currstate == 3'h1;
assign _022_ = currstate == 3'h4;
assign _023_ = _021_ | _022_;
assign _024_ = ~ data_valid;
assign _025_ = _024_ & _023_;
assign _026_ = _025_ ? 1'h0 : 1'h1;
assign _027_ = currstate == 3'h3;
assign _028_ = ~ control_flags[0];
assign _029_ = _028_ & _027_;
assign _030_ = currstate == 3'h4;
assign _031_ = data_valid & _030_;
assign _032_ = _029_ | _031_;
assign _033_ = _032_ ? 1'h1 : 1'h0;
assign _034_ = currstate == 3'h3;
assign _035_ = control_flags[0] & _034_;
assign _036_ = control_flags[1] & _035_;
assign _037_ = currstate == 3'h4;
assign _038_ = control_flags[1] & _037_;
assign _039_ = _036_ | _038_;
assign _040_ = _039_ ? 1'h1 : 1'h0;
assign _041_ = currstate == 3'h4;
assign _042_ = control_flags[2] & _041_;
assign _043_ = data_valid & _042_;
assign _044_ = currstate == 3'h3;
assign _045_ = control_flags[2] & _044_;
assign _046_ = ~ control_flags[0];
assign _047_ = _046_ & _045_;
assign _048_ = _043_ | _047_;
assign _049_ = _048_ ? 1'h1 : 1'h0;
assign _050_ = currstate == 3'h1;
assign _051_ = data_valid & _050_;
assign _052_ = _051_ ? 1'h1 : 1'h0;
assign _053_ = currstate == 3'h1;
assign _054_ = currstate == 3'h0;
assign _055_ = _053_ | _054_;
assign _056_ = currstate == 3'h5;
assign _057_ = _055_ | _056_;
assign _058_ = _057_ ? 1'h1 : 1'h0;
assign _059_ = iword[6:0] == 7'h67;
assign _060_ = _059_ ? 1'h1 : 1'h0;
assign _061_ = iword[6:0] == 7'h03;
assign _062_ = iword[6:0] == 7'h13;
assign _063_ = _061_ | _062_;
assign _064_ = iword[6:0] == 7'h67;
assign _065_ = _063_ | _064_;
assign _066_ = _065_ ? { w31_to_w11, iword[30:20] } : _068_;
assign _067_ = iword[6:0] == 7'h23;
assign _068_ = _067_ ? { w31_to_w11, iword[30:25], iword[11:7] } : _070_;
assign _069_ = iword[6:0] == 7'h63;
assign _070_ = _069_ ? { w31_to_w11[20:1], iword[7], iword[30:25], iword[11:8], 1'h0 } : _072_;
assign _071_ = iword[6:0] == 7'h6f;
assign _072_ = _071_ ? { w31_to_w11[11:0], iword[19:12], iword[20], iword[30:21], 1'h0 } : 32'd0;
assign _073_ = iword[6:0] == 7'h03;
assign _074_ = iword[6:0] == 7'h23;
assign _075_ = _073_ | _074_;
assign _076_ = iword[14:12] == 3'h2;
assign _077_ = _076_ & _075_;
assign _078_ = _077_ ? 1'h1 : 1'h0;
assign _079_ = iword[6:0] == 7'h23;
assign _080_ = iword[14:12] == 3'h2;
assign _081_ = _080_ & _079_;
assign _082_ = _081_ ? 1'h1 : 1'h0;
assign _083_ = iword[6:0] == 7'h63;
assign _084_ = _083_ ? 1'h0 : 1'h1;
assign _085_ = iword[6:0] == 7'h13;
assign _086_ = iword[6:0] == 7'h37;
assign _087_ = _085_ | _086_;
assign _088_ = iword[6:0] == 7'h17;
assign _089_ = _087_ | _088_;
assign _090_ = iword[6:0] == 7'h03;
assign _091_ = iword[6:0] == 7'h23;
assign _092_ = _090_ | _091_;
assign _093_ = iword[14:12] == 3'h2;
assign _094_ = _093_ & _092_;
assign _095_ = _089_ | _094_;
assign _096_ = iword[6:0] == 7'h6f;
assign _097_ = _095_ | _096_;
assign _098_ = iword[6:0] == 7'h67;
assign _099_ = _097_ | _098_;
assign _100_ = _099_ ? 1'h1 : 1'h0;
assign _101_ = iword[6:0] == 7'h63;
assign _102_ = iword[6:0] == 7'h6f;
assign _103_ = _101_ | _102_;
assign _104_ = iword[6:0] == 7'h67;
assign _105_ = _103_ | _104_;
assign _106_ = iword[6:0] == 7'h67;
assign _107_ = _105_ | _106_;
assign _108_ = _107_ ? 1'h1 : 1'h0;
always @(posedge clk, posedge reset)
if (reset) _109_ <= 3'h0;
else _109_ <= _020_;
assign currstate = _109_;
assign control_flags = { _060_, _058_, _108_, _100_, _084_, _082_, _078_ };
assign w31_to_w11 = { iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31] };
assign imm = _066_;
assign control_flags_out = control_flags;
assign wbflag = _049_;
assign memflag = _040_;
assign pcflag = _033_;
assign fetchflag = _052_;
assign mem_req = _026_;
endmodule
module cpu(clk, reset, data_in, data_valid, data_out, addr_out, write_en, mem_req, x1);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module instructioncounter(clk, reset, pcflag, s0, s1, pc_offset, pc_inc, pc_new);
wire [15:0] _00_;
wire [15:0] _01_;
wire _02_;
wire [15:0] _03_;
wire _04_;
wire _05_;
wire [15:0] _06_;
wire [15:0] _07_;
wire [15:0] _08_;
reg [15:0] _09_ = 16'h0000;
reg [15:0] _10_;
input clk;
wire clk;
output [15:0] pc_inc;
wire [15:0] pc_inc;
output [15:0] pc_new;
wire [15:0] pc_new;
input [15:0] pc_offset;
wire [15:0] pc_offset;
input pcflag;
wire pcflag;
wire [15:0] \reg ;
input reset;
wire reset;
input s0;
wire s0;
input s1;
wire s1;
wire [1:0] s1s0;
assign _00_ = \reg + 16'h0004;
assign _01_ = pc_offset + \reg ;
assign _02_ = s1s0 == 2'h0;
assign _03_ = \reg + 16'h0004;
assign _04_ = s1s0 == 2'h2;
assign _05_ = s1s0 == 2'h1;
function [15:0] \1383 ;
input [15:0] a;
input [47:0] b;
input [2:0] s;
(* parallel_case *)
casez (s)
3'b??1:
\1383 = b[15:0];
3'b?1?:
\1383 = b[31:16];
3'b1??:
\1383 = b[47:32];
default:
\1383 = a;
endcase
endfunction
assign _06_ = \1383 (16'h0000, { pc_offset, _03_, _01_ }, { _05_, _04_, _02_ });
assign _07_ = pcflag ? _06_ : \reg ;
assign _08_ = reset ? 16'h0000 : _07_;
always @(posedge clk)
_09_ <= _08_;
always @(posedge clk)
_10_ <= _00_;
assign s1s0 = { s1, s0 };
assign \reg = _09_;
assign pc_inc = _10_;
assign pc_new = \reg ;
endmodule
module regs(clk, reset, rs1adr, rs2adr, rdadr, rd, regwrite, rs1, rs2, x1);
wire [31:0] _000_;
wire [31:0] _001_;
wire [31:0] _002_;
wire [31:0] _003_;
wire [31:0] _004_;
wire [31:0] _005_;
wire [31:0] _006_;
wire [31:0] _007_;
wire [31:0] _008_;
wire [31:0] _009_;
wire [31:0] _010_;
wire [31:0] _011_;
wire [31:0] _012_;
wire [31:0] _013_;
wire [31:0] _014_;
wire [31:0] _015_;
wire [31:0] _016_;
wire [31:0] _017_;
wire [31:0] _018_;
wire [31:0] _019_;
wire [31:0] _020_;
wire [31:0] _021_;
wire [31:0] _022_;
wire [31:0] _023_;
wire [31:0] _024_;
wire [31:0] _025_;
wire [31:0] _026_;
wire [31:0] _027_;
wire [31:0] _028_;
wire [31:0] _029_;
wire [31:0] _030_;
wire [31:0] _031_;
wire [31:0] _032_;
wire [31:0] _033_;
wire [31:0] _034_;
wire [31:0] _035_;
wire [31:0] _036_;
wire [31:0] _037_;
wire [31:0] _038_;
wire [31:0] _039_;
wire _040_;
wire _041_;
wire [4:0] _042_;
wire [4:0] _043_;
wire [4:0] _044_;
wire [1023:0] _045_;
reg [1023:0] _046_;
reg [31:0] _047_;
reg [31:0] _048_;
wire _049_;
wire [12:0] _050_;
reg [12:0] _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire [31:0] _117_;
wire [31:0] _118_;
wire [31:0] _119_;
wire [31:0] _120_;
wire [31:0] _121_;
wire [31:0] _122_;
wire [31:0] _123_;
wire [31:0] _124_;
wire [31:0] _125_;
wire [31:0] _126_;
wire [31:0] _127_;
wire [31:0] _128_;
wire [31:0] _129_;
wire [31:0] _130_;
wire [31:0] _131_;
wire [31:0] _132_;
wire [31:0] _133_;
wire [31:0] _134_;
wire [31:0] _135_;
wire [31:0] _136_;
wire [31:0] _137_;
wire [31:0] _138_;
wire [31:0] _139_;
wire [31:0] _140_;
wire [31:0] _141_;
wire [31:0] _142_;
wire [31:0] _143_;
wire [31:0] _144_;
wire [31:0] _145_;
wire [31:0] _146_;
wire [31:0] _147_;
wire [31:0] _148_;
wire [31:0] _149_;
wire [31:0] _150_;
wire [31:0] _151_;
wire [31:0] _152_;
wire [31:0] _153_;
wire [31:0] _154_;
wire [31:0] _155_;
wire [31:0] _156_;
wire [31:0] _157_;
wire [31:0] _158_;
wire [31:0] _159_;
wire [31:0] _160_;
wire [31:0] _161_;
wire [31:0] _162_;
wire [31:0] _163_;
wire [31:0] _164_;
wire [31:0] _165_;
wire [31:0] _166_;
wire [31:0] _167_;
wire [31:0] _168_;
wire [31:0] _169_;
wire [31:0] _170_;
input clk;
wire clk;
input [31:0] rd;
wire [31:0] rd;
input [4:0] rdadr;
wire [4:0] rdadr;
wire [1023:0] registers;
input regwrite;
wire regwrite;
input reset;
wire reset;
output [31:0] rs1;
wire [31:0] rs1;
input [4:0] rs1adr;
wire [4:0] rs1adr;
output [31:0] rs2;
wire [31:0] rs2;
input [4:0] rs2adr;
wire [4:0] rs2adr;
output [12:0] x1;
wire [12:0] x1;
assign _000_ = _043_[0] ? registers[63:32] : registers[31:0];
assign _001_ = _043_[0] ? registers[191:160] : registers[159:128];
assign _002_ = _043_[0] ? registers[319:288] : registers[287:256];
assign _003_ = _043_[0] ? registers[447:416] : registers[415:384];
assign _004_ = _043_[0] ? registers[575:544] : registers[543:512];
assign _005_ = _043_[0] ? registers[703:672] : registers[671:640];
assign _006_ = _043_[0] ? registers[831:800] : registers[799:768];
assign _007_ = _043_[0] ? registers[959:928] : registers[927:896];
assign _008_ = _043_[2] ? _150_ : _149_;
assign _009_ = _043_[2] ? _154_ : _153_;
assign _010_ = _044_[0] ? registers[63:32] : registers[31:0];
assign _011_ = _044_[0] ? registers[191:160] : registers[159:128];
assign _012_ = _044_[0] ? registers[319:288] : registers[287:256];
assign _013_ = _044_[0] ? registers[447:416] : registers[415:384];
assign _014_ = _044_[0] ? registers[575:544] : registers[543:512];
assign _015_ = _044_[0] ? registers[703:672] : registers[671:640];
assign _016_ = _044_[0] ? registers[831:800] : registers[799:768];
assign _017_ = _044_[0] ? registers[959:928] : registers[927:896];
assign _018_ = _044_[2] ? _161_ : _160_;
assign _019_ = _044_[2] ? _165_ : _164_;
assign _020_ = _043_[0] ? registers[127:96] : registers[95:64];
assign _021_ = _043_[0] ? registers[255:224] : registers[223:192];
assign _022_ = _043_[0] ? registers[383:352] : registers[351:320];
assign _023_ = _043_[0] ? registers[511:480] : registers[479:448];
assign _024_ = _043_[0] ? registers[639:608] : registers[607:576];
assign _025_ = _043_[0] ? registers[767:736] : registers[735:704];
assign _026_ = _043_[0] ? registers[895:864] : registers[863:832];
assign _027_ = _043_[0] ? registers[1023:992] : registers[991:960];
assign _028_ = _043_[2] ? _152_ : _151_;
assign _029_ = _043_[2] ? _156_ : _155_;
assign _030_ = _044_[0] ? registers[127:96] : registers[95:64];
assign _031_ = _044_[0] ? registers[255:224] : registers[223:192];
assign _032_ = _044_[0] ? registers[383:352] : registers[351:320];
assign _033_ = _044_[0] ? registers[511:480] : registers[479:448];
assign _034_ = _044_[0] ? registers[639:608] : registers[607:576];
assign _035_ = _044_[0] ? registers[767:736] : registers[735:704];
assign _036_ = _044_[0] ? registers[895:864] : registers[863:832];
assign _037_ = _044_[0] ? registers[1023:992] : registers[991:960];
assign _038_ = _044_[2] ? _163_ : _162_;
assign _039_ = _044_[2] ? _167_ : _166_;
assign _149_ = _043_[1] ? _020_ : _000_;
assign _150_ = _043_[1] ? _021_ : _001_;
assign _151_ = _043_[1] ? _022_ : _002_;
assign _152_ = _043_[1] ? _023_ : _003_;
assign _153_ = _043_[1] ? _024_ : _004_;
assign _154_ = _043_[1] ? _025_ : _005_;
assign _155_ = _043_[1] ? _026_ : _006_;
assign _156_ = _043_[1] ? _027_ : _007_;
assign _157_ = _043_[3] ? _028_ : _008_;
assign _158_ = _043_[3] ? _029_ : _009_;
assign _160_ = _044_[1] ? _030_ : _010_;
assign _161_ = _044_[1] ? _031_ : _011_;
assign _162_ = _044_[1] ? _032_ : _012_;
assign _163_ = _044_[1] ? _033_ : _013_;
assign _164_ = _044_[1] ? _034_ : _014_;
assign _165_ = _044_[1] ? _035_ : _015_;
assign _166_ = _044_[1] ? _036_ : _016_;
assign _167_ = _044_[1] ? _037_ : _017_;
assign _168_ = _044_[3] ? _038_ : _018_;
assign _169_ = _044_[3] ? _039_ : _019_;
assign _170_ = _044_[4] ? _169_ : _168_;
assign _040_ = rdadr != 5'h00;
assign _041_ = _040_ & regwrite;
assign _042_ = 5'h1f - rdadr;
assign _043_ = 5'h1f - rs1adr;
assign _044_ = 5'h1f - rs2adr;
assign _045_ = _041_ ? { _148_, _147_, _146_, _145_, _144_, _143_, _142_, _141_, _140_, _139_, _138_, _137_, _136_, _135_, _134_, _133_, _132_, _131_, _130_, _129_, _128_, _127_, _126_, _125_, _124_, _123_, _122_, _121_, _120_, _119_, _118_, _117_ } : registers;
always @(posedge clk, posedge reset)
if (reset) _046_ <= 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
else _046_ <= _045_;
always @(posedge clk, posedge reset)
if (reset) _047_ <= 32'd0;
else _047_ <= _159_;
always @(posedge clk, posedge reset)
if (reset) _048_ <= 32'd0;
else _048_ <= _170_;
assign _049_ = ~ reset;
assign _050_ = _049_ ? registers[972:960] : _051_;
always @(posedge clk)
_051_ <= _050_;
assign _052_ = ~ _042_[4];
assign _053_ = ~ _042_[3];
assign _054_ = _052_ & _053_;
assign _055_ = _052_ & _042_[3];
assign _056_ = _042_[4] & _053_;
assign _057_ = _042_[4] & _042_[3];
assign _058_ = ~ _042_[2];
assign _059_ = _054_ & _058_;
assign _060_ = _054_ & _042_[2];
assign _061_ = _055_ & _058_;
assign _062_ = _055_ & _042_[2];
assign _063_ = _056_ & _058_;
assign _064_ = _056_ & _042_[2];
assign _065_ = _057_ & _058_;
assign _066_ = _057_ & _042_[2];
assign _067_ = ~ _042_[1];
assign _068_ = _059_ & _067_;
assign _069_ = _059_ & _042_[1];
assign _070_ = _060_ & _067_;
assign _071_ = _060_ & _042_[1];
assign _072_ = _061_ & _067_;
assign _073_ = _061_ & _042_[1];
assign _074_ = _062_ & _067_;
assign _075_ = _062_ & _042_[1];
assign _076_ = _063_ & _067_;
assign _077_ = _063_ & _042_[1];
assign _078_ = _064_ & _067_;
assign _079_ = _064_ & _042_[1];
assign _080_ = _065_ & _067_;
assign _081_ = _065_ & _042_[1];
assign _082_ = _066_ & _067_;
assign _083_ = _066_ & _042_[1];
assign _084_ = ~ _042_[0];
assign _085_ = _068_ & _084_;
assign _086_ = _068_ & _042_[0];
assign _087_ = _069_ & _084_;
assign _088_ = _069_ & _042_[0];
assign _089_ = _070_ & _084_;
assign _090_ = _070_ & _042_[0];
assign _091_ = _071_ & _084_;
assign _092_ = _071_ & _042_[0];
assign _093_ = _072_ & _084_;
assign _094_ = _072_ & _042_[0];
assign _095_ = _073_ & _084_;
assign _096_ = _073_ & _042_[0];
assign _097_ = _074_ & _084_;
assign _098_ = _074_ & _042_[0];
assign _099_ = _075_ & _084_;
assign _100_ = _075_ & _042_[0];
assign _101_ = _076_ & _084_;
assign _102_ = _076_ & _042_[0];
assign _103_ = _077_ & _084_;
assign _104_ = _077_ & _042_[0];
assign _105_ = _078_ & _084_;
assign _106_ = _078_ & _042_[0];
assign _107_ = _079_ & _084_;
assign _108_ = _079_ & _042_[0];
assign _109_ = _080_ & _084_;
assign _110_ = _080_ & _042_[0];
assign _111_ = _081_ & _084_;
assign _112_ = _081_ & _042_[0];
assign _113_ = _082_ & _084_;
assign _114_ = _082_ & _042_[0];
assign _115_ = _083_ & _084_;
assign _116_ = _083_ & _042_[0];
assign _117_ = _085_ ? rd : registers[31:0];
assign _118_ = _086_ ? rd : registers[63:32];
assign _119_ = _087_ ? rd : registers[95:64];
assign _120_ = _088_ ? rd : registers[127:96];
assign _121_ = _089_ ? rd : registers[159:128];
assign _122_ = _090_ ? rd : registers[191:160];
assign _123_ = _091_ ? rd : registers[223:192];
assign _124_ = _092_ ? rd : registers[255:224];
assign _125_ = _093_ ? rd : registers[287:256];
assign _126_ = _094_ ? rd : registers[319:288];
assign _127_ = _095_ ? rd : registers[351:320];
assign _128_ = _096_ ? rd : registers[383:352];
assign _129_ = _097_ ? rd : registers[415:384];
assign _130_ = _098_ ? rd : registers[447:416];
assign _131_ = _099_ ? rd : registers[479:448];
assign _132_ = _100_ ? rd : registers[511:480];
assign _133_ = _101_ ? rd : registers[543:512];
assign _134_ = _102_ ? rd : registers[575:544];
assign _135_ = _103_ ? rd : registers[607:576];
assign _136_ = _104_ ? rd : registers[639:608];
assign _137_ = _105_ ? rd : registers[671:640];
assign _138_ = _106_ ? rd : registers[703:672];
assign _139_ = _107_ ? rd : registers[735:704];
assign _140_ = _108_ ? rd : registers[767:736];
assign _141_ = _109_ ? rd : registers[799:768];
assign _142_ = _110_ ? rd : registers[831:800];
assign _143_ = _111_ ? rd : registers[863:832];
assign _144_ = _112_ ? rd : registers[895:864];
assign _145_ = _113_ ? rd : registers[927:896];
assign _146_ = _114_ ? rd : registers[959:928];
assign _147_ = _115_ ? rd : registers[991:960];
assign _148_ = _116_ ? rd : registers[1023:992];
assign _159_ = _043_[4] ? _158_ : _157_;
assign registers = _046_;
assign rs1 = _047_;
assign rs2 = _048_;
assign x1 = _051_;
endmodule
module spi_master(clk, mode_select, reset, miso, cs, data_in, addr, sclk, mosi, data_out, data_valid);
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire [31:0] _060_;
wire [31:0] _061_;
wire [31:0] _062_;
wire [2:0] _063_;
wire _064_;
wire [31:0] _065_;
reg [31:0] _066_;
wire _067_;
wire _068_;
wire _069_;
reg _070_;
wire _071_;
wire [31:0] _072_;
reg [31:0] _073_ = 32'd16;
wire _074_;
wire [31:0] _075_;
reg [31:0] _076_ = 32'd33;
reg [2:0] _077_;
wire _078_;
wire _079_;
reg _080_;
wire _081_;
wire [31:0] _082_;
reg [31:0] _083_;
wire _084_;
wire _085_;
reg _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
wire _203_;
wire _204_;
wire _205_;
wire _206_;
wire _207_;
wire _208_;
wire _209_;
wire _210_;
wire _211_;
wire _212_;
wire _213_;
wire _214_;
wire _215_;
wire _216_;
wire _217_;
wire _218_;
wire _219_;
wire _220_;
wire _221_;
wire _222_;
wire _223_;
wire _224_;
wire _225_;
wire _226_;
wire _227_;
wire _228_;
wire _229_;
wire _230_;
wire _231_;
wire _232_;
wire _233_;
wire _234_;
wire _235_;
wire _236_;
wire _237_;
wire _238_;
wire _239_;
wire _240_;
wire _241_;
wire _242_;
wire _243_;
wire _244_;
wire _245_;
wire _246_;
wire _247_;
wire _248_;
wire _249_;
wire _250_;
wire _251_;
wire _252_;
wire _253_;
wire _254_;
wire _255_;
wire _256_;
wire _257_;
wire _258_;
wire _259_;
wire _260_;
wire _261_;
wire _262_;
wire _263_;
wire _264_;
wire _265_;
wire _266_;
wire _267_;
wire _268_;
wire _269_;
wire _270_;
wire _271_;
wire _272_;
wire _273_;
wire _274_;
wire _275_;
wire _276_;
wire _277_;
wire _278_;
wire _279_;
wire _280_;
wire _281_;
wire _282_;
wire _283_;
wire _284_;
wire _285_;
wire _286_;
wire _287_;
wire _288_;
wire _289_;
wire _290_;
wire _291_;
wire _292_;
wire _293_;
wire _294_;
wire _295_;
wire _296_;
wire _297_;
wire _298_;
wire _299_;
wire _300_;
wire _301_;
wire _302_;
wire _303_;
wire _304_;
wire _305_;
wire _306_;
wire _307_;
wire _308_;
wire _309_;
wire _310_;
wire _311_;
wire _312_;
wire _313_;
wire _314_;
wire _315_;
wire [2:0] _316_;
wire _317_;
wire _318_;
wire [31:0] _319_;
wire _320_;
wire _321_;
wire _322_;
wire [31:0] _323_;
wire _324_;
wire [2:0] _325_;
wire [2:0] _326_;
wire _327_;
wire [31:0] _328_;
wire [2:0] _329_;
wire _330_;
wire [31:0] _331_;
wire [2:0] _332_;
wire _333_;
wire _334_;
wire [31:0] _335_;
wire _336_;
wire [31:0] _337_;
wire [31:0] _338_;
wire [31:0] _339_;
wire [2:0] _340_;
wire [31:0] _341_;
wire [31:0] _342_;
wire [2:0] _343_;
wire _344_;
wire _345_;
wire [31:0] _346_;
wire _347_;
wire [31:0] _348_;
wire _349_;
wire [31:0] _350_;
wire [2:0] _351_;
wire _352_;
wire [31:0] _353_;
wire [2:0] _354_;
wire _355_;
wire [31:0] _356_;
wire _357_;
wire [2:0] _358_;
wire _359_;
wire [31:0] _360_;
wire _361_;
wire [31:0] _362_;
wire [2:0] _363_;
wire _364_;
wire [31:0] _365_;
wire _366_;
wire [31:0] _367_;
wire [31:0] _368_;
wire [2:0] _369_;
wire _370_;
wire [31:0] _371_;
wire _372_;
wire [31:0] _373_;
wire [31:0] _374_;
wire [31:0] _375_;
wire [2:0] _376_;
wire _377_;
wire [31:0] _378_;
wire _379_;
input [15:0] addr;
wire [15:0] addr;
input clk;
wire clk;
input cs;
wire cs;
wire [2:0] currstate;
input [31:0] data_in;
wire [31:0] data_in;
output [31:0] data_out;
wire [31:0] data_out;
wire [31:0] data_reg;
output data_valid;
wire data_valid;
input miso;
wire miso;
input mode_select;
wire mode_select;
wire mode_select_zw;
output mosi;
wire mosi;
wire [31:0] read_adress_counter;
input reset;
wire reset;
output sclk;
wire sclk;
wire [31:0] write_adress_counter;
assign _000_ = write_adress_counter[0] ? addr[1] : addr[0];
assign _001_ = write_adress_counter[0] ? addr[5] : addr[4];
assign _002_ = write_adress_counter[0] ? addr[9] : addr[8];
assign _003_ = write_adress_counter[0] ? addr[13] : addr[12];
assign _004_ = write_adress_counter[2] ? _088_ : _087_;
assign _005_ = write_adress_counter[0] ? addr[1] : addr[0];
assign _006_ = write_adress_counter[0] ? addr[5] : addr[4];
assign _007_ = write_adress_counter[0] ? addr[9] : addr[8];
assign _008_ = write_adress_counter[0] ? addr[13] : addr[12];
assign _009_ = write_adress_counter[2] ? _093_ : _092_;
assign _010_ = read_adress_counter[0] ? data_in[1] : data_in[0];
assign _011_ = read_adress_counter[0] ? data_in[5] : data_in[4];
assign _012_ = read_adress_counter[0] ? data_in[9] : data_in[8];
assign _013_ = read_adress_counter[0] ? data_in[13] : data_in[12];
assign _014_ = read_adress_counter[0] ? data_in[17] : data_in[16];
assign _015_ = read_adress_counter[0] ? data_in[21] : data_in[20];
assign _016_ = read_adress_counter[0] ? data_in[25] : data_in[24];
assign _017_ = read_adress_counter[0] ? data_in[29] : data_in[28];
assign _018_ = read_adress_counter[2] ? _293_ : _292_;
assign _019_ = read_adress_counter[2] ? _297_ : _296_;
assign _020_ = read_adress_counter[0] ? data_in[1] : data_in[0];
assign _021_ = read_adress_counter[0] ? data_in[5] : data_in[4];
assign _022_ = read_adress_counter[0] ? data_in[9] : data_in[8];
assign _023_ = read_adress_counter[0] ? data_in[13] : data_in[12];
assign _024_ = read_adress_counter[0] ? data_in[17] : data_in[16];
assign _025_ = read_adress_counter[0] ? data_in[21] : data_in[20];
assign _026_ = read_adress_counter[0] ? data_in[25] : data_in[24];
assign _027_ = read_adress_counter[0] ? data_in[29] : data_in[28];
assign _028_ = read_adress_counter[2] ? _305_ : _304_;
assign _029_ = read_adress_counter[2] ? _309_ : _308_;
assign _030_ = write_adress_counter[0] ? addr[3] : addr[2];
assign _031_ = write_adress_counter[0] ? addr[7] : addr[6];
assign _032_ = write_adress_counter[0] ? addr[11] : addr[10];
assign _033_ = write_adress_counter[0] ? addr[15] : addr[14];
assign _034_ = write_adress_counter[2] ? _090_ : _089_;
assign _035_ = write_adress_counter[0] ? addr[3] : addr[2];
assign _036_ = write_adress_counter[0] ? addr[7] : addr[6];
assign _037_ = write_adress_counter[0] ? addr[11] : addr[10];
assign _038_ = write_adress_counter[0] ? addr[15] : addr[14];
assign _039_ = write_adress_counter[2] ? _095_ : _094_;
assign _040_ = read_adress_counter[0] ? data_in[3] : data_in[2];
assign _041_ = read_adress_counter[0] ? data_in[7] : data_in[6];
assign _042_ = read_adress_counter[0] ? data_in[11] : data_in[10];
assign _043_ = read_adress_counter[0] ? data_in[15] : data_in[14];
assign _044_ = read_adress_counter[0] ? data_in[19] : data_in[18];
assign _045_ = read_adress_counter[0] ? data_in[23] : data_in[22];
assign _046_ = read_adress_counter[0] ? data_in[27] : data_in[26];
assign _047_ = read_adress_counter[0] ? data_in[31] : data_in[30];
assign _048_ = read_adress_counter[2] ? _295_ : _294_;
assign _049_ = read_adress_counter[2] ? _299_ : _298_;
assign _050_ = read_adress_counter[0] ? data_in[3] : data_in[2];
assign _051_ = read_adress_counter[0] ? data_in[7] : data_in[6];
assign _052_ = read_adress_counter[0] ? data_in[11] : data_in[10];
assign _053_ = read_adress_counter[0] ? data_in[15] : data_in[14];
assign _054_ = read_adress_counter[0] ? data_in[19] : data_in[18];
assign _055_ = read_adress_counter[0] ? data_in[23] : data_in[22];
assign _056_ = read_adress_counter[0] ? data_in[27] : data_in[26];
assign _057_ = read_adress_counter[0] ? data_in[31] : data_in[30];
assign _058_ = read_adress_counter[2] ? _307_ : _306_;
assign _059_ = read_adress_counter[2] ? _311_ : _310_;
assign _087_ = write_adress_counter[1] ? _030_ : _000_;
assign _088_ = write_adress_counter[1] ? _031_ : _001_;
assign _089_ = write_adress_counter[1] ? _032_ : _002_;
assign _090_ = write_adress_counter[1] ? _033_ : _003_;
assign _091_ = write_adress_counter[3] ? _034_ : _004_;
assign _092_ = write_adress_counter[1] ? _035_ : _005_;
assign _093_ = write_adress_counter[1] ? _036_ : _006_;
assign _094_ = write_adress_counter[1] ? _037_ : _007_;
assign _095_ = write_adress_counter[1] ? _038_ : _008_;
assign _096_ = write_adress_counter[3] ? _039_ : _009_;
assign _292_ = read_adress_counter[1] ? _040_ : _010_;
assign _293_ = read_adress_counter[1] ? _041_ : _011_;
assign _294_ = read_adress_counter[1] ? _042_ : _012_;
assign _295_ = read_adress_counter[1] ? _043_ : _013_;
assign _296_ = read_adress_counter[1] ? _044_ : _014_;
assign _297_ = read_adress_counter[1] ? _045_ : _015_;
assign _298_ = read_adress_counter[1] ? _046_ : _016_;
assign _299_ = read_adress_counter[1] ? _047_ : _017_;
assign _300_ = read_adress_counter[3] ? _048_ : _018_;
assign _302_ = read_adress_counter[3] ? _049_ : _019_;
assign _304_ = read_adress_counter[1] ? _050_ : _020_;
assign _305_ = read_adress_counter[1] ? _051_ : _021_;
assign _306_ = read_adress_counter[1] ? _052_ : _022_;
assign _307_ = read_adress_counter[1] ? _053_ : _023_;
assign _308_ = read_adress_counter[1] ? _054_ : _024_;
assign _309_ = read_adress_counter[1] ? _055_ : _025_;
assign _310_ = read_adress_counter[1] ? _056_ : _026_;
assign _311_ = read_adress_counter[1] ? _057_ : _027_;
assign _313_ = read_adress_counter[3] ? _058_ : _028_;
assign _314_ = read_adress_counter[3] ? _059_ : _029_;
assign _316_ = _301_ ? 3'h1 : currstate;
assign _317_ = currstate == 3'h1;
assign _318_ = write_adress_counter == 32'd16;
assign _319_ = write_adress_counter - 32'd1;
assign _320_ = $signed(write_adress_counter) > $signed(32'd0);
assign _321_ = $signed(write_adress_counter) <= $signed(32'd15);
assign _322_ = _321_ & _320_;
assign _323_ = write_adress_counter - 32'd1;
assign _324_ = ~ mode_select_zw;
assign _325_ = mode_select_zw ? 3'h2 : currstate;
assign _326_ = _324_ ? 3'h3 : _325_;
assign _327_ = _322_ ? _091_ : _096_;
assign _328_ = _322_ ? _323_ : write_adress_counter;
assign _329_ = _322_ ? currstate : _326_;
assign _330_ = _318_ ? mode_select_zw : _327_;
assign _331_ = _318_ ? _319_ : _328_;
assign _332_ = _318_ ? currstate : _329_;
assign _333_ = currstate == 3'h3;
assign _334_ = $signed(read_adress_counter) >= $signed(32'd32);
assign _335_ = read_adress_counter - 32'd1;
assign _336_ = $signed(read_adress_counter) > $signed(32'd0);
assign _337_ = read_adress_counter - 32'd1;
assign _338_ = _336_ ? { _193_, _192_, _191_, _190_, _189_, _188_, _187_, _186_, _185_, _184_, _183_, _182_, _181_, _180_, _179_, _178_, _177_, _176_, _175_, _174_, _173_, _172_, _171_, _170_, _169_, _168_, _167_, _166_, _165_, _164_, _163_, _162_ } : { _291_, _289_, _288_, _287_, _286_, _285_, _284_, _283_, _282_, _281_, _280_, _279_, _278_, _277_, _276_, _275_, _274_, _273_, _272_, _271_, _270_, _269_, _268_, _267_, _266_, _265_, _264_, _263_, _262_, _261_, _260_, _259_ };
assign _339_ = _336_ ? _337_ : read_adress_counter;
assign _340_ = _336_ ? currstate : 3'h4;
assign _341_ = _334_ ? data_reg : _338_;
assign _342_ = _334_ ? _335_ : _339_;
assign _343_ = _334_ ? currstate : _340_;
assign _344_ = currstate == 3'h2;
assign _345_ = $signed(read_adress_counter) >= $signed(32'd32);
assign _346_ = read_adress_counter - 32'd1;
assign _347_ = $signed(read_adress_counter) > $signed(32'd0);
assign _348_ = read_adress_counter - 32'd1;
assign _349_ = _347_ ? _303_ : _315_;
assign _350_ = _347_ ? _348_ : read_adress_counter;
assign _351_ = _347_ ? currstate : 3'h4;
assign _352_ = _345_ ? _080_ : _349_;
assign _353_ = _345_ ? _346_ : _350_;
assign _354_ = _345_ ? currstate : _351_;
assign _355_ = currstate == 3'h4;
assign _356_ = _355_ ? data_reg : _083_;
assign _357_ = _355_ ? 1'h1 : _086_;
assign _358_ = _355_ ? 3'h0 : currstate;
assign _359_ = _344_ ? _352_ : _080_;
assign _360_ = _344_ ? _083_ : _356_;
assign _361_ = _344_ ? _086_ : _357_;
assign _362_ = _344_ ? _353_ : read_adress_counter;
assign _363_ = _344_ ? _354_ : _358_;
assign _364_ = _333_ ? _080_ : _359_;
assign _365_ = _333_ ? _083_ : _360_;
assign _366_ = _333_ ? _086_ : _361_;
assign _367_ = _333_ ? _341_ : data_reg;
assign _368_ = _333_ ? _342_ : _362_;
assign _369_ = _333_ ? _343_ : _363_;
assign _370_ = _317_ ? _330_ : _364_;
assign _371_ = _317_ ? _083_ : _365_;
assign _372_ = _317_ ? _086_ : _366_;
assign _373_ = _317_ ? data_reg : _367_;
assign _374_ = _317_ ? _331_ : write_adress_counter;
assign _375_ = _317_ ? read_adress_counter : _368_;
assign _376_ = _317_ ? _332_ : _369_;
assign _377_ = _290_ ? 1'h0 : _370_;
assign _378_ = _290_ ? 32'd0 : _371_;
assign _379_ = _290_ ? 1'h0 : _372_;
assign _060_ = _290_ ? 32'd0 : _373_;
assign _061_ = _290_ ? 32'd16 : _374_;
assign _062_ = _290_ ? 32'd33 : _375_;
assign _063_ = _290_ ? _316_ : _376_;
assign _064_ = ~ reset;
assign _065_ = _064_ ? _060_ : data_reg;
always @(posedge clk)
_066_ <= _065_;
assign _067_ = ~ reset;
assign _068_ = _290_ & _067_;
assign _069_ = _068_ ? _312_ : mode_select_zw;
always @(posedge clk)
_070_ <= _069_;
assign _071_ = ~ reset;
assign _072_ = _071_ ? _061_ : write_adress_counter;
always @(posedge clk)
_073_ <= _072_;
assign _074_ = ~ reset;
assign _075_ = _074_ ? _062_ : read_adress_counter;
always @(posedge clk)
_076_ <= _075_;
always @(posedge clk, posedge reset)
if (reset) _077_ <= 3'h0;
else _077_ <= _063_;
assign _078_ = ~ reset;
assign _079_ = _078_ ? _377_ : _080_;
always @(posedge clk)
_080_ <= _079_;
assign _081_ = ~ reset;
assign _082_ = _081_ ? _378_ : _083_;
always @(posedge clk)
_083_ <= _082_;
assign _084_ = ~ reset;
assign _085_ = _084_ ? _379_ : _086_;
always @(posedge clk)
_086_ <= _085_;
assign _097_ = ~ read_adress_counter[4];
assign _098_ = ~ read_adress_counter[3];
assign _099_ = _097_ & _098_;
assign _100_ = _097_ & read_adress_counter[3];
assign _101_ = read_adress_counter[4] & _098_;
assign _102_ = read_adress_counter[4] & read_adress_counter[3];
assign _103_ = ~ read_adress_counter[2];
assign _104_ = _099_ & _103_;
assign _105_ = _099_ & read_adress_counter[2];
assign _106_ = _100_ & _103_;
assign _107_ = _100_ & read_adress_counter[2];
assign _108_ = _101_ & _103_;
assign _109_ = _101_ & read_adress_counter[2];
assign _110_ = _102_ & _103_;
assign _111_ = _102_ & read_adress_counter[2];
assign _112_ = ~ read_adress_counter[1];
assign _113_ = _104_ & _112_;
assign _114_ = _104_ & read_adress_counter[1];
assign _115_ = _105_ & _112_;
assign _116_ = _105_ & read_adress_counter[1];
assign _117_ = _106_ & _112_;
assign _118_ = _106_ & read_adress_counter[1];
assign _119_ = _107_ & _112_;
assign _120_ = _107_ & read_adress_counter[1];
assign _121_ = _108_ & _112_;
assign _122_ = _108_ & read_adress_counter[1];
assign _123_ = _109_ & _112_;
assign _124_ = _109_ & read_adress_counter[1];
assign _125_ = _110_ & _112_;
assign _126_ = _110_ & read_adress_counter[1];
assign _127_ = _111_ & _112_;
assign _128_ = _111_ & read_adress_counter[1];
assign _129_ = ~ read_adress_counter[0];
assign _130_ = _113_ & _129_;
assign _131_ = _113_ & read_adress_counter[0];
assign _132_ = _114_ & _129_;
assign _133_ = _114_ & read_adress_counter[0];
assign _134_ = _115_ & _129_;
assign _135_ = _115_ & read_adress_counter[0];
assign _136_ = _116_ & _129_;
assign _137_ = _116_ & read_adress_counter[0];
assign _138_ = _117_ & _129_;
assign _139_ = _117_ & read_adress_counter[0];
assign _140_ = _118_ & _129_;
assign _141_ = _118_ & read_adress_counter[0];
assign _142_ = _119_ & _129_;
assign _143_ = _119_ & read_adress_counter[0];
assign _144_ = _120_ & _129_;
assign _145_ = _120_ & read_adress_counter[0];
assign _146_ = _121_ & _129_;
assign _147_ = _121_ & read_adress_counter[0];
assign _148_ = _122_ & _129_;
assign _149_ = _122_ & read_adress_counter[0];
assign _150_ = _123_ & _129_;
assign _151_ = _123_ & read_adress_counter[0];
assign _152_ = _124_ & _129_;
assign _153_ = _124_ & read_adress_counter[0];
assign _154_ = _125_ & _129_;
assign _155_ = _125_ & read_adress_counter[0];
assign _156_ = _126_ & _129_;
assign _157_ = _126_ & read_adress_counter[0];
assign _158_ = _127_ & _129_;
assign _159_ = _127_ & read_adress_counter[0];
assign _160_ = _128_ & _129_;
assign _161_ = _128_ & read_adress_counter[0];
assign _162_ = _130_ ? miso : data_reg[0];
assign _163_ = _131_ ? miso : data_reg[1];
assign _164_ = _132_ ? miso : data_reg[2];
assign _165_ = _133_ ? miso : data_reg[3];
assign _166_ = _134_ ? miso : data_reg[4];
assign _167_ = _135_ ? miso : data_reg[5];
assign _168_ = _136_ ? miso : data_reg[6];
assign _169_ = _137_ ? miso : data_reg[7];
assign _170_ = _138_ ? miso : data_reg[8];
assign _171_ = _139_ ? miso : data_reg[9];
assign _172_ = _140_ ? miso : data_reg[10];
assign _173_ = _141_ ? miso : data_reg[11];
assign _174_ = _142_ ? miso : data_reg[12];
assign _175_ = _143_ ? miso : data_reg[13];
assign _176_ = _144_ ? miso : data_reg[14];
assign _177_ = _145_ ? miso : data_reg[15];
assign _178_ = _146_ ? miso : data_reg[16];
assign _179_ = _147_ ? miso : data_reg[17];
assign _180_ = _148_ ? miso : data_reg[18];
assign _181_ = _149_ ? miso : data_reg[19];
assign _182_ = _150_ ? miso : data_reg[20];
assign _183_ = _151_ ? miso : data_reg[21];
assign _184_ = _152_ ? miso : data_reg[22];
assign _185_ = _153_ ? miso : data_reg[23];
assign _186_ = _154_ ? miso : data_reg[24];
assign _187_ = _155_ ? miso : data_reg[25];
assign _188_ = _156_ ? miso : data_reg[26];
assign _189_ = _157_ ? miso : data_reg[27];
assign _190_ = _158_ ? miso : data_reg[28];
assign _191_ = _159_ ? miso : data_reg[29];
assign _192_ = _160_ ? miso : data_reg[30];
assign _193_ = _161_ ? miso : data_reg[31];
assign _194_ = ~ read_adress_counter[4];
assign _195_ = ~ read_adress_counter[3];
assign _196_ = _194_ & _195_;
assign _197_ = _194_ & read_adress_counter[3];
assign _198_ = read_adress_counter[4] & _195_;
assign _199_ = read_adress_counter[4] & read_adress_counter[3];
assign _200_ = ~ read_adress_counter[2];
assign _201_ = _196_ & _200_;
assign _202_ = _196_ & read_adress_counter[2];
assign _203_ = _197_ & _200_;
assign _204_ = _197_ & read_adress_counter[2];
assign _205_ = _198_ & _200_;
assign _206_ = _198_ & read_adress_counter[2];
assign _207_ = _199_ & _200_;
assign _208_ = _199_ & read_adress_counter[2];
assign _209_ = ~ read_adress_counter[1];
assign _210_ = _201_ & _209_;
assign _211_ = _201_ & read_adress_counter[1];
assign _212_ = _202_ & _209_;
assign _213_ = _202_ & read_adress_counter[1];
assign _214_ = _203_ & _209_;
assign _215_ = _203_ & read_adress_counter[1];
assign _216_ = _204_ & _209_;
assign _217_ = _204_ & read_adress_counter[1];
assign _218_ = _205_ & _209_;
assign _219_ = _205_ & read_adress_counter[1];
assign _220_ = _206_ & _209_;
assign _221_ = _206_ & read_adress_counter[1];
assign _222_ = _207_ & _209_;
assign _223_ = _207_ & read_adress_counter[1];
assign _224_ = _208_ & _209_;
assign _225_ = _208_ & read_adress_counter[1];
assign _226_ = ~ read_adress_counter[0];
assign _227_ = _210_ & _226_;
assign _228_ = _210_ & read_adress_counter[0];
assign _229_ = _211_ & _226_;
assign _230_ = _211_ & read_adress_counter[0];
assign _231_ = _212_ & _226_;
assign _232_ = _212_ & read_adress_counter[0];
assign _233_ = _213_ & _226_;
assign _234_ = _213_ & read_adress_counter[0];
assign _235_ = _214_ & _226_;
assign _236_ = _214_ & read_adress_counter[0];
assign _237_ = _215_ & _226_;
assign _238_ = _215_ & read_adress_counter[0];
assign _239_ = _216_ & _226_;
assign _240_ = _216_ & read_adress_counter[0];
assign _241_ = _217_ & _226_;
assign _242_ = _217_ & read_adress_counter[0];
assign _243_ = _218_ & _226_;
assign _244_ = _218_ & read_adress_counter[0];
assign _245_ = _219_ & _226_;
assign _246_ = _219_ & read_adress_counter[0];
assign _247_ = _220_ & _226_;
assign _248_ = _220_ & read_adress_counter[0];
assign _249_ = _221_ & _226_;
assign _250_ = _221_ & read_adress_counter[0];
assign _251_ = _222_ & _226_;
assign _252_ = _222_ & read_adress_counter[0];
assign _253_ = _223_ & _226_;
assign _254_ = _223_ & read_adress_counter[0];
assign _255_ = _224_ & _226_;
assign _256_ = _224_ & read_adress_counter[0];
assign _257_ = _225_ & _226_;
assign _258_ = _225_ & read_adress_counter[0];
assign _259_ = _227_ ? miso : data_reg[0];
assign _260_ = _228_ ? miso : data_reg[1];
assign _261_ = _229_ ? miso : data_reg[2];
assign _262_ = _230_ ? miso : data_reg[3];
assign _263_ = _231_ ? miso : data_reg[4];
assign _264_ = _232_ ? miso : data_reg[5];
assign _265_ = _233_ ? miso : data_reg[6];
assign _266_ = _234_ ? miso : data_reg[7];
assign _267_ = _235_ ? miso : data_reg[8];
assign _268_ = _236_ ? miso : data_reg[9];
assign _269_ = _237_ ? miso : data_reg[10];
assign _270_ = _238_ ? miso : data_reg[11];
assign _271_ = _239_ ? miso : data_reg[12];
assign _272_ = _240_ ? miso : data_reg[13];
assign _273_ = _241_ ? miso : data_reg[14];
assign _274_ = _242_ ? miso : data_reg[15];
assign _275_ = _243_ ? miso : data_reg[16];
assign _276_ = _244_ ? miso : data_reg[17];
assign _277_ = _245_ ? miso : data_reg[18];
assign _278_ = _246_ ? miso : data_reg[19];
assign _279_ = _247_ ? miso : data_reg[20];
assign _280_ = _248_ ? miso : data_reg[21];
assign _281_ = _249_ ? miso : data_reg[22];
assign _282_ = _250_ ? miso : data_reg[23];
assign _283_ = _251_ ? miso : data_reg[24];
assign _284_ = _252_ ? miso : data_reg[25];
assign _285_ = _253_ ? miso : data_reg[26];
assign _286_ = _254_ ? miso : data_reg[27];
assign _287_ = _255_ ? miso : data_reg[28];
assign _288_ = _256_ ? miso : data_reg[29];
assign _289_ = _257_ ? miso : data_reg[30];
assign _291_ = _258_ ? miso : data_reg[31];
assign _303_ = read_adress_counter[4] ? _302_ : _300_;
assign _315_ = read_adress_counter[4] ? _314_ : _313_;
assign _290_ = currstate == 3'h0;
assign _301_ = ~ cs;
assign _312_ = _301_ ? mode_select : 1'h0;
assign data_reg = _066_;
assign mode_select_zw = _070_;
assign write_adress_counter = _073_;
assign read_adress_counter = _076_;
assign currstate = _077_;
assign sclk = clk;
assign mosi = _080_;
assign data_out = _083_;
assign data_valid = _086_;
endmodule
module tt_um_cejmu_riscv(clk, ena, rst_n, ui_in, uio_in, uo_out, uio_out, uio_oe);
wire _0_;
wire _1_;
wire [31:0] _2_;
wire [13:0] _3_;
wire _4_;
wire _5_;
wire [12:0] _6_;
wire _7_;
wire _8_;
wire [31:0] _9_;
input clk;
wire clk;
wire [13:0] cpu_addr_out;
wire data_valid;
input ena;
wire ena;
wire mem_req;
wire reset;
input rst_n;
wire rst_n;
wire [15:0] spi_addr_in;
wire [31:0] spi_data_in;
wire [31:0] spi_data_out;
input [7:0] ui_in;
wire [7:0] ui_in;
input [7:0] uio_in;
wire [7:0] uio_in;
output [7:0] uio_oe;
wire [7:0] uio_oe;
output [7:0] uio_out;
wire [7:0] uio_out;
output [7:0] uo_out;
wire [7:0] uo_out;
wire write_enable;
wire [12:0] x1;
assign _0_ = ~ rst_n;
cpu cpu_inst (
.addr_out(_3_),
.clk(clk),
.data_in(spi_data_out),
.data_out(_2_),
.data_valid(data_valid),
.mem_req(_5_),
.reset(reset),
.write_en(_4_),
.x1(_6_)
);
spi_master spi_master_inst (
.addr(spi_addr_in),
.clk(clk),
.cs(mem_req),
.data_in(spi_data_in),
.data_out(_9_),
.data_valid(_1_),
.miso(ui_in[0]),
.mode_select(write_enable),
.mosi(_8_),
.reset(reset),
.sclk(_7_)
);
assign write_enable = _4_;
assign cpu_addr_out = _3_;
assign spi_addr_in = { 2'h0, cpu_addr_out };
assign spi_data_out = _9_;
assign spi_data_in = _2_;
assign mem_req = _5_;
assign data_valid = _1_;
assign reset = _0_;
assign x1 = _6_;
assign uo_out = { x1[4:0], mem_req, _7_, _8_ };
assign uio_out = x1[12:5];
assign uio_oe = 8'hff;
endmodule
|
module cpu(clk, reset, data_in, data_valid, data_out, addr_out, write_en, mem_req, x1);
wire [31:0] _00_;
wire [31:0] _01_;
wire [12:0] _02_;
wire [31:0] _03_;
wire [31:0] _04_;
wire [6:0] _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire [31:0] _11_;
wire [31:0] _12_;
wire [31:0] _13_;
wire _14_;
wire _15_;
wire [15:0] _16_;
wire [15:0] _17_;
wire [15:0] _18_;
wire [13:0] _19_;
wire [31:0] _20_;
reg [31:0] _21_;
output [13:0] addr_out;
wire [13:0] addr_out;
wire [31:0] b;
input clk;
wire clk;
wire [6:0] control_flags_out;
input [31:0] data_in;
wire [31:0] data_in;
output [31:0] data_out;
wire [31:0] data_out;
input data_valid;
wire data_valid;
wire fetchflag;
wire [31:0] imm;
wire [16:0] instruction;
wire [31:0] iword_reg;
output mem_req;
wire mem_req;
wire memflag;
wire [15:0] pc_inc;
wire [15:0] pc_offset;
wire [15:0] pc_out;
wire pcflag;
wire [31:0] rd;
wire [31:0] rdalu;
input reset;
wire reset;
wire [31:0] rs1;
wire [31:0] rs2;
wire s0;
wire s1;
wire wbflag;
output write_en;
wire write_en;
output [12:0] x1;
wire [12:0] x1;
assign _11_ = control_flags_out[3] ? imm : rs2;
assign _12_ = control_flags_out[4] ? { 16'h0000, pc_inc } : _13_;
assign _13_ = control_flags_out[0] ? data_in : rdalu;
assign _14_ = control_flags_out[4] ? rdalu[16] : 1'h0;
assign _15_ = control_flags_out[4] ? rdalu[17] : 1'h1;
assign _18_ = control_flags_out[6] ? rs1[15:0] : imm[15:0];
assign _19_ = control_flags_out[5] ? pc_out[15:2] : rdalu[13:0];
assign _20_ = fetchflag ? data_in : iword_reg;
always @(posedge clk, posedge reset)
if (reset) _21_ <= 32'd0;
else _21_ <= _20_;
alu alu_inst (
.a(rs1),
.b(b),
.clk(clk),
.instruction(instruction),
.rd(_03_),
.reset(reset)
);
control control_inst (
.clk(clk),
.control_flags_out(_05_),
.data_valid(data_valid),
.fetchflag(_09_),
.imm(_04_),
.iword(iword_reg),
.mem_req(_10_),
.memflag(_07_),
.pcflag(_08_),
.reset(reset),
.wbflag(_06_)
);
instructioncounter instruction_inst (
.clk(clk),
.pc_inc(_16_),
.pc_new(_17_),
.pc_offset(pc_offset),
.pcflag(pcflag),
.reset(reset),
.s0(s0),
.s1(s1)
);
regs regs_inst (
.clk(clk),
.rd(rd),
.rdadr(iword_reg[11:7]),
.regwrite(wbflag),
.reset(reset),
.rs1(_00_),
.rs1adr(iword_reg[19:15]),
.rs2(_01_),
.rs2adr(iword_reg[24:20]),
.x1(_02_)
);
assign s0 = _14_;
assign s1 = _15_;
assign imm = _04_;
assign control_flags_out = _05_;
assign rs1 = _00_;
assign rs2 = _01_;
assign b = _11_;
assign rdalu = _03_;
assign rd = _12_;
assign wbflag = _06_;
assign memflag = _07_;
assign pcflag = _08_;
assign fetchflag = _09_;
assign instruction = { iword_reg[31:25], iword_reg[14:12], iword_reg[6:0] };
assign iword_reg = _21_;
assign pc_inc = _16_;
assign pc_out = _17_;
assign pc_offset = _18_;
assign data_out = rs2;
assign addr_out = _19_;
assign write_en = memflag;
assign mem_req = _10_;
assign x1 = _02_;
endmodule
|
tt06-finale_0004
|
tt06-finale
|
CEJMU-tt06_tinyrv1
|
task_instructioncounter
|
tt_um_cejmu_riscv
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/* Generated by Yosys 0.39+165 (git sha1 22c5ab90d, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */
module alu(clk, reset, a, b, instruction, rd);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire [31:0] _15_;
wire _16_;
wire _17_;
wire _18_;
wire _19_;
wire _20_;
wire [31:0] _21_;
wire _22_;
wire _23_;
wire _24_;
wire _25_;
wire _26_;
wire [31:0] _27_;
wire _28_;
wire _29_;
wire _30_;
wire _31_;
wire _32_;
wire _33_;
wire [1:0] _34_;
wire [31:0] _35_;
wire [31:0] _36_;
wire [31:0] _37_;
wire [31:0] _38_;
wire [31:0] _39_;
wire [31:0] _40_;
wire [31:0] _41_;
reg [31:0] _42_;
input [31:0] a;
wire [31:0] a;
input [31:0] b;
wire [31:0] b;
input clk;
wire clk;
input [16:0] instruction;
wire [16:0] instruction;
output [31:0] rd;
wire [31:0] rd;
input reset;
wire reset;
assign _00_ = instruction[16:10] == 7'h00;
assign _01_ = instruction[9:7] == 3'h0;
assign _02_ = _01_ & _00_;
assign _03_ = instruction[6:0] == 7'h33;
assign _04_ = _03_ & _02_;
assign _05_ = instruction[9:7] == 3'h0;
assign _06_ = instruction[6:0] == 7'h13;
assign _07_ = _06_ & _05_;
assign _08_ = _04_ | _07_;
assign _09_ = instruction[6:0] == 7'h23;
assign _10_ = instruction[6:0] == 7'h03;
assign _11_ = _09_ | _10_;
assign _12_ = instruction[9:7] == 3'h2;
assign _13_ = _12_ & _11_;
assign _14_ = _08_ | _13_;
assign _15_ = a + b;
assign _16_ = instruction[16:10] == 7'h00;
assign _17_ = instruction[9:7] == 3'h7;
assign _18_ = _17_ & _16_;
assign _19_ = instruction[6:0] == 7'h33;
assign _20_ = _19_ & _18_;
assign _21_ = a & b;
assign _22_ = instruction[16:10] == 7'h00;
assign _23_ = instruction[9:7] == 3'h4;
assign _24_ = _23_ & _22_;
assign _25_ = instruction[6:0] == 7'h33;
assign _26_ = _25_ & _24_;
assign _27_ = a ^ b;
assign _28_ = instruction[6:0] == 7'h6f;
assign _29_ = instruction[6:0] == 7'h67;
assign _30_ = instruction[6:0] == 7'h63;
assign _31_ = instruction[9:7] == 3'h1;
assign _32_ = _31_ & _30_;
assign _33_ = a == b;
assign _34_ = _33_ ? 2'h2 : 2'h0;
assign _35_ = _32_ ? { 14'h0000, _34_, 16'h0000 } : 32'd0;
assign _36_ = _29_ ? 32'd65536 : _35_;
assign _37_ = _28_ ? 32'd0 : _36_;
assign _38_ = _26_ ? _27_ : _37_;
assign _39_ = _20_ ? _21_ : _38_;
assign _40_ = _14_ ? _15_ : _39_;
assign _41_ = reset ? 32'd0 : _40_;
always @(posedge clk)
_42_ <= _41_;
assign rd = _42_;
endmodule
module control(clk, reset, iword, data_valid, imm, control_flags_out, wbflag, memflag, pcflag, fetchflag, mem_req);
wire _000_;
wire _001_;
wire _002_;
wire [2:0] _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire [2:0] _012_;
wire _013_;
wire [2:0] _014_;
wire [2:0] _015_;
wire [2:0] _016_;
wire [2:0] _017_;
wire [2:0] _018_;
wire [2:0] _019_;
wire [2:0] _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire [31:0] _066_;
wire _067_;
wire [31:0] _068_;
wire _069_;
wire [31:0] _070_;
wire _071_;
wire [31:0] _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
reg [2:0] _109_;
input clk;
wire clk;
wire [6:0] control_flags;
output [6:0] control_flags_out;
wire [6:0] control_flags_out;
wire [2:0] currstate;
input data_valid;
wire data_valid;
output fetchflag;
wire fetchflag;
output [31:0] imm;
wire [31:0] imm;
input [31:0] iword;
wire [31:0] iword;
output mem_req;
wire mem_req;
output memflag;
wire memflag;
output pcflag;
wire pcflag;
input reset;
wire reset;
wire [20:0] w31_to_w11;
output wbflag;
wire wbflag;
assign _000_ = currstate == 3'h0;
assign _001_ = currstate == 3'h5;
assign _002_ = currstate == 3'h1;
assign _003_ = data_valid ? 3'h6 : currstate;
assign _004_ = currstate == 3'h6;
assign _005_ = currstate == 3'h2;
assign _006_ = currstate == 3'h3;
assign _007_ = control_flags[0] & _006_;
assign _008_ = currstate == 3'h3;
assign _009_ = ~ control_flags[0];
assign _010_ = _009_ & _008_;
assign _011_ = currstate == 3'h4;
assign _012_ = _013_ ? 3'h5 : currstate;
assign _013_ = data_valid & _011_;
assign _014_ = _010_ ? 3'h5 : _012_;
assign _015_ = _007_ ? 3'h4 : _014_;
assign _016_ = _005_ ? 3'h3 : _015_;
assign _017_ = _004_ ? 3'h2 : _016_;
assign _018_ = _002_ ? _003_ : _017_;
assign _019_ = _001_ ? 3'h1 : _018_;
assign _020_ = _000_ ? 3'h1 : _019_;
assign _021_ = currstate == 3'h1;
assign _022_ = currstate == 3'h4;
assign _023_ = _021_ | _022_;
assign _024_ = ~ data_valid;
assign _025_ = _024_ & _023_;
assign _026_ = _025_ ? 1'h0 : 1'h1;
assign _027_ = currstate == 3'h3;
assign _028_ = ~ control_flags[0];
assign _029_ = _028_ & _027_;
assign _030_ = currstate == 3'h4;
assign _031_ = data_valid & _030_;
assign _032_ = _029_ | _031_;
assign _033_ = _032_ ? 1'h1 : 1'h0;
assign _034_ = currstate == 3'h3;
assign _035_ = control_flags[0] & _034_;
assign _036_ = control_flags[1] & _035_;
assign _037_ = currstate == 3'h4;
assign _038_ = control_flags[1] & _037_;
assign _039_ = _036_ | _038_;
assign _040_ = _039_ ? 1'h1 : 1'h0;
assign _041_ = currstate == 3'h4;
assign _042_ = control_flags[2] & _041_;
assign _043_ = data_valid & _042_;
assign _044_ = currstate == 3'h3;
assign _045_ = control_flags[2] & _044_;
assign _046_ = ~ control_flags[0];
assign _047_ = _046_ & _045_;
assign _048_ = _043_ | _047_;
assign _049_ = _048_ ? 1'h1 : 1'h0;
assign _050_ = currstate == 3'h1;
assign _051_ = data_valid & _050_;
assign _052_ = _051_ ? 1'h1 : 1'h0;
assign _053_ = currstate == 3'h1;
assign _054_ = currstate == 3'h0;
assign _055_ = _053_ | _054_;
assign _056_ = currstate == 3'h5;
assign _057_ = _055_ | _056_;
assign _058_ = _057_ ? 1'h1 : 1'h0;
assign _059_ = iword[6:0] == 7'h67;
assign _060_ = _059_ ? 1'h1 : 1'h0;
assign _061_ = iword[6:0] == 7'h03;
assign _062_ = iword[6:0] == 7'h13;
assign _063_ = _061_ | _062_;
assign _064_ = iword[6:0] == 7'h67;
assign _065_ = _063_ | _064_;
assign _066_ = _065_ ? { w31_to_w11, iword[30:20] } : _068_;
assign _067_ = iword[6:0] == 7'h23;
assign _068_ = _067_ ? { w31_to_w11, iword[30:25], iword[11:7] } : _070_;
assign _069_ = iword[6:0] == 7'h63;
assign _070_ = _069_ ? { w31_to_w11[20:1], iword[7], iword[30:25], iword[11:8], 1'h0 } : _072_;
assign _071_ = iword[6:0] == 7'h6f;
assign _072_ = _071_ ? { w31_to_w11[11:0], iword[19:12], iword[20], iword[30:21], 1'h0 } : 32'd0;
assign _073_ = iword[6:0] == 7'h03;
assign _074_ = iword[6:0] == 7'h23;
assign _075_ = _073_ | _074_;
assign _076_ = iword[14:12] == 3'h2;
assign _077_ = _076_ & _075_;
assign _078_ = _077_ ? 1'h1 : 1'h0;
assign _079_ = iword[6:0] == 7'h23;
assign _080_ = iword[14:12] == 3'h2;
assign _081_ = _080_ & _079_;
assign _082_ = _081_ ? 1'h1 : 1'h0;
assign _083_ = iword[6:0] == 7'h63;
assign _084_ = _083_ ? 1'h0 : 1'h1;
assign _085_ = iword[6:0] == 7'h13;
assign _086_ = iword[6:0] == 7'h37;
assign _087_ = _085_ | _086_;
assign _088_ = iword[6:0] == 7'h17;
assign _089_ = _087_ | _088_;
assign _090_ = iword[6:0] == 7'h03;
assign _091_ = iword[6:0] == 7'h23;
assign _092_ = _090_ | _091_;
assign _093_ = iword[14:12] == 3'h2;
assign _094_ = _093_ & _092_;
assign _095_ = _089_ | _094_;
assign _096_ = iword[6:0] == 7'h6f;
assign _097_ = _095_ | _096_;
assign _098_ = iword[6:0] == 7'h67;
assign _099_ = _097_ | _098_;
assign _100_ = _099_ ? 1'h1 : 1'h0;
assign _101_ = iword[6:0] == 7'h63;
assign _102_ = iword[6:0] == 7'h6f;
assign _103_ = _101_ | _102_;
assign _104_ = iword[6:0] == 7'h67;
assign _105_ = _103_ | _104_;
assign _106_ = iword[6:0] == 7'h67;
assign _107_ = _105_ | _106_;
assign _108_ = _107_ ? 1'h1 : 1'h0;
always @(posedge clk, posedge reset)
if (reset) _109_ <= 3'h0;
else _109_ <= _020_;
assign currstate = _109_;
assign control_flags = { _060_, _058_, _108_, _100_, _084_, _082_, _078_ };
assign w31_to_w11 = { iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31] };
assign imm = _066_;
assign control_flags_out = control_flags;
assign wbflag = _049_;
assign memflag = _040_;
assign pcflag = _033_;
assign fetchflag = _052_;
assign mem_req = _026_;
endmodule
module cpu(clk, reset, data_in, data_valid, data_out, addr_out, write_en, mem_req, x1);
wire [31:0] _00_;
wire [31:0] _01_;
wire [12:0] _02_;
wire [31:0] _03_;
wire [31:0] _04_;
wire [6:0] _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire [31:0] _11_;
wire [31:0] _12_;
wire [31:0] _13_;
wire _14_;
wire _15_;
wire [15:0] _16_;
wire [15:0] _17_;
wire [15:0] _18_;
wire [13:0] _19_;
wire [31:0] _20_;
reg [31:0] _21_;
output [13:0] addr_out;
wire [13:0] addr_out;
wire [31:0] b;
input clk;
wire clk;
wire [6:0] control_flags_out;
input [31:0] data_in;
wire [31:0] data_in;
output [31:0] data_out;
wire [31:0] data_out;
input data_valid;
wire data_valid;
wire fetchflag;
wire [31:0] imm;
wire [16:0] instruction;
wire [31:0] iword_reg;
output mem_req;
wire mem_req;
wire memflag;
wire [15:0] pc_inc;
wire [15:0] pc_offset;
wire [15:0] pc_out;
wire pcflag;
wire [31:0] rd;
wire [31:0] rdalu;
input reset;
wire reset;
wire [31:0] rs1;
wire [31:0] rs2;
wire s0;
wire s1;
wire wbflag;
output write_en;
wire write_en;
output [12:0] x1;
wire [12:0] x1;
assign _11_ = control_flags_out[3] ? imm : rs2;
assign _12_ = control_flags_out[4] ? { 16'h0000, pc_inc } : _13_;
assign _13_ = control_flags_out[0] ? data_in : rdalu;
assign _14_ = control_flags_out[4] ? rdalu[16] : 1'h0;
assign _15_ = control_flags_out[4] ? rdalu[17] : 1'h1;
assign _18_ = control_flags_out[6] ? rs1[15:0] : imm[15:0];
assign _19_ = control_flags_out[5] ? pc_out[15:2] : rdalu[13:0];
assign _20_ = fetchflag ? data_in : iword_reg;
always @(posedge clk, posedge reset)
if (reset) _21_ <= 32'd0;
else _21_ <= _20_;
alu alu_inst (
.a(rs1),
.b(b),
.clk(clk),
.instruction(instruction),
.rd(_03_),
.reset(reset)
);
control control_inst (
.clk(clk),
.control_flags_out(_05_),
.data_valid(data_valid),
.fetchflag(_09_),
.imm(_04_),
.iword(iword_reg),
.mem_req(_10_),
.memflag(_07_),
.pcflag(_08_),
.reset(reset),
.wbflag(_06_)
);
instructioncounter instruction_inst (
.clk(clk),
.pc_inc(_16_),
.pc_new(_17_),
.pc_offset(pc_offset),
.pcflag(pcflag),
.reset(reset),
.s0(s0),
.s1(s1)
);
regs regs_inst (
.clk(clk),
.rd(rd),
.rdadr(iword_reg[11:7]),
.regwrite(wbflag),
.reset(reset),
.rs1(_00_),
.rs1adr(iword_reg[19:15]),
.rs2(_01_),
.rs2adr(iword_reg[24:20]),
.x1(_02_)
);
assign s0 = _14_;
assign s1 = _15_;
assign imm = _04_;
assign control_flags_out = _05_;
assign rs1 = _00_;
assign rs2 = _01_;
assign b = _11_;
assign rdalu = _03_;
assign rd = _12_;
assign wbflag = _06_;
assign memflag = _07_;
assign pcflag = _08_;
assign fetchflag = _09_;
assign instruction = { iword_reg[31:25], iword_reg[14:12], iword_reg[6:0] };
assign iword_reg = _21_;
assign pc_inc = _16_;
assign pc_out = _17_;
assign pc_offset = _18_;
assign data_out = rs2;
assign addr_out = _19_;
assign write_en = memflag;
assign mem_req = _10_;
assign x1 = _02_;
endmodule
module instructioncounter(clk, reset, pcflag, s0, s1, pc_offset, pc_inc, pc_new);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module regs(clk, reset, rs1adr, rs2adr, rdadr, rd, regwrite, rs1, rs2, x1);
wire [31:0] _000_;
wire [31:0] _001_;
wire [31:0] _002_;
wire [31:0] _003_;
wire [31:0] _004_;
wire [31:0] _005_;
wire [31:0] _006_;
wire [31:0] _007_;
wire [31:0] _008_;
wire [31:0] _009_;
wire [31:0] _010_;
wire [31:0] _011_;
wire [31:0] _012_;
wire [31:0] _013_;
wire [31:0] _014_;
wire [31:0] _015_;
wire [31:0] _016_;
wire [31:0] _017_;
wire [31:0] _018_;
wire [31:0] _019_;
wire [31:0] _020_;
wire [31:0] _021_;
wire [31:0] _022_;
wire [31:0] _023_;
wire [31:0] _024_;
wire [31:0] _025_;
wire [31:0] _026_;
wire [31:0] _027_;
wire [31:0] _028_;
wire [31:0] _029_;
wire [31:0] _030_;
wire [31:0] _031_;
wire [31:0] _032_;
wire [31:0] _033_;
wire [31:0] _034_;
wire [31:0] _035_;
wire [31:0] _036_;
wire [31:0] _037_;
wire [31:0] _038_;
wire [31:0] _039_;
wire _040_;
wire _041_;
wire [4:0] _042_;
wire [4:0] _043_;
wire [4:0] _044_;
wire [1023:0] _045_;
reg [1023:0] _046_;
reg [31:0] _047_;
reg [31:0] _048_;
wire _049_;
wire [12:0] _050_;
reg [12:0] _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire [31:0] _117_;
wire [31:0] _118_;
wire [31:0] _119_;
wire [31:0] _120_;
wire [31:0] _121_;
wire [31:0] _122_;
wire [31:0] _123_;
wire [31:0] _124_;
wire [31:0] _125_;
wire [31:0] _126_;
wire [31:0] _127_;
wire [31:0] _128_;
wire [31:0] _129_;
wire [31:0] _130_;
wire [31:0] _131_;
wire [31:0] _132_;
wire [31:0] _133_;
wire [31:0] _134_;
wire [31:0] _135_;
wire [31:0] _136_;
wire [31:0] _137_;
wire [31:0] _138_;
wire [31:0] _139_;
wire [31:0] _140_;
wire [31:0] _141_;
wire [31:0] _142_;
wire [31:0] _143_;
wire [31:0] _144_;
wire [31:0] _145_;
wire [31:0] _146_;
wire [31:0] _147_;
wire [31:0] _148_;
wire [31:0] _149_;
wire [31:0] _150_;
wire [31:0] _151_;
wire [31:0] _152_;
wire [31:0] _153_;
wire [31:0] _154_;
wire [31:0] _155_;
wire [31:0] _156_;
wire [31:0] _157_;
wire [31:0] _158_;
wire [31:0] _159_;
wire [31:0] _160_;
wire [31:0] _161_;
wire [31:0] _162_;
wire [31:0] _163_;
wire [31:0] _164_;
wire [31:0] _165_;
wire [31:0] _166_;
wire [31:0] _167_;
wire [31:0] _168_;
wire [31:0] _169_;
wire [31:0] _170_;
input clk;
wire clk;
input [31:0] rd;
wire [31:0] rd;
input [4:0] rdadr;
wire [4:0] rdadr;
wire [1023:0] registers;
input regwrite;
wire regwrite;
input reset;
wire reset;
output [31:0] rs1;
wire [31:0] rs1;
input [4:0] rs1adr;
wire [4:0] rs1adr;
output [31:0] rs2;
wire [31:0] rs2;
input [4:0] rs2adr;
wire [4:0] rs2adr;
output [12:0] x1;
wire [12:0] x1;
assign _000_ = _043_[0] ? registers[63:32] : registers[31:0];
assign _001_ = _043_[0] ? registers[191:160] : registers[159:128];
assign _002_ = _043_[0] ? registers[319:288] : registers[287:256];
assign _003_ = _043_[0] ? registers[447:416] : registers[415:384];
assign _004_ = _043_[0] ? registers[575:544] : registers[543:512];
assign _005_ = _043_[0] ? registers[703:672] : registers[671:640];
assign _006_ = _043_[0] ? registers[831:800] : registers[799:768];
assign _007_ = _043_[0] ? registers[959:928] : registers[927:896];
assign _008_ = _043_[2] ? _150_ : _149_;
assign _009_ = _043_[2] ? _154_ : _153_;
assign _010_ = _044_[0] ? registers[63:32] : registers[31:0];
assign _011_ = _044_[0] ? registers[191:160] : registers[159:128];
assign _012_ = _044_[0] ? registers[319:288] : registers[287:256];
assign _013_ = _044_[0] ? registers[447:416] : registers[415:384];
assign _014_ = _044_[0] ? registers[575:544] : registers[543:512];
assign _015_ = _044_[0] ? registers[703:672] : registers[671:640];
assign _016_ = _044_[0] ? registers[831:800] : registers[799:768];
assign _017_ = _044_[0] ? registers[959:928] : registers[927:896];
assign _018_ = _044_[2] ? _161_ : _160_;
assign _019_ = _044_[2] ? _165_ : _164_;
assign _020_ = _043_[0] ? registers[127:96] : registers[95:64];
assign _021_ = _043_[0] ? registers[255:224] : registers[223:192];
assign _022_ = _043_[0] ? registers[383:352] : registers[351:320];
assign _023_ = _043_[0] ? registers[511:480] : registers[479:448];
assign _024_ = _043_[0] ? registers[639:608] : registers[607:576];
assign _025_ = _043_[0] ? registers[767:736] : registers[735:704];
assign _026_ = _043_[0] ? registers[895:864] : registers[863:832];
assign _027_ = _043_[0] ? registers[1023:992] : registers[991:960];
assign _028_ = _043_[2] ? _152_ : _151_;
assign _029_ = _043_[2] ? _156_ : _155_;
assign _030_ = _044_[0] ? registers[127:96] : registers[95:64];
assign _031_ = _044_[0] ? registers[255:224] : registers[223:192];
assign _032_ = _044_[0] ? registers[383:352] : registers[351:320];
assign _033_ = _044_[0] ? registers[511:480] : registers[479:448];
assign _034_ = _044_[0] ? registers[639:608] : registers[607:576];
assign _035_ = _044_[0] ? registers[767:736] : registers[735:704];
assign _036_ = _044_[0] ? registers[895:864] : registers[863:832];
assign _037_ = _044_[0] ? registers[1023:992] : registers[991:960];
assign _038_ = _044_[2] ? _163_ : _162_;
assign _039_ = _044_[2] ? _167_ : _166_;
assign _149_ = _043_[1] ? _020_ : _000_;
assign _150_ = _043_[1] ? _021_ : _001_;
assign _151_ = _043_[1] ? _022_ : _002_;
assign _152_ = _043_[1] ? _023_ : _003_;
assign _153_ = _043_[1] ? _024_ : _004_;
assign _154_ = _043_[1] ? _025_ : _005_;
assign _155_ = _043_[1] ? _026_ : _006_;
assign _156_ = _043_[1] ? _027_ : _007_;
assign _157_ = _043_[3] ? _028_ : _008_;
assign _158_ = _043_[3] ? _029_ : _009_;
assign _160_ = _044_[1] ? _030_ : _010_;
assign _161_ = _044_[1] ? _031_ : _011_;
assign _162_ = _044_[1] ? _032_ : _012_;
assign _163_ = _044_[1] ? _033_ : _013_;
assign _164_ = _044_[1] ? _034_ : _014_;
assign _165_ = _044_[1] ? _035_ : _015_;
assign _166_ = _044_[1] ? _036_ : _016_;
assign _167_ = _044_[1] ? _037_ : _017_;
assign _168_ = _044_[3] ? _038_ : _018_;
assign _169_ = _044_[3] ? _039_ : _019_;
assign _170_ = _044_[4] ? _169_ : _168_;
assign _040_ = rdadr != 5'h00;
assign _041_ = _040_ & regwrite;
assign _042_ = 5'h1f - rdadr;
assign _043_ = 5'h1f - rs1adr;
assign _044_ = 5'h1f - rs2adr;
assign _045_ = _041_ ? { _148_, _147_, _146_, _145_, _144_, _143_, _142_, _141_, _140_, _139_, _138_, _137_, _136_, _135_, _134_, _133_, _132_, _131_, _130_, _129_, _128_, _127_, _126_, _125_, _124_, _123_, _122_, _121_, _120_, _119_, _118_, _117_ } : registers;
always @(posedge clk, posedge reset)
if (reset) _046_ <= 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
else _046_ <= _045_;
always @(posedge clk, posedge reset)
if (reset) _047_ <= 32'd0;
else _047_ <= _159_;
always @(posedge clk, posedge reset)
if (reset) _048_ <= 32'd0;
else _048_ <= _170_;
assign _049_ = ~ reset;
assign _050_ = _049_ ? registers[972:960] : _051_;
always @(posedge clk)
_051_ <= _050_;
assign _052_ = ~ _042_[4];
assign _053_ = ~ _042_[3];
assign _054_ = _052_ & _053_;
assign _055_ = _052_ & _042_[3];
assign _056_ = _042_[4] & _053_;
assign _057_ = _042_[4] & _042_[3];
assign _058_ = ~ _042_[2];
assign _059_ = _054_ & _058_;
assign _060_ = _054_ & _042_[2];
assign _061_ = _055_ & _058_;
assign _062_ = _055_ & _042_[2];
assign _063_ = _056_ & _058_;
assign _064_ = _056_ & _042_[2];
assign _065_ = _057_ & _058_;
assign _066_ = _057_ & _042_[2];
assign _067_ = ~ _042_[1];
assign _068_ = _059_ & _067_;
assign _069_ = _059_ & _042_[1];
assign _070_ = _060_ & _067_;
assign _071_ = _060_ & _042_[1];
assign _072_ = _061_ & _067_;
assign _073_ = _061_ & _042_[1];
assign _074_ = _062_ & _067_;
assign _075_ = _062_ & _042_[1];
assign _076_ = _063_ & _067_;
assign _077_ = _063_ & _042_[1];
assign _078_ = _064_ & _067_;
assign _079_ = _064_ & _042_[1];
assign _080_ = _065_ & _067_;
assign _081_ = _065_ & _042_[1];
assign _082_ = _066_ & _067_;
assign _083_ = _066_ & _042_[1];
assign _084_ = ~ _042_[0];
assign _085_ = _068_ & _084_;
assign _086_ = _068_ & _042_[0];
assign _087_ = _069_ & _084_;
assign _088_ = _069_ & _042_[0];
assign _089_ = _070_ & _084_;
assign _090_ = _070_ & _042_[0];
assign _091_ = _071_ & _084_;
assign _092_ = _071_ & _042_[0];
assign _093_ = _072_ & _084_;
assign _094_ = _072_ & _042_[0];
assign _095_ = _073_ & _084_;
assign _096_ = _073_ & _042_[0];
assign _097_ = _074_ & _084_;
assign _098_ = _074_ & _042_[0];
assign _099_ = _075_ & _084_;
assign _100_ = _075_ & _042_[0];
assign _101_ = _076_ & _084_;
assign _102_ = _076_ & _042_[0];
assign _103_ = _077_ & _084_;
assign _104_ = _077_ & _042_[0];
assign _105_ = _078_ & _084_;
assign _106_ = _078_ & _042_[0];
assign _107_ = _079_ & _084_;
assign _108_ = _079_ & _042_[0];
assign _109_ = _080_ & _084_;
assign _110_ = _080_ & _042_[0];
assign _111_ = _081_ & _084_;
assign _112_ = _081_ & _042_[0];
assign _113_ = _082_ & _084_;
assign _114_ = _082_ & _042_[0];
assign _115_ = _083_ & _084_;
assign _116_ = _083_ & _042_[0];
assign _117_ = _085_ ? rd : registers[31:0];
assign _118_ = _086_ ? rd : registers[63:32];
assign _119_ = _087_ ? rd : registers[95:64];
assign _120_ = _088_ ? rd : registers[127:96];
assign _121_ = _089_ ? rd : registers[159:128];
assign _122_ = _090_ ? rd : registers[191:160];
assign _123_ = _091_ ? rd : registers[223:192];
assign _124_ = _092_ ? rd : registers[255:224];
assign _125_ = _093_ ? rd : registers[287:256];
assign _126_ = _094_ ? rd : registers[319:288];
assign _127_ = _095_ ? rd : registers[351:320];
assign _128_ = _096_ ? rd : registers[383:352];
assign _129_ = _097_ ? rd : registers[415:384];
assign _130_ = _098_ ? rd : registers[447:416];
assign _131_ = _099_ ? rd : registers[479:448];
assign _132_ = _100_ ? rd : registers[511:480];
assign _133_ = _101_ ? rd : registers[543:512];
assign _134_ = _102_ ? rd : registers[575:544];
assign _135_ = _103_ ? rd : registers[607:576];
assign _136_ = _104_ ? rd : registers[639:608];
assign _137_ = _105_ ? rd : registers[671:640];
assign _138_ = _106_ ? rd : registers[703:672];
assign _139_ = _107_ ? rd : registers[735:704];
assign _140_ = _108_ ? rd : registers[767:736];
assign _141_ = _109_ ? rd : registers[799:768];
assign _142_ = _110_ ? rd : registers[831:800];
assign _143_ = _111_ ? rd : registers[863:832];
assign _144_ = _112_ ? rd : registers[895:864];
assign _145_ = _113_ ? rd : registers[927:896];
assign _146_ = _114_ ? rd : registers[959:928];
assign _147_ = _115_ ? rd : registers[991:960];
assign _148_ = _116_ ? rd : registers[1023:992];
assign _159_ = _043_[4] ? _158_ : _157_;
assign registers = _046_;
assign rs1 = _047_;
assign rs2 = _048_;
assign x1 = _051_;
endmodule
module spi_master(clk, mode_select, reset, miso, cs, data_in, addr, sclk, mosi, data_out, data_valid);
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire [31:0] _060_;
wire [31:0] _061_;
wire [31:0] _062_;
wire [2:0] _063_;
wire _064_;
wire [31:0] _065_;
reg [31:0] _066_;
wire _067_;
wire _068_;
wire _069_;
reg _070_;
wire _071_;
wire [31:0] _072_;
reg [31:0] _073_ = 32'd16;
wire _074_;
wire [31:0] _075_;
reg [31:0] _076_ = 32'd33;
reg [2:0] _077_;
wire _078_;
wire _079_;
reg _080_;
wire _081_;
wire [31:0] _082_;
reg [31:0] _083_;
wire _084_;
wire _085_;
reg _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
wire _203_;
wire _204_;
wire _205_;
wire _206_;
wire _207_;
wire _208_;
wire _209_;
wire _210_;
wire _211_;
wire _212_;
wire _213_;
wire _214_;
wire _215_;
wire _216_;
wire _217_;
wire _218_;
wire _219_;
wire _220_;
wire _221_;
wire _222_;
wire _223_;
wire _224_;
wire _225_;
wire _226_;
wire _227_;
wire _228_;
wire _229_;
wire _230_;
wire _231_;
wire _232_;
wire _233_;
wire _234_;
wire _235_;
wire _236_;
wire _237_;
wire _238_;
wire _239_;
wire _240_;
wire _241_;
wire _242_;
wire _243_;
wire _244_;
wire _245_;
wire _246_;
wire _247_;
wire _248_;
wire _249_;
wire _250_;
wire _251_;
wire _252_;
wire _253_;
wire _254_;
wire _255_;
wire _256_;
wire _257_;
wire _258_;
wire _259_;
wire _260_;
wire _261_;
wire _262_;
wire _263_;
wire _264_;
wire _265_;
wire _266_;
wire _267_;
wire _268_;
wire _269_;
wire _270_;
wire _271_;
wire _272_;
wire _273_;
wire _274_;
wire _275_;
wire _276_;
wire _277_;
wire _278_;
wire _279_;
wire _280_;
wire _281_;
wire _282_;
wire _283_;
wire _284_;
wire _285_;
wire _286_;
wire _287_;
wire _288_;
wire _289_;
wire _290_;
wire _291_;
wire _292_;
wire _293_;
wire _294_;
wire _295_;
wire _296_;
wire _297_;
wire _298_;
wire _299_;
wire _300_;
wire _301_;
wire _302_;
wire _303_;
wire _304_;
wire _305_;
wire _306_;
wire _307_;
wire _308_;
wire _309_;
wire _310_;
wire _311_;
wire _312_;
wire _313_;
wire _314_;
wire _315_;
wire [2:0] _316_;
wire _317_;
wire _318_;
wire [31:0] _319_;
wire _320_;
wire _321_;
wire _322_;
wire [31:0] _323_;
wire _324_;
wire [2:0] _325_;
wire [2:0] _326_;
wire _327_;
wire [31:0] _328_;
wire [2:0] _329_;
wire _330_;
wire [31:0] _331_;
wire [2:0] _332_;
wire _333_;
wire _334_;
wire [31:0] _335_;
wire _336_;
wire [31:0] _337_;
wire [31:0] _338_;
wire [31:0] _339_;
wire [2:0] _340_;
wire [31:0] _341_;
wire [31:0] _342_;
wire [2:0] _343_;
wire _344_;
wire _345_;
wire [31:0] _346_;
wire _347_;
wire [31:0] _348_;
wire _349_;
wire [31:0] _350_;
wire [2:0] _351_;
wire _352_;
wire [31:0] _353_;
wire [2:0] _354_;
wire _355_;
wire [31:0] _356_;
wire _357_;
wire [2:0] _358_;
wire _359_;
wire [31:0] _360_;
wire _361_;
wire [31:0] _362_;
wire [2:0] _363_;
wire _364_;
wire [31:0] _365_;
wire _366_;
wire [31:0] _367_;
wire [31:0] _368_;
wire [2:0] _369_;
wire _370_;
wire [31:0] _371_;
wire _372_;
wire [31:0] _373_;
wire [31:0] _374_;
wire [31:0] _375_;
wire [2:0] _376_;
wire _377_;
wire [31:0] _378_;
wire _379_;
input [15:0] addr;
wire [15:0] addr;
input clk;
wire clk;
input cs;
wire cs;
wire [2:0] currstate;
input [31:0] data_in;
wire [31:0] data_in;
output [31:0] data_out;
wire [31:0] data_out;
wire [31:0] data_reg;
output data_valid;
wire data_valid;
input miso;
wire miso;
input mode_select;
wire mode_select;
wire mode_select_zw;
output mosi;
wire mosi;
wire [31:0] read_adress_counter;
input reset;
wire reset;
output sclk;
wire sclk;
wire [31:0] write_adress_counter;
assign _000_ = write_adress_counter[0] ? addr[1] : addr[0];
assign _001_ = write_adress_counter[0] ? addr[5] : addr[4];
assign _002_ = write_adress_counter[0] ? addr[9] : addr[8];
assign _003_ = write_adress_counter[0] ? addr[13] : addr[12];
assign _004_ = write_adress_counter[2] ? _088_ : _087_;
assign _005_ = write_adress_counter[0] ? addr[1] : addr[0];
assign _006_ = write_adress_counter[0] ? addr[5] : addr[4];
assign _007_ = write_adress_counter[0] ? addr[9] : addr[8];
assign _008_ = write_adress_counter[0] ? addr[13] : addr[12];
assign _009_ = write_adress_counter[2] ? _093_ : _092_;
assign _010_ = read_adress_counter[0] ? data_in[1] : data_in[0];
assign _011_ = read_adress_counter[0] ? data_in[5] : data_in[4];
assign _012_ = read_adress_counter[0] ? data_in[9] : data_in[8];
assign _013_ = read_adress_counter[0] ? data_in[13] : data_in[12];
assign _014_ = read_adress_counter[0] ? data_in[17] : data_in[16];
assign _015_ = read_adress_counter[0] ? data_in[21] : data_in[20];
assign _016_ = read_adress_counter[0] ? data_in[25] : data_in[24];
assign _017_ = read_adress_counter[0] ? data_in[29] : data_in[28];
assign _018_ = read_adress_counter[2] ? _293_ : _292_;
assign _019_ = read_adress_counter[2] ? _297_ : _296_;
assign _020_ = read_adress_counter[0] ? data_in[1] : data_in[0];
assign _021_ = read_adress_counter[0] ? data_in[5] : data_in[4];
assign _022_ = read_adress_counter[0] ? data_in[9] : data_in[8];
assign _023_ = read_adress_counter[0] ? data_in[13] : data_in[12];
assign _024_ = read_adress_counter[0] ? data_in[17] : data_in[16];
assign _025_ = read_adress_counter[0] ? data_in[21] : data_in[20];
assign _026_ = read_adress_counter[0] ? data_in[25] : data_in[24];
assign _027_ = read_adress_counter[0] ? data_in[29] : data_in[28];
assign _028_ = read_adress_counter[2] ? _305_ : _304_;
assign _029_ = read_adress_counter[2] ? _309_ : _308_;
assign _030_ = write_adress_counter[0] ? addr[3] : addr[2];
assign _031_ = write_adress_counter[0] ? addr[7] : addr[6];
assign _032_ = write_adress_counter[0] ? addr[11] : addr[10];
assign _033_ = write_adress_counter[0] ? addr[15] : addr[14];
assign _034_ = write_adress_counter[2] ? _090_ : _089_;
assign _035_ = write_adress_counter[0] ? addr[3] : addr[2];
assign _036_ = write_adress_counter[0] ? addr[7] : addr[6];
assign _037_ = write_adress_counter[0] ? addr[11] : addr[10];
assign _038_ = write_adress_counter[0] ? addr[15] : addr[14];
assign _039_ = write_adress_counter[2] ? _095_ : _094_;
assign _040_ = read_adress_counter[0] ? data_in[3] : data_in[2];
assign _041_ = read_adress_counter[0] ? data_in[7] : data_in[6];
assign _042_ = read_adress_counter[0] ? data_in[11] : data_in[10];
assign _043_ = read_adress_counter[0] ? data_in[15] : data_in[14];
assign _044_ = read_adress_counter[0] ? data_in[19] : data_in[18];
assign _045_ = read_adress_counter[0] ? data_in[23] : data_in[22];
assign _046_ = read_adress_counter[0] ? data_in[27] : data_in[26];
assign _047_ = read_adress_counter[0] ? data_in[31] : data_in[30];
assign _048_ = read_adress_counter[2] ? _295_ : _294_;
assign _049_ = read_adress_counter[2] ? _299_ : _298_;
assign _050_ = read_adress_counter[0] ? data_in[3] : data_in[2];
assign _051_ = read_adress_counter[0] ? data_in[7] : data_in[6];
assign _052_ = read_adress_counter[0] ? data_in[11] : data_in[10];
assign _053_ = read_adress_counter[0] ? data_in[15] : data_in[14];
assign _054_ = read_adress_counter[0] ? data_in[19] : data_in[18];
assign _055_ = read_adress_counter[0] ? data_in[23] : data_in[22];
assign _056_ = read_adress_counter[0] ? data_in[27] : data_in[26];
assign _057_ = read_adress_counter[0] ? data_in[31] : data_in[30];
assign _058_ = read_adress_counter[2] ? _307_ : _306_;
assign _059_ = read_adress_counter[2] ? _311_ : _310_;
assign _087_ = write_adress_counter[1] ? _030_ : _000_;
assign _088_ = write_adress_counter[1] ? _031_ : _001_;
assign _089_ = write_adress_counter[1] ? _032_ : _002_;
assign _090_ = write_adress_counter[1] ? _033_ : _003_;
assign _091_ = write_adress_counter[3] ? _034_ : _004_;
assign _092_ = write_adress_counter[1] ? _035_ : _005_;
assign _093_ = write_adress_counter[1] ? _036_ : _006_;
assign _094_ = write_adress_counter[1] ? _037_ : _007_;
assign _095_ = write_adress_counter[1] ? _038_ : _008_;
assign _096_ = write_adress_counter[3] ? _039_ : _009_;
assign _292_ = read_adress_counter[1] ? _040_ : _010_;
assign _293_ = read_adress_counter[1] ? _041_ : _011_;
assign _294_ = read_adress_counter[1] ? _042_ : _012_;
assign _295_ = read_adress_counter[1] ? _043_ : _013_;
assign _296_ = read_adress_counter[1] ? _044_ : _014_;
assign _297_ = read_adress_counter[1] ? _045_ : _015_;
assign _298_ = read_adress_counter[1] ? _046_ : _016_;
assign _299_ = read_adress_counter[1] ? _047_ : _017_;
assign _300_ = read_adress_counter[3] ? _048_ : _018_;
assign _302_ = read_adress_counter[3] ? _049_ : _019_;
assign _304_ = read_adress_counter[1] ? _050_ : _020_;
assign _305_ = read_adress_counter[1] ? _051_ : _021_;
assign _306_ = read_adress_counter[1] ? _052_ : _022_;
assign _307_ = read_adress_counter[1] ? _053_ : _023_;
assign _308_ = read_adress_counter[1] ? _054_ : _024_;
assign _309_ = read_adress_counter[1] ? _055_ : _025_;
assign _310_ = read_adress_counter[1] ? _056_ : _026_;
assign _311_ = read_adress_counter[1] ? _057_ : _027_;
assign _313_ = read_adress_counter[3] ? _058_ : _028_;
assign _314_ = read_adress_counter[3] ? _059_ : _029_;
assign _316_ = _301_ ? 3'h1 : currstate;
assign _317_ = currstate == 3'h1;
assign _318_ = write_adress_counter == 32'd16;
assign _319_ = write_adress_counter - 32'd1;
assign _320_ = $signed(write_adress_counter) > $signed(32'd0);
assign _321_ = $signed(write_adress_counter) <= $signed(32'd15);
assign _322_ = _321_ & _320_;
assign _323_ = write_adress_counter - 32'd1;
assign _324_ = ~ mode_select_zw;
assign _325_ = mode_select_zw ? 3'h2 : currstate;
assign _326_ = _324_ ? 3'h3 : _325_;
assign _327_ = _322_ ? _091_ : _096_;
assign _328_ = _322_ ? _323_ : write_adress_counter;
assign _329_ = _322_ ? currstate : _326_;
assign _330_ = _318_ ? mode_select_zw : _327_;
assign _331_ = _318_ ? _319_ : _328_;
assign _332_ = _318_ ? currstate : _329_;
assign _333_ = currstate == 3'h3;
assign _334_ = $signed(read_adress_counter) >= $signed(32'd32);
assign _335_ = read_adress_counter - 32'd1;
assign _336_ = $signed(read_adress_counter) > $signed(32'd0);
assign _337_ = read_adress_counter - 32'd1;
assign _338_ = _336_ ? { _193_, _192_, _191_, _190_, _189_, _188_, _187_, _186_, _185_, _184_, _183_, _182_, _181_, _180_, _179_, _178_, _177_, _176_, _175_, _174_, _173_, _172_, _171_, _170_, _169_, _168_, _167_, _166_, _165_, _164_, _163_, _162_ } : { _291_, _289_, _288_, _287_, _286_, _285_, _284_, _283_, _282_, _281_, _280_, _279_, _278_, _277_, _276_, _275_, _274_, _273_, _272_, _271_, _270_, _269_, _268_, _267_, _266_, _265_, _264_, _263_, _262_, _261_, _260_, _259_ };
assign _339_ = _336_ ? _337_ : read_adress_counter;
assign _340_ = _336_ ? currstate : 3'h4;
assign _341_ = _334_ ? data_reg : _338_;
assign _342_ = _334_ ? _335_ : _339_;
assign _343_ = _334_ ? currstate : _340_;
assign _344_ = currstate == 3'h2;
assign _345_ = $signed(read_adress_counter) >= $signed(32'd32);
assign _346_ = read_adress_counter - 32'd1;
assign _347_ = $signed(read_adress_counter) > $signed(32'd0);
assign _348_ = read_adress_counter - 32'd1;
assign _349_ = _347_ ? _303_ : _315_;
assign _350_ = _347_ ? _348_ : read_adress_counter;
assign _351_ = _347_ ? currstate : 3'h4;
assign _352_ = _345_ ? _080_ : _349_;
assign _353_ = _345_ ? _346_ : _350_;
assign _354_ = _345_ ? currstate : _351_;
assign _355_ = currstate == 3'h4;
assign _356_ = _355_ ? data_reg : _083_;
assign _357_ = _355_ ? 1'h1 : _086_;
assign _358_ = _355_ ? 3'h0 : currstate;
assign _359_ = _344_ ? _352_ : _080_;
assign _360_ = _344_ ? _083_ : _356_;
assign _361_ = _344_ ? _086_ : _357_;
assign _362_ = _344_ ? _353_ : read_adress_counter;
assign _363_ = _344_ ? _354_ : _358_;
assign _364_ = _333_ ? _080_ : _359_;
assign _365_ = _333_ ? _083_ : _360_;
assign _366_ = _333_ ? _086_ : _361_;
assign _367_ = _333_ ? _341_ : data_reg;
assign _368_ = _333_ ? _342_ : _362_;
assign _369_ = _333_ ? _343_ : _363_;
assign _370_ = _317_ ? _330_ : _364_;
assign _371_ = _317_ ? _083_ : _365_;
assign _372_ = _317_ ? _086_ : _366_;
assign _373_ = _317_ ? data_reg : _367_;
assign _374_ = _317_ ? _331_ : write_adress_counter;
assign _375_ = _317_ ? read_adress_counter : _368_;
assign _376_ = _317_ ? _332_ : _369_;
assign _377_ = _290_ ? 1'h0 : _370_;
assign _378_ = _290_ ? 32'd0 : _371_;
assign _379_ = _290_ ? 1'h0 : _372_;
assign _060_ = _290_ ? 32'd0 : _373_;
assign _061_ = _290_ ? 32'd16 : _374_;
assign _062_ = _290_ ? 32'd33 : _375_;
assign _063_ = _290_ ? _316_ : _376_;
assign _064_ = ~ reset;
assign _065_ = _064_ ? _060_ : data_reg;
always @(posedge clk)
_066_ <= _065_;
assign _067_ = ~ reset;
assign _068_ = _290_ & _067_;
assign _069_ = _068_ ? _312_ : mode_select_zw;
always @(posedge clk)
_070_ <= _069_;
assign _071_ = ~ reset;
assign _072_ = _071_ ? _061_ : write_adress_counter;
always @(posedge clk)
_073_ <= _072_;
assign _074_ = ~ reset;
assign _075_ = _074_ ? _062_ : read_adress_counter;
always @(posedge clk)
_076_ <= _075_;
always @(posedge clk, posedge reset)
if (reset) _077_ <= 3'h0;
else _077_ <= _063_;
assign _078_ = ~ reset;
assign _079_ = _078_ ? _377_ : _080_;
always @(posedge clk)
_080_ <= _079_;
assign _081_ = ~ reset;
assign _082_ = _081_ ? _378_ : _083_;
always @(posedge clk)
_083_ <= _082_;
assign _084_ = ~ reset;
assign _085_ = _084_ ? _379_ : _086_;
always @(posedge clk)
_086_ <= _085_;
assign _097_ = ~ read_adress_counter[4];
assign _098_ = ~ read_adress_counter[3];
assign _099_ = _097_ & _098_;
assign _100_ = _097_ & read_adress_counter[3];
assign _101_ = read_adress_counter[4] & _098_;
assign _102_ = read_adress_counter[4] & read_adress_counter[3];
assign _103_ = ~ read_adress_counter[2];
assign _104_ = _099_ & _103_;
assign _105_ = _099_ & read_adress_counter[2];
assign _106_ = _100_ & _103_;
assign _107_ = _100_ & read_adress_counter[2];
assign _108_ = _101_ & _103_;
assign _109_ = _101_ & read_adress_counter[2];
assign _110_ = _102_ & _103_;
assign _111_ = _102_ & read_adress_counter[2];
assign _112_ = ~ read_adress_counter[1];
assign _113_ = _104_ & _112_;
assign _114_ = _104_ & read_adress_counter[1];
assign _115_ = _105_ & _112_;
assign _116_ = _105_ & read_adress_counter[1];
assign _117_ = _106_ & _112_;
assign _118_ = _106_ & read_adress_counter[1];
assign _119_ = _107_ & _112_;
assign _120_ = _107_ & read_adress_counter[1];
assign _121_ = _108_ & _112_;
assign _122_ = _108_ & read_adress_counter[1];
assign _123_ = _109_ & _112_;
assign _124_ = _109_ & read_adress_counter[1];
assign _125_ = _110_ & _112_;
assign _126_ = _110_ & read_adress_counter[1];
assign _127_ = _111_ & _112_;
assign _128_ = _111_ & read_adress_counter[1];
assign _129_ = ~ read_adress_counter[0];
assign _130_ = _113_ & _129_;
assign _131_ = _113_ & read_adress_counter[0];
assign _132_ = _114_ & _129_;
assign _133_ = _114_ & read_adress_counter[0];
assign _134_ = _115_ & _129_;
assign _135_ = _115_ & read_adress_counter[0];
assign _136_ = _116_ & _129_;
assign _137_ = _116_ & read_adress_counter[0];
assign _138_ = _117_ & _129_;
assign _139_ = _117_ & read_adress_counter[0];
assign _140_ = _118_ & _129_;
assign _141_ = _118_ & read_adress_counter[0];
assign _142_ = _119_ & _129_;
assign _143_ = _119_ & read_adress_counter[0];
assign _144_ = _120_ & _129_;
assign _145_ = _120_ & read_adress_counter[0];
assign _146_ = _121_ & _129_;
assign _147_ = _121_ & read_adress_counter[0];
assign _148_ = _122_ & _129_;
assign _149_ = _122_ & read_adress_counter[0];
assign _150_ = _123_ & _129_;
assign _151_ = _123_ & read_adress_counter[0];
assign _152_ = _124_ & _129_;
assign _153_ = _124_ & read_adress_counter[0];
assign _154_ = _125_ & _129_;
assign _155_ = _125_ & read_adress_counter[0];
assign _156_ = _126_ & _129_;
assign _157_ = _126_ & read_adress_counter[0];
assign _158_ = _127_ & _129_;
assign _159_ = _127_ & read_adress_counter[0];
assign _160_ = _128_ & _129_;
assign _161_ = _128_ & read_adress_counter[0];
assign _162_ = _130_ ? miso : data_reg[0];
assign _163_ = _131_ ? miso : data_reg[1];
assign _164_ = _132_ ? miso : data_reg[2];
assign _165_ = _133_ ? miso : data_reg[3];
assign _166_ = _134_ ? miso : data_reg[4];
assign _167_ = _135_ ? miso : data_reg[5];
assign _168_ = _136_ ? miso : data_reg[6];
assign _169_ = _137_ ? miso : data_reg[7];
assign _170_ = _138_ ? miso : data_reg[8];
assign _171_ = _139_ ? miso : data_reg[9];
assign _172_ = _140_ ? miso : data_reg[10];
assign _173_ = _141_ ? miso : data_reg[11];
assign _174_ = _142_ ? miso : data_reg[12];
assign _175_ = _143_ ? miso : data_reg[13];
assign _176_ = _144_ ? miso : data_reg[14];
assign _177_ = _145_ ? miso : data_reg[15];
assign _178_ = _146_ ? miso : data_reg[16];
assign _179_ = _147_ ? miso : data_reg[17];
assign _180_ = _148_ ? miso : data_reg[18];
assign _181_ = _149_ ? miso : data_reg[19];
assign _182_ = _150_ ? miso : data_reg[20];
assign _183_ = _151_ ? miso : data_reg[21];
assign _184_ = _152_ ? miso : data_reg[22];
assign _185_ = _153_ ? miso : data_reg[23];
assign _186_ = _154_ ? miso : data_reg[24];
assign _187_ = _155_ ? miso : data_reg[25];
assign _188_ = _156_ ? miso : data_reg[26];
assign _189_ = _157_ ? miso : data_reg[27];
assign _190_ = _158_ ? miso : data_reg[28];
assign _191_ = _159_ ? miso : data_reg[29];
assign _192_ = _160_ ? miso : data_reg[30];
assign _193_ = _161_ ? miso : data_reg[31];
assign _194_ = ~ read_adress_counter[4];
assign _195_ = ~ read_adress_counter[3];
assign _196_ = _194_ & _195_;
assign _197_ = _194_ & read_adress_counter[3];
assign _198_ = read_adress_counter[4] & _195_;
assign _199_ = read_adress_counter[4] & read_adress_counter[3];
assign _200_ = ~ read_adress_counter[2];
assign _201_ = _196_ & _200_;
assign _202_ = _196_ & read_adress_counter[2];
assign _203_ = _197_ & _200_;
assign _204_ = _197_ & read_adress_counter[2];
assign _205_ = _198_ & _200_;
assign _206_ = _198_ & read_adress_counter[2];
assign _207_ = _199_ & _200_;
assign _208_ = _199_ & read_adress_counter[2];
assign _209_ = ~ read_adress_counter[1];
assign _210_ = _201_ & _209_;
assign _211_ = _201_ & read_adress_counter[1];
assign _212_ = _202_ & _209_;
assign _213_ = _202_ & read_adress_counter[1];
assign _214_ = _203_ & _209_;
assign _215_ = _203_ & read_adress_counter[1];
assign _216_ = _204_ & _209_;
assign _217_ = _204_ & read_adress_counter[1];
assign _218_ = _205_ & _209_;
assign _219_ = _205_ & read_adress_counter[1];
assign _220_ = _206_ & _209_;
assign _221_ = _206_ & read_adress_counter[1];
assign _222_ = _207_ & _209_;
assign _223_ = _207_ & read_adress_counter[1];
assign _224_ = _208_ & _209_;
assign _225_ = _208_ & read_adress_counter[1];
assign _226_ = ~ read_adress_counter[0];
assign _227_ = _210_ & _226_;
assign _228_ = _210_ & read_adress_counter[0];
assign _229_ = _211_ & _226_;
assign _230_ = _211_ & read_adress_counter[0];
assign _231_ = _212_ & _226_;
assign _232_ = _212_ & read_adress_counter[0];
assign _233_ = _213_ & _226_;
assign _234_ = _213_ & read_adress_counter[0];
assign _235_ = _214_ & _226_;
assign _236_ = _214_ & read_adress_counter[0];
assign _237_ = _215_ & _226_;
assign _238_ = _215_ & read_adress_counter[0];
assign _239_ = _216_ & _226_;
assign _240_ = _216_ & read_adress_counter[0];
assign _241_ = _217_ & _226_;
assign _242_ = _217_ & read_adress_counter[0];
assign _243_ = _218_ & _226_;
assign _244_ = _218_ & read_adress_counter[0];
assign _245_ = _219_ & _226_;
assign _246_ = _219_ & read_adress_counter[0];
assign _247_ = _220_ & _226_;
assign _248_ = _220_ & read_adress_counter[0];
assign _249_ = _221_ & _226_;
assign _250_ = _221_ & read_adress_counter[0];
assign _251_ = _222_ & _226_;
assign _252_ = _222_ & read_adress_counter[0];
assign _253_ = _223_ & _226_;
assign _254_ = _223_ & read_adress_counter[0];
assign _255_ = _224_ & _226_;
assign _256_ = _224_ & read_adress_counter[0];
assign _257_ = _225_ & _226_;
assign _258_ = _225_ & read_adress_counter[0];
assign _259_ = _227_ ? miso : data_reg[0];
assign _260_ = _228_ ? miso : data_reg[1];
assign _261_ = _229_ ? miso : data_reg[2];
assign _262_ = _230_ ? miso : data_reg[3];
assign _263_ = _231_ ? miso : data_reg[4];
assign _264_ = _232_ ? miso : data_reg[5];
assign _265_ = _233_ ? miso : data_reg[6];
assign _266_ = _234_ ? miso : data_reg[7];
assign _267_ = _235_ ? miso : data_reg[8];
assign _268_ = _236_ ? miso : data_reg[9];
assign _269_ = _237_ ? miso : data_reg[10];
assign _270_ = _238_ ? miso : data_reg[11];
assign _271_ = _239_ ? miso : data_reg[12];
assign _272_ = _240_ ? miso : data_reg[13];
assign _273_ = _241_ ? miso : data_reg[14];
assign _274_ = _242_ ? miso : data_reg[15];
assign _275_ = _243_ ? miso : data_reg[16];
assign _276_ = _244_ ? miso : data_reg[17];
assign _277_ = _245_ ? miso : data_reg[18];
assign _278_ = _246_ ? miso : data_reg[19];
assign _279_ = _247_ ? miso : data_reg[20];
assign _280_ = _248_ ? miso : data_reg[21];
assign _281_ = _249_ ? miso : data_reg[22];
assign _282_ = _250_ ? miso : data_reg[23];
assign _283_ = _251_ ? miso : data_reg[24];
assign _284_ = _252_ ? miso : data_reg[25];
assign _285_ = _253_ ? miso : data_reg[26];
assign _286_ = _254_ ? miso : data_reg[27];
assign _287_ = _255_ ? miso : data_reg[28];
assign _288_ = _256_ ? miso : data_reg[29];
assign _289_ = _257_ ? miso : data_reg[30];
assign _291_ = _258_ ? miso : data_reg[31];
assign _303_ = read_adress_counter[4] ? _302_ : _300_;
assign _315_ = read_adress_counter[4] ? _314_ : _313_;
assign _290_ = currstate == 3'h0;
assign _301_ = ~ cs;
assign _312_ = _301_ ? mode_select : 1'h0;
assign data_reg = _066_;
assign mode_select_zw = _070_;
assign write_adress_counter = _073_;
assign read_adress_counter = _076_;
assign currstate = _077_;
assign sclk = clk;
assign mosi = _080_;
assign data_out = _083_;
assign data_valid = _086_;
endmodule
module tt_um_cejmu_riscv(clk, ena, rst_n, ui_in, uio_in, uo_out, uio_out, uio_oe);
wire _0_;
wire _1_;
wire [31:0] _2_;
wire [13:0] _3_;
wire _4_;
wire _5_;
wire [12:0] _6_;
wire _7_;
wire _8_;
wire [31:0] _9_;
input clk;
wire clk;
wire [13:0] cpu_addr_out;
wire data_valid;
input ena;
wire ena;
wire mem_req;
wire reset;
input rst_n;
wire rst_n;
wire [15:0] spi_addr_in;
wire [31:0] spi_data_in;
wire [31:0] spi_data_out;
input [7:0] ui_in;
wire [7:0] ui_in;
input [7:0] uio_in;
wire [7:0] uio_in;
output [7:0] uio_oe;
wire [7:0] uio_oe;
output [7:0] uio_out;
wire [7:0] uio_out;
output [7:0] uo_out;
wire [7:0] uo_out;
wire write_enable;
wire [12:0] x1;
assign _0_ = ~ rst_n;
cpu cpu_inst (
.addr_out(_3_),
.clk(clk),
.data_in(spi_data_out),
.data_out(_2_),
.data_valid(data_valid),
.mem_req(_5_),
.reset(reset),
.write_en(_4_),
.x1(_6_)
);
spi_master spi_master_inst (
.addr(spi_addr_in),
.clk(clk),
.cs(mem_req),
.data_in(spi_data_in),
.data_out(_9_),
.data_valid(_1_),
.miso(ui_in[0]),
.mode_select(write_enable),
.mosi(_8_),
.reset(reset),
.sclk(_7_)
);
assign write_enable = _4_;
assign cpu_addr_out = _3_;
assign spi_addr_in = { 2'h0, cpu_addr_out };
assign spi_data_out = _9_;
assign spi_data_in = _2_;
assign mem_req = _5_;
assign data_valid = _1_;
assign reset = _0_;
assign x1 = _6_;
assign uo_out = { x1[4:0], mem_req, _7_, _8_ };
assign uio_out = x1[12:5];
assign uio_oe = 8'hff;
endmodule
|
module instructioncounter(clk, reset, pcflag, s0, s1, pc_offset, pc_inc, pc_new);
wire [15:0] _00_;
wire [15:0] _01_;
wire _02_;
wire [15:0] _03_;
wire _04_;
wire _05_;
wire [15:0] _06_;
wire [15:0] _07_;
wire [15:0] _08_;
reg [15:0] _09_ = 16'h0000;
reg [15:0] _10_;
input clk;
wire clk;
output [15:0] pc_inc;
wire [15:0] pc_inc;
output [15:0] pc_new;
wire [15:0] pc_new;
input [15:0] pc_offset;
wire [15:0] pc_offset;
input pcflag;
wire pcflag;
wire [15:0] \reg ;
input reset;
wire reset;
input s0;
wire s0;
input s1;
wire s1;
wire [1:0] s1s0;
assign _00_ = \reg + 16'h0004;
assign _01_ = pc_offset + \reg ;
assign _02_ = s1s0 == 2'h0;
assign _03_ = \reg + 16'h0004;
assign _04_ = s1s0 == 2'h2;
assign _05_ = s1s0 == 2'h1;
function [15:0] \1383 ;
input [15:0] a;
input [47:0] b;
input [2:0] s;
(* parallel_case *)
casez (s)
3'b??1:
\1383 = b[15:0];
3'b?1?:
\1383 = b[31:16];
3'b1??:
\1383 = b[47:32];
default:
\1383 = a;
endcase
endfunction
assign _06_ = \1383 (16'h0000, { pc_offset, _03_, _01_ }, { _05_, _04_, _02_ });
assign _07_ = pcflag ? _06_ : \reg ;
assign _08_ = reset ? 16'h0000 : _07_;
always @(posedge clk)
_09_ <= _08_;
always @(posedge clk)
_10_ <= _00_;
assign s1s0 = { s1, s0 };
assign \reg = _09_;
assign pc_inc = _10_;
assign pc_new = \reg ;
endmodule
|
tt06-finale_0005
|
tt06-finale
|
CEJMU-tt06_tinyrv1
|
task_regs
|
tt_um_cejmu_riscv
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/* Generated by Yosys 0.39+165 (git sha1 22c5ab90d, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */
module alu(clk, reset, a, b, instruction, rd);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire [31:0] _15_;
wire _16_;
wire _17_;
wire _18_;
wire _19_;
wire _20_;
wire [31:0] _21_;
wire _22_;
wire _23_;
wire _24_;
wire _25_;
wire _26_;
wire [31:0] _27_;
wire _28_;
wire _29_;
wire _30_;
wire _31_;
wire _32_;
wire _33_;
wire [1:0] _34_;
wire [31:0] _35_;
wire [31:0] _36_;
wire [31:0] _37_;
wire [31:0] _38_;
wire [31:0] _39_;
wire [31:0] _40_;
wire [31:0] _41_;
reg [31:0] _42_;
input [31:0] a;
wire [31:0] a;
input [31:0] b;
wire [31:0] b;
input clk;
wire clk;
input [16:0] instruction;
wire [16:0] instruction;
output [31:0] rd;
wire [31:0] rd;
input reset;
wire reset;
assign _00_ = instruction[16:10] == 7'h00;
assign _01_ = instruction[9:7] == 3'h0;
assign _02_ = _01_ & _00_;
assign _03_ = instruction[6:0] == 7'h33;
assign _04_ = _03_ & _02_;
assign _05_ = instruction[9:7] == 3'h0;
assign _06_ = instruction[6:0] == 7'h13;
assign _07_ = _06_ & _05_;
assign _08_ = _04_ | _07_;
assign _09_ = instruction[6:0] == 7'h23;
assign _10_ = instruction[6:0] == 7'h03;
assign _11_ = _09_ | _10_;
assign _12_ = instruction[9:7] == 3'h2;
assign _13_ = _12_ & _11_;
assign _14_ = _08_ | _13_;
assign _15_ = a + b;
assign _16_ = instruction[16:10] == 7'h00;
assign _17_ = instruction[9:7] == 3'h7;
assign _18_ = _17_ & _16_;
assign _19_ = instruction[6:0] == 7'h33;
assign _20_ = _19_ & _18_;
assign _21_ = a & b;
assign _22_ = instruction[16:10] == 7'h00;
assign _23_ = instruction[9:7] == 3'h4;
assign _24_ = _23_ & _22_;
assign _25_ = instruction[6:0] == 7'h33;
assign _26_ = _25_ & _24_;
assign _27_ = a ^ b;
assign _28_ = instruction[6:0] == 7'h6f;
assign _29_ = instruction[6:0] == 7'h67;
assign _30_ = instruction[6:0] == 7'h63;
assign _31_ = instruction[9:7] == 3'h1;
assign _32_ = _31_ & _30_;
assign _33_ = a == b;
assign _34_ = _33_ ? 2'h2 : 2'h0;
assign _35_ = _32_ ? { 14'h0000, _34_, 16'h0000 } : 32'd0;
assign _36_ = _29_ ? 32'd65536 : _35_;
assign _37_ = _28_ ? 32'd0 : _36_;
assign _38_ = _26_ ? _27_ : _37_;
assign _39_ = _20_ ? _21_ : _38_;
assign _40_ = _14_ ? _15_ : _39_;
assign _41_ = reset ? 32'd0 : _40_;
always @(posedge clk)
_42_ <= _41_;
assign rd = _42_;
endmodule
module control(clk, reset, iword, data_valid, imm, control_flags_out, wbflag, memflag, pcflag, fetchflag, mem_req);
wire _000_;
wire _001_;
wire _002_;
wire [2:0] _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire [2:0] _012_;
wire _013_;
wire [2:0] _014_;
wire [2:0] _015_;
wire [2:0] _016_;
wire [2:0] _017_;
wire [2:0] _018_;
wire [2:0] _019_;
wire [2:0] _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire [31:0] _066_;
wire _067_;
wire [31:0] _068_;
wire _069_;
wire [31:0] _070_;
wire _071_;
wire [31:0] _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
reg [2:0] _109_;
input clk;
wire clk;
wire [6:0] control_flags;
output [6:0] control_flags_out;
wire [6:0] control_flags_out;
wire [2:0] currstate;
input data_valid;
wire data_valid;
output fetchflag;
wire fetchflag;
output [31:0] imm;
wire [31:0] imm;
input [31:0] iword;
wire [31:0] iword;
output mem_req;
wire mem_req;
output memflag;
wire memflag;
output pcflag;
wire pcflag;
input reset;
wire reset;
wire [20:0] w31_to_w11;
output wbflag;
wire wbflag;
assign _000_ = currstate == 3'h0;
assign _001_ = currstate == 3'h5;
assign _002_ = currstate == 3'h1;
assign _003_ = data_valid ? 3'h6 : currstate;
assign _004_ = currstate == 3'h6;
assign _005_ = currstate == 3'h2;
assign _006_ = currstate == 3'h3;
assign _007_ = control_flags[0] & _006_;
assign _008_ = currstate == 3'h3;
assign _009_ = ~ control_flags[0];
assign _010_ = _009_ & _008_;
assign _011_ = currstate == 3'h4;
assign _012_ = _013_ ? 3'h5 : currstate;
assign _013_ = data_valid & _011_;
assign _014_ = _010_ ? 3'h5 : _012_;
assign _015_ = _007_ ? 3'h4 : _014_;
assign _016_ = _005_ ? 3'h3 : _015_;
assign _017_ = _004_ ? 3'h2 : _016_;
assign _018_ = _002_ ? _003_ : _017_;
assign _019_ = _001_ ? 3'h1 : _018_;
assign _020_ = _000_ ? 3'h1 : _019_;
assign _021_ = currstate == 3'h1;
assign _022_ = currstate == 3'h4;
assign _023_ = _021_ | _022_;
assign _024_ = ~ data_valid;
assign _025_ = _024_ & _023_;
assign _026_ = _025_ ? 1'h0 : 1'h1;
assign _027_ = currstate == 3'h3;
assign _028_ = ~ control_flags[0];
assign _029_ = _028_ & _027_;
assign _030_ = currstate == 3'h4;
assign _031_ = data_valid & _030_;
assign _032_ = _029_ | _031_;
assign _033_ = _032_ ? 1'h1 : 1'h0;
assign _034_ = currstate == 3'h3;
assign _035_ = control_flags[0] & _034_;
assign _036_ = control_flags[1] & _035_;
assign _037_ = currstate == 3'h4;
assign _038_ = control_flags[1] & _037_;
assign _039_ = _036_ | _038_;
assign _040_ = _039_ ? 1'h1 : 1'h0;
assign _041_ = currstate == 3'h4;
assign _042_ = control_flags[2] & _041_;
assign _043_ = data_valid & _042_;
assign _044_ = currstate == 3'h3;
assign _045_ = control_flags[2] & _044_;
assign _046_ = ~ control_flags[0];
assign _047_ = _046_ & _045_;
assign _048_ = _043_ | _047_;
assign _049_ = _048_ ? 1'h1 : 1'h0;
assign _050_ = currstate == 3'h1;
assign _051_ = data_valid & _050_;
assign _052_ = _051_ ? 1'h1 : 1'h0;
assign _053_ = currstate == 3'h1;
assign _054_ = currstate == 3'h0;
assign _055_ = _053_ | _054_;
assign _056_ = currstate == 3'h5;
assign _057_ = _055_ | _056_;
assign _058_ = _057_ ? 1'h1 : 1'h0;
assign _059_ = iword[6:0] == 7'h67;
assign _060_ = _059_ ? 1'h1 : 1'h0;
assign _061_ = iword[6:0] == 7'h03;
assign _062_ = iword[6:0] == 7'h13;
assign _063_ = _061_ | _062_;
assign _064_ = iword[6:0] == 7'h67;
assign _065_ = _063_ | _064_;
assign _066_ = _065_ ? { w31_to_w11, iword[30:20] } : _068_;
assign _067_ = iword[6:0] == 7'h23;
assign _068_ = _067_ ? { w31_to_w11, iword[30:25], iword[11:7] } : _070_;
assign _069_ = iword[6:0] == 7'h63;
assign _070_ = _069_ ? { w31_to_w11[20:1], iword[7], iword[30:25], iword[11:8], 1'h0 } : _072_;
assign _071_ = iword[6:0] == 7'h6f;
assign _072_ = _071_ ? { w31_to_w11[11:0], iword[19:12], iword[20], iword[30:21], 1'h0 } : 32'd0;
assign _073_ = iword[6:0] == 7'h03;
assign _074_ = iword[6:0] == 7'h23;
assign _075_ = _073_ | _074_;
assign _076_ = iword[14:12] == 3'h2;
assign _077_ = _076_ & _075_;
assign _078_ = _077_ ? 1'h1 : 1'h0;
assign _079_ = iword[6:0] == 7'h23;
assign _080_ = iword[14:12] == 3'h2;
assign _081_ = _080_ & _079_;
assign _082_ = _081_ ? 1'h1 : 1'h0;
assign _083_ = iword[6:0] == 7'h63;
assign _084_ = _083_ ? 1'h0 : 1'h1;
assign _085_ = iword[6:0] == 7'h13;
assign _086_ = iword[6:0] == 7'h37;
assign _087_ = _085_ | _086_;
assign _088_ = iword[6:0] == 7'h17;
assign _089_ = _087_ | _088_;
assign _090_ = iword[6:0] == 7'h03;
assign _091_ = iword[6:0] == 7'h23;
assign _092_ = _090_ | _091_;
assign _093_ = iword[14:12] == 3'h2;
assign _094_ = _093_ & _092_;
assign _095_ = _089_ | _094_;
assign _096_ = iword[6:0] == 7'h6f;
assign _097_ = _095_ | _096_;
assign _098_ = iword[6:0] == 7'h67;
assign _099_ = _097_ | _098_;
assign _100_ = _099_ ? 1'h1 : 1'h0;
assign _101_ = iword[6:0] == 7'h63;
assign _102_ = iword[6:0] == 7'h6f;
assign _103_ = _101_ | _102_;
assign _104_ = iword[6:0] == 7'h67;
assign _105_ = _103_ | _104_;
assign _106_ = iword[6:0] == 7'h67;
assign _107_ = _105_ | _106_;
assign _108_ = _107_ ? 1'h1 : 1'h0;
always @(posedge clk, posedge reset)
if (reset) _109_ <= 3'h0;
else _109_ <= _020_;
assign currstate = _109_;
assign control_flags = { _060_, _058_, _108_, _100_, _084_, _082_, _078_ };
assign w31_to_w11 = { iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31] };
assign imm = _066_;
assign control_flags_out = control_flags;
assign wbflag = _049_;
assign memflag = _040_;
assign pcflag = _033_;
assign fetchflag = _052_;
assign mem_req = _026_;
endmodule
module cpu(clk, reset, data_in, data_valid, data_out, addr_out, write_en, mem_req, x1);
wire [31:0] _00_;
wire [31:0] _01_;
wire [12:0] _02_;
wire [31:0] _03_;
wire [31:0] _04_;
wire [6:0] _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire [31:0] _11_;
wire [31:0] _12_;
wire [31:0] _13_;
wire _14_;
wire _15_;
wire [15:0] _16_;
wire [15:0] _17_;
wire [15:0] _18_;
wire [13:0] _19_;
wire [31:0] _20_;
reg [31:0] _21_;
output [13:0] addr_out;
wire [13:0] addr_out;
wire [31:0] b;
input clk;
wire clk;
wire [6:0] control_flags_out;
input [31:0] data_in;
wire [31:0] data_in;
output [31:0] data_out;
wire [31:0] data_out;
input data_valid;
wire data_valid;
wire fetchflag;
wire [31:0] imm;
wire [16:0] instruction;
wire [31:0] iword_reg;
output mem_req;
wire mem_req;
wire memflag;
wire [15:0] pc_inc;
wire [15:0] pc_offset;
wire [15:0] pc_out;
wire pcflag;
wire [31:0] rd;
wire [31:0] rdalu;
input reset;
wire reset;
wire [31:0] rs1;
wire [31:0] rs2;
wire s0;
wire s1;
wire wbflag;
output write_en;
wire write_en;
output [12:0] x1;
wire [12:0] x1;
assign _11_ = control_flags_out[3] ? imm : rs2;
assign _12_ = control_flags_out[4] ? { 16'h0000, pc_inc } : _13_;
assign _13_ = control_flags_out[0] ? data_in : rdalu;
assign _14_ = control_flags_out[4] ? rdalu[16] : 1'h0;
assign _15_ = control_flags_out[4] ? rdalu[17] : 1'h1;
assign _18_ = control_flags_out[6] ? rs1[15:0] : imm[15:0];
assign _19_ = control_flags_out[5] ? pc_out[15:2] : rdalu[13:0];
assign _20_ = fetchflag ? data_in : iword_reg;
always @(posedge clk, posedge reset)
if (reset) _21_ <= 32'd0;
else _21_ <= _20_;
alu alu_inst (
.a(rs1),
.b(b),
.clk(clk),
.instruction(instruction),
.rd(_03_),
.reset(reset)
);
control control_inst (
.clk(clk),
.control_flags_out(_05_),
.data_valid(data_valid),
.fetchflag(_09_),
.imm(_04_),
.iword(iword_reg),
.mem_req(_10_),
.memflag(_07_),
.pcflag(_08_),
.reset(reset),
.wbflag(_06_)
);
instructioncounter instruction_inst (
.clk(clk),
.pc_inc(_16_),
.pc_new(_17_),
.pc_offset(pc_offset),
.pcflag(pcflag),
.reset(reset),
.s0(s0),
.s1(s1)
);
regs regs_inst (
.clk(clk),
.rd(rd),
.rdadr(iword_reg[11:7]),
.regwrite(wbflag),
.reset(reset),
.rs1(_00_),
.rs1adr(iword_reg[19:15]),
.rs2(_01_),
.rs2adr(iword_reg[24:20]),
.x1(_02_)
);
assign s0 = _14_;
assign s1 = _15_;
assign imm = _04_;
assign control_flags_out = _05_;
assign rs1 = _00_;
assign rs2 = _01_;
assign b = _11_;
assign rdalu = _03_;
assign rd = _12_;
assign wbflag = _06_;
assign memflag = _07_;
assign pcflag = _08_;
assign fetchflag = _09_;
assign instruction = { iword_reg[31:25], iword_reg[14:12], iword_reg[6:0] };
assign iword_reg = _21_;
assign pc_inc = _16_;
assign pc_out = _17_;
assign pc_offset = _18_;
assign data_out = rs2;
assign addr_out = _19_;
assign write_en = memflag;
assign mem_req = _10_;
assign x1 = _02_;
endmodule
module instructioncounter(clk, reset, pcflag, s0, s1, pc_offset, pc_inc, pc_new);
wire [15:0] _00_;
wire [15:0] _01_;
wire _02_;
wire [15:0] _03_;
wire _04_;
wire _05_;
wire [15:0] _06_;
wire [15:0] _07_;
wire [15:0] _08_;
reg [15:0] _09_ = 16'h0000;
reg [15:0] _10_;
input clk;
wire clk;
output [15:0] pc_inc;
wire [15:0] pc_inc;
output [15:0] pc_new;
wire [15:0] pc_new;
input [15:0] pc_offset;
wire [15:0] pc_offset;
input pcflag;
wire pcflag;
wire [15:0] \reg ;
input reset;
wire reset;
input s0;
wire s0;
input s1;
wire s1;
wire [1:0] s1s0;
assign _00_ = \reg + 16'h0004;
assign _01_ = pc_offset + \reg ;
assign _02_ = s1s0 == 2'h0;
assign _03_ = \reg + 16'h0004;
assign _04_ = s1s0 == 2'h2;
assign _05_ = s1s0 == 2'h1;
function [15:0] \1383 ;
input [15:0] a;
input [47:0] b;
input [2:0] s;
(* parallel_case *)
casez (s)
3'b??1:
\1383 = b[15:0];
3'b?1?:
\1383 = b[31:16];
3'b1??:
\1383 = b[47:32];
default:
\1383 = a;
endcase
endfunction
assign _06_ = \1383 (16'h0000, { pc_offset, _03_, _01_ }, { _05_, _04_, _02_ });
assign _07_ = pcflag ? _06_ : \reg ;
assign _08_ = reset ? 16'h0000 : _07_;
always @(posedge clk)
_09_ <= _08_;
always @(posedge clk)
_10_ <= _00_;
assign s1s0 = { s1, s0 };
assign \reg = _09_;
assign pc_inc = _10_;
assign pc_new = \reg ;
endmodule
module regs(clk, reset, rs1adr, rs2adr, rdadr, rd, regwrite, rs1, rs2, x1);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module spi_master(clk, mode_select, reset, miso, cs, data_in, addr, sclk, mosi, data_out, data_valid);
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire [31:0] _060_;
wire [31:0] _061_;
wire [31:0] _062_;
wire [2:0] _063_;
wire _064_;
wire [31:0] _065_;
reg [31:0] _066_;
wire _067_;
wire _068_;
wire _069_;
reg _070_;
wire _071_;
wire [31:0] _072_;
reg [31:0] _073_ = 32'd16;
wire _074_;
wire [31:0] _075_;
reg [31:0] _076_ = 32'd33;
reg [2:0] _077_;
wire _078_;
wire _079_;
reg _080_;
wire _081_;
wire [31:0] _082_;
reg [31:0] _083_;
wire _084_;
wire _085_;
reg _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
wire _203_;
wire _204_;
wire _205_;
wire _206_;
wire _207_;
wire _208_;
wire _209_;
wire _210_;
wire _211_;
wire _212_;
wire _213_;
wire _214_;
wire _215_;
wire _216_;
wire _217_;
wire _218_;
wire _219_;
wire _220_;
wire _221_;
wire _222_;
wire _223_;
wire _224_;
wire _225_;
wire _226_;
wire _227_;
wire _228_;
wire _229_;
wire _230_;
wire _231_;
wire _232_;
wire _233_;
wire _234_;
wire _235_;
wire _236_;
wire _237_;
wire _238_;
wire _239_;
wire _240_;
wire _241_;
wire _242_;
wire _243_;
wire _244_;
wire _245_;
wire _246_;
wire _247_;
wire _248_;
wire _249_;
wire _250_;
wire _251_;
wire _252_;
wire _253_;
wire _254_;
wire _255_;
wire _256_;
wire _257_;
wire _258_;
wire _259_;
wire _260_;
wire _261_;
wire _262_;
wire _263_;
wire _264_;
wire _265_;
wire _266_;
wire _267_;
wire _268_;
wire _269_;
wire _270_;
wire _271_;
wire _272_;
wire _273_;
wire _274_;
wire _275_;
wire _276_;
wire _277_;
wire _278_;
wire _279_;
wire _280_;
wire _281_;
wire _282_;
wire _283_;
wire _284_;
wire _285_;
wire _286_;
wire _287_;
wire _288_;
wire _289_;
wire _290_;
wire _291_;
wire _292_;
wire _293_;
wire _294_;
wire _295_;
wire _296_;
wire _297_;
wire _298_;
wire _299_;
wire _300_;
wire _301_;
wire _302_;
wire _303_;
wire _304_;
wire _305_;
wire _306_;
wire _307_;
wire _308_;
wire _309_;
wire _310_;
wire _311_;
wire _312_;
wire _313_;
wire _314_;
wire _315_;
wire [2:0] _316_;
wire _317_;
wire _318_;
wire [31:0] _319_;
wire _320_;
wire _321_;
wire _322_;
wire [31:0] _323_;
wire _324_;
wire [2:0] _325_;
wire [2:0] _326_;
wire _327_;
wire [31:0] _328_;
wire [2:0] _329_;
wire _330_;
wire [31:0] _331_;
wire [2:0] _332_;
wire _333_;
wire _334_;
wire [31:0] _335_;
wire _336_;
wire [31:0] _337_;
wire [31:0] _338_;
wire [31:0] _339_;
wire [2:0] _340_;
wire [31:0] _341_;
wire [31:0] _342_;
wire [2:0] _343_;
wire _344_;
wire _345_;
wire [31:0] _346_;
wire _347_;
wire [31:0] _348_;
wire _349_;
wire [31:0] _350_;
wire [2:0] _351_;
wire _352_;
wire [31:0] _353_;
wire [2:0] _354_;
wire _355_;
wire [31:0] _356_;
wire _357_;
wire [2:0] _358_;
wire _359_;
wire [31:0] _360_;
wire _361_;
wire [31:0] _362_;
wire [2:0] _363_;
wire _364_;
wire [31:0] _365_;
wire _366_;
wire [31:0] _367_;
wire [31:0] _368_;
wire [2:0] _369_;
wire _370_;
wire [31:0] _371_;
wire _372_;
wire [31:0] _373_;
wire [31:0] _374_;
wire [31:0] _375_;
wire [2:0] _376_;
wire _377_;
wire [31:0] _378_;
wire _379_;
input [15:0] addr;
wire [15:0] addr;
input clk;
wire clk;
input cs;
wire cs;
wire [2:0] currstate;
input [31:0] data_in;
wire [31:0] data_in;
output [31:0] data_out;
wire [31:0] data_out;
wire [31:0] data_reg;
output data_valid;
wire data_valid;
input miso;
wire miso;
input mode_select;
wire mode_select;
wire mode_select_zw;
output mosi;
wire mosi;
wire [31:0] read_adress_counter;
input reset;
wire reset;
output sclk;
wire sclk;
wire [31:0] write_adress_counter;
assign _000_ = write_adress_counter[0] ? addr[1] : addr[0];
assign _001_ = write_adress_counter[0] ? addr[5] : addr[4];
assign _002_ = write_adress_counter[0] ? addr[9] : addr[8];
assign _003_ = write_adress_counter[0] ? addr[13] : addr[12];
assign _004_ = write_adress_counter[2] ? _088_ : _087_;
assign _005_ = write_adress_counter[0] ? addr[1] : addr[0];
assign _006_ = write_adress_counter[0] ? addr[5] : addr[4];
assign _007_ = write_adress_counter[0] ? addr[9] : addr[8];
assign _008_ = write_adress_counter[0] ? addr[13] : addr[12];
assign _009_ = write_adress_counter[2] ? _093_ : _092_;
assign _010_ = read_adress_counter[0] ? data_in[1] : data_in[0];
assign _011_ = read_adress_counter[0] ? data_in[5] : data_in[4];
assign _012_ = read_adress_counter[0] ? data_in[9] : data_in[8];
assign _013_ = read_adress_counter[0] ? data_in[13] : data_in[12];
assign _014_ = read_adress_counter[0] ? data_in[17] : data_in[16];
assign _015_ = read_adress_counter[0] ? data_in[21] : data_in[20];
assign _016_ = read_adress_counter[0] ? data_in[25] : data_in[24];
assign _017_ = read_adress_counter[0] ? data_in[29] : data_in[28];
assign _018_ = read_adress_counter[2] ? _293_ : _292_;
assign _019_ = read_adress_counter[2] ? _297_ : _296_;
assign _020_ = read_adress_counter[0] ? data_in[1] : data_in[0];
assign _021_ = read_adress_counter[0] ? data_in[5] : data_in[4];
assign _022_ = read_adress_counter[0] ? data_in[9] : data_in[8];
assign _023_ = read_adress_counter[0] ? data_in[13] : data_in[12];
assign _024_ = read_adress_counter[0] ? data_in[17] : data_in[16];
assign _025_ = read_adress_counter[0] ? data_in[21] : data_in[20];
assign _026_ = read_adress_counter[0] ? data_in[25] : data_in[24];
assign _027_ = read_adress_counter[0] ? data_in[29] : data_in[28];
assign _028_ = read_adress_counter[2] ? _305_ : _304_;
assign _029_ = read_adress_counter[2] ? _309_ : _308_;
assign _030_ = write_adress_counter[0] ? addr[3] : addr[2];
assign _031_ = write_adress_counter[0] ? addr[7] : addr[6];
assign _032_ = write_adress_counter[0] ? addr[11] : addr[10];
assign _033_ = write_adress_counter[0] ? addr[15] : addr[14];
assign _034_ = write_adress_counter[2] ? _090_ : _089_;
assign _035_ = write_adress_counter[0] ? addr[3] : addr[2];
assign _036_ = write_adress_counter[0] ? addr[7] : addr[6];
assign _037_ = write_adress_counter[0] ? addr[11] : addr[10];
assign _038_ = write_adress_counter[0] ? addr[15] : addr[14];
assign _039_ = write_adress_counter[2] ? _095_ : _094_;
assign _040_ = read_adress_counter[0] ? data_in[3] : data_in[2];
assign _041_ = read_adress_counter[0] ? data_in[7] : data_in[6];
assign _042_ = read_adress_counter[0] ? data_in[11] : data_in[10];
assign _043_ = read_adress_counter[0] ? data_in[15] : data_in[14];
assign _044_ = read_adress_counter[0] ? data_in[19] : data_in[18];
assign _045_ = read_adress_counter[0] ? data_in[23] : data_in[22];
assign _046_ = read_adress_counter[0] ? data_in[27] : data_in[26];
assign _047_ = read_adress_counter[0] ? data_in[31] : data_in[30];
assign _048_ = read_adress_counter[2] ? _295_ : _294_;
assign _049_ = read_adress_counter[2] ? _299_ : _298_;
assign _050_ = read_adress_counter[0] ? data_in[3] : data_in[2];
assign _051_ = read_adress_counter[0] ? data_in[7] : data_in[6];
assign _052_ = read_adress_counter[0] ? data_in[11] : data_in[10];
assign _053_ = read_adress_counter[0] ? data_in[15] : data_in[14];
assign _054_ = read_adress_counter[0] ? data_in[19] : data_in[18];
assign _055_ = read_adress_counter[0] ? data_in[23] : data_in[22];
assign _056_ = read_adress_counter[0] ? data_in[27] : data_in[26];
assign _057_ = read_adress_counter[0] ? data_in[31] : data_in[30];
assign _058_ = read_adress_counter[2] ? _307_ : _306_;
assign _059_ = read_adress_counter[2] ? _311_ : _310_;
assign _087_ = write_adress_counter[1] ? _030_ : _000_;
assign _088_ = write_adress_counter[1] ? _031_ : _001_;
assign _089_ = write_adress_counter[1] ? _032_ : _002_;
assign _090_ = write_adress_counter[1] ? _033_ : _003_;
assign _091_ = write_adress_counter[3] ? _034_ : _004_;
assign _092_ = write_adress_counter[1] ? _035_ : _005_;
assign _093_ = write_adress_counter[1] ? _036_ : _006_;
assign _094_ = write_adress_counter[1] ? _037_ : _007_;
assign _095_ = write_adress_counter[1] ? _038_ : _008_;
assign _096_ = write_adress_counter[3] ? _039_ : _009_;
assign _292_ = read_adress_counter[1] ? _040_ : _010_;
assign _293_ = read_adress_counter[1] ? _041_ : _011_;
assign _294_ = read_adress_counter[1] ? _042_ : _012_;
assign _295_ = read_adress_counter[1] ? _043_ : _013_;
assign _296_ = read_adress_counter[1] ? _044_ : _014_;
assign _297_ = read_adress_counter[1] ? _045_ : _015_;
assign _298_ = read_adress_counter[1] ? _046_ : _016_;
assign _299_ = read_adress_counter[1] ? _047_ : _017_;
assign _300_ = read_adress_counter[3] ? _048_ : _018_;
assign _302_ = read_adress_counter[3] ? _049_ : _019_;
assign _304_ = read_adress_counter[1] ? _050_ : _020_;
assign _305_ = read_adress_counter[1] ? _051_ : _021_;
assign _306_ = read_adress_counter[1] ? _052_ : _022_;
assign _307_ = read_adress_counter[1] ? _053_ : _023_;
assign _308_ = read_adress_counter[1] ? _054_ : _024_;
assign _309_ = read_adress_counter[1] ? _055_ : _025_;
assign _310_ = read_adress_counter[1] ? _056_ : _026_;
assign _311_ = read_adress_counter[1] ? _057_ : _027_;
assign _313_ = read_adress_counter[3] ? _058_ : _028_;
assign _314_ = read_adress_counter[3] ? _059_ : _029_;
assign _316_ = _301_ ? 3'h1 : currstate;
assign _317_ = currstate == 3'h1;
assign _318_ = write_adress_counter == 32'd16;
assign _319_ = write_adress_counter - 32'd1;
assign _320_ = $signed(write_adress_counter) > $signed(32'd0);
assign _321_ = $signed(write_adress_counter) <= $signed(32'd15);
assign _322_ = _321_ & _320_;
assign _323_ = write_adress_counter - 32'd1;
assign _324_ = ~ mode_select_zw;
assign _325_ = mode_select_zw ? 3'h2 : currstate;
assign _326_ = _324_ ? 3'h3 : _325_;
assign _327_ = _322_ ? _091_ : _096_;
assign _328_ = _322_ ? _323_ : write_adress_counter;
assign _329_ = _322_ ? currstate : _326_;
assign _330_ = _318_ ? mode_select_zw : _327_;
assign _331_ = _318_ ? _319_ : _328_;
assign _332_ = _318_ ? currstate : _329_;
assign _333_ = currstate == 3'h3;
assign _334_ = $signed(read_adress_counter) >= $signed(32'd32);
assign _335_ = read_adress_counter - 32'd1;
assign _336_ = $signed(read_adress_counter) > $signed(32'd0);
assign _337_ = read_adress_counter - 32'd1;
assign _338_ = _336_ ? { _193_, _192_, _191_, _190_, _189_, _188_, _187_, _186_, _185_, _184_, _183_, _182_, _181_, _180_, _179_, _178_, _177_, _176_, _175_, _174_, _173_, _172_, _171_, _170_, _169_, _168_, _167_, _166_, _165_, _164_, _163_, _162_ } : { _291_, _289_, _288_, _287_, _286_, _285_, _284_, _283_, _282_, _281_, _280_, _279_, _278_, _277_, _276_, _275_, _274_, _273_, _272_, _271_, _270_, _269_, _268_, _267_, _266_, _265_, _264_, _263_, _262_, _261_, _260_, _259_ };
assign _339_ = _336_ ? _337_ : read_adress_counter;
assign _340_ = _336_ ? currstate : 3'h4;
assign _341_ = _334_ ? data_reg : _338_;
assign _342_ = _334_ ? _335_ : _339_;
assign _343_ = _334_ ? currstate : _340_;
assign _344_ = currstate == 3'h2;
assign _345_ = $signed(read_adress_counter) >= $signed(32'd32);
assign _346_ = read_adress_counter - 32'd1;
assign _347_ = $signed(read_adress_counter) > $signed(32'd0);
assign _348_ = read_adress_counter - 32'd1;
assign _349_ = _347_ ? _303_ : _315_;
assign _350_ = _347_ ? _348_ : read_adress_counter;
assign _351_ = _347_ ? currstate : 3'h4;
assign _352_ = _345_ ? _080_ : _349_;
assign _353_ = _345_ ? _346_ : _350_;
assign _354_ = _345_ ? currstate : _351_;
assign _355_ = currstate == 3'h4;
assign _356_ = _355_ ? data_reg : _083_;
assign _357_ = _355_ ? 1'h1 : _086_;
assign _358_ = _355_ ? 3'h0 : currstate;
assign _359_ = _344_ ? _352_ : _080_;
assign _360_ = _344_ ? _083_ : _356_;
assign _361_ = _344_ ? _086_ : _357_;
assign _362_ = _344_ ? _353_ : read_adress_counter;
assign _363_ = _344_ ? _354_ : _358_;
assign _364_ = _333_ ? _080_ : _359_;
assign _365_ = _333_ ? _083_ : _360_;
assign _366_ = _333_ ? _086_ : _361_;
assign _367_ = _333_ ? _341_ : data_reg;
assign _368_ = _333_ ? _342_ : _362_;
assign _369_ = _333_ ? _343_ : _363_;
assign _370_ = _317_ ? _330_ : _364_;
assign _371_ = _317_ ? _083_ : _365_;
assign _372_ = _317_ ? _086_ : _366_;
assign _373_ = _317_ ? data_reg : _367_;
assign _374_ = _317_ ? _331_ : write_adress_counter;
assign _375_ = _317_ ? read_adress_counter : _368_;
assign _376_ = _317_ ? _332_ : _369_;
assign _377_ = _290_ ? 1'h0 : _370_;
assign _378_ = _290_ ? 32'd0 : _371_;
assign _379_ = _290_ ? 1'h0 : _372_;
assign _060_ = _290_ ? 32'd0 : _373_;
assign _061_ = _290_ ? 32'd16 : _374_;
assign _062_ = _290_ ? 32'd33 : _375_;
assign _063_ = _290_ ? _316_ : _376_;
assign _064_ = ~ reset;
assign _065_ = _064_ ? _060_ : data_reg;
always @(posedge clk)
_066_ <= _065_;
assign _067_ = ~ reset;
assign _068_ = _290_ & _067_;
assign _069_ = _068_ ? _312_ : mode_select_zw;
always @(posedge clk)
_070_ <= _069_;
assign _071_ = ~ reset;
assign _072_ = _071_ ? _061_ : write_adress_counter;
always @(posedge clk)
_073_ <= _072_;
assign _074_ = ~ reset;
assign _075_ = _074_ ? _062_ : read_adress_counter;
always @(posedge clk)
_076_ <= _075_;
always @(posedge clk, posedge reset)
if (reset) _077_ <= 3'h0;
else _077_ <= _063_;
assign _078_ = ~ reset;
assign _079_ = _078_ ? _377_ : _080_;
always @(posedge clk)
_080_ <= _079_;
assign _081_ = ~ reset;
assign _082_ = _081_ ? _378_ : _083_;
always @(posedge clk)
_083_ <= _082_;
assign _084_ = ~ reset;
assign _085_ = _084_ ? _379_ : _086_;
always @(posedge clk)
_086_ <= _085_;
assign _097_ = ~ read_adress_counter[4];
assign _098_ = ~ read_adress_counter[3];
assign _099_ = _097_ & _098_;
assign _100_ = _097_ & read_adress_counter[3];
assign _101_ = read_adress_counter[4] & _098_;
assign _102_ = read_adress_counter[4] & read_adress_counter[3];
assign _103_ = ~ read_adress_counter[2];
assign _104_ = _099_ & _103_;
assign _105_ = _099_ & read_adress_counter[2];
assign _106_ = _100_ & _103_;
assign _107_ = _100_ & read_adress_counter[2];
assign _108_ = _101_ & _103_;
assign _109_ = _101_ & read_adress_counter[2];
assign _110_ = _102_ & _103_;
assign _111_ = _102_ & read_adress_counter[2];
assign _112_ = ~ read_adress_counter[1];
assign _113_ = _104_ & _112_;
assign _114_ = _104_ & read_adress_counter[1];
assign _115_ = _105_ & _112_;
assign _116_ = _105_ & read_adress_counter[1];
assign _117_ = _106_ & _112_;
assign _118_ = _106_ & read_adress_counter[1];
assign _119_ = _107_ & _112_;
assign _120_ = _107_ & read_adress_counter[1];
assign _121_ = _108_ & _112_;
assign _122_ = _108_ & read_adress_counter[1];
assign _123_ = _109_ & _112_;
assign _124_ = _109_ & read_adress_counter[1];
assign _125_ = _110_ & _112_;
assign _126_ = _110_ & read_adress_counter[1];
assign _127_ = _111_ & _112_;
assign _128_ = _111_ & read_adress_counter[1];
assign _129_ = ~ read_adress_counter[0];
assign _130_ = _113_ & _129_;
assign _131_ = _113_ & read_adress_counter[0];
assign _132_ = _114_ & _129_;
assign _133_ = _114_ & read_adress_counter[0];
assign _134_ = _115_ & _129_;
assign _135_ = _115_ & read_adress_counter[0];
assign _136_ = _116_ & _129_;
assign _137_ = _116_ & read_adress_counter[0];
assign _138_ = _117_ & _129_;
assign _139_ = _117_ & read_adress_counter[0];
assign _140_ = _118_ & _129_;
assign _141_ = _118_ & read_adress_counter[0];
assign _142_ = _119_ & _129_;
assign _143_ = _119_ & read_adress_counter[0];
assign _144_ = _120_ & _129_;
assign _145_ = _120_ & read_adress_counter[0];
assign _146_ = _121_ & _129_;
assign _147_ = _121_ & read_adress_counter[0];
assign _148_ = _122_ & _129_;
assign _149_ = _122_ & read_adress_counter[0];
assign _150_ = _123_ & _129_;
assign _151_ = _123_ & read_adress_counter[0];
assign _152_ = _124_ & _129_;
assign _153_ = _124_ & read_adress_counter[0];
assign _154_ = _125_ & _129_;
assign _155_ = _125_ & read_adress_counter[0];
assign _156_ = _126_ & _129_;
assign _157_ = _126_ & read_adress_counter[0];
assign _158_ = _127_ & _129_;
assign _159_ = _127_ & read_adress_counter[0];
assign _160_ = _128_ & _129_;
assign _161_ = _128_ & read_adress_counter[0];
assign _162_ = _130_ ? miso : data_reg[0];
assign _163_ = _131_ ? miso : data_reg[1];
assign _164_ = _132_ ? miso : data_reg[2];
assign _165_ = _133_ ? miso : data_reg[3];
assign _166_ = _134_ ? miso : data_reg[4];
assign _167_ = _135_ ? miso : data_reg[5];
assign _168_ = _136_ ? miso : data_reg[6];
assign _169_ = _137_ ? miso : data_reg[7];
assign _170_ = _138_ ? miso : data_reg[8];
assign _171_ = _139_ ? miso : data_reg[9];
assign _172_ = _140_ ? miso : data_reg[10];
assign _173_ = _141_ ? miso : data_reg[11];
assign _174_ = _142_ ? miso : data_reg[12];
assign _175_ = _143_ ? miso : data_reg[13];
assign _176_ = _144_ ? miso : data_reg[14];
assign _177_ = _145_ ? miso : data_reg[15];
assign _178_ = _146_ ? miso : data_reg[16];
assign _179_ = _147_ ? miso : data_reg[17];
assign _180_ = _148_ ? miso : data_reg[18];
assign _181_ = _149_ ? miso : data_reg[19];
assign _182_ = _150_ ? miso : data_reg[20];
assign _183_ = _151_ ? miso : data_reg[21];
assign _184_ = _152_ ? miso : data_reg[22];
assign _185_ = _153_ ? miso : data_reg[23];
assign _186_ = _154_ ? miso : data_reg[24];
assign _187_ = _155_ ? miso : data_reg[25];
assign _188_ = _156_ ? miso : data_reg[26];
assign _189_ = _157_ ? miso : data_reg[27];
assign _190_ = _158_ ? miso : data_reg[28];
assign _191_ = _159_ ? miso : data_reg[29];
assign _192_ = _160_ ? miso : data_reg[30];
assign _193_ = _161_ ? miso : data_reg[31];
assign _194_ = ~ read_adress_counter[4];
assign _195_ = ~ read_adress_counter[3];
assign _196_ = _194_ & _195_;
assign _197_ = _194_ & read_adress_counter[3];
assign _198_ = read_adress_counter[4] & _195_;
assign _199_ = read_adress_counter[4] & read_adress_counter[3];
assign _200_ = ~ read_adress_counter[2];
assign _201_ = _196_ & _200_;
assign _202_ = _196_ & read_adress_counter[2];
assign _203_ = _197_ & _200_;
assign _204_ = _197_ & read_adress_counter[2];
assign _205_ = _198_ & _200_;
assign _206_ = _198_ & read_adress_counter[2];
assign _207_ = _199_ & _200_;
assign _208_ = _199_ & read_adress_counter[2];
assign _209_ = ~ read_adress_counter[1];
assign _210_ = _201_ & _209_;
assign _211_ = _201_ & read_adress_counter[1];
assign _212_ = _202_ & _209_;
assign _213_ = _202_ & read_adress_counter[1];
assign _214_ = _203_ & _209_;
assign _215_ = _203_ & read_adress_counter[1];
assign _216_ = _204_ & _209_;
assign _217_ = _204_ & read_adress_counter[1];
assign _218_ = _205_ & _209_;
assign _219_ = _205_ & read_adress_counter[1];
assign _220_ = _206_ & _209_;
assign _221_ = _206_ & read_adress_counter[1];
assign _222_ = _207_ & _209_;
assign _223_ = _207_ & read_adress_counter[1];
assign _224_ = _208_ & _209_;
assign _225_ = _208_ & read_adress_counter[1];
assign _226_ = ~ read_adress_counter[0];
assign _227_ = _210_ & _226_;
assign _228_ = _210_ & read_adress_counter[0];
assign _229_ = _211_ & _226_;
assign _230_ = _211_ & read_adress_counter[0];
assign _231_ = _212_ & _226_;
assign _232_ = _212_ & read_adress_counter[0];
assign _233_ = _213_ & _226_;
assign _234_ = _213_ & read_adress_counter[0];
assign _235_ = _214_ & _226_;
assign _236_ = _214_ & read_adress_counter[0];
assign _237_ = _215_ & _226_;
assign _238_ = _215_ & read_adress_counter[0];
assign _239_ = _216_ & _226_;
assign _240_ = _216_ & read_adress_counter[0];
assign _241_ = _217_ & _226_;
assign _242_ = _217_ & read_adress_counter[0];
assign _243_ = _218_ & _226_;
assign _244_ = _218_ & read_adress_counter[0];
assign _245_ = _219_ & _226_;
assign _246_ = _219_ & read_adress_counter[0];
assign _247_ = _220_ & _226_;
assign _248_ = _220_ & read_adress_counter[0];
assign _249_ = _221_ & _226_;
assign _250_ = _221_ & read_adress_counter[0];
assign _251_ = _222_ & _226_;
assign _252_ = _222_ & read_adress_counter[0];
assign _253_ = _223_ & _226_;
assign _254_ = _223_ & read_adress_counter[0];
assign _255_ = _224_ & _226_;
assign _256_ = _224_ & read_adress_counter[0];
assign _257_ = _225_ & _226_;
assign _258_ = _225_ & read_adress_counter[0];
assign _259_ = _227_ ? miso : data_reg[0];
assign _260_ = _228_ ? miso : data_reg[1];
assign _261_ = _229_ ? miso : data_reg[2];
assign _262_ = _230_ ? miso : data_reg[3];
assign _263_ = _231_ ? miso : data_reg[4];
assign _264_ = _232_ ? miso : data_reg[5];
assign _265_ = _233_ ? miso : data_reg[6];
assign _266_ = _234_ ? miso : data_reg[7];
assign _267_ = _235_ ? miso : data_reg[8];
assign _268_ = _236_ ? miso : data_reg[9];
assign _269_ = _237_ ? miso : data_reg[10];
assign _270_ = _238_ ? miso : data_reg[11];
assign _271_ = _239_ ? miso : data_reg[12];
assign _272_ = _240_ ? miso : data_reg[13];
assign _273_ = _241_ ? miso : data_reg[14];
assign _274_ = _242_ ? miso : data_reg[15];
assign _275_ = _243_ ? miso : data_reg[16];
assign _276_ = _244_ ? miso : data_reg[17];
assign _277_ = _245_ ? miso : data_reg[18];
assign _278_ = _246_ ? miso : data_reg[19];
assign _279_ = _247_ ? miso : data_reg[20];
assign _280_ = _248_ ? miso : data_reg[21];
assign _281_ = _249_ ? miso : data_reg[22];
assign _282_ = _250_ ? miso : data_reg[23];
assign _283_ = _251_ ? miso : data_reg[24];
assign _284_ = _252_ ? miso : data_reg[25];
assign _285_ = _253_ ? miso : data_reg[26];
assign _286_ = _254_ ? miso : data_reg[27];
assign _287_ = _255_ ? miso : data_reg[28];
assign _288_ = _256_ ? miso : data_reg[29];
assign _289_ = _257_ ? miso : data_reg[30];
assign _291_ = _258_ ? miso : data_reg[31];
assign _303_ = read_adress_counter[4] ? _302_ : _300_;
assign _315_ = read_adress_counter[4] ? _314_ : _313_;
assign _290_ = currstate == 3'h0;
assign _301_ = ~ cs;
assign _312_ = _301_ ? mode_select : 1'h0;
assign data_reg = _066_;
assign mode_select_zw = _070_;
assign write_adress_counter = _073_;
assign read_adress_counter = _076_;
assign currstate = _077_;
assign sclk = clk;
assign mosi = _080_;
assign data_out = _083_;
assign data_valid = _086_;
endmodule
module tt_um_cejmu_riscv(clk, ena, rst_n, ui_in, uio_in, uo_out, uio_out, uio_oe);
wire _0_;
wire _1_;
wire [31:0] _2_;
wire [13:0] _3_;
wire _4_;
wire _5_;
wire [12:0] _6_;
wire _7_;
wire _8_;
wire [31:0] _9_;
input clk;
wire clk;
wire [13:0] cpu_addr_out;
wire data_valid;
input ena;
wire ena;
wire mem_req;
wire reset;
input rst_n;
wire rst_n;
wire [15:0] spi_addr_in;
wire [31:0] spi_data_in;
wire [31:0] spi_data_out;
input [7:0] ui_in;
wire [7:0] ui_in;
input [7:0] uio_in;
wire [7:0] uio_in;
output [7:0] uio_oe;
wire [7:0] uio_oe;
output [7:0] uio_out;
wire [7:0] uio_out;
output [7:0] uo_out;
wire [7:0] uo_out;
wire write_enable;
wire [12:0] x1;
assign _0_ = ~ rst_n;
cpu cpu_inst (
.addr_out(_3_),
.clk(clk),
.data_in(spi_data_out),
.data_out(_2_),
.data_valid(data_valid),
.mem_req(_5_),
.reset(reset),
.write_en(_4_),
.x1(_6_)
);
spi_master spi_master_inst (
.addr(spi_addr_in),
.clk(clk),
.cs(mem_req),
.data_in(spi_data_in),
.data_out(_9_),
.data_valid(_1_),
.miso(ui_in[0]),
.mode_select(write_enable),
.mosi(_8_),
.reset(reset),
.sclk(_7_)
);
assign write_enable = _4_;
assign cpu_addr_out = _3_;
assign spi_addr_in = { 2'h0, cpu_addr_out };
assign spi_data_out = _9_;
assign spi_data_in = _2_;
assign mem_req = _5_;
assign data_valid = _1_;
assign reset = _0_;
assign x1 = _6_;
assign uo_out = { x1[4:0], mem_req, _7_, _8_ };
assign uio_out = x1[12:5];
assign uio_oe = 8'hff;
endmodule
|
module regs(clk, reset, rs1adr, rs2adr, rdadr, rd, regwrite, rs1, rs2, x1);
wire [31:0] _000_;
wire [31:0] _001_;
wire [31:0] _002_;
wire [31:0] _003_;
wire [31:0] _004_;
wire [31:0] _005_;
wire [31:0] _006_;
wire [31:0] _007_;
wire [31:0] _008_;
wire [31:0] _009_;
wire [31:0] _010_;
wire [31:0] _011_;
wire [31:0] _012_;
wire [31:0] _013_;
wire [31:0] _014_;
wire [31:0] _015_;
wire [31:0] _016_;
wire [31:0] _017_;
wire [31:0] _018_;
wire [31:0] _019_;
wire [31:0] _020_;
wire [31:0] _021_;
wire [31:0] _022_;
wire [31:0] _023_;
wire [31:0] _024_;
wire [31:0] _025_;
wire [31:0] _026_;
wire [31:0] _027_;
wire [31:0] _028_;
wire [31:0] _029_;
wire [31:0] _030_;
wire [31:0] _031_;
wire [31:0] _032_;
wire [31:0] _033_;
wire [31:0] _034_;
wire [31:0] _035_;
wire [31:0] _036_;
wire [31:0] _037_;
wire [31:0] _038_;
wire [31:0] _039_;
wire _040_;
wire _041_;
wire [4:0] _042_;
wire [4:0] _043_;
wire [4:0] _044_;
wire [1023:0] _045_;
reg [1023:0] _046_;
reg [31:0] _047_;
reg [31:0] _048_;
wire _049_;
wire [12:0] _050_;
reg [12:0] _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire [31:0] _117_;
wire [31:0] _118_;
wire [31:0] _119_;
wire [31:0] _120_;
wire [31:0] _121_;
wire [31:0] _122_;
wire [31:0] _123_;
wire [31:0] _124_;
wire [31:0] _125_;
wire [31:0] _126_;
wire [31:0] _127_;
wire [31:0] _128_;
wire [31:0] _129_;
wire [31:0] _130_;
wire [31:0] _131_;
wire [31:0] _132_;
wire [31:0] _133_;
wire [31:0] _134_;
wire [31:0] _135_;
wire [31:0] _136_;
wire [31:0] _137_;
wire [31:0] _138_;
wire [31:0] _139_;
wire [31:0] _140_;
wire [31:0] _141_;
wire [31:0] _142_;
wire [31:0] _143_;
wire [31:0] _144_;
wire [31:0] _145_;
wire [31:0] _146_;
wire [31:0] _147_;
wire [31:0] _148_;
wire [31:0] _149_;
wire [31:0] _150_;
wire [31:0] _151_;
wire [31:0] _152_;
wire [31:0] _153_;
wire [31:0] _154_;
wire [31:0] _155_;
wire [31:0] _156_;
wire [31:0] _157_;
wire [31:0] _158_;
wire [31:0] _159_;
wire [31:0] _160_;
wire [31:0] _161_;
wire [31:0] _162_;
wire [31:0] _163_;
wire [31:0] _164_;
wire [31:0] _165_;
wire [31:0] _166_;
wire [31:0] _167_;
wire [31:0] _168_;
wire [31:0] _169_;
wire [31:0] _170_;
input clk;
wire clk;
input [31:0] rd;
wire [31:0] rd;
input [4:0] rdadr;
wire [4:0] rdadr;
wire [1023:0] registers;
input regwrite;
wire regwrite;
input reset;
wire reset;
output [31:0] rs1;
wire [31:0] rs1;
input [4:0] rs1adr;
wire [4:0] rs1adr;
output [31:0] rs2;
wire [31:0] rs2;
input [4:0] rs2adr;
wire [4:0] rs2adr;
output [12:0] x1;
wire [12:0] x1;
assign _000_ = _043_[0] ? registers[63:32] : registers[31:0];
assign _001_ = _043_[0] ? registers[191:160] : registers[159:128];
assign _002_ = _043_[0] ? registers[319:288] : registers[287:256];
assign _003_ = _043_[0] ? registers[447:416] : registers[415:384];
assign _004_ = _043_[0] ? registers[575:544] : registers[543:512];
assign _005_ = _043_[0] ? registers[703:672] : registers[671:640];
assign _006_ = _043_[0] ? registers[831:800] : registers[799:768];
assign _007_ = _043_[0] ? registers[959:928] : registers[927:896];
assign _008_ = _043_[2] ? _150_ : _149_;
assign _009_ = _043_[2] ? _154_ : _153_;
assign _010_ = _044_[0] ? registers[63:32] : registers[31:0];
assign _011_ = _044_[0] ? registers[191:160] : registers[159:128];
assign _012_ = _044_[0] ? registers[319:288] : registers[287:256];
assign _013_ = _044_[0] ? registers[447:416] : registers[415:384];
assign _014_ = _044_[0] ? registers[575:544] : registers[543:512];
assign _015_ = _044_[0] ? registers[703:672] : registers[671:640];
assign _016_ = _044_[0] ? registers[831:800] : registers[799:768];
assign _017_ = _044_[0] ? registers[959:928] : registers[927:896];
assign _018_ = _044_[2] ? _161_ : _160_;
assign _019_ = _044_[2] ? _165_ : _164_;
assign _020_ = _043_[0] ? registers[127:96] : registers[95:64];
assign _021_ = _043_[0] ? registers[255:224] : registers[223:192];
assign _022_ = _043_[0] ? registers[383:352] : registers[351:320];
assign _023_ = _043_[0] ? registers[511:480] : registers[479:448];
assign _024_ = _043_[0] ? registers[639:608] : registers[607:576];
assign _025_ = _043_[0] ? registers[767:736] : registers[735:704];
assign _026_ = _043_[0] ? registers[895:864] : registers[863:832];
assign _027_ = _043_[0] ? registers[1023:992] : registers[991:960];
assign _028_ = _043_[2] ? _152_ : _151_;
assign _029_ = _043_[2] ? _156_ : _155_;
assign _030_ = _044_[0] ? registers[127:96] : registers[95:64];
assign _031_ = _044_[0] ? registers[255:224] : registers[223:192];
assign _032_ = _044_[0] ? registers[383:352] : registers[351:320];
assign _033_ = _044_[0] ? registers[511:480] : registers[479:448];
assign _034_ = _044_[0] ? registers[639:608] : registers[607:576];
assign _035_ = _044_[0] ? registers[767:736] : registers[735:704];
assign _036_ = _044_[0] ? registers[895:864] : registers[863:832];
assign _037_ = _044_[0] ? registers[1023:992] : registers[991:960];
assign _038_ = _044_[2] ? _163_ : _162_;
assign _039_ = _044_[2] ? _167_ : _166_;
assign _149_ = _043_[1] ? _020_ : _000_;
assign _150_ = _043_[1] ? _021_ : _001_;
assign _151_ = _043_[1] ? _022_ : _002_;
assign _152_ = _043_[1] ? _023_ : _003_;
assign _153_ = _043_[1] ? _024_ : _004_;
assign _154_ = _043_[1] ? _025_ : _005_;
assign _155_ = _043_[1] ? _026_ : _006_;
assign _156_ = _043_[1] ? _027_ : _007_;
assign _157_ = _043_[3] ? _028_ : _008_;
assign _158_ = _043_[3] ? _029_ : _009_;
assign _160_ = _044_[1] ? _030_ : _010_;
assign _161_ = _044_[1] ? _031_ : _011_;
assign _162_ = _044_[1] ? _032_ : _012_;
assign _163_ = _044_[1] ? _033_ : _013_;
assign _164_ = _044_[1] ? _034_ : _014_;
assign _165_ = _044_[1] ? _035_ : _015_;
assign _166_ = _044_[1] ? _036_ : _016_;
assign _167_ = _044_[1] ? _037_ : _017_;
assign _168_ = _044_[3] ? _038_ : _018_;
assign _169_ = _044_[3] ? _039_ : _019_;
assign _170_ = _044_[4] ? _169_ : _168_;
assign _040_ = rdadr != 5'h00;
assign _041_ = _040_ & regwrite;
assign _042_ = 5'h1f - rdadr;
assign _043_ = 5'h1f - rs1adr;
assign _044_ = 5'h1f - rs2adr;
assign _045_ = _041_ ? { _148_, _147_, _146_, _145_, _144_, _143_, _142_, _141_, _140_, _139_, _138_, _137_, _136_, _135_, _134_, _133_, _132_, _131_, _130_, _129_, _128_, _127_, _126_, _125_, _124_, _123_, _122_, _121_, _120_, _119_, _118_, _117_ } : registers;
always @(posedge clk, posedge reset)
if (reset) _046_ <= 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
else _046_ <= _045_;
always @(posedge clk, posedge reset)
if (reset) _047_ <= 32'd0;
else _047_ <= _159_;
always @(posedge clk, posedge reset)
if (reset) _048_ <= 32'd0;
else _048_ <= _170_;
assign _049_ = ~ reset;
assign _050_ = _049_ ? registers[972:960] : _051_;
always @(posedge clk)
_051_ <= _050_;
assign _052_ = ~ _042_[4];
assign _053_ = ~ _042_[3];
assign _054_ = _052_ & _053_;
assign _055_ = _052_ & _042_[3];
assign _056_ = _042_[4] & _053_;
assign _057_ = _042_[4] & _042_[3];
assign _058_ = ~ _042_[2];
assign _059_ = _054_ & _058_;
assign _060_ = _054_ & _042_[2];
assign _061_ = _055_ & _058_;
assign _062_ = _055_ & _042_[2];
assign _063_ = _056_ & _058_;
assign _064_ = _056_ & _042_[2];
assign _065_ = _057_ & _058_;
assign _066_ = _057_ & _042_[2];
assign _067_ = ~ _042_[1];
assign _068_ = _059_ & _067_;
assign _069_ = _059_ & _042_[1];
assign _070_ = _060_ & _067_;
assign _071_ = _060_ & _042_[1];
assign _072_ = _061_ & _067_;
assign _073_ = _061_ & _042_[1];
assign _074_ = _062_ & _067_;
assign _075_ = _062_ & _042_[1];
assign _076_ = _063_ & _067_;
assign _077_ = _063_ & _042_[1];
assign _078_ = _064_ & _067_;
assign _079_ = _064_ & _042_[1];
assign _080_ = _065_ & _067_;
assign _081_ = _065_ & _042_[1];
assign _082_ = _066_ & _067_;
assign _083_ = _066_ & _042_[1];
assign _084_ = ~ _042_[0];
assign _085_ = _068_ & _084_;
assign _086_ = _068_ & _042_[0];
assign _087_ = _069_ & _084_;
assign _088_ = _069_ & _042_[0];
assign _089_ = _070_ & _084_;
assign _090_ = _070_ & _042_[0];
assign _091_ = _071_ & _084_;
assign _092_ = _071_ & _042_[0];
assign _093_ = _072_ & _084_;
assign _094_ = _072_ & _042_[0];
assign _095_ = _073_ & _084_;
assign _096_ = _073_ & _042_[0];
assign _097_ = _074_ & _084_;
assign _098_ = _074_ & _042_[0];
assign _099_ = _075_ & _084_;
assign _100_ = _075_ & _042_[0];
assign _101_ = _076_ & _084_;
assign _102_ = _076_ & _042_[0];
assign _103_ = _077_ & _084_;
assign _104_ = _077_ & _042_[0];
assign _105_ = _078_ & _084_;
assign _106_ = _078_ & _042_[0];
assign _107_ = _079_ & _084_;
assign _108_ = _079_ & _042_[0];
assign _109_ = _080_ & _084_;
assign _110_ = _080_ & _042_[0];
assign _111_ = _081_ & _084_;
assign _112_ = _081_ & _042_[0];
assign _113_ = _082_ & _084_;
assign _114_ = _082_ & _042_[0];
assign _115_ = _083_ & _084_;
assign _116_ = _083_ & _042_[0];
assign _117_ = _085_ ? rd : registers[31:0];
assign _118_ = _086_ ? rd : registers[63:32];
assign _119_ = _087_ ? rd : registers[95:64];
assign _120_ = _088_ ? rd : registers[127:96];
assign _121_ = _089_ ? rd : registers[159:128];
assign _122_ = _090_ ? rd : registers[191:160];
assign _123_ = _091_ ? rd : registers[223:192];
assign _124_ = _092_ ? rd : registers[255:224];
assign _125_ = _093_ ? rd : registers[287:256];
assign _126_ = _094_ ? rd : registers[319:288];
assign _127_ = _095_ ? rd : registers[351:320];
assign _128_ = _096_ ? rd : registers[383:352];
assign _129_ = _097_ ? rd : registers[415:384];
assign _130_ = _098_ ? rd : registers[447:416];
assign _131_ = _099_ ? rd : registers[479:448];
assign _132_ = _100_ ? rd : registers[511:480];
assign _133_ = _101_ ? rd : registers[543:512];
assign _134_ = _102_ ? rd : registers[575:544];
assign _135_ = _103_ ? rd : registers[607:576];
assign _136_ = _104_ ? rd : registers[639:608];
assign _137_ = _105_ ? rd : registers[671:640];
assign _138_ = _106_ ? rd : registers[703:672];
assign _139_ = _107_ ? rd : registers[735:704];
assign _140_ = _108_ ? rd : registers[767:736];
assign _141_ = _109_ ? rd : registers[799:768];
assign _142_ = _110_ ? rd : registers[831:800];
assign _143_ = _111_ ? rd : registers[863:832];
assign _144_ = _112_ ? rd : registers[895:864];
assign _145_ = _113_ ? rd : registers[927:896];
assign _146_ = _114_ ? rd : registers[959:928];
assign _147_ = _115_ ? rd : registers[991:960];
assign _148_ = _116_ ? rd : registers[1023:992];
assign _159_ = _043_[4] ? _158_ : _157_;
assign registers = _046_;
assign rs1 = _047_;
assign rs2 = _048_;
assign x1 = _051_;
endmodule
|
tt06-finale_0006
|
tt06-finale
|
CEJMU-tt06_tinyrv1
|
task_spi_master
|
tt_um_cejmu_riscv
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/* Generated by Yosys 0.39+165 (git sha1 22c5ab90d, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */
module alu(clk, reset, a, b, instruction, rd);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire [31:0] _15_;
wire _16_;
wire _17_;
wire _18_;
wire _19_;
wire _20_;
wire [31:0] _21_;
wire _22_;
wire _23_;
wire _24_;
wire _25_;
wire _26_;
wire [31:0] _27_;
wire _28_;
wire _29_;
wire _30_;
wire _31_;
wire _32_;
wire _33_;
wire [1:0] _34_;
wire [31:0] _35_;
wire [31:0] _36_;
wire [31:0] _37_;
wire [31:0] _38_;
wire [31:0] _39_;
wire [31:0] _40_;
wire [31:0] _41_;
reg [31:0] _42_;
input [31:0] a;
wire [31:0] a;
input [31:0] b;
wire [31:0] b;
input clk;
wire clk;
input [16:0] instruction;
wire [16:0] instruction;
output [31:0] rd;
wire [31:0] rd;
input reset;
wire reset;
assign _00_ = instruction[16:10] == 7'h00;
assign _01_ = instruction[9:7] == 3'h0;
assign _02_ = _01_ & _00_;
assign _03_ = instruction[6:0] == 7'h33;
assign _04_ = _03_ & _02_;
assign _05_ = instruction[9:7] == 3'h0;
assign _06_ = instruction[6:0] == 7'h13;
assign _07_ = _06_ & _05_;
assign _08_ = _04_ | _07_;
assign _09_ = instruction[6:0] == 7'h23;
assign _10_ = instruction[6:0] == 7'h03;
assign _11_ = _09_ | _10_;
assign _12_ = instruction[9:7] == 3'h2;
assign _13_ = _12_ & _11_;
assign _14_ = _08_ | _13_;
assign _15_ = a + b;
assign _16_ = instruction[16:10] == 7'h00;
assign _17_ = instruction[9:7] == 3'h7;
assign _18_ = _17_ & _16_;
assign _19_ = instruction[6:0] == 7'h33;
assign _20_ = _19_ & _18_;
assign _21_ = a & b;
assign _22_ = instruction[16:10] == 7'h00;
assign _23_ = instruction[9:7] == 3'h4;
assign _24_ = _23_ & _22_;
assign _25_ = instruction[6:0] == 7'h33;
assign _26_ = _25_ & _24_;
assign _27_ = a ^ b;
assign _28_ = instruction[6:0] == 7'h6f;
assign _29_ = instruction[6:0] == 7'h67;
assign _30_ = instruction[6:0] == 7'h63;
assign _31_ = instruction[9:7] == 3'h1;
assign _32_ = _31_ & _30_;
assign _33_ = a == b;
assign _34_ = _33_ ? 2'h2 : 2'h0;
assign _35_ = _32_ ? { 14'h0000, _34_, 16'h0000 } : 32'd0;
assign _36_ = _29_ ? 32'd65536 : _35_;
assign _37_ = _28_ ? 32'd0 : _36_;
assign _38_ = _26_ ? _27_ : _37_;
assign _39_ = _20_ ? _21_ : _38_;
assign _40_ = _14_ ? _15_ : _39_;
assign _41_ = reset ? 32'd0 : _40_;
always @(posedge clk)
_42_ <= _41_;
assign rd = _42_;
endmodule
module control(clk, reset, iword, data_valid, imm, control_flags_out, wbflag, memflag, pcflag, fetchflag, mem_req);
wire _000_;
wire _001_;
wire _002_;
wire [2:0] _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire [2:0] _012_;
wire _013_;
wire [2:0] _014_;
wire [2:0] _015_;
wire [2:0] _016_;
wire [2:0] _017_;
wire [2:0] _018_;
wire [2:0] _019_;
wire [2:0] _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire [31:0] _066_;
wire _067_;
wire [31:0] _068_;
wire _069_;
wire [31:0] _070_;
wire _071_;
wire [31:0] _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
reg [2:0] _109_;
input clk;
wire clk;
wire [6:0] control_flags;
output [6:0] control_flags_out;
wire [6:0] control_flags_out;
wire [2:0] currstate;
input data_valid;
wire data_valid;
output fetchflag;
wire fetchflag;
output [31:0] imm;
wire [31:0] imm;
input [31:0] iword;
wire [31:0] iword;
output mem_req;
wire mem_req;
output memflag;
wire memflag;
output pcflag;
wire pcflag;
input reset;
wire reset;
wire [20:0] w31_to_w11;
output wbflag;
wire wbflag;
assign _000_ = currstate == 3'h0;
assign _001_ = currstate == 3'h5;
assign _002_ = currstate == 3'h1;
assign _003_ = data_valid ? 3'h6 : currstate;
assign _004_ = currstate == 3'h6;
assign _005_ = currstate == 3'h2;
assign _006_ = currstate == 3'h3;
assign _007_ = control_flags[0] & _006_;
assign _008_ = currstate == 3'h3;
assign _009_ = ~ control_flags[0];
assign _010_ = _009_ & _008_;
assign _011_ = currstate == 3'h4;
assign _012_ = _013_ ? 3'h5 : currstate;
assign _013_ = data_valid & _011_;
assign _014_ = _010_ ? 3'h5 : _012_;
assign _015_ = _007_ ? 3'h4 : _014_;
assign _016_ = _005_ ? 3'h3 : _015_;
assign _017_ = _004_ ? 3'h2 : _016_;
assign _018_ = _002_ ? _003_ : _017_;
assign _019_ = _001_ ? 3'h1 : _018_;
assign _020_ = _000_ ? 3'h1 : _019_;
assign _021_ = currstate == 3'h1;
assign _022_ = currstate == 3'h4;
assign _023_ = _021_ | _022_;
assign _024_ = ~ data_valid;
assign _025_ = _024_ & _023_;
assign _026_ = _025_ ? 1'h0 : 1'h1;
assign _027_ = currstate == 3'h3;
assign _028_ = ~ control_flags[0];
assign _029_ = _028_ & _027_;
assign _030_ = currstate == 3'h4;
assign _031_ = data_valid & _030_;
assign _032_ = _029_ | _031_;
assign _033_ = _032_ ? 1'h1 : 1'h0;
assign _034_ = currstate == 3'h3;
assign _035_ = control_flags[0] & _034_;
assign _036_ = control_flags[1] & _035_;
assign _037_ = currstate == 3'h4;
assign _038_ = control_flags[1] & _037_;
assign _039_ = _036_ | _038_;
assign _040_ = _039_ ? 1'h1 : 1'h0;
assign _041_ = currstate == 3'h4;
assign _042_ = control_flags[2] & _041_;
assign _043_ = data_valid & _042_;
assign _044_ = currstate == 3'h3;
assign _045_ = control_flags[2] & _044_;
assign _046_ = ~ control_flags[0];
assign _047_ = _046_ & _045_;
assign _048_ = _043_ | _047_;
assign _049_ = _048_ ? 1'h1 : 1'h0;
assign _050_ = currstate == 3'h1;
assign _051_ = data_valid & _050_;
assign _052_ = _051_ ? 1'h1 : 1'h0;
assign _053_ = currstate == 3'h1;
assign _054_ = currstate == 3'h0;
assign _055_ = _053_ | _054_;
assign _056_ = currstate == 3'h5;
assign _057_ = _055_ | _056_;
assign _058_ = _057_ ? 1'h1 : 1'h0;
assign _059_ = iword[6:0] == 7'h67;
assign _060_ = _059_ ? 1'h1 : 1'h0;
assign _061_ = iword[6:0] == 7'h03;
assign _062_ = iword[6:0] == 7'h13;
assign _063_ = _061_ | _062_;
assign _064_ = iword[6:0] == 7'h67;
assign _065_ = _063_ | _064_;
assign _066_ = _065_ ? { w31_to_w11, iword[30:20] } : _068_;
assign _067_ = iword[6:0] == 7'h23;
assign _068_ = _067_ ? { w31_to_w11, iword[30:25], iword[11:7] } : _070_;
assign _069_ = iword[6:0] == 7'h63;
assign _070_ = _069_ ? { w31_to_w11[20:1], iword[7], iword[30:25], iword[11:8], 1'h0 } : _072_;
assign _071_ = iword[6:0] == 7'h6f;
assign _072_ = _071_ ? { w31_to_w11[11:0], iword[19:12], iword[20], iword[30:21], 1'h0 } : 32'd0;
assign _073_ = iword[6:0] == 7'h03;
assign _074_ = iword[6:0] == 7'h23;
assign _075_ = _073_ | _074_;
assign _076_ = iword[14:12] == 3'h2;
assign _077_ = _076_ & _075_;
assign _078_ = _077_ ? 1'h1 : 1'h0;
assign _079_ = iword[6:0] == 7'h23;
assign _080_ = iword[14:12] == 3'h2;
assign _081_ = _080_ & _079_;
assign _082_ = _081_ ? 1'h1 : 1'h0;
assign _083_ = iword[6:0] == 7'h63;
assign _084_ = _083_ ? 1'h0 : 1'h1;
assign _085_ = iword[6:0] == 7'h13;
assign _086_ = iword[6:0] == 7'h37;
assign _087_ = _085_ | _086_;
assign _088_ = iword[6:0] == 7'h17;
assign _089_ = _087_ | _088_;
assign _090_ = iword[6:0] == 7'h03;
assign _091_ = iword[6:0] == 7'h23;
assign _092_ = _090_ | _091_;
assign _093_ = iword[14:12] == 3'h2;
assign _094_ = _093_ & _092_;
assign _095_ = _089_ | _094_;
assign _096_ = iword[6:0] == 7'h6f;
assign _097_ = _095_ | _096_;
assign _098_ = iword[6:0] == 7'h67;
assign _099_ = _097_ | _098_;
assign _100_ = _099_ ? 1'h1 : 1'h0;
assign _101_ = iword[6:0] == 7'h63;
assign _102_ = iword[6:0] == 7'h6f;
assign _103_ = _101_ | _102_;
assign _104_ = iword[6:0] == 7'h67;
assign _105_ = _103_ | _104_;
assign _106_ = iword[6:0] == 7'h67;
assign _107_ = _105_ | _106_;
assign _108_ = _107_ ? 1'h1 : 1'h0;
always @(posedge clk, posedge reset)
if (reset) _109_ <= 3'h0;
else _109_ <= _020_;
assign currstate = _109_;
assign control_flags = { _060_, _058_, _108_, _100_, _084_, _082_, _078_ };
assign w31_to_w11 = { iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31] };
assign imm = _066_;
assign control_flags_out = control_flags;
assign wbflag = _049_;
assign memflag = _040_;
assign pcflag = _033_;
assign fetchflag = _052_;
assign mem_req = _026_;
endmodule
module cpu(clk, reset, data_in, data_valid, data_out, addr_out, write_en, mem_req, x1);
wire [31:0] _00_;
wire [31:0] _01_;
wire [12:0] _02_;
wire [31:0] _03_;
wire [31:0] _04_;
wire [6:0] _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire [31:0] _11_;
wire [31:0] _12_;
wire [31:0] _13_;
wire _14_;
wire _15_;
wire [15:0] _16_;
wire [15:0] _17_;
wire [15:0] _18_;
wire [13:0] _19_;
wire [31:0] _20_;
reg [31:0] _21_;
output [13:0] addr_out;
wire [13:0] addr_out;
wire [31:0] b;
input clk;
wire clk;
wire [6:0] control_flags_out;
input [31:0] data_in;
wire [31:0] data_in;
output [31:0] data_out;
wire [31:0] data_out;
input data_valid;
wire data_valid;
wire fetchflag;
wire [31:0] imm;
wire [16:0] instruction;
wire [31:0] iword_reg;
output mem_req;
wire mem_req;
wire memflag;
wire [15:0] pc_inc;
wire [15:0] pc_offset;
wire [15:0] pc_out;
wire pcflag;
wire [31:0] rd;
wire [31:0] rdalu;
input reset;
wire reset;
wire [31:0] rs1;
wire [31:0] rs2;
wire s0;
wire s1;
wire wbflag;
output write_en;
wire write_en;
output [12:0] x1;
wire [12:0] x1;
assign _11_ = control_flags_out[3] ? imm : rs2;
assign _12_ = control_flags_out[4] ? { 16'h0000, pc_inc } : _13_;
assign _13_ = control_flags_out[0] ? data_in : rdalu;
assign _14_ = control_flags_out[4] ? rdalu[16] : 1'h0;
assign _15_ = control_flags_out[4] ? rdalu[17] : 1'h1;
assign _18_ = control_flags_out[6] ? rs1[15:0] : imm[15:0];
assign _19_ = control_flags_out[5] ? pc_out[15:2] : rdalu[13:0];
assign _20_ = fetchflag ? data_in : iword_reg;
always @(posedge clk, posedge reset)
if (reset) _21_ <= 32'd0;
else _21_ <= _20_;
alu alu_inst (
.a(rs1),
.b(b),
.clk(clk),
.instruction(instruction),
.rd(_03_),
.reset(reset)
);
control control_inst (
.clk(clk),
.control_flags_out(_05_),
.data_valid(data_valid),
.fetchflag(_09_),
.imm(_04_),
.iword(iword_reg),
.mem_req(_10_),
.memflag(_07_),
.pcflag(_08_),
.reset(reset),
.wbflag(_06_)
);
instructioncounter instruction_inst (
.clk(clk),
.pc_inc(_16_),
.pc_new(_17_),
.pc_offset(pc_offset),
.pcflag(pcflag),
.reset(reset),
.s0(s0),
.s1(s1)
);
regs regs_inst (
.clk(clk),
.rd(rd),
.rdadr(iword_reg[11:7]),
.regwrite(wbflag),
.reset(reset),
.rs1(_00_),
.rs1adr(iword_reg[19:15]),
.rs2(_01_),
.rs2adr(iword_reg[24:20]),
.x1(_02_)
);
assign s0 = _14_;
assign s1 = _15_;
assign imm = _04_;
assign control_flags_out = _05_;
assign rs1 = _00_;
assign rs2 = _01_;
assign b = _11_;
assign rdalu = _03_;
assign rd = _12_;
assign wbflag = _06_;
assign memflag = _07_;
assign pcflag = _08_;
assign fetchflag = _09_;
assign instruction = { iword_reg[31:25], iword_reg[14:12], iword_reg[6:0] };
assign iword_reg = _21_;
assign pc_inc = _16_;
assign pc_out = _17_;
assign pc_offset = _18_;
assign data_out = rs2;
assign addr_out = _19_;
assign write_en = memflag;
assign mem_req = _10_;
assign x1 = _02_;
endmodule
module instructioncounter(clk, reset, pcflag, s0, s1, pc_offset, pc_inc, pc_new);
wire [15:0] _00_;
wire [15:0] _01_;
wire _02_;
wire [15:0] _03_;
wire _04_;
wire _05_;
wire [15:0] _06_;
wire [15:0] _07_;
wire [15:0] _08_;
reg [15:0] _09_ = 16'h0000;
reg [15:0] _10_;
input clk;
wire clk;
output [15:0] pc_inc;
wire [15:0] pc_inc;
output [15:0] pc_new;
wire [15:0] pc_new;
input [15:0] pc_offset;
wire [15:0] pc_offset;
input pcflag;
wire pcflag;
wire [15:0] \reg ;
input reset;
wire reset;
input s0;
wire s0;
input s1;
wire s1;
wire [1:0] s1s0;
assign _00_ = \reg + 16'h0004;
assign _01_ = pc_offset + \reg ;
assign _02_ = s1s0 == 2'h0;
assign _03_ = \reg + 16'h0004;
assign _04_ = s1s0 == 2'h2;
assign _05_ = s1s0 == 2'h1;
function [15:0] \1383 ;
input [15:0] a;
input [47:0] b;
input [2:0] s;
(* parallel_case *)
casez (s)
3'b??1:
\1383 = b[15:0];
3'b?1?:
\1383 = b[31:16];
3'b1??:
\1383 = b[47:32];
default:
\1383 = a;
endcase
endfunction
assign _06_ = \1383 (16'h0000, { pc_offset, _03_, _01_ }, { _05_, _04_, _02_ });
assign _07_ = pcflag ? _06_ : \reg ;
assign _08_ = reset ? 16'h0000 : _07_;
always @(posedge clk)
_09_ <= _08_;
always @(posedge clk)
_10_ <= _00_;
assign s1s0 = { s1, s0 };
assign \reg = _09_;
assign pc_inc = _10_;
assign pc_new = \reg ;
endmodule
module regs(clk, reset, rs1adr, rs2adr, rdadr, rd, regwrite, rs1, rs2, x1);
wire [31:0] _000_;
wire [31:0] _001_;
wire [31:0] _002_;
wire [31:0] _003_;
wire [31:0] _004_;
wire [31:0] _005_;
wire [31:0] _006_;
wire [31:0] _007_;
wire [31:0] _008_;
wire [31:0] _009_;
wire [31:0] _010_;
wire [31:0] _011_;
wire [31:0] _012_;
wire [31:0] _013_;
wire [31:0] _014_;
wire [31:0] _015_;
wire [31:0] _016_;
wire [31:0] _017_;
wire [31:0] _018_;
wire [31:0] _019_;
wire [31:0] _020_;
wire [31:0] _021_;
wire [31:0] _022_;
wire [31:0] _023_;
wire [31:0] _024_;
wire [31:0] _025_;
wire [31:0] _026_;
wire [31:0] _027_;
wire [31:0] _028_;
wire [31:0] _029_;
wire [31:0] _030_;
wire [31:0] _031_;
wire [31:0] _032_;
wire [31:0] _033_;
wire [31:0] _034_;
wire [31:0] _035_;
wire [31:0] _036_;
wire [31:0] _037_;
wire [31:0] _038_;
wire [31:0] _039_;
wire _040_;
wire _041_;
wire [4:0] _042_;
wire [4:0] _043_;
wire [4:0] _044_;
wire [1023:0] _045_;
reg [1023:0] _046_;
reg [31:0] _047_;
reg [31:0] _048_;
wire _049_;
wire [12:0] _050_;
reg [12:0] _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire [31:0] _117_;
wire [31:0] _118_;
wire [31:0] _119_;
wire [31:0] _120_;
wire [31:0] _121_;
wire [31:0] _122_;
wire [31:0] _123_;
wire [31:0] _124_;
wire [31:0] _125_;
wire [31:0] _126_;
wire [31:0] _127_;
wire [31:0] _128_;
wire [31:0] _129_;
wire [31:0] _130_;
wire [31:0] _131_;
wire [31:0] _132_;
wire [31:0] _133_;
wire [31:0] _134_;
wire [31:0] _135_;
wire [31:0] _136_;
wire [31:0] _137_;
wire [31:0] _138_;
wire [31:0] _139_;
wire [31:0] _140_;
wire [31:0] _141_;
wire [31:0] _142_;
wire [31:0] _143_;
wire [31:0] _144_;
wire [31:0] _145_;
wire [31:0] _146_;
wire [31:0] _147_;
wire [31:0] _148_;
wire [31:0] _149_;
wire [31:0] _150_;
wire [31:0] _151_;
wire [31:0] _152_;
wire [31:0] _153_;
wire [31:0] _154_;
wire [31:0] _155_;
wire [31:0] _156_;
wire [31:0] _157_;
wire [31:0] _158_;
wire [31:0] _159_;
wire [31:0] _160_;
wire [31:0] _161_;
wire [31:0] _162_;
wire [31:0] _163_;
wire [31:0] _164_;
wire [31:0] _165_;
wire [31:0] _166_;
wire [31:0] _167_;
wire [31:0] _168_;
wire [31:0] _169_;
wire [31:0] _170_;
input clk;
wire clk;
input [31:0] rd;
wire [31:0] rd;
input [4:0] rdadr;
wire [4:0] rdadr;
wire [1023:0] registers;
input regwrite;
wire regwrite;
input reset;
wire reset;
output [31:0] rs1;
wire [31:0] rs1;
input [4:0] rs1adr;
wire [4:0] rs1adr;
output [31:0] rs2;
wire [31:0] rs2;
input [4:0] rs2adr;
wire [4:0] rs2adr;
output [12:0] x1;
wire [12:0] x1;
assign _000_ = _043_[0] ? registers[63:32] : registers[31:0];
assign _001_ = _043_[0] ? registers[191:160] : registers[159:128];
assign _002_ = _043_[0] ? registers[319:288] : registers[287:256];
assign _003_ = _043_[0] ? registers[447:416] : registers[415:384];
assign _004_ = _043_[0] ? registers[575:544] : registers[543:512];
assign _005_ = _043_[0] ? registers[703:672] : registers[671:640];
assign _006_ = _043_[0] ? registers[831:800] : registers[799:768];
assign _007_ = _043_[0] ? registers[959:928] : registers[927:896];
assign _008_ = _043_[2] ? _150_ : _149_;
assign _009_ = _043_[2] ? _154_ : _153_;
assign _010_ = _044_[0] ? registers[63:32] : registers[31:0];
assign _011_ = _044_[0] ? registers[191:160] : registers[159:128];
assign _012_ = _044_[0] ? registers[319:288] : registers[287:256];
assign _013_ = _044_[0] ? registers[447:416] : registers[415:384];
assign _014_ = _044_[0] ? registers[575:544] : registers[543:512];
assign _015_ = _044_[0] ? registers[703:672] : registers[671:640];
assign _016_ = _044_[0] ? registers[831:800] : registers[799:768];
assign _017_ = _044_[0] ? registers[959:928] : registers[927:896];
assign _018_ = _044_[2] ? _161_ : _160_;
assign _019_ = _044_[2] ? _165_ : _164_;
assign _020_ = _043_[0] ? registers[127:96] : registers[95:64];
assign _021_ = _043_[0] ? registers[255:224] : registers[223:192];
assign _022_ = _043_[0] ? registers[383:352] : registers[351:320];
assign _023_ = _043_[0] ? registers[511:480] : registers[479:448];
assign _024_ = _043_[0] ? registers[639:608] : registers[607:576];
assign _025_ = _043_[0] ? registers[767:736] : registers[735:704];
assign _026_ = _043_[0] ? registers[895:864] : registers[863:832];
assign _027_ = _043_[0] ? registers[1023:992] : registers[991:960];
assign _028_ = _043_[2] ? _152_ : _151_;
assign _029_ = _043_[2] ? _156_ : _155_;
assign _030_ = _044_[0] ? registers[127:96] : registers[95:64];
assign _031_ = _044_[0] ? registers[255:224] : registers[223:192];
assign _032_ = _044_[0] ? registers[383:352] : registers[351:320];
assign _033_ = _044_[0] ? registers[511:480] : registers[479:448];
assign _034_ = _044_[0] ? registers[639:608] : registers[607:576];
assign _035_ = _044_[0] ? registers[767:736] : registers[735:704];
assign _036_ = _044_[0] ? registers[895:864] : registers[863:832];
assign _037_ = _044_[0] ? registers[1023:992] : registers[991:960];
assign _038_ = _044_[2] ? _163_ : _162_;
assign _039_ = _044_[2] ? _167_ : _166_;
assign _149_ = _043_[1] ? _020_ : _000_;
assign _150_ = _043_[1] ? _021_ : _001_;
assign _151_ = _043_[1] ? _022_ : _002_;
assign _152_ = _043_[1] ? _023_ : _003_;
assign _153_ = _043_[1] ? _024_ : _004_;
assign _154_ = _043_[1] ? _025_ : _005_;
assign _155_ = _043_[1] ? _026_ : _006_;
assign _156_ = _043_[1] ? _027_ : _007_;
assign _157_ = _043_[3] ? _028_ : _008_;
assign _158_ = _043_[3] ? _029_ : _009_;
assign _160_ = _044_[1] ? _030_ : _010_;
assign _161_ = _044_[1] ? _031_ : _011_;
assign _162_ = _044_[1] ? _032_ : _012_;
assign _163_ = _044_[1] ? _033_ : _013_;
assign _164_ = _044_[1] ? _034_ : _014_;
assign _165_ = _044_[1] ? _035_ : _015_;
assign _166_ = _044_[1] ? _036_ : _016_;
assign _167_ = _044_[1] ? _037_ : _017_;
assign _168_ = _044_[3] ? _038_ : _018_;
assign _169_ = _044_[3] ? _039_ : _019_;
assign _170_ = _044_[4] ? _169_ : _168_;
assign _040_ = rdadr != 5'h00;
assign _041_ = _040_ & regwrite;
assign _042_ = 5'h1f - rdadr;
assign _043_ = 5'h1f - rs1adr;
assign _044_ = 5'h1f - rs2adr;
assign _045_ = _041_ ? { _148_, _147_, _146_, _145_, _144_, _143_, _142_, _141_, _140_, _139_, _138_, _137_, _136_, _135_, _134_, _133_, _132_, _131_, _130_, _129_, _128_, _127_, _126_, _125_, _124_, _123_, _122_, _121_, _120_, _119_, _118_, _117_ } : registers;
always @(posedge clk, posedge reset)
if (reset) _046_ <= 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
else _046_ <= _045_;
always @(posedge clk, posedge reset)
if (reset) _047_ <= 32'd0;
else _047_ <= _159_;
always @(posedge clk, posedge reset)
if (reset) _048_ <= 32'd0;
else _048_ <= _170_;
assign _049_ = ~ reset;
assign _050_ = _049_ ? registers[972:960] : _051_;
always @(posedge clk)
_051_ <= _050_;
assign _052_ = ~ _042_[4];
assign _053_ = ~ _042_[3];
assign _054_ = _052_ & _053_;
assign _055_ = _052_ & _042_[3];
assign _056_ = _042_[4] & _053_;
assign _057_ = _042_[4] & _042_[3];
assign _058_ = ~ _042_[2];
assign _059_ = _054_ & _058_;
assign _060_ = _054_ & _042_[2];
assign _061_ = _055_ & _058_;
assign _062_ = _055_ & _042_[2];
assign _063_ = _056_ & _058_;
assign _064_ = _056_ & _042_[2];
assign _065_ = _057_ & _058_;
assign _066_ = _057_ & _042_[2];
assign _067_ = ~ _042_[1];
assign _068_ = _059_ & _067_;
assign _069_ = _059_ & _042_[1];
assign _070_ = _060_ & _067_;
assign _071_ = _060_ & _042_[1];
assign _072_ = _061_ & _067_;
assign _073_ = _061_ & _042_[1];
assign _074_ = _062_ & _067_;
assign _075_ = _062_ & _042_[1];
assign _076_ = _063_ & _067_;
assign _077_ = _063_ & _042_[1];
assign _078_ = _064_ & _067_;
assign _079_ = _064_ & _042_[1];
assign _080_ = _065_ & _067_;
assign _081_ = _065_ & _042_[1];
assign _082_ = _066_ & _067_;
assign _083_ = _066_ & _042_[1];
assign _084_ = ~ _042_[0];
assign _085_ = _068_ & _084_;
assign _086_ = _068_ & _042_[0];
assign _087_ = _069_ & _084_;
assign _088_ = _069_ & _042_[0];
assign _089_ = _070_ & _084_;
assign _090_ = _070_ & _042_[0];
assign _091_ = _071_ & _084_;
assign _092_ = _071_ & _042_[0];
assign _093_ = _072_ & _084_;
assign _094_ = _072_ & _042_[0];
assign _095_ = _073_ & _084_;
assign _096_ = _073_ & _042_[0];
assign _097_ = _074_ & _084_;
assign _098_ = _074_ & _042_[0];
assign _099_ = _075_ & _084_;
assign _100_ = _075_ & _042_[0];
assign _101_ = _076_ & _084_;
assign _102_ = _076_ & _042_[0];
assign _103_ = _077_ & _084_;
assign _104_ = _077_ & _042_[0];
assign _105_ = _078_ & _084_;
assign _106_ = _078_ & _042_[0];
assign _107_ = _079_ & _084_;
assign _108_ = _079_ & _042_[0];
assign _109_ = _080_ & _084_;
assign _110_ = _080_ & _042_[0];
assign _111_ = _081_ & _084_;
assign _112_ = _081_ & _042_[0];
assign _113_ = _082_ & _084_;
assign _114_ = _082_ & _042_[0];
assign _115_ = _083_ & _084_;
assign _116_ = _083_ & _042_[0];
assign _117_ = _085_ ? rd : registers[31:0];
assign _118_ = _086_ ? rd : registers[63:32];
assign _119_ = _087_ ? rd : registers[95:64];
assign _120_ = _088_ ? rd : registers[127:96];
assign _121_ = _089_ ? rd : registers[159:128];
assign _122_ = _090_ ? rd : registers[191:160];
assign _123_ = _091_ ? rd : registers[223:192];
assign _124_ = _092_ ? rd : registers[255:224];
assign _125_ = _093_ ? rd : registers[287:256];
assign _126_ = _094_ ? rd : registers[319:288];
assign _127_ = _095_ ? rd : registers[351:320];
assign _128_ = _096_ ? rd : registers[383:352];
assign _129_ = _097_ ? rd : registers[415:384];
assign _130_ = _098_ ? rd : registers[447:416];
assign _131_ = _099_ ? rd : registers[479:448];
assign _132_ = _100_ ? rd : registers[511:480];
assign _133_ = _101_ ? rd : registers[543:512];
assign _134_ = _102_ ? rd : registers[575:544];
assign _135_ = _103_ ? rd : registers[607:576];
assign _136_ = _104_ ? rd : registers[639:608];
assign _137_ = _105_ ? rd : registers[671:640];
assign _138_ = _106_ ? rd : registers[703:672];
assign _139_ = _107_ ? rd : registers[735:704];
assign _140_ = _108_ ? rd : registers[767:736];
assign _141_ = _109_ ? rd : registers[799:768];
assign _142_ = _110_ ? rd : registers[831:800];
assign _143_ = _111_ ? rd : registers[863:832];
assign _144_ = _112_ ? rd : registers[895:864];
assign _145_ = _113_ ? rd : registers[927:896];
assign _146_ = _114_ ? rd : registers[959:928];
assign _147_ = _115_ ? rd : registers[991:960];
assign _148_ = _116_ ? rd : registers[1023:992];
assign _159_ = _043_[4] ? _158_ : _157_;
assign registers = _046_;
assign rs1 = _047_;
assign rs2 = _048_;
assign x1 = _051_;
endmodule
module spi_master(clk, mode_select, reset, miso, cs, data_in, addr, sclk, mosi, data_out, data_valid);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module tt_um_cejmu_riscv(clk, ena, rst_n, ui_in, uio_in, uo_out, uio_out, uio_oe);
wire _0_;
wire _1_;
wire [31:0] _2_;
wire [13:0] _3_;
wire _4_;
wire _5_;
wire [12:0] _6_;
wire _7_;
wire _8_;
wire [31:0] _9_;
input clk;
wire clk;
wire [13:0] cpu_addr_out;
wire data_valid;
input ena;
wire ena;
wire mem_req;
wire reset;
input rst_n;
wire rst_n;
wire [15:0] spi_addr_in;
wire [31:0] spi_data_in;
wire [31:0] spi_data_out;
input [7:0] ui_in;
wire [7:0] ui_in;
input [7:0] uio_in;
wire [7:0] uio_in;
output [7:0] uio_oe;
wire [7:0] uio_oe;
output [7:0] uio_out;
wire [7:0] uio_out;
output [7:0] uo_out;
wire [7:0] uo_out;
wire write_enable;
wire [12:0] x1;
assign _0_ = ~ rst_n;
cpu cpu_inst (
.addr_out(_3_),
.clk(clk),
.data_in(spi_data_out),
.data_out(_2_),
.data_valid(data_valid),
.mem_req(_5_),
.reset(reset),
.write_en(_4_),
.x1(_6_)
);
spi_master spi_master_inst (
.addr(spi_addr_in),
.clk(clk),
.cs(mem_req),
.data_in(spi_data_in),
.data_out(_9_),
.data_valid(_1_),
.miso(ui_in[0]),
.mode_select(write_enable),
.mosi(_8_),
.reset(reset),
.sclk(_7_)
);
assign write_enable = _4_;
assign cpu_addr_out = _3_;
assign spi_addr_in = { 2'h0, cpu_addr_out };
assign spi_data_out = _9_;
assign spi_data_in = _2_;
assign mem_req = _5_;
assign data_valid = _1_;
assign reset = _0_;
assign x1 = _6_;
assign uo_out = { x1[4:0], mem_req, _7_, _8_ };
assign uio_out = x1[12:5];
assign uio_oe = 8'hff;
endmodule
|
module spi_master(clk, mode_select, reset, miso, cs, data_in, addr, sclk, mosi, data_out, data_valid);
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire [31:0] _060_;
wire [31:0] _061_;
wire [31:0] _062_;
wire [2:0] _063_;
wire _064_;
wire [31:0] _065_;
reg [31:0] _066_;
wire _067_;
wire _068_;
wire _069_;
reg _070_;
wire _071_;
wire [31:0] _072_;
reg [31:0] _073_ = 32'd16;
wire _074_;
wire [31:0] _075_;
reg [31:0] _076_ = 32'd33;
reg [2:0] _077_;
wire _078_;
wire _079_;
reg _080_;
wire _081_;
wire [31:0] _082_;
reg [31:0] _083_;
wire _084_;
wire _085_;
reg _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
wire _203_;
wire _204_;
wire _205_;
wire _206_;
wire _207_;
wire _208_;
wire _209_;
wire _210_;
wire _211_;
wire _212_;
wire _213_;
wire _214_;
wire _215_;
wire _216_;
wire _217_;
wire _218_;
wire _219_;
wire _220_;
wire _221_;
wire _222_;
wire _223_;
wire _224_;
wire _225_;
wire _226_;
wire _227_;
wire _228_;
wire _229_;
wire _230_;
wire _231_;
wire _232_;
wire _233_;
wire _234_;
wire _235_;
wire _236_;
wire _237_;
wire _238_;
wire _239_;
wire _240_;
wire _241_;
wire _242_;
wire _243_;
wire _244_;
wire _245_;
wire _246_;
wire _247_;
wire _248_;
wire _249_;
wire _250_;
wire _251_;
wire _252_;
wire _253_;
wire _254_;
wire _255_;
wire _256_;
wire _257_;
wire _258_;
wire _259_;
wire _260_;
wire _261_;
wire _262_;
wire _263_;
wire _264_;
wire _265_;
wire _266_;
wire _267_;
wire _268_;
wire _269_;
wire _270_;
wire _271_;
wire _272_;
wire _273_;
wire _274_;
wire _275_;
wire _276_;
wire _277_;
wire _278_;
wire _279_;
wire _280_;
wire _281_;
wire _282_;
wire _283_;
wire _284_;
wire _285_;
wire _286_;
wire _287_;
wire _288_;
wire _289_;
wire _290_;
wire _291_;
wire _292_;
wire _293_;
wire _294_;
wire _295_;
wire _296_;
wire _297_;
wire _298_;
wire _299_;
wire _300_;
wire _301_;
wire _302_;
wire _303_;
wire _304_;
wire _305_;
wire _306_;
wire _307_;
wire _308_;
wire _309_;
wire _310_;
wire _311_;
wire _312_;
wire _313_;
wire _314_;
wire _315_;
wire [2:0] _316_;
wire _317_;
wire _318_;
wire [31:0] _319_;
wire _320_;
wire _321_;
wire _322_;
wire [31:0] _323_;
wire _324_;
wire [2:0] _325_;
wire [2:0] _326_;
wire _327_;
wire [31:0] _328_;
wire [2:0] _329_;
wire _330_;
wire [31:0] _331_;
wire [2:0] _332_;
wire _333_;
wire _334_;
wire [31:0] _335_;
wire _336_;
wire [31:0] _337_;
wire [31:0] _338_;
wire [31:0] _339_;
wire [2:0] _340_;
wire [31:0] _341_;
wire [31:0] _342_;
wire [2:0] _343_;
wire _344_;
wire _345_;
wire [31:0] _346_;
wire _347_;
wire [31:0] _348_;
wire _349_;
wire [31:0] _350_;
wire [2:0] _351_;
wire _352_;
wire [31:0] _353_;
wire [2:0] _354_;
wire _355_;
wire [31:0] _356_;
wire _357_;
wire [2:0] _358_;
wire _359_;
wire [31:0] _360_;
wire _361_;
wire [31:0] _362_;
wire [2:0] _363_;
wire _364_;
wire [31:0] _365_;
wire _366_;
wire [31:0] _367_;
wire [31:0] _368_;
wire [2:0] _369_;
wire _370_;
wire [31:0] _371_;
wire _372_;
wire [31:0] _373_;
wire [31:0] _374_;
wire [31:0] _375_;
wire [2:0] _376_;
wire _377_;
wire [31:0] _378_;
wire _379_;
input [15:0] addr;
wire [15:0] addr;
input clk;
wire clk;
input cs;
wire cs;
wire [2:0] currstate;
input [31:0] data_in;
wire [31:0] data_in;
output [31:0] data_out;
wire [31:0] data_out;
wire [31:0] data_reg;
output data_valid;
wire data_valid;
input miso;
wire miso;
input mode_select;
wire mode_select;
wire mode_select_zw;
output mosi;
wire mosi;
wire [31:0] read_adress_counter;
input reset;
wire reset;
output sclk;
wire sclk;
wire [31:0] write_adress_counter;
assign _000_ = write_adress_counter[0] ? addr[1] : addr[0];
assign _001_ = write_adress_counter[0] ? addr[5] : addr[4];
assign _002_ = write_adress_counter[0] ? addr[9] : addr[8];
assign _003_ = write_adress_counter[0] ? addr[13] : addr[12];
assign _004_ = write_adress_counter[2] ? _088_ : _087_;
assign _005_ = write_adress_counter[0] ? addr[1] : addr[0];
assign _006_ = write_adress_counter[0] ? addr[5] : addr[4];
assign _007_ = write_adress_counter[0] ? addr[9] : addr[8];
assign _008_ = write_adress_counter[0] ? addr[13] : addr[12];
assign _009_ = write_adress_counter[2] ? _093_ : _092_;
assign _010_ = read_adress_counter[0] ? data_in[1] : data_in[0];
assign _011_ = read_adress_counter[0] ? data_in[5] : data_in[4];
assign _012_ = read_adress_counter[0] ? data_in[9] : data_in[8];
assign _013_ = read_adress_counter[0] ? data_in[13] : data_in[12];
assign _014_ = read_adress_counter[0] ? data_in[17] : data_in[16];
assign _015_ = read_adress_counter[0] ? data_in[21] : data_in[20];
assign _016_ = read_adress_counter[0] ? data_in[25] : data_in[24];
assign _017_ = read_adress_counter[0] ? data_in[29] : data_in[28];
assign _018_ = read_adress_counter[2] ? _293_ : _292_;
assign _019_ = read_adress_counter[2] ? _297_ : _296_;
assign _020_ = read_adress_counter[0] ? data_in[1] : data_in[0];
assign _021_ = read_adress_counter[0] ? data_in[5] : data_in[4];
assign _022_ = read_adress_counter[0] ? data_in[9] : data_in[8];
assign _023_ = read_adress_counter[0] ? data_in[13] : data_in[12];
assign _024_ = read_adress_counter[0] ? data_in[17] : data_in[16];
assign _025_ = read_adress_counter[0] ? data_in[21] : data_in[20];
assign _026_ = read_adress_counter[0] ? data_in[25] : data_in[24];
assign _027_ = read_adress_counter[0] ? data_in[29] : data_in[28];
assign _028_ = read_adress_counter[2] ? _305_ : _304_;
assign _029_ = read_adress_counter[2] ? _309_ : _308_;
assign _030_ = write_adress_counter[0] ? addr[3] : addr[2];
assign _031_ = write_adress_counter[0] ? addr[7] : addr[6];
assign _032_ = write_adress_counter[0] ? addr[11] : addr[10];
assign _033_ = write_adress_counter[0] ? addr[15] : addr[14];
assign _034_ = write_adress_counter[2] ? _090_ : _089_;
assign _035_ = write_adress_counter[0] ? addr[3] : addr[2];
assign _036_ = write_adress_counter[0] ? addr[7] : addr[6];
assign _037_ = write_adress_counter[0] ? addr[11] : addr[10];
assign _038_ = write_adress_counter[0] ? addr[15] : addr[14];
assign _039_ = write_adress_counter[2] ? _095_ : _094_;
assign _040_ = read_adress_counter[0] ? data_in[3] : data_in[2];
assign _041_ = read_adress_counter[0] ? data_in[7] : data_in[6];
assign _042_ = read_adress_counter[0] ? data_in[11] : data_in[10];
assign _043_ = read_adress_counter[0] ? data_in[15] : data_in[14];
assign _044_ = read_adress_counter[0] ? data_in[19] : data_in[18];
assign _045_ = read_adress_counter[0] ? data_in[23] : data_in[22];
assign _046_ = read_adress_counter[0] ? data_in[27] : data_in[26];
assign _047_ = read_adress_counter[0] ? data_in[31] : data_in[30];
assign _048_ = read_adress_counter[2] ? _295_ : _294_;
assign _049_ = read_adress_counter[2] ? _299_ : _298_;
assign _050_ = read_adress_counter[0] ? data_in[3] : data_in[2];
assign _051_ = read_adress_counter[0] ? data_in[7] : data_in[6];
assign _052_ = read_adress_counter[0] ? data_in[11] : data_in[10];
assign _053_ = read_adress_counter[0] ? data_in[15] : data_in[14];
assign _054_ = read_adress_counter[0] ? data_in[19] : data_in[18];
assign _055_ = read_adress_counter[0] ? data_in[23] : data_in[22];
assign _056_ = read_adress_counter[0] ? data_in[27] : data_in[26];
assign _057_ = read_adress_counter[0] ? data_in[31] : data_in[30];
assign _058_ = read_adress_counter[2] ? _307_ : _306_;
assign _059_ = read_adress_counter[2] ? _311_ : _310_;
assign _087_ = write_adress_counter[1] ? _030_ : _000_;
assign _088_ = write_adress_counter[1] ? _031_ : _001_;
assign _089_ = write_adress_counter[1] ? _032_ : _002_;
assign _090_ = write_adress_counter[1] ? _033_ : _003_;
assign _091_ = write_adress_counter[3] ? _034_ : _004_;
assign _092_ = write_adress_counter[1] ? _035_ : _005_;
assign _093_ = write_adress_counter[1] ? _036_ : _006_;
assign _094_ = write_adress_counter[1] ? _037_ : _007_;
assign _095_ = write_adress_counter[1] ? _038_ : _008_;
assign _096_ = write_adress_counter[3] ? _039_ : _009_;
assign _292_ = read_adress_counter[1] ? _040_ : _010_;
assign _293_ = read_adress_counter[1] ? _041_ : _011_;
assign _294_ = read_adress_counter[1] ? _042_ : _012_;
assign _295_ = read_adress_counter[1] ? _043_ : _013_;
assign _296_ = read_adress_counter[1] ? _044_ : _014_;
assign _297_ = read_adress_counter[1] ? _045_ : _015_;
assign _298_ = read_adress_counter[1] ? _046_ : _016_;
assign _299_ = read_adress_counter[1] ? _047_ : _017_;
assign _300_ = read_adress_counter[3] ? _048_ : _018_;
assign _302_ = read_adress_counter[3] ? _049_ : _019_;
assign _304_ = read_adress_counter[1] ? _050_ : _020_;
assign _305_ = read_adress_counter[1] ? _051_ : _021_;
assign _306_ = read_adress_counter[1] ? _052_ : _022_;
assign _307_ = read_adress_counter[1] ? _053_ : _023_;
assign _308_ = read_adress_counter[1] ? _054_ : _024_;
assign _309_ = read_adress_counter[1] ? _055_ : _025_;
assign _310_ = read_adress_counter[1] ? _056_ : _026_;
assign _311_ = read_adress_counter[1] ? _057_ : _027_;
assign _313_ = read_adress_counter[3] ? _058_ : _028_;
assign _314_ = read_adress_counter[3] ? _059_ : _029_;
assign _316_ = _301_ ? 3'h1 : currstate;
assign _317_ = currstate == 3'h1;
assign _318_ = write_adress_counter == 32'd16;
assign _319_ = write_adress_counter - 32'd1;
assign _320_ = $signed(write_adress_counter) > $signed(32'd0);
assign _321_ = $signed(write_adress_counter) <= $signed(32'd15);
assign _322_ = _321_ & _320_;
assign _323_ = write_adress_counter - 32'd1;
assign _324_ = ~ mode_select_zw;
assign _325_ = mode_select_zw ? 3'h2 : currstate;
assign _326_ = _324_ ? 3'h3 : _325_;
assign _327_ = _322_ ? _091_ : _096_;
assign _328_ = _322_ ? _323_ : write_adress_counter;
assign _329_ = _322_ ? currstate : _326_;
assign _330_ = _318_ ? mode_select_zw : _327_;
assign _331_ = _318_ ? _319_ : _328_;
assign _332_ = _318_ ? currstate : _329_;
assign _333_ = currstate == 3'h3;
assign _334_ = $signed(read_adress_counter) >= $signed(32'd32);
assign _335_ = read_adress_counter - 32'd1;
assign _336_ = $signed(read_adress_counter) > $signed(32'd0);
assign _337_ = read_adress_counter - 32'd1;
assign _338_ = _336_ ? { _193_, _192_, _191_, _190_, _189_, _188_, _187_, _186_, _185_, _184_, _183_, _182_, _181_, _180_, _179_, _178_, _177_, _176_, _175_, _174_, _173_, _172_, _171_, _170_, _169_, _168_, _167_, _166_, _165_, _164_, _163_, _162_ } : { _291_, _289_, _288_, _287_, _286_, _285_, _284_, _283_, _282_, _281_, _280_, _279_, _278_, _277_, _276_, _275_, _274_, _273_, _272_, _271_, _270_, _269_, _268_, _267_, _266_, _265_, _264_, _263_, _262_, _261_, _260_, _259_ };
assign _339_ = _336_ ? _337_ : read_adress_counter;
assign _340_ = _336_ ? currstate : 3'h4;
assign _341_ = _334_ ? data_reg : _338_;
assign _342_ = _334_ ? _335_ : _339_;
assign _343_ = _334_ ? currstate : _340_;
assign _344_ = currstate == 3'h2;
assign _345_ = $signed(read_adress_counter) >= $signed(32'd32);
assign _346_ = read_adress_counter - 32'd1;
assign _347_ = $signed(read_adress_counter) > $signed(32'd0);
assign _348_ = read_adress_counter - 32'd1;
assign _349_ = _347_ ? _303_ : _315_;
assign _350_ = _347_ ? _348_ : read_adress_counter;
assign _351_ = _347_ ? currstate : 3'h4;
assign _352_ = _345_ ? _080_ : _349_;
assign _353_ = _345_ ? _346_ : _350_;
assign _354_ = _345_ ? currstate : _351_;
assign _355_ = currstate == 3'h4;
assign _356_ = _355_ ? data_reg : _083_;
assign _357_ = _355_ ? 1'h1 : _086_;
assign _358_ = _355_ ? 3'h0 : currstate;
assign _359_ = _344_ ? _352_ : _080_;
assign _360_ = _344_ ? _083_ : _356_;
assign _361_ = _344_ ? _086_ : _357_;
assign _362_ = _344_ ? _353_ : read_adress_counter;
assign _363_ = _344_ ? _354_ : _358_;
assign _364_ = _333_ ? _080_ : _359_;
assign _365_ = _333_ ? _083_ : _360_;
assign _366_ = _333_ ? _086_ : _361_;
assign _367_ = _333_ ? _341_ : data_reg;
assign _368_ = _333_ ? _342_ : _362_;
assign _369_ = _333_ ? _343_ : _363_;
assign _370_ = _317_ ? _330_ : _364_;
assign _371_ = _317_ ? _083_ : _365_;
assign _372_ = _317_ ? _086_ : _366_;
assign _373_ = _317_ ? data_reg : _367_;
assign _374_ = _317_ ? _331_ : write_adress_counter;
assign _375_ = _317_ ? read_adress_counter : _368_;
assign _376_ = _317_ ? _332_ : _369_;
assign _377_ = _290_ ? 1'h0 : _370_;
assign _378_ = _290_ ? 32'd0 : _371_;
assign _379_ = _290_ ? 1'h0 : _372_;
assign _060_ = _290_ ? 32'd0 : _373_;
assign _061_ = _290_ ? 32'd16 : _374_;
assign _062_ = _290_ ? 32'd33 : _375_;
assign _063_ = _290_ ? _316_ : _376_;
assign _064_ = ~ reset;
assign _065_ = _064_ ? _060_ : data_reg;
always @(posedge clk)
_066_ <= _065_;
assign _067_ = ~ reset;
assign _068_ = _290_ & _067_;
assign _069_ = _068_ ? _312_ : mode_select_zw;
always @(posedge clk)
_070_ <= _069_;
assign _071_ = ~ reset;
assign _072_ = _071_ ? _061_ : write_adress_counter;
always @(posedge clk)
_073_ <= _072_;
assign _074_ = ~ reset;
assign _075_ = _074_ ? _062_ : read_adress_counter;
always @(posedge clk)
_076_ <= _075_;
always @(posedge clk, posedge reset)
if (reset) _077_ <= 3'h0;
else _077_ <= _063_;
assign _078_ = ~ reset;
assign _079_ = _078_ ? _377_ : _080_;
always @(posedge clk)
_080_ <= _079_;
assign _081_ = ~ reset;
assign _082_ = _081_ ? _378_ : _083_;
always @(posedge clk)
_083_ <= _082_;
assign _084_ = ~ reset;
assign _085_ = _084_ ? _379_ : _086_;
always @(posedge clk)
_086_ <= _085_;
assign _097_ = ~ read_adress_counter[4];
assign _098_ = ~ read_adress_counter[3];
assign _099_ = _097_ & _098_;
assign _100_ = _097_ & read_adress_counter[3];
assign _101_ = read_adress_counter[4] & _098_;
assign _102_ = read_adress_counter[4] & read_adress_counter[3];
assign _103_ = ~ read_adress_counter[2];
assign _104_ = _099_ & _103_;
assign _105_ = _099_ & read_adress_counter[2];
assign _106_ = _100_ & _103_;
assign _107_ = _100_ & read_adress_counter[2];
assign _108_ = _101_ & _103_;
assign _109_ = _101_ & read_adress_counter[2];
assign _110_ = _102_ & _103_;
assign _111_ = _102_ & read_adress_counter[2];
assign _112_ = ~ read_adress_counter[1];
assign _113_ = _104_ & _112_;
assign _114_ = _104_ & read_adress_counter[1];
assign _115_ = _105_ & _112_;
assign _116_ = _105_ & read_adress_counter[1];
assign _117_ = _106_ & _112_;
assign _118_ = _106_ & read_adress_counter[1];
assign _119_ = _107_ & _112_;
assign _120_ = _107_ & read_adress_counter[1];
assign _121_ = _108_ & _112_;
assign _122_ = _108_ & read_adress_counter[1];
assign _123_ = _109_ & _112_;
assign _124_ = _109_ & read_adress_counter[1];
assign _125_ = _110_ & _112_;
assign _126_ = _110_ & read_adress_counter[1];
assign _127_ = _111_ & _112_;
assign _128_ = _111_ & read_adress_counter[1];
assign _129_ = ~ read_adress_counter[0];
assign _130_ = _113_ & _129_;
assign _131_ = _113_ & read_adress_counter[0];
assign _132_ = _114_ & _129_;
assign _133_ = _114_ & read_adress_counter[0];
assign _134_ = _115_ & _129_;
assign _135_ = _115_ & read_adress_counter[0];
assign _136_ = _116_ & _129_;
assign _137_ = _116_ & read_adress_counter[0];
assign _138_ = _117_ & _129_;
assign _139_ = _117_ & read_adress_counter[0];
assign _140_ = _118_ & _129_;
assign _141_ = _118_ & read_adress_counter[0];
assign _142_ = _119_ & _129_;
assign _143_ = _119_ & read_adress_counter[0];
assign _144_ = _120_ & _129_;
assign _145_ = _120_ & read_adress_counter[0];
assign _146_ = _121_ & _129_;
assign _147_ = _121_ & read_adress_counter[0];
assign _148_ = _122_ & _129_;
assign _149_ = _122_ & read_adress_counter[0];
assign _150_ = _123_ & _129_;
assign _151_ = _123_ & read_adress_counter[0];
assign _152_ = _124_ & _129_;
assign _153_ = _124_ & read_adress_counter[0];
assign _154_ = _125_ & _129_;
assign _155_ = _125_ & read_adress_counter[0];
assign _156_ = _126_ & _129_;
assign _157_ = _126_ & read_adress_counter[0];
assign _158_ = _127_ & _129_;
assign _159_ = _127_ & read_adress_counter[0];
assign _160_ = _128_ & _129_;
assign _161_ = _128_ & read_adress_counter[0];
assign _162_ = _130_ ? miso : data_reg[0];
assign _163_ = _131_ ? miso : data_reg[1];
assign _164_ = _132_ ? miso : data_reg[2];
assign _165_ = _133_ ? miso : data_reg[3];
assign _166_ = _134_ ? miso : data_reg[4];
assign _167_ = _135_ ? miso : data_reg[5];
assign _168_ = _136_ ? miso : data_reg[6];
assign _169_ = _137_ ? miso : data_reg[7];
assign _170_ = _138_ ? miso : data_reg[8];
assign _171_ = _139_ ? miso : data_reg[9];
assign _172_ = _140_ ? miso : data_reg[10];
assign _173_ = _141_ ? miso : data_reg[11];
assign _174_ = _142_ ? miso : data_reg[12];
assign _175_ = _143_ ? miso : data_reg[13];
assign _176_ = _144_ ? miso : data_reg[14];
assign _177_ = _145_ ? miso : data_reg[15];
assign _178_ = _146_ ? miso : data_reg[16];
assign _179_ = _147_ ? miso : data_reg[17];
assign _180_ = _148_ ? miso : data_reg[18];
assign _181_ = _149_ ? miso : data_reg[19];
assign _182_ = _150_ ? miso : data_reg[20];
assign _183_ = _151_ ? miso : data_reg[21];
assign _184_ = _152_ ? miso : data_reg[22];
assign _185_ = _153_ ? miso : data_reg[23];
assign _186_ = _154_ ? miso : data_reg[24];
assign _187_ = _155_ ? miso : data_reg[25];
assign _188_ = _156_ ? miso : data_reg[26];
assign _189_ = _157_ ? miso : data_reg[27];
assign _190_ = _158_ ? miso : data_reg[28];
assign _191_ = _159_ ? miso : data_reg[29];
assign _192_ = _160_ ? miso : data_reg[30];
assign _193_ = _161_ ? miso : data_reg[31];
assign _194_ = ~ read_adress_counter[4];
assign _195_ = ~ read_adress_counter[3];
assign _196_ = _194_ & _195_;
assign _197_ = _194_ & read_adress_counter[3];
assign _198_ = read_adress_counter[4] & _195_;
assign _199_ = read_adress_counter[4] & read_adress_counter[3];
assign _200_ = ~ read_adress_counter[2];
assign _201_ = _196_ & _200_;
assign _202_ = _196_ & read_adress_counter[2];
assign _203_ = _197_ & _200_;
assign _204_ = _197_ & read_adress_counter[2];
assign _205_ = _198_ & _200_;
assign _206_ = _198_ & read_adress_counter[2];
assign _207_ = _199_ & _200_;
assign _208_ = _199_ & read_adress_counter[2];
assign _209_ = ~ read_adress_counter[1];
assign _210_ = _201_ & _209_;
assign _211_ = _201_ & read_adress_counter[1];
assign _212_ = _202_ & _209_;
assign _213_ = _202_ & read_adress_counter[1];
assign _214_ = _203_ & _209_;
assign _215_ = _203_ & read_adress_counter[1];
assign _216_ = _204_ & _209_;
assign _217_ = _204_ & read_adress_counter[1];
assign _218_ = _205_ & _209_;
assign _219_ = _205_ & read_adress_counter[1];
assign _220_ = _206_ & _209_;
assign _221_ = _206_ & read_adress_counter[1];
assign _222_ = _207_ & _209_;
assign _223_ = _207_ & read_adress_counter[1];
assign _224_ = _208_ & _209_;
assign _225_ = _208_ & read_adress_counter[1];
assign _226_ = ~ read_adress_counter[0];
assign _227_ = _210_ & _226_;
assign _228_ = _210_ & read_adress_counter[0];
assign _229_ = _211_ & _226_;
assign _230_ = _211_ & read_adress_counter[0];
assign _231_ = _212_ & _226_;
assign _232_ = _212_ & read_adress_counter[0];
assign _233_ = _213_ & _226_;
assign _234_ = _213_ & read_adress_counter[0];
assign _235_ = _214_ & _226_;
assign _236_ = _214_ & read_adress_counter[0];
assign _237_ = _215_ & _226_;
assign _238_ = _215_ & read_adress_counter[0];
assign _239_ = _216_ & _226_;
assign _240_ = _216_ & read_adress_counter[0];
assign _241_ = _217_ & _226_;
assign _242_ = _217_ & read_adress_counter[0];
assign _243_ = _218_ & _226_;
assign _244_ = _218_ & read_adress_counter[0];
assign _245_ = _219_ & _226_;
assign _246_ = _219_ & read_adress_counter[0];
assign _247_ = _220_ & _226_;
assign _248_ = _220_ & read_adress_counter[0];
assign _249_ = _221_ & _226_;
assign _250_ = _221_ & read_adress_counter[0];
assign _251_ = _222_ & _226_;
assign _252_ = _222_ & read_adress_counter[0];
assign _253_ = _223_ & _226_;
assign _254_ = _223_ & read_adress_counter[0];
assign _255_ = _224_ & _226_;
assign _256_ = _224_ & read_adress_counter[0];
assign _257_ = _225_ & _226_;
assign _258_ = _225_ & read_adress_counter[0];
assign _259_ = _227_ ? miso : data_reg[0];
assign _260_ = _228_ ? miso : data_reg[1];
assign _261_ = _229_ ? miso : data_reg[2];
assign _262_ = _230_ ? miso : data_reg[3];
assign _263_ = _231_ ? miso : data_reg[4];
assign _264_ = _232_ ? miso : data_reg[5];
assign _265_ = _233_ ? miso : data_reg[6];
assign _266_ = _234_ ? miso : data_reg[7];
assign _267_ = _235_ ? miso : data_reg[8];
assign _268_ = _236_ ? miso : data_reg[9];
assign _269_ = _237_ ? miso : data_reg[10];
assign _270_ = _238_ ? miso : data_reg[11];
assign _271_ = _239_ ? miso : data_reg[12];
assign _272_ = _240_ ? miso : data_reg[13];
assign _273_ = _241_ ? miso : data_reg[14];
assign _274_ = _242_ ? miso : data_reg[15];
assign _275_ = _243_ ? miso : data_reg[16];
assign _276_ = _244_ ? miso : data_reg[17];
assign _277_ = _245_ ? miso : data_reg[18];
assign _278_ = _246_ ? miso : data_reg[19];
assign _279_ = _247_ ? miso : data_reg[20];
assign _280_ = _248_ ? miso : data_reg[21];
assign _281_ = _249_ ? miso : data_reg[22];
assign _282_ = _250_ ? miso : data_reg[23];
assign _283_ = _251_ ? miso : data_reg[24];
assign _284_ = _252_ ? miso : data_reg[25];
assign _285_ = _253_ ? miso : data_reg[26];
assign _286_ = _254_ ? miso : data_reg[27];
assign _287_ = _255_ ? miso : data_reg[28];
assign _288_ = _256_ ? miso : data_reg[29];
assign _289_ = _257_ ? miso : data_reg[30];
assign _291_ = _258_ ? miso : data_reg[31];
assign _303_ = read_adress_counter[4] ? _302_ : _300_;
assign _315_ = read_adress_counter[4] ? _314_ : _313_;
assign _290_ = currstate == 3'h0;
assign _301_ = ~ cs;
assign _312_ = _301_ ? mode_select : 1'h0;
assign data_reg = _066_;
assign mode_select_zw = _070_;
assign write_adress_counter = _073_;
assign read_adress_counter = _076_;
assign currstate = _077_;
assign sclk = clk;
assign mosi = _080_;
assign data_out = _083_;
assign data_valid = _086_;
endmodule
|
tt06-finale_0007
|
tt06-finale
|
CEJMU-tt06_tinyrv1
|
task_tt_um_cejmu_riscv
|
tt_um_cejmu_riscv
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/* Generated by Yosys 0.39+165 (git sha1 22c5ab90d, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */
module alu(clk, reset, a, b, instruction, rd);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire [31:0] _15_;
wire _16_;
wire _17_;
wire _18_;
wire _19_;
wire _20_;
wire [31:0] _21_;
wire _22_;
wire _23_;
wire _24_;
wire _25_;
wire _26_;
wire [31:0] _27_;
wire _28_;
wire _29_;
wire _30_;
wire _31_;
wire _32_;
wire _33_;
wire [1:0] _34_;
wire [31:0] _35_;
wire [31:0] _36_;
wire [31:0] _37_;
wire [31:0] _38_;
wire [31:0] _39_;
wire [31:0] _40_;
wire [31:0] _41_;
reg [31:0] _42_;
input [31:0] a;
wire [31:0] a;
input [31:0] b;
wire [31:0] b;
input clk;
wire clk;
input [16:0] instruction;
wire [16:0] instruction;
output [31:0] rd;
wire [31:0] rd;
input reset;
wire reset;
assign _00_ = instruction[16:10] == 7'h00;
assign _01_ = instruction[9:7] == 3'h0;
assign _02_ = _01_ & _00_;
assign _03_ = instruction[6:0] == 7'h33;
assign _04_ = _03_ & _02_;
assign _05_ = instruction[9:7] == 3'h0;
assign _06_ = instruction[6:0] == 7'h13;
assign _07_ = _06_ & _05_;
assign _08_ = _04_ | _07_;
assign _09_ = instruction[6:0] == 7'h23;
assign _10_ = instruction[6:0] == 7'h03;
assign _11_ = _09_ | _10_;
assign _12_ = instruction[9:7] == 3'h2;
assign _13_ = _12_ & _11_;
assign _14_ = _08_ | _13_;
assign _15_ = a + b;
assign _16_ = instruction[16:10] == 7'h00;
assign _17_ = instruction[9:7] == 3'h7;
assign _18_ = _17_ & _16_;
assign _19_ = instruction[6:0] == 7'h33;
assign _20_ = _19_ & _18_;
assign _21_ = a & b;
assign _22_ = instruction[16:10] == 7'h00;
assign _23_ = instruction[9:7] == 3'h4;
assign _24_ = _23_ & _22_;
assign _25_ = instruction[6:0] == 7'h33;
assign _26_ = _25_ & _24_;
assign _27_ = a ^ b;
assign _28_ = instruction[6:0] == 7'h6f;
assign _29_ = instruction[6:0] == 7'h67;
assign _30_ = instruction[6:0] == 7'h63;
assign _31_ = instruction[9:7] == 3'h1;
assign _32_ = _31_ & _30_;
assign _33_ = a == b;
assign _34_ = _33_ ? 2'h2 : 2'h0;
assign _35_ = _32_ ? { 14'h0000, _34_, 16'h0000 } : 32'd0;
assign _36_ = _29_ ? 32'd65536 : _35_;
assign _37_ = _28_ ? 32'd0 : _36_;
assign _38_ = _26_ ? _27_ : _37_;
assign _39_ = _20_ ? _21_ : _38_;
assign _40_ = _14_ ? _15_ : _39_;
assign _41_ = reset ? 32'd0 : _40_;
always @(posedge clk)
_42_ <= _41_;
assign rd = _42_;
endmodule
module control(clk, reset, iword, data_valid, imm, control_flags_out, wbflag, memflag, pcflag, fetchflag, mem_req);
wire _000_;
wire _001_;
wire _002_;
wire [2:0] _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire [2:0] _012_;
wire _013_;
wire [2:0] _014_;
wire [2:0] _015_;
wire [2:0] _016_;
wire [2:0] _017_;
wire [2:0] _018_;
wire [2:0] _019_;
wire [2:0] _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire [31:0] _066_;
wire _067_;
wire [31:0] _068_;
wire _069_;
wire [31:0] _070_;
wire _071_;
wire [31:0] _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
reg [2:0] _109_;
input clk;
wire clk;
wire [6:0] control_flags;
output [6:0] control_flags_out;
wire [6:0] control_flags_out;
wire [2:0] currstate;
input data_valid;
wire data_valid;
output fetchflag;
wire fetchflag;
output [31:0] imm;
wire [31:0] imm;
input [31:0] iword;
wire [31:0] iword;
output mem_req;
wire mem_req;
output memflag;
wire memflag;
output pcflag;
wire pcflag;
input reset;
wire reset;
wire [20:0] w31_to_w11;
output wbflag;
wire wbflag;
assign _000_ = currstate == 3'h0;
assign _001_ = currstate == 3'h5;
assign _002_ = currstate == 3'h1;
assign _003_ = data_valid ? 3'h6 : currstate;
assign _004_ = currstate == 3'h6;
assign _005_ = currstate == 3'h2;
assign _006_ = currstate == 3'h3;
assign _007_ = control_flags[0] & _006_;
assign _008_ = currstate == 3'h3;
assign _009_ = ~ control_flags[0];
assign _010_ = _009_ & _008_;
assign _011_ = currstate == 3'h4;
assign _012_ = _013_ ? 3'h5 : currstate;
assign _013_ = data_valid & _011_;
assign _014_ = _010_ ? 3'h5 : _012_;
assign _015_ = _007_ ? 3'h4 : _014_;
assign _016_ = _005_ ? 3'h3 : _015_;
assign _017_ = _004_ ? 3'h2 : _016_;
assign _018_ = _002_ ? _003_ : _017_;
assign _019_ = _001_ ? 3'h1 : _018_;
assign _020_ = _000_ ? 3'h1 : _019_;
assign _021_ = currstate == 3'h1;
assign _022_ = currstate == 3'h4;
assign _023_ = _021_ | _022_;
assign _024_ = ~ data_valid;
assign _025_ = _024_ & _023_;
assign _026_ = _025_ ? 1'h0 : 1'h1;
assign _027_ = currstate == 3'h3;
assign _028_ = ~ control_flags[0];
assign _029_ = _028_ & _027_;
assign _030_ = currstate == 3'h4;
assign _031_ = data_valid & _030_;
assign _032_ = _029_ | _031_;
assign _033_ = _032_ ? 1'h1 : 1'h0;
assign _034_ = currstate == 3'h3;
assign _035_ = control_flags[0] & _034_;
assign _036_ = control_flags[1] & _035_;
assign _037_ = currstate == 3'h4;
assign _038_ = control_flags[1] & _037_;
assign _039_ = _036_ | _038_;
assign _040_ = _039_ ? 1'h1 : 1'h0;
assign _041_ = currstate == 3'h4;
assign _042_ = control_flags[2] & _041_;
assign _043_ = data_valid & _042_;
assign _044_ = currstate == 3'h3;
assign _045_ = control_flags[2] & _044_;
assign _046_ = ~ control_flags[0];
assign _047_ = _046_ & _045_;
assign _048_ = _043_ | _047_;
assign _049_ = _048_ ? 1'h1 : 1'h0;
assign _050_ = currstate == 3'h1;
assign _051_ = data_valid & _050_;
assign _052_ = _051_ ? 1'h1 : 1'h0;
assign _053_ = currstate == 3'h1;
assign _054_ = currstate == 3'h0;
assign _055_ = _053_ | _054_;
assign _056_ = currstate == 3'h5;
assign _057_ = _055_ | _056_;
assign _058_ = _057_ ? 1'h1 : 1'h0;
assign _059_ = iword[6:0] == 7'h67;
assign _060_ = _059_ ? 1'h1 : 1'h0;
assign _061_ = iword[6:0] == 7'h03;
assign _062_ = iword[6:0] == 7'h13;
assign _063_ = _061_ | _062_;
assign _064_ = iword[6:0] == 7'h67;
assign _065_ = _063_ | _064_;
assign _066_ = _065_ ? { w31_to_w11, iword[30:20] } : _068_;
assign _067_ = iword[6:0] == 7'h23;
assign _068_ = _067_ ? { w31_to_w11, iword[30:25], iword[11:7] } : _070_;
assign _069_ = iword[6:0] == 7'h63;
assign _070_ = _069_ ? { w31_to_w11[20:1], iword[7], iword[30:25], iword[11:8], 1'h0 } : _072_;
assign _071_ = iword[6:0] == 7'h6f;
assign _072_ = _071_ ? { w31_to_w11[11:0], iword[19:12], iword[20], iword[30:21], 1'h0 } : 32'd0;
assign _073_ = iword[6:0] == 7'h03;
assign _074_ = iword[6:0] == 7'h23;
assign _075_ = _073_ | _074_;
assign _076_ = iword[14:12] == 3'h2;
assign _077_ = _076_ & _075_;
assign _078_ = _077_ ? 1'h1 : 1'h0;
assign _079_ = iword[6:0] == 7'h23;
assign _080_ = iword[14:12] == 3'h2;
assign _081_ = _080_ & _079_;
assign _082_ = _081_ ? 1'h1 : 1'h0;
assign _083_ = iword[6:0] == 7'h63;
assign _084_ = _083_ ? 1'h0 : 1'h1;
assign _085_ = iword[6:0] == 7'h13;
assign _086_ = iword[6:0] == 7'h37;
assign _087_ = _085_ | _086_;
assign _088_ = iword[6:0] == 7'h17;
assign _089_ = _087_ | _088_;
assign _090_ = iword[6:0] == 7'h03;
assign _091_ = iword[6:0] == 7'h23;
assign _092_ = _090_ | _091_;
assign _093_ = iword[14:12] == 3'h2;
assign _094_ = _093_ & _092_;
assign _095_ = _089_ | _094_;
assign _096_ = iword[6:0] == 7'h6f;
assign _097_ = _095_ | _096_;
assign _098_ = iword[6:0] == 7'h67;
assign _099_ = _097_ | _098_;
assign _100_ = _099_ ? 1'h1 : 1'h0;
assign _101_ = iword[6:0] == 7'h63;
assign _102_ = iword[6:0] == 7'h6f;
assign _103_ = _101_ | _102_;
assign _104_ = iword[6:0] == 7'h67;
assign _105_ = _103_ | _104_;
assign _106_ = iword[6:0] == 7'h67;
assign _107_ = _105_ | _106_;
assign _108_ = _107_ ? 1'h1 : 1'h0;
always @(posedge clk, posedge reset)
if (reset) _109_ <= 3'h0;
else _109_ <= _020_;
assign currstate = _109_;
assign control_flags = { _060_, _058_, _108_, _100_, _084_, _082_, _078_ };
assign w31_to_w11 = { iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31], iword[31] };
assign imm = _066_;
assign control_flags_out = control_flags;
assign wbflag = _049_;
assign memflag = _040_;
assign pcflag = _033_;
assign fetchflag = _052_;
assign mem_req = _026_;
endmodule
module cpu(clk, reset, data_in, data_valid, data_out, addr_out, write_en, mem_req, x1);
wire [31:0] _00_;
wire [31:0] _01_;
wire [12:0] _02_;
wire [31:0] _03_;
wire [31:0] _04_;
wire [6:0] _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire [31:0] _11_;
wire [31:0] _12_;
wire [31:0] _13_;
wire _14_;
wire _15_;
wire [15:0] _16_;
wire [15:0] _17_;
wire [15:0] _18_;
wire [13:0] _19_;
wire [31:0] _20_;
reg [31:0] _21_;
output [13:0] addr_out;
wire [13:0] addr_out;
wire [31:0] b;
input clk;
wire clk;
wire [6:0] control_flags_out;
input [31:0] data_in;
wire [31:0] data_in;
output [31:0] data_out;
wire [31:0] data_out;
input data_valid;
wire data_valid;
wire fetchflag;
wire [31:0] imm;
wire [16:0] instruction;
wire [31:0] iword_reg;
output mem_req;
wire mem_req;
wire memflag;
wire [15:0] pc_inc;
wire [15:0] pc_offset;
wire [15:0] pc_out;
wire pcflag;
wire [31:0] rd;
wire [31:0] rdalu;
input reset;
wire reset;
wire [31:0] rs1;
wire [31:0] rs2;
wire s0;
wire s1;
wire wbflag;
output write_en;
wire write_en;
output [12:0] x1;
wire [12:0] x1;
assign _11_ = control_flags_out[3] ? imm : rs2;
assign _12_ = control_flags_out[4] ? { 16'h0000, pc_inc } : _13_;
assign _13_ = control_flags_out[0] ? data_in : rdalu;
assign _14_ = control_flags_out[4] ? rdalu[16] : 1'h0;
assign _15_ = control_flags_out[4] ? rdalu[17] : 1'h1;
assign _18_ = control_flags_out[6] ? rs1[15:0] : imm[15:0];
assign _19_ = control_flags_out[5] ? pc_out[15:2] : rdalu[13:0];
assign _20_ = fetchflag ? data_in : iword_reg;
always @(posedge clk, posedge reset)
if (reset) _21_ <= 32'd0;
else _21_ <= _20_;
alu alu_inst (
.a(rs1),
.b(b),
.clk(clk),
.instruction(instruction),
.rd(_03_),
.reset(reset)
);
control control_inst (
.clk(clk),
.control_flags_out(_05_),
.data_valid(data_valid),
.fetchflag(_09_),
.imm(_04_),
.iword(iword_reg),
.mem_req(_10_),
.memflag(_07_),
.pcflag(_08_),
.reset(reset),
.wbflag(_06_)
);
instructioncounter instruction_inst (
.clk(clk),
.pc_inc(_16_),
.pc_new(_17_),
.pc_offset(pc_offset),
.pcflag(pcflag),
.reset(reset),
.s0(s0),
.s1(s1)
);
regs regs_inst (
.clk(clk),
.rd(rd),
.rdadr(iword_reg[11:7]),
.regwrite(wbflag),
.reset(reset),
.rs1(_00_),
.rs1adr(iword_reg[19:15]),
.rs2(_01_),
.rs2adr(iword_reg[24:20]),
.x1(_02_)
);
assign s0 = _14_;
assign s1 = _15_;
assign imm = _04_;
assign control_flags_out = _05_;
assign rs1 = _00_;
assign rs2 = _01_;
assign b = _11_;
assign rdalu = _03_;
assign rd = _12_;
assign wbflag = _06_;
assign memflag = _07_;
assign pcflag = _08_;
assign fetchflag = _09_;
assign instruction = { iword_reg[31:25], iword_reg[14:12], iword_reg[6:0] };
assign iword_reg = _21_;
assign pc_inc = _16_;
assign pc_out = _17_;
assign pc_offset = _18_;
assign data_out = rs2;
assign addr_out = _19_;
assign write_en = memflag;
assign mem_req = _10_;
assign x1 = _02_;
endmodule
module instructioncounter(clk, reset, pcflag, s0, s1, pc_offset, pc_inc, pc_new);
wire [15:0] _00_;
wire [15:0] _01_;
wire _02_;
wire [15:0] _03_;
wire _04_;
wire _05_;
wire [15:0] _06_;
wire [15:0] _07_;
wire [15:0] _08_;
reg [15:0] _09_ = 16'h0000;
reg [15:0] _10_;
input clk;
wire clk;
output [15:0] pc_inc;
wire [15:0] pc_inc;
output [15:0] pc_new;
wire [15:0] pc_new;
input [15:0] pc_offset;
wire [15:0] pc_offset;
input pcflag;
wire pcflag;
wire [15:0] \reg ;
input reset;
wire reset;
input s0;
wire s0;
input s1;
wire s1;
wire [1:0] s1s0;
assign _00_ = \reg + 16'h0004;
assign _01_ = pc_offset + \reg ;
assign _02_ = s1s0 == 2'h0;
assign _03_ = \reg + 16'h0004;
assign _04_ = s1s0 == 2'h2;
assign _05_ = s1s0 == 2'h1;
function [15:0] \1383 ;
input [15:0] a;
input [47:0] b;
input [2:0] s;
(* parallel_case *)
casez (s)
3'b??1:
\1383 = b[15:0];
3'b?1?:
\1383 = b[31:16];
3'b1??:
\1383 = b[47:32];
default:
\1383 = a;
endcase
endfunction
assign _06_ = \1383 (16'h0000, { pc_offset, _03_, _01_ }, { _05_, _04_, _02_ });
assign _07_ = pcflag ? _06_ : \reg ;
assign _08_ = reset ? 16'h0000 : _07_;
always @(posedge clk)
_09_ <= _08_;
always @(posedge clk)
_10_ <= _00_;
assign s1s0 = { s1, s0 };
assign \reg = _09_;
assign pc_inc = _10_;
assign pc_new = \reg ;
endmodule
module regs(clk, reset, rs1adr, rs2adr, rdadr, rd, regwrite, rs1, rs2, x1);
wire [31:0] _000_;
wire [31:0] _001_;
wire [31:0] _002_;
wire [31:0] _003_;
wire [31:0] _004_;
wire [31:0] _005_;
wire [31:0] _006_;
wire [31:0] _007_;
wire [31:0] _008_;
wire [31:0] _009_;
wire [31:0] _010_;
wire [31:0] _011_;
wire [31:0] _012_;
wire [31:0] _013_;
wire [31:0] _014_;
wire [31:0] _015_;
wire [31:0] _016_;
wire [31:0] _017_;
wire [31:0] _018_;
wire [31:0] _019_;
wire [31:0] _020_;
wire [31:0] _021_;
wire [31:0] _022_;
wire [31:0] _023_;
wire [31:0] _024_;
wire [31:0] _025_;
wire [31:0] _026_;
wire [31:0] _027_;
wire [31:0] _028_;
wire [31:0] _029_;
wire [31:0] _030_;
wire [31:0] _031_;
wire [31:0] _032_;
wire [31:0] _033_;
wire [31:0] _034_;
wire [31:0] _035_;
wire [31:0] _036_;
wire [31:0] _037_;
wire [31:0] _038_;
wire [31:0] _039_;
wire _040_;
wire _041_;
wire [4:0] _042_;
wire [4:0] _043_;
wire [4:0] _044_;
wire [1023:0] _045_;
reg [1023:0] _046_;
reg [31:0] _047_;
reg [31:0] _048_;
wire _049_;
wire [12:0] _050_;
reg [12:0] _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire [31:0] _117_;
wire [31:0] _118_;
wire [31:0] _119_;
wire [31:0] _120_;
wire [31:0] _121_;
wire [31:0] _122_;
wire [31:0] _123_;
wire [31:0] _124_;
wire [31:0] _125_;
wire [31:0] _126_;
wire [31:0] _127_;
wire [31:0] _128_;
wire [31:0] _129_;
wire [31:0] _130_;
wire [31:0] _131_;
wire [31:0] _132_;
wire [31:0] _133_;
wire [31:0] _134_;
wire [31:0] _135_;
wire [31:0] _136_;
wire [31:0] _137_;
wire [31:0] _138_;
wire [31:0] _139_;
wire [31:0] _140_;
wire [31:0] _141_;
wire [31:0] _142_;
wire [31:0] _143_;
wire [31:0] _144_;
wire [31:0] _145_;
wire [31:0] _146_;
wire [31:0] _147_;
wire [31:0] _148_;
wire [31:0] _149_;
wire [31:0] _150_;
wire [31:0] _151_;
wire [31:0] _152_;
wire [31:0] _153_;
wire [31:0] _154_;
wire [31:0] _155_;
wire [31:0] _156_;
wire [31:0] _157_;
wire [31:0] _158_;
wire [31:0] _159_;
wire [31:0] _160_;
wire [31:0] _161_;
wire [31:0] _162_;
wire [31:0] _163_;
wire [31:0] _164_;
wire [31:0] _165_;
wire [31:0] _166_;
wire [31:0] _167_;
wire [31:0] _168_;
wire [31:0] _169_;
wire [31:0] _170_;
input clk;
wire clk;
input [31:0] rd;
wire [31:0] rd;
input [4:0] rdadr;
wire [4:0] rdadr;
wire [1023:0] registers;
input regwrite;
wire regwrite;
input reset;
wire reset;
output [31:0] rs1;
wire [31:0] rs1;
input [4:0] rs1adr;
wire [4:0] rs1adr;
output [31:0] rs2;
wire [31:0] rs2;
input [4:0] rs2adr;
wire [4:0] rs2adr;
output [12:0] x1;
wire [12:0] x1;
assign _000_ = _043_[0] ? registers[63:32] : registers[31:0];
assign _001_ = _043_[0] ? registers[191:160] : registers[159:128];
assign _002_ = _043_[0] ? registers[319:288] : registers[287:256];
assign _003_ = _043_[0] ? registers[447:416] : registers[415:384];
assign _004_ = _043_[0] ? registers[575:544] : registers[543:512];
assign _005_ = _043_[0] ? registers[703:672] : registers[671:640];
assign _006_ = _043_[0] ? registers[831:800] : registers[799:768];
assign _007_ = _043_[0] ? registers[959:928] : registers[927:896];
assign _008_ = _043_[2] ? _150_ : _149_;
assign _009_ = _043_[2] ? _154_ : _153_;
assign _010_ = _044_[0] ? registers[63:32] : registers[31:0];
assign _011_ = _044_[0] ? registers[191:160] : registers[159:128];
assign _012_ = _044_[0] ? registers[319:288] : registers[287:256];
assign _013_ = _044_[0] ? registers[447:416] : registers[415:384];
assign _014_ = _044_[0] ? registers[575:544] : registers[543:512];
assign _015_ = _044_[0] ? registers[703:672] : registers[671:640];
assign _016_ = _044_[0] ? registers[831:800] : registers[799:768];
assign _017_ = _044_[0] ? registers[959:928] : registers[927:896];
assign _018_ = _044_[2] ? _161_ : _160_;
assign _019_ = _044_[2] ? _165_ : _164_;
assign _020_ = _043_[0] ? registers[127:96] : registers[95:64];
assign _021_ = _043_[0] ? registers[255:224] : registers[223:192];
assign _022_ = _043_[0] ? registers[383:352] : registers[351:320];
assign _023_ = _043_[0] ? registers[511:480] : registers[479:448];
assign _024_ = _043_[0] ? registers[639:608] : registers[607:576];
assign _025_ = _043_[0] ? registers[767:736] : registers[735:704];
assign _026_ = _043_[0] ? registers[895:864] : registers[863:832];
assign _027_ = _043_[0] ? registers[1023:992] : registers[991:960];
assign _028_ = _043_[2] ? _152_ : _151_;
assign _029_ = _043_[2] ? _156_ : _155_;
assign _030_ = _044_[0] ? registers[127:96] : registers[95:64];
assign _031_ = _044_[0] ? registers[255:224] : registers[223:192];
assign _032_ = _044_[0] ? registers[383:352] : registers[351:320];
assign _033_ = _044_[0] ? registers[511:480] : registers[479:448];
assign _034_ = _044_[0] ? registers[639:608] : registers[607:576];
assign _035_ = _044_[0] ? registers[767:736] : registers[735:704];
assign _036_ = _044_[0] ? registers[895:864] : registers[863:832];
assign _037_ = _044_[0] ? registers[1023:992] : registers[991:960];
assign _038_ = _044_[2] ? _163_ : _162_;
assign _039_ = _044_[2] ? _167_ : _166_;
assign _149_ = _043_[1] ? _020_ : _000_;
assign _150_ = _043_[1] ? _021_ : _001_;
assign _151_ = _043_[1] ? _022_ : _002_;
assign _152_ = _043_[1] ? _023_ : _003_;
assign _153_ = _043_[1] ? _024_ : _004_;
assign _154_ = _043_[1] ? _025_ : _005_;
assign _155_ = _043_[1] ? _026_ : _006_;
assign _156_ = _043_[1] ? _027_ : _007_;
assign _157_ = _043_[3] ? _028_ : _008_;
assign _158_ = _043_[3] ? _029_ : _009_;
assign _160_ = _044_[1] ? _030_ : _010_;
assign _161_ = _044_[1] ? _031_ : _011_;
assign _162_ = _044_[1] ? _032_ : _012_;
assign _163_ = _044_[1] ? _033_ : _013_;
assign _164_ = _044_[1] ? _034_ : _014_;
assign _165_ = _044_[1] ? _035_ : _015_;
assign _166_ = _044_[1] ? _036_ : _016_;
assign _167_ = _044_[1] ? _037_ : _017_;
assign _168_ = _044_[3] ? _038_ : _018_;
assign _169_ = _044_[3] ? _039_ : _019_;
assign _170_ = _044_[4] ? _169_ : _168_;
assign _040_ = rdadr != 5'h00;
assign _041_ = _040_ & regwrite;
assign _042_ = 5'h1f - rdadr;
assign _043_ = 5'h1f - rs1adr;
assign _044_ = 5'h1f - rs2adr;
assign _045_ = _041_ ? { _148_, _147_, _146_, _145_, _144_, _143_, _142_, _141_, _140_, _139_, _138_, _137_, _136_, _135_, _134_, _133_, _132_, _131_, _130_, _129_, _128_, _127_, _126_, _125_, _124_, _123_, _122_, _121_, _120_, _119_, _118_, _117_ } : registers;
always @(posedge clk, posedge reset)
if (reset) _046_ <= 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
else _046_ <= _045_;
always @(posedge clk, posedge reset)
if (reset) _047_ <= 32'd0;
else _047_ <= _159_;
always @(posedge clk, posedge reset)
if (reset) _048_ <= 32'd0;
else _048_ <= _170_;
assign _049_ = ~ reset;
assign _050_ = _049_ ? registers[972:960] : _051_;
always @(posedge clk)
_051_ <= _050_;
assign _052_ = ~ _042_[4];
assign _053_ = ~ _042_[3];
assign _054_ = _052_ & _053_;
assign _055_ = _052_ & _042_[3];
assign _056_ = _042_[4] & _053_;
assign _057_ = _042_[4] & _042_[3];
assign _058_ = ~ _042_[2];
assign _059_ = _054_ & _058_;
assign _060_ = _054_ & _042_[2];
assign _061_ = _055_ & _058_;
assign _062_ = _055_ & _042_[2];
assign _063_ = _056_ & _058_;
assign _064_ = _056_ & _042_[2];
assign _065_ = _057_ & _058_;
assign _066_ = _057_ & _042_[2];
assign _067_ = ~ _042_[1];
assign _068_ = _059_ & _067_;
assign _069_ = _059_ & _042_[1];
assign _070_ = _060_ & _067_;
assign _071_ = _060_ & _042_[1];
assign _072_ = _061_ & _067_;
assign _073_ = _061_ & _042_[1];
assign _074_ = _062_ & _067_;
assign _075_ = _062_ & _042_[1];
assign _076_ = _063_ & _067_;
assign _077_ = _063_ & _042_[1];
assign _078_ = _064_ & _067_;
assign _079_ = _064_ & _042_[1];
assign _080_ = _065_ & _067_;
assign _081_ = _065_ & _042_[1];
assign _082_ = _066_ & _067_;
assign _083_ = _066_ & _042_[1];
assign _084_ = ~ _042_[0];
assign _085_ = _068_ & _084_;
assign _086_ = _068_ & _042_[0];
assign _087_ = _069_ & _084_;
assign _088_ = _069_ & _042_[0];
assign _089_ = _070_ & _084_;
assign _090_ = _070_ & _042_[0];
assign _091_ = _071_ & _084_;
assign _092_ = _071_ & _042_[0];
assign _093_ = _072_ & _084_;
assign _094_ = _072_ & _042_[0];
assign _095_ = _073_ & _084_;
assign _096_ = _073_ & _042_[0];
assign _097_ = _074_ & _084_;
assign _098_ = _074_ & _042_[0];
assign _099_ = _075_ & _084_;
assign _100_ = _075_ & _042_[0];
assign _101_ = _076_ & _084_;
assign _102_ = _076_ & _042_[0];
assign _103_ = _077_ & _084_;
assign _104_ = _077_ & _042_[0];
assign _105_ = _078_ & _084_;
assign _106_ = _078_ & _042_[0];
assign _107_ = _079_ & _084_;
assign _108_ = _079_ & _042_[0];
assign _109_ = _080_ & _084_;
assign _110_ = _080_ & _042_[0];
assign _111_ = _081_ & _084_;
assign _112_ = _081_ & _042_[0];
assign _113_ = _082_ & _084_;
assign _114_ = _082_ & _042_[0];
assign _115_ = _083_ & _084_;
assign _116_ = _083_ & _042_[0];
assign _117_ = _085_ ? rd : registers[31:0];
assign _118_ = _086_ ? rd : registers[63:32];
assign _119_ = _087_ ? rd : registers[95:64];
assign _120_ = _088_ ? rd : registers[127:96];
assign _121_ = _089_ ? rd : registers[159:128];
assign _122_ = _090_ ? rd : registers[191:160];
assign _123_ = _091_ ? rd : registers[223:192];
assign _124_ = _092_ ? rd : registers[255:224];
assign _125_ = _093_ ? rd : registers[287:256];
assign _126_ = _094_ ? rd : registers[319:288];
assign _127_ = _095_ ? rd : registers[351:320];
assign _128_ = _096_ ? rd : registers[383:352];
assign _129_ = _097_ ? rd : registers[415:384];
assign _130_ = _098_ ? rd : registers[447:416];
assign _131_ = _099_ ? rd : registers[479:448];
assign _132_ = _100_ ? rd : registers[511:480];
assign _133_ = _101_ ? rd : registers[543:512];
assign _134_ = _102_ ? rd : registers[575:544];
assign _135_ = _103_ ? rd : registers[607:576];
assign _136_ = _104_ ? rd : registers[639:608];
assign _137_ = _105_ ? rd : registers[671:640];
assign _138_ = _106_ ? rd : registers[703:672];
assign _139_ = _107_ ? rd : registers[735:704];
assign _140_ = _108_ ? rd : registers[767:736];
assign _141_ = _109_ ? rd : registers[799:768];
assign _142_ = _110_ ? rd : registers[831:800];
assign _143_ = _111_ ? rd : registers[863:832];
assign _144_ = _112_ ? rd : registers[895:864];
assign _145_ = _113_ ? rd : registers[927:896];
assign _146_ = _114_ ? rd : registers[959:928];
assign _147_ = _115_ ? rd : registers[991:960];
assign _148_ = _116_ ? rd : registers[1023:992];
assign _159_ = _043_[4] ? _158_ : _157_;
assign registers = _046_;
assign rs1 = _047_;
assign rs2 = _048_;
assign x1 = _051_;
endmodule
module spi_master(clk, mode_select, reset, miso, cs, data_in, addr, sclk, mosi, data_out, data_valid);
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire [31:0] _060_;
wire [31:0] _061_;
wire [31:0] _062_;
wire [2:0] _063_;
wire _064_;
wire [31:0] _065_;
reg [31:0] _066_;
wire _067_;
wire _068_;
wire _069_;
reg _070_;
wire _071_;
wire [31:0] _072_;
reg [31:0] _073_ = 32'd16;
wire _074_;
wire [31:0] _075_;
reg [31:0] _076_ = 32'd33;
reg [2:0] _077_;
wire _078_;
wire _079_;
reg _080_;
wire _081_;
wire [31:0] _082_;
reg [31:0] _083_;
wire _084_;
wire _085_;
reg _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
wire _203_;
wire _204_;
wire _205_;
wire _206_;
wire _207_;
wire _208_;
wire _209_;
wire _210_;
wire _211_;
wire _212_;
wire _213_;
wire _214_;
wire _215_;
wire _216_;
wire _217_;
wire _218_;
wire _219_;
wire _220_;
wire _221_;
wire _222_;
wire _223_;
wire _224_;
wire _225_;
wire _226_;
wire _227_;
wire _228_;
wire _229_;
wire _230_;
wire _231_;
wire _232_;
wire _233_;
wire _234_;
wire _235_;
wire _236_;
wire _237_;
wire _238_;
wire _239_;
wire _240_;
wire _241_;
wire _242_;
wire _243_;
wire _244_;
wire _245_;
wire _246_;
wire _247_;
wire _248_;
wire _249_;
wire _250_;
wire _251_;
wire _252_;
wire _253_;
wire _254_;
wire _255_;
wire _256_;
wire _257_;
wire _258_;
wire _259_;
wire _260_;
wire _261_;
wire _262_;
wire _263_;
wire _264_;
wire _265_;
wire _266_;
wire _267_;
wire _268_;
wire _269_;
wire _270_;
wire _271_;
wire _272_;
wire _273_;
wire _274_;
wire _275_;
wire _276_;
wire _277_;
wire _278_;
wire _279_;
wire _280_;
wire _281_;
wire _282_;
wire _283_;
wire _284_;
wire _285_;
wire _286_;
wire _287_;
wire _288_;
wire _289_;
wire _290_;
wire _291_;
wire _292_;
wire _293_;
wire _294_;
wire _295_;
wire _296_;
wire _297_;
wire _298_;
wire _299_;
wire _300_;
wire _301_;
wire _302_;
wire _303_;
wire _304_;
wire _305_;
wire _306_;
wire _307_;
wire _308_;
wire _309_;
wire _310_;
wire _311_;
wire _312_;
wire _313_;
wire _314_;
wire _315_;
wire [2:0] _316_;
wire _317_;
wire _318_;
wire [31:0] _319_;
wire _320_;
wire _321_;
wire _322_;
wire [31:0] _323_;
wire _324_;
wire [2:0] _325_;
wire [2:0] _326_;
wire _327_;
wire [31:0] _328_;
wire [2:0] _329_;
wire _330_;
wire [31:0] _331_;
wire [2:0] _332_;
wire _333_;
wire _334_;
wire [31:0] _335_;
wire _336_;
wire [31:0] _337_;
wire [31:0] _338_;
wire [31:0] _339_;
wire [2:0] _340_;
wire [31:0] _341_;
wire [31:0] _342_;
wire [2:0] _343_;
wire _344_;
wire _345_;
wire [31:0] _346_;
wire _347_;
wire [31:0] _348_;
wire _349_;
wire [31:0] _350_;
wire [2:0] _351_;
wire _352_;
wire [31:0] _353_;
wire [2:0] _354_;
wire _355_;
wire [31:0] _356_;
wire _357_;
wire [2:0] _358_;
wire _359_;
wire [31:0] _360_;
wire _361_;
wire [31:0] _362_;
wire [2:0] _363_;
wire _364_;
wire [31:0] _365_;
wire _366_;
wire [31:0] _367_;
wire [31:0] _368_;
wire [2:0] _369_;
wire _370_;
wire [31:0] _371_;
wire _372_;
wire [31:0] _373_;
wire [31:0] _374_;
wire [31:0] _375_;
wire [2:0] _376_;
wire _377_;
wire [31:0] _378_;
wire _379_;
input [15:0] addr;
wire [15:0] addr;
input clk;
wire clk;
input cs;
wire cs;
wire [2:0] currstate;
input [31:0] data_in;
wire [31:0] data_in;
output [31:0] data_out;
wire [31:0] data_out;
wire [31:0] data_reg;
output data_valid;
wire data_valid;
input miso;
wire miso;
input mode_select;
wire mode_select;
wire mode_select_zw;
output mosi;
wire mosi;
wire [31:0] read_adress_counter;
input reset;
wire reset;
output sclk;
wire sclk;
wire [31:0] write_adress_counter;
assign _000_ = write_adress_counter[0] ? addr[1] : addr[0];
assign _001_ = write_adress_counter[0] ? addr[5] : addr[4];
assign _002_ = write_adress_counter[0] ? addr[9] : addr[8];
assign _003_ = write_adress_counter[0] ? addr[13] : addr[12];
assign _004_ = write_adress_counter[2] ? _088_ : _087_;
assign _005_ = write_adress_counter[0] ? addr[1] : addr[0];
assign _006_ = write_adress_counter[0] ? addr[5] : addr[4];
assign _007_ = write_adress_counter[0] ? addr[9] : addr[8];
assign _008_ = write_adress_counter[0] ? addr[13] : addr[12];
assign _009_ = write_adress_counter[2] ? _093_ : _092_;
assign _010_ = read_adress_counter[0] ? data_in[1] : data_in[0];
assign _011_ = read_adress_counter[0] ? data_in[5] : data_in[4];
assign _012_ = read_adress_counter[0] ? data_in[9] : data_in[8];
assign _013_ = read_adress_counter[0] ? data_in[13] : data_in[12];
assign _014_ = read_adress_counter[0] ? data_in[17] : data_in[16];
assign _015_ = read_adress_counter[0] ? data_in[21] : data_in[20];
assign _016_ = read_adress_counter[0] ? data_in[25] : data_in[24];
assign _017_ = read_adress_counter[0] ? data_in[29] : data_in[28];
assign _018_ = read_adress_counter[2] ? _293_ : _292_;
assign _019_ = read_adress_counter[2] ? _297_ : _296_;
assign _020_ = read_adress_counter[0] ? data_in[1] : data_in[0];
assign _021_ = read_adress_counter[0] ? data_in[5] : data_in[4];
assign _022_ = read_adress_counter[0] ? data_in[9] : data_in[8];
assign _023_ = read_adress_counter[0] ? data_in[13] : data_in[12];
assign _024_ = read_adress_counter[0] ? data_in[17] : data_in[16];
assign _025_ = read_adress_counter[0] ? data_in[21] : data_in[20];
assign _026_ = read_adress_counter[0] ? data_in[25] : data_in[24];
assign _027_ = read_adress_counter[0] ? data_in[29] : data_in[28];
assign _028_ = read_adress_counter[2] ? _305_ : _304_;
assign _029_ = read_adress_counter[2] ? _309_ : _308_;
assign _030_ = write_adress_counter[0] ? addr[3] : addr[2];
assign _031_ = write_adress_counter[0] ? addr[7] : addr[6];
assign _032_ = write_adress_counter[0] ? addr[11] : addr[10];
assign _033_ = write_adress_counter[0] ? addr[15] : addr[14];
assign _034_ = write_adress_counter[2] ? _090_ : _089_;
assign _035_ = write_adress_counter[0] ? addr[3] : addr[2];
assign _036_ = write_adress_counter[0] ? addr[7] : addr[6];
assign _037_ = write_adress_counter[0] ? addr[11] : addr[10];
assign _038_ = write_adress_counter[0] ? addr[15] : addr[14];
assign _039_ = write_adress_counter[2] ? _095_ : _094_;
assign _040_ = read_adress_counter[0] ? data_in[3] : data_in[2];
assign _041_ = read_adress_counter[0] ? data_in[7] : data_in[6];
assign _042_ = read_adress_counter[0] ? data_in[11] : data_in[10];
assign _043_ = read_adress_counter[0] ? data_in[15] : data_in[14];
assign _044_ = read_adress_counter[0] ? data_in[19] : data_in[18];
assign _045_ = read_adress_counter[0] ? data_in[23] : data_in[22];
assign _046_ = read_adress_counter[0] ? data_in[27] : data_in[26];
assign _047_ = read_adress_counter[0] ? data_in[31] : data_in[30];
assign _048_ = read_adress_counter[2] ? _295_ : _294_;
assign _049_ = read_adress_counter[2] ? _299_ : _298_;
assign _050_ = read_adress_counter[0] ? data_in[3] : data_in[2];
assign _051_ = read_adress_counter[0] ? data_in[7] : data_in[6];
assign _052_ = read_adress_counter[0] ? data_in[11] : data_in[10];
assign _053_ = read_adress_counter[0] ? data_in[15] : data_in[14];
assign _054_ = read_adress_counter[0] ? data_in[19] : data_in[18];
assign _055_ = read_adress_counter[0] ? data_in[23] : data_in[22];
assign _056_ = read_adress_counter[0] ? data_in[27] : data_in[26];
assign _057_ = read_adress_counter[0] ? data_in[31] : data_in[30];
assign _058_ = read_adress_counter[2] ? _307_ : _306_;
assign _059_ = read_adress_counter[2] ? _311_ : _310_;
assign _087_ = write_adress_counter[1] ? _030_ : _000_;
assign _088_ = write_adress_counter[1] ? _031_ : _001_;
assign _089_ = write_adress_counter[1] ? _032_ : _002_;
assign _090_ = write_adress_counter[1] ? _033_ : _003_;
assign _091_ = write_adress_counter[3] ? _034_ : _004_;
assign _092_ = write_adress_counter[1] ? _035_ : _005_;
assign _093_ = write_adress_counter[1] ? _036_ : _006_;
assign _094_ = write_adress_counter[1] ? _037_ : _007_;
assign _095_ = write_adress_counter[1] ? _038_ : _008_;
assign _096_ = write_adress_counter[3] ? _039_ : _009_;
assign _292_ = read_adress_counter[1] ? _040_ : _010_;
assign _293_ = read_adress_counter[1] ? _041_ : _011_;
assign _294_ = read_adress_counter[1] ? _042_ : _012_;
assign _295_ = read_adress_counter[1] ? _043_ : _013_;
assign _296_ = read_adress_counter[1] ? _044_ : _014_;
assign _297_ = read_adress_counter[1] ? _045_ : _015_;
assign _298_ = read_adress_counter[1] ? _046_ : _016_;
assign _299_ = read_adress_counter[1] ? _047_ : _017_;
assign _300_ = read_adress_counter[3] ? _048_ : _018_;
assign _302_ = read_adress_counter[3] ? _049_ : _019_;
assign _304_ = read_adress_counter[1] ? _050_ : _020_;
assign _305_ = read_adress_counter[1] ? _051_ : _021_;
assign _306_ = read_adress_counter[1] ? _052_ : _022_;
assign _307_ = read_adress_counter[1] ? _053_ : _023_;
assign _308_ = read_adress_counter[1] ? _054_ : _024_;
assign _309_ = read_adress_counter[1] ? _055_ : _025_;
assign _310_ = read_adress_counter[1] ? _056_ : _026_;
assign _311_ = read_adress_counter[1] ? _057_ : _027_;
assign _313_ = read_adress_counter[3] ? _058_ : _028_;
assign _314_ = read_adress_counter[3] ? _059_ : _029_;
assign _316_ = _301_ ? 3'h1 : currstate;
assign _317_ = currstate == 3'h1;
assign _318_ = write_adress_counter == 32'd16;
assign _319_ = write_adress_counter - 32'd1;
assign _320_ = $signed(write_adress_counter) > $signed(32'd0);
assign _321_ = $signed(write_adress_counter) <= $signed(32'd15);
assign _322_ = _321_ & _320_;
assign _323_ = write_adress_counter - 32'd1;
assign _324_ = ~ mode_select_zw;
assign _325_ = mode_select_zw ? 3'h2 : currstate;
assign _326_ = _324_ ? 3'h3 : _325_;
assign _327_ = _322_ ? _091_ : _096_;
assign _328_ = _322_ ? _323_ : write_adress_counter;
assign _329_ = _322_ ? currstate : _326_;
assign _330_ = _318_ ? mode_select_zw : _327_;
assign _331_ = _318_ ? _319_ : _328_;
assign _332_ = _318_ ? currstate : _329_;
assign _333_ = currstate == 3'h3;
assign _334_ = $signed(read_adress_counter) >= $signed(32'd32);
assign _335_ = read_adress_counter - 32'd1;
assign _336_ = $signed(read_adress_counter) > $signed(32'd0);
assign _337_ = read_adress_counter - 32'd1;
assign _338_ = _336_ ? { _193_, _192_, _191_, _190_, _189_, _188_, _187_, _186_, _185_, _184_, _183_, _182_, _181_, _180_, _179_, _178_, _177_, _176_, _175_, _174_, _173_, _172_, _171_, _170_, _169_, _168_, _167_, _166_, _165_, _164_, _163_, _162_ } : { _291_, _289_, _288_, _287_, _286_, _285_, _284_, _283_, _282_, _281_, _280_, _279_, _278_, _277_, _276_, _275_, _274_, _273_, _272_, _271_, _270_, _269_, _268_, _267_, _266_, _265_, _264_, _263_, _262_, _261_, _260_, _259_ };
assign _339_ = _336_ ? _337_ : read_adress_counter;
assign _340_ = _336_ ? currstate : 3'h4;
assign _341_ = _334_ ? data_reg : _338_;
assign _342_ = _334_ ? _335_ : _339_;
assign _343_ = _334_ ? currstate : _340_;
assign _344_ = currstate == 3'h2;
assign _345_ = $signed(read_adress_counter) >= $signed(32'd32);
assign _346_ = read_adress_counter - 32'd1;
assign _347_ = $signed(read_adress_counter) > $signed(32'd0);
assign _348_ = read_adress_counter - 32'd1;
assign _349_ = _347_ ? _303_ : _315_;
assign _350_ = _347_ ? _348_ : read_adress_counter;
assign _351_ = _347_ ? currstate : 3'h4;
assign _352_ = _345_ ? _080_ : _349_;
assign _353_ = _345_ ? _346_ : _350_;
assign _354_ = _345_ ? currstate : _351_;
assign _355_ = currstate == 3'h4;
assign _356_ = _355_ ? data_reg : _083_;
assign _357_ = _355_ ? 1'h1 : _086_;
assign _358_ = _355_ ? 3'h0 : currstate;
assign _359_ = _344_ ? _352_ : _080_;
assign _360_ = _344_ ? _083_ : _356_;
assign _361_ = _344_ ? _086_ : _357_;
assign _362_ = _344_ ? _353_ : read_adress_counter;
assign _363_ = _344_ ? _354_ : _358_;
assign _364_ = _333_ ? _080_ : _359_;
assign _365_ = _333_ ? _083_ : _360_;
assign _366_ = _333_ ? _086_ : _361_;
assign _367_ = _333_ ? _341_ : data_reg;
assign _368_ = _333_ ? _342_ : _362_;
assign _369_ = _333_ ? _343_ : _363_;
assign _370_ = _317_ ? _330_ : _364_;
assign _371_ = _317_ ? _083_ : _365_;
assign _372_ = _317_ ? _086_ : _366_;
assign _373_ = _317_ ? data_reg : _367_;
assign _374_ = _317_ ? _331_ : write_adress_counter;
assign _375_ = _317_ ? read_adress_counter : _368_;
assign _376_ = _317_ ? _332_ : _369_;
assign _377_ = _290_ ? 1'h0 : _370_;
assign _378_ = _290_ ? 32'd0 : _371_;
assign _379_ = _290_ ? 1'h0 : _372_;
assign _060_ = _290_ ? 32'd0 : _373_;
assign _061_ = _290_ ? 32'd16 : _374_;
assign _062_ = _290_ ? 32'd33 : _375_;
assign _063_ = _290_ ? _316_ : _376_;
assign _064_ = ~ reset;
assign _065_ = _064_ ? _060_ : data_reg;
always @(posedge clk)
_066_ <= _065_;
assign _067_ = ~ reset;
assign _068_ = _290_ & _067_;
assign _069_ = _068_ ? _312_ : mode_select_zw;
always @(posedge clk)
_070_ <= _069_;
assign _071_ = ~ reset;
assign _072_ = _071_ ? _061_ : write_adress_counter;
always @(posedge clk)
_073_ <= _072_;
assign _074_ = ~ reset;
assign _075_ = _074_ ? _062_ : read_adress_counter;
always @(posedge clk)
_076_ <= _075_;
always @(posedge clk, posedge reset)
if (reset) _077_ <= 3'h0;
else _077_ <= _063_;
assign _078_ = ~ reset;
assign _079_ = _078_ ? _377_ : _080_;
always @(posedge clk)
_080_ <= _079_;
assign _081_ = ~ reset;
assign _082_ = _081_ ? _378_ : _083_;
always @(posedge clk)
_083_ <= _082_;
assign _084_ = ~ reset;
assign _085_ = _084_ ? _379_ : _086_;
always @(posedge clk)
_086_ <= _085_;
assign _097_ = ~ read_adress_counter[4];
assign _098_ = ~ read_adress_counter[3];
assign _099_ = _097_ & _098_;
assign _100_ = _097_ & read_adress_counter[3];
assign _101_ = read_adress_counter[4] & _098_;
assign _102_ = read_adress_counter[4] & read_adress_counter[3];
assign _103_ = ~ read_adress_counter[2];
assign _104_ = _099_ & _103_;
assign _105_ = _099_ & read_adress_counter[2];
assign _106_ = _100_ & _103_;
assign _107_ = _100_ & read_adress_counter[2];
assign _108_ = _101_ & _103_;
assign _109_ = _101_ & read_adress_counter[2];
assign _110_ = _102_ & _103_;
assign _111_ = _102_ & read_adress_counter[2];
assign _112_ = ~ read_adress_counter[1];
assign _113_ = _104_ & _112_;
assign _114_ = _104_ & read_adress_counter[1];
assign _115_ = _105_ & _112_;
assign _116_ = _105_ & read_adress_counter[1];
assign _117_ = _106_ & _112_;
assign _118_ = _106_ & read_adress_counter[1];
assign _119_ = _107_ & _112_;
assign _120_ = _107_ & read_adress_counter[1];
assign _121_ = _108_ & _112_;
assign _122_ = _108_ & read_adress_counter[1];
assign _123_ = _109_ & _112_;
assign _124_ = _109_ & read_adress_counter[1];
assign _125_ = _110_ & _112_;
assign _126_ = _110_ & read_adress_counter[1];
assign _127_ = _111_ & _112_;
assign _128_ = _111_ & read_adress_counter[1];
assign _129_ = ~ read_adress_counter[0];
assign _130_ = _113_ & _129_;
assign _131_ = _113_ & read_adress_counter[0];
assign _132_ = _114_ & _129_;
assign _133_ = _114_ & read_adress_counter[0];
assign _134_ = _115_ & _129_;
assign _135_ = _115_ & read_adress_counter[0];
assign _136_ = _116_ & _129_;
assign _137_ = _116_ & read_adress_counter[0];
assign _138_ = _117_ & _129_;
assign _139_ = _117_ & read_adress_counter[0];
assign _140_ = _118_ & _129_;
assign _141_ = _118_ & read_adress_counter[0];
assign _142_ = _119_ & _129_;
assign _143_ = _119_ & read_adress_counter[0];
assign _144_ = _120_ & _129_;
assign _145_ = _120_ & read_adress_counter[0];
assign _146_ = _121_ & _129_;
assign _147_ = _121_ & read_adress_counter[0];
assign _148_ = _122_ & _129_;
assign _149_ = _122_ & read_adress_counter[0];
assign _150_ = _123_ & _129_;
assign _151_ = _123_ & read_adress_counter[0];
assign _152_ = _124_ & _129_;
assign _153_ = _124_ & read_adress_counter[0];
assign _154_ = _125_ & _129_;
assign _155_ = _125_ & read_adress_counter[0];
assign _156_ = _126_ & _129_;
assign _157_ = _126_ & read_adress_counter[0];
assign _158_ = _127_ & _129_;
assign _159_ = _127_ & read_adress_counter[0];
assign _160_ = _128_ & _129_;
assign _161_ = _128_ & read_adress_counter[0];
assign _162_ = _130_ ? miso : data_reg[0];
assign _163_ = _131_ ? miso : data_reg[1];
assign _164_ = _132_ ? miso : data_reg[2];
assign _165_ = _133_ ? miso : data_reg[3];
assign _166_ = _134_ ? miso : data_reg[4];
assign _167_ = _135_ ? miso : data_reg[5];
assign _168_ = _136_ ? miso : data_reg[6];
assign _169_ = _137_ ? miso : data_reg[7];
assign _170_ = _138_ ? miso : data_reg[8];
assign _171_ = _139_ ? miso : data_reg[9];
assign _172_ = _140_ ? miso : data_reg[10];
assign _173_ = _141_ ? miso : data_reg[11];
assign _174_ = _142_ ? miso : data_reg[12];
assign _175_ = _143_ ? miso : data_reg[13];
assign _176_ = _144_ ? miso : data_reg[14];
assign _177_ = _145_ ? miso : data_reg[15];
assign _178_ = _146_ ? miso : data_reg[16];
assign _179_ = _147_ ? miso : data_reg[17];
assign _180_ = _148_ ? miso : data_reg[18];
assign _181_ = _149_ ? miso : data_reg[19];
assign _182_ = _150_ ? miso : data_reg[20];
assign _183_ = _151_ ? miso : data_reg[21];
assign _184_ = _152_ ? miso : data_reg[22];
assign _185_ = _153_ ? miso : data_reg[23];
assign _186_ = _154_ ? miso : data_reg[24];
assign _187_ = _155_ ? miso : data_reg[25];
assign _188_ = _156_ ? miso : data_reg[26];
assign _189_ = _157_ ? miso : data_reg[27];
assign _190_ = _158_ ? miso : data_reg[28];
assign _191_ = _159_ ? miso : data_reg[29];
assign _192_ = _160_ ? miso : data_reg[30];
assign _193_ = _161_ ? miso : data_reg[31];
assign _194_ = ~ read_adress_counter[4];
assign _195_ = ~ read_adress_counter[3];
assign _196_ = _194_ & _195_;
assign _197_ = _194_ & read_adress_counter[3];
assign _198_ = read_adress_counter[4] & _195_;
assign _199_ = read_adress_counter[4] & read_adress_counter[3];
assign _200_ = ~ read_adress_counter[2];
assign _201_ = _196_ & _200_;
assign _202_ = _196_ & read_adress_counter[2];
assign _203_ = _197_ & _200_;
assign _204_ = _197_ & read_adress_counter[2];
assign _205_ = _198_ & _200_;
assign _206_ = _198_ & read_adress_counter[2];
assign _207_ = _199_ & _200_;
assign _208_ = _199_ & read_adress_counter[2];
assign _209_ = ~ read_adress_counter[1];
assign _210_ = _201_ & _209_;
assign _211_ = _201_ & read_adress_counter[1];
assign _212_ = _202_ & _209_;
assign _213_ = _202_ & read_adress_counter[1];
assign _214_ = _203_ & _209_;
assign _215_ = _203_ & read_adress_counter[1];
assign _216_ = _204_ & _209_;
assign _217_ = _204_ & read_adress_counter[1];
assign _218_ = _205_ & _209_;
assign _219_ = _205_ & read_adress_counter[1];
assign _220_ = _206_ & _209_;
assign _221_ = _206_ & read_adress_counter[1];
assign _222_ = _207_ & _209_;
assign _223_ = _207_ & read_adress_counter[1];
assign _224_ = _208_ & _209_;
assign _225_ = _208_ & read_adress_counter[1];
assign _226_ = ~ read_adress_counter[0];
assign _227_ = _210_ & _226_;
assign _228_ = _210_ & read_adress_counter[0];
assign _229_ = _211_ & _226_;
assign _230_ = _211_ & read_adress_counter[0];
assign _231_ = _212_ & _226_;
assign _232_ = _212_ & read_adress_counter[0];
assign _233_ = _213_ & _226_;
assign _234_ = _213_ & read_adress_counter[0];
assign _235_ = _214_ & _226_;
assign _236_ = _214_ & read_adress_counter[0];
assign _237_ = _215_ & _226_;
assign _238_ = _215_ & read_adress_counter[0];
assign _239_ = _216_ & _226_;
assign _240_ = _216_ & read_adress_counter[0];
assign _241_ = _217_ & _226_;
assign _242_ = _217_ & read_adress_counter[0];
assign _243_ = _218_ & _226_;
assign _244_ = _218_ & read_adress_counter[0];
assign _245_ = _219_ & _226_;
assign _246_ = _219_ & read_adress_counter[0];
assign _247_ = _220_ & _226_;
assign _248_ = _220_ & read_adress_counter[0];
assign _249_ = _221_ & _226_;
assign _250_ = _221_ & read_adress_counter[0];
assign _251_ = _222_ & _226_;
assign _252_ = _222_ & read_adress_counter[0];
assign _253_ = _223_ & _226_;
assign _254_ = _223_ & read_adress_counter[0];
assign _255_ = _224_ & _226_;
assign _256_ = _224_ & read_adress_counter[0];
assign _257_ = _225_ & _226_;
assign _258_ = _225_ & read_adress_counter[0];
assign _259_ = _227_ ? miso : data_reg[0];
assign _260_ = _228_ ? miso : data_reg[1];
assign _261_ = _229_ ? miso : data_reg[2];
assign _262_ = _230_ ? miso : data_reg[3];
assign _263_ = _231_ ? miso : data_reg[4];
assign _264_ = _232_ ? miso : data_reg[5];
assign _265_ = _233_ ? miso : data_reg[6];
assign _266_ = _234_ ? miso : data_reg[7];
assign _267_ = _235_ ? miso : data_reg[8];
assign _268_ = _236_ ? miso : data_reg[9];
assign _269_ = _237_ ? miso : data_reg[10];
assign _270_ = _238_ ? miso : data_reg[11];
assign _271_ = _239_ ? miso : data_reg[12];
assign _272_ = _240_ ? miso : data_reg[13];
assign _273_ = _241_ ? miso : data_reg[14];
assign _274_ = _242_ ? miso : data_reg[15];
assign _275_ = _243_ ? miso : data_reg[16];
assign _276_ = _244_ ? miso : data_reg[17];
assign _277_ = _245_ ? miso : data_reg[18];
assign _278_ = _246_ ? miso : data_reg[19];
assign _279_ = _247_ ? miso : data_reg[20];
assign _280_ = _248_ ? miso : data_reg[21];
assign _281_ = _249_ ? miso : data_reg[22];
assign _282_ = _250_ ? miso : data_reg[23];
assign _283_ = _251_ ? miso : data_reg[24];
assign _284_ = _252_ ? miso : data_reg[25];
assign _285_ = _253_ ? miso : data_reg[26];
assign _286_ = _254_ ? miso : data_reg[27];
assign _287_ = _255_ ? miso : data_reg[28];
assign _288_ = _256_ ? miso : data_reg[29];
assign _289_ = _257_ ? miso : data_reg[30];
assign _291_ = _258_ ? miso : data_reg[31];
assign _303_ = read_adress_counter[4] ? _302_ : _300_;
assign _315_ = read_adress_counter[4] ? _314_ : _313_;
assign _290_ = currstate == 3'h0;
assign _301_ = ~ cs;
assign _312_ = _301_ ? mode_select : 1'h0;
assign data_reg = _066_;
assign mode_select_zw = _070_;
assign write_adress_counter = _073_;
assign read_adress_counter = _076_;
assign currstate = _077_;
assign sclk = clk;
assign mosi = _080_;
assign data_out = _083_;
assign data_valid = _086_;
endmodule
module tt_um_cejmu_riscv(clk, ena, rst_n, ui_in, uio_in, uo_out, uio_out, uio_oe);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
|
module tt_um_cejmu_riscv(clk, ena, rst_n, ui_in, uio_in, uo_out, uio_out, uio_oe);
wire _0_;
wire _1_;
wire [31:0] _2_;
wire [13:0] _3_;
wire _4_;
wire _5_;
wire [12:0] _6_;
wire _7_;
wire _8_;
wire [31:0] _9_;
input clk;
wire clk;
wire [13:0] cpu_addr_out;
wire data_valid;
input ena;
wire ena;
wire mem_req;
wire reset;
input rst_n;
wire rst_n;
wire [15:0] spi_addr_in;
wire [31:0] spi_data_in;
wire [31:0] spi_data_out;
input [7:0] ui_in;
wire [7:0] ui_in;
input [7:0] uio_in;
wire [7:0] uio_in;
output [7:0] uio_oe;
wire [7:0] uio_oe;
output [7:0] uio_out;
wire [7:0] uio_out;
output [7:0] uo_out;
wire [7:0] uo_out;
wire write_enable;
wire [12:0] x1;
assign _0_ = ~ rst_n;
cpu cpu_inst (
.addr_out(_3_),
.clk(clk),
.data_in(spi_data_out),
.data_out(_2_),
.data_valid(data_valid),
.mem_req(_5_),
.reset(reset),
.write_en(_4_),
.x1(_6_)
);
spi_master spi_master_inst (
.addr(spi_addr_in),
.clk(clk),
.cs(mem_req),
.data_in(spi_data_in),
.data_out(_9_),
.data_valid(_1_),
.miso(ui_in[0]),
.mode_select(write_enable),
.mosi(_8_),
.reset(reset),
.sclk(_7_)
);
assign write_enable = _4_;
assign cpu_addr_out = _3_;
assign spi_addr_in = { 2'h0, cpu_addr_out };
assign spi_data_out = _9_;
assign spi_data_in = _2_;
assign mem_req = _5_;
assign data_valid = _1_;
assign reset = _0_;
assign x1 = _6_;
assign uo_out = { x1[4:0], mem_req, _7_, _8_ };
assign uio_out = x1[12:5];
assign uio_oe = 8'hff;
endmodule
|
tt06-finale_0008
|
tt06-finale
|
CKPope-tt06-verilog-template
|
task_Compx1
|
tt_um_CKPope_top
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
module tt_um_CKPope_top
(
input wire [7:0] ui_in, // Dedicated inputs for X and Y Target coordinates (BCD: 7:4 for X; 3:0 for Y)
output wire [7:0] uo_out, // Dedicated outputs for X Position and Y Position (BCD: 7:4 for X; 3:0 for Y)
input wire [7:0] uio_in, // IOs: Input path for FSM Control MOTION control input plus spares
output wire [7:0] uio_out, // IOs: Output path (not used)
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output) - TIED For UIO BEING INPUTS ONLY
input wire ena, // will go high when the design is enabled
input wire clk, // clock
// ---------------------------------------------------------------
//outputs for simulation diagnostics
// output wire init_regs_out,
// output wire load_xy_out,
// output wire [3:0] x_target_reg_out,
// output wire [3:0] y_target_reg_out,
// output wire x_comp_eq_out, x_comp_gt_out, x_comp_lt_out,
// output wire x_counten_out, x_count_up1_dwn0_out,
// output wire y_comp_eq_out, y_comp_gt_out, y_comp_lt_out,
// output wire y_counten_out, y_count_up1_dwn0_out,
// output wire reset_n_out, reset_out, motion_out,
//-- --------------------------------------------------------------
input wire rst_n // reset_n - low to reset
);// Quartus Prime Verilog Template
//----------------------------------------------------------------
//Local tile signal Inputs
wire clock, sync_reset, reset_n;
//FSM Initialization of external registers
wire init_regs;
//FSM control inputs;
wire motion_inp,sync_motion;
// x-y target data inputs
wire [3:0] x_target;
wire [3:0] y_target;
// x-y target_register signals
wire [3:0] x_target_reg;
wire [3:0] y_target_reg;
wire load_xy;
// x-y counter signals
wire x_counten, x_count_up1_dwn0, y_counten, y_count_up1_dwn0;
wire [3:0] x_pos;
wire [3:0] y_pos;
// X-Y Counter comparator signals
wire x_comp_eq, x_comp_gt, x_comp_lt;
wire y_comp_eq, y_comp_gt, y_comp_lt;
//----------------------------------------------------------------
// make Connections to infrastructure signals. clock can only run when the module is enabled (selected)
assign clock = clk;
assign reset_n = rst_n;
//----------------------------------------------------------------
// make Connections to uio, ui, uo ports
assign motion_inp = (uio_in[0]);
assign x_target = ui_in[7:4];
assign y_target = ui_in[3:0];
assign uo_out[7:4] = x_pos[3:0];
assign uo_out[3:0] = y_pos[3:0];
// TIE OFF Unused uio ports
assign uio_oe = 8'b0;
assign uio_out = 8'b0;
//----------------------------------------------------------------
// module instantiation
// Input Synchronizer
input_synch buttons
(.clk (clock), .reset(!reset_n), .sync_reset(sync_reset), .sync_in(motion_inp), .sync_out (sync_motion));
//FSM:
Mealy_SM xycontroller
(.clk(clock), .reset(!reset_n | sync_reset), .motion(sync_motion), .init(init_regs),
.x_comp_eq(x_comp_eq), .x_comp_gt(x_comp_gt), .x_comp_lt(x_comp_lt), .x_count_en(x_counten), .x_up1_dwn0(x_count_up1_dwn0),
.y_comp_eq(y_comp_eq), .y_comp_gt(y_comp_gt), .y_comp_lt(y_comp_lt), .y_count_en(y_counten), .y_up1_dwn0(y_count_up1_dwn0),
.capt_enbl(load_xy));
//X, Y Target Capture Registers
target_reg x_treg (.clk (clock), .load (load_xy), .data (x_target), .reset ((sync_reset | init_regs)), .target_reg (x_target_reg));
target_reg y_treg (.clk (clock), .load (load_xy), .data (y_target), .reset ((sync_reset | init_regs)), .target_reg (y_target_reg));
//X, Y Counters:
ud_counter x_counter (.clk (clock), .count_en (x_counten), .count_up1_dwn0 (x_count_up1_dwn0), .reset ((sync_reset | init_regs)), .count (x_pos[3:0]));
ud_counter y_counter (.clk (clock), .count_en (y_counten), .count_up1_dwn0 (y_count_up1_dwn0), .reset ((sync_reset | init_regs)), .count (y_pos[3:0]));
// X, Y Comparators
Compx4 x_comp (.a_hex(x_pos), .b_hex(x_target_reg), .a_eq_b(x_comp_eq), .a_gt_b(x_comp_gt), .a_lt_b(x_comp_lt));
Compx4 y_comp (.a_hex(y_pos), .b_hex(y_target_reg), .a_eq_b(y_comp_eq), .a_gt_b(y_comp_gt), .a_lt_b(y_comp_lt));
//----------------------------------------------------------------
// temporary connections for diagnostics outputs
//assign x_target_reg_out = x_target_reg;
//assign y_target_reg_out = y_target_reg;
//assign load_xy_out = load_xy;
//assign x_counten_out = x_counten;
//assign x_comp_eq_out = x_comp_eq;
//assign x_comp_gt_out = x_comp_gt;
//assign x_comp_lt_out = x_comp_lt;
//assign x_count_up1_dwn0_out = x_count_up1_dwn0;
//assign y_counten_out = y_counten;
//assign y_comp_eq_out = y_comp_eq;
//assign y_comp_gt_out = y_comp_gt;
//assign y_comp_lt_out = y_comp_lt;
//assign y_count_up1_dwn0_out = y_count_up1_dwn0;
//assign reset_out = sync_reset;
//assign reset_n_out = reset_n;
//assign init_regs_out = init_regs;
//assign motion_out= sync_motion;
endmodule
module Compx1
(
input a,
input b,
output reg aeqb,
output reg agtb,
output reg altb
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module Compx4
(
input [3:0] a_hex,
input [3:0] b_hex,
output reg a_eq_b,
output reg a_gt_b,
output reg a_lt_b
);
wire [3:0] aeqb;
wire [3:0] agtb;
wire [3:0] altb;
// connections to single bit comparators
Compx1 Bit3_COMP(.a(a_hex[3]), .b(b_hex[3]), .aeqb(aeqb[3]), .agtb(agtb[3]), .altb(altb[3]));
Compx1 Bit2_COMP(.a(a_hex[2]), .b(b_hex[2]), .aeqb(aeqb[2]), .agtb(agtb[2]), .altb(altb[2]));
Compx1 Bit1_COMP(.a(a_hex[1]), .b(b_hex[1]), .aeqb(aeqb[1]), .agtb(agtb[1]), .altb(altb[1]));
Compx1 Bit0_COMP(.a(a_hex[0]), .b(b_hex[0]), .aeqb(aeqb[0]), .agtb(agtb[0]), .altb(altb[0]));
always @(*)
begin
a_eq_b = aeqb[3] & aeqb[2] & aeqb[1] & aeqb[0];
a_gt_b = agtb[3] | (aeqb[3] & agtb[2]) | (aeqb[3] & aeqb[2] & agtb[1]) | (aeqb[3] & aeqb[2] & aeqb[1] & agtb[0]);
a_lt_b = altb[3] | (aeqb[3] & altb[2]) | (aeqb[3] & aeqb[2] & altb[1]) | (aeqb[3] & aeqb[2] & aeqb[1] & altb[0]);
end
endmodule
module Mealy_SM
(
input clk,
input reset,
input motion,
input x_comp_eq,
input x_comp_gt,
input x_comp_lt,
input y_comp_eq,
input y_comp_gt,
input y_comp_lt,
output reg init,
output reg x_count_en,
output reg x_up1_dwn0,
output reg y_count_en,
output reg y_up1_dwn0,
output reg capt_enbl
);
parameter INITIALIZE1 =3'b000,
INITIALIZE2 =3'b001,
AT_REST =3'b010,
CAPTURE_XY =3'b011,
IN_MOTION =3'b100,
XY_REACHED =3'b101;
// RANGE of STATE VALUES (INITIALIZE, AT_REST, CAPTURE_XY, IN_MOTION, XY_REACHED);
reg [2:0] current_state, next_state; // current_state, next_state registers of type STATES
// STATE MACHINE: MEALY Type
//REGISTER SECTION OF STATE MACHINE
always @(posedge clk, posedge reset) // sequential logic to latch the FSM state (FSM REGISTER SECTION)
begin
if (reset==1)
current_state <= INITIALIZE1;
else
current_state <= next_state; // on the rising edge of clock the current state is updated with next state value
end
//TRANSITION SECTION OF STATE MACHINE
always @(*) // logic to determine next state. (FSM TRANSITION SECTION)
begin
case (current_state)
INITIALIZE1:
begin
next_state = INITIALIZE2;
end
INITIALIZE2:
begin
next_state = AT_REST;
end
AT_REST:
begin
if (motion)
next_state = CAPTURE_XY;
else
next_state = AT_REST;
end
CAPTURE_XY:
begin
if (motion)
next_state = CAPTURE_XY; // stay here until MOTION goes off. Then go to IN_MOTION
else
next_state = IN_MOTION;
end
IN_MOTION:
begin
if ((x_comp_eq) & (y_comp_eq))
next_state = XY_REACHED;
else
next_state = IN_MOTION;
end
XY_REACHED:
begin
next_state = AT_REST;
end
default:
next_state = AT_REST;
endcase
end
//DECODER SECTION OF STATE MACHINE
always @(*) // logic to drive MEALY FSM outputs (FSM DECODER SECTION)
begin
if (current_state == INITIALIZE1) // force outside counters to be initialized to zero for first state
begin
init = 1'b1;
x_count_en = 1'b0;
x_up1_dwn0 = 1'b0;
y_count_en = 1'b0;
y_up1_dwn0 = 1'b0;
capt_enbl = 1'b0;
end
else if (current_state == INITIALIZE2) // keep outside counters initialized to zero for another state
begin
init = 1'b0;
x_count_en = 1'b0;
x_up1_dwn0 = 1'b0;
y_count_en = 1'b0;
y_up1_dwn0 = 1'b0;
capt_enbl = 1'b0;
end
else if (current_state == CAPTURE_XY) // motion button has been pressed. activate outside x/y register capture enables
begin
init = 1'b0;
x_count_en = 1'b0;
x_up1_dwn0 = 1'b0;
y_count_en = 1'b0;
y_up1_dwn0 = 1'b0;
capt_enbl = 1'b1;
end
else if (current_state == IN_MOTION) // motion input button release. x/Y motion is now enabled
begin
init = 1'b0;
x_count_en = ((x_comp_gt) | (x_comp_lt));
x_up1_dwn0 = x_comp_lt;
y_count_en = ((y_comp_gt) | (y_comp_lt));
y_up1_dwn0 = y_comp_lt;
capt_enbl = 1'b0;
end
else // default case (used in AT_REST and XY_REACHED states), is to deactivate all FSM outputs.
begin
init = 1'b0;
x_count_en = 1'b0;
x_up1_dwn0 = 1'b0;
y_count_en = 1'b0;
y_up1_dwn0 = 1'b0;
capt_enbl = 1'b0;
end
end
endmodule
module input_synch
(
input wire clk,
input wire reset,
output wire sync_reset,
input wire sync_in,
output wire sync_out
);
reg [1:0] chain0, chain1;
always @ (posedge clk)
begin
chain0[1:0] <= {chain0[0], reset};
chain1[1:0] <= {chain1[0], sync_in};
end
assign sync_reset = (chain0[1]);
assign sync_out = (chain1[1]);
endmodule
module target_reg
(
input wire clk,
input wire load,
input wire [3:0] data,
input wire reset,
output reg [3:0] target_reg
);
// Reset if needed, increment or decrement if counter is not saturated
always @ (posedge clk)
begin
if (reset)
target_reg <= 4'b0000;
else if (load)
target_reg <= data ;
end
endmodule
module ud_counter
(
input wire clk,
input wire count_en,
input wire count_up1_dwn0,
input wire reset,
output reg [3:0] count
);
// Reset if needed, increment or decrement if counter is not saturated
always @ (posedge clk)
begin
if (reset)
count <= 4'b0000;
else if ((count_en & count_up1_dwn0) & (count!= 4'b1111))
count <= count + 4'd0001;
else if ((count_en & (!count_up1_dwn0)) & (count!= 4'b0000))
count <= count - 4'd0001;
end
endmodule
|
module Compx1
(
input a,
input b,
output reg aeqb,
output reg agtb,
output reg altb
);
always @(*)
begin
aeqb = (a & b) | ((!(a)) & (!(b)));
agtb = a & (!(b));
altb = (!(a)) & b ;
end
endmodule
|
tt06-finale_0009
|
tt06-finale
|
CKPope-tt06-verilog-template
|
task_Compx4
|
tt_um_CKPope_top
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
module tt_um_CKPope_top
(
input wire [7:0] ui_in, // Dedicated inputs for X and Y Target coordinates (BCD: 7:4 for X; 3:0 for Y)
output wire [7:0] uo_out, // Dedicated outputs for X Position and Y Position (BCD: 7:4 for X; 3:0 for Y)
input wire [7:0] uio_in, // IOs: Input path for FSM Control MOTION control input plus spares
output wire [7:0] uio_out, // IOs: Output path (not used)
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output) - TIED For UIO BEING INPUTS ONLY
input wire ena, // will go high when the design is enabled
input wire clk, // clock
// ---------------------------------------------------------------
//outputs for simulation diagnostics
// output wire init_regs_out,
// output wire load_xy_out,
// output wire [3:0] x_target_reg_out,
// output wire [3:0] y_target_reg_out,
// output wire x_comp_eq_out, x_comp_gt_out, x_comp_lt_out,
// output wire x_counten_out, x_count_up1_dwn0_out,
// output wire y_comp_eq_out, y_comp_gt_out, y_comp_lt_out,
// output wire y_counten_out, y_count_up1_dwn0_out,
// output wire reset_n_out, reset_out, motion_out,
//-- --------------------------------------------------------------
input wire rst_n // reset_n - low to reset
);// Quartus Prime Verilog Template
//----------------------------------------------------------------
//Local tile signal Inputs
wire clock, sync_reset, reset_n;
//FSM Initialization of external registers
wire init_regs;
//FSM control inputs;
wire motion_inp,sync_motion;
// x-y target data inputs
wire [3:0] x_target;
wire [3:0] y_target;
// x-y target_register signals
wire [3:0] x_target_reg;
wire [3:0] y_target_reg;
wire load_xy;
// x-y counter signals
wire x_counten, x_count_up1_dwn0, y_counten, y_count_up1_dwn0;
wire [3:0] x_pos;
wire [3:0] y_pos;
// X-Y Counter comparator signals
wire x_comp_eq, x_comp_gt, x_comp_lt;
wire y_comp_eq, y_comp_gt, y_comp_lt;
//----------------------------------------------------------------
// make Connections to infrastructure signals. clock can only run when the module is enabled (selected)
assign clock = clk;
assign reset_n = rst_n;
//----------------------------------------------------------------
// make Connections to uio, ui, uo ports
assign motion_inp = (uio_in[0]);
assign x_target = ui_in[7:4];
assign y_target = ui_in[3:0];
assign uo_out[7:4] = x_pos[3:0];
assign uo_out[3:0] = y_pos[3:0];
// TIE OFF Unused uio ports
assign uio_oe = 8'b0;
assign uio_out = 8'b0;
//----------------------------------------------------------------
// module instantiation
// Input Synchronizer
input_synch buttons
(.clk (clock), .reset(!reset_n), .sync_reset(sync_reset), .sync_in(motion_inp), .sync_out (sync_motion));
//FSM:
Mealy_SM xycontroller
(.clk(clock), .reset(!reset_n | sync_reset), .motion(sync_motion), .init(init_regs),
.x_comp_eq(x_comp_eq), .x_comp_gt(x_comp_gt), .x_comp_lt(x_comp_lt), .x_count_en(x_counten), .x_up1_dwn0(x_count_up1_dwn0),
.y_comp_eq(y_comp_eq), .y_comp_gt(y_comp_gt), .y_comp_lt(y_comp_lt), .y_count_en(y_counten), .y_up1_dwn0(y_count_up1_dwn0),
.capt_enbl(load_xy));
//X, Y Target Capture Registers
target_reg x_treg (.clk (clock), .load (load_xy), .data (x_target), .reset ((sync_reset | init_regs)), .target_reg (x_target_reg));
target_reg y_treg (.clk (clock), .load (load_xy), .data (y_target), .reset ((sync_reset | init_regs)), .target_reg (y_target_reg));
//X, Y Counters:
ud_counter x_counter (.clk (clock), .count_en (x_counten), .count_up1_dwn0 (x_count_up1_dwn0), .reset ((sync_reset | init_regs)), .count (x_pos[3:0]));
ud_counter y_counter (.clk (clock), .count_en (y_counten), .count_up1_dwn0 (y_count_up1_dwn0), .reset ((sync_reset | init_regs)), .count (y_pos[3:0]));
// X, Y Comparators
Compx4 x_comp (.a_hex(x_pos), .b_hex(x_target_reg), .a_eq_b(x_comp_eq), .a_gt_b(x_comp_gt), .a_lt_b(x_comp_lt));
Compx4 y_comp (.a_hex(y_pos), .b_hex(y_target_reg), .a_eq_b(y_comp_eq), .a_gt_b(y_comp_gt), .a_lt_b(y_comp_lt));
//----------------------------------------------------------------
// temporary connections for diagnostics outputs
//assign x_target_reg_out = x_target_reg;
//assign y_target_reg_out = y_target_reg;
//assign load_xy_out = load_xy;
//assign x_counten_out = x_counten;
//assign x_comp_eq_out = x_comp_eq;
//assign x_comp_gt_out = x_comp_gt;
//assign x_comp_lt_out = x_comp_lt;
//assign x_count_up1_dwn0_out = x_count_up1_dwn0;
//assign y_counten_out = y_counten;
//assign y_comp_eq_out = y_comp_eq;
//assign y_comp_gt_out = y_comp_gt;
//assign y_comp_lt_out = y_comp_lt;
//assign y_count_up1_dwn0_out = y_count_up1_dwn0;
//assign reset_out = sync_reset;
//assign reset_n_out = reset_n;
//assign init_regs_out = init_regs;
//assign motion_out= sync_motion;
endmodule
module Compx1
(
input a,
input b,
output reg aeqb,
output reg agtb,
output reg altb
);
always @(*)
begin
aeqb = (a & b) | ((!(a)) & (!(b)));
agtb = a & (!(b));
altb = (!(a)) & b ;
end
endmodule
module Compx4
(
input [3:0] a_hex,
input [3:0] b_hex,
output reg a_eq_b,
output reg a_gt_b,
output reg a_lt_b
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module Mealy_SM
(
input clk,
input reset,
input motion,
input x_comp_eq,
input x_comp_gt,
input x_comp_lt,
input y_comp_eq,
input y_comp_gt,
input y_comp_lt,
output reg init,
output reg x_count_en,
output reg x_up1_dwn0,
output reg y_count_en,
output reg y_up1_dwn0,
output reg capt_enbl
);
parameter INITIALIZE1 =3'b000,
INITIALIZE2 =3'b001,
AT_REST =3'b010,
CAPTURE_XY =3'b011,
IN_MOTION =3'b100,
XY_REACHED =3'b101;
// RANGE of STATE VALUES (INITIALIZE, AT_REST, CAPTURE_XY, IN_MOTION, XY_REACHED);
reg [2:0] current_state, next_state; // current_state, next_state registers of type STATES
// STATE MACHINE: MEALY Type
//REGISTER SECTION OF STATE MACHINE
always @(posedge clk, posedge reset) // sequential logic to latch the FSM state (FSM REGISTER SECTION)
begin
if (reset==1)
current_state <= INITIALIZE1;
else
current_state <= next_state; // on the rising edge of clock the current state is updated with next state value
end
//TRANSITION SECTION OF STATE MACHINE
always @(*) // logic to determine next state. (FSM TRANSITION SECTION)
begin
case (current_state)
INITIALIZE1:
begin
next_state = INITIALIZE2;
end
INITIALIZE2:
begin
next_state = AT_REST;
end
AT_REST:
begin
if (motion)
next_state = CAPTURE_XY;
else
next_state = AT_REST;
end
CAPTURE_XY:
begin
if (motion)
next_state = CAPTURE_XY; // stay here until MOTION goes off. Then go to IN_MOTION
else
next_state = IN_MOTION;
end
IN_MOTION:
begin
if ((x_comp_eq) & (y_comp_eq))
next_state = XY_REACHED;
else
next_state = IN_MOTION;
end
XY_REACHED:
begin
next_state = AT_REST;
end
default:
next_state = AT_REST;
endcase
end
//DECODER SECTION OF STATE MACHINE
always @(*) // logic to drive MEALY FSM outputs (FSM DECODER SECTION)
begin
if (current_state == INITIALIZE1) // force outside counters to be initialized to zero for first state
begin
init = 1'b1;
x_count_en = 1'b0;
x_up1_dwn0 = 1'b0;
y_count_en = 1'b0;
y_up1_dwn0 = 1'b0;
capt_enbl = 1'b0;
end
else if (current_state == INITIALIZE2) // keep outside counters initialized to zero for another state
begin
init = 1'b0;
x_count_en = 1'b0;
x_up1_dwn0 = 1'b0;
y_count_en = 1'b0;
y_up1_dwn0 = 1'b0;
capt_enbl = 1'b0;
end
else if (current_state == CAPTURE_XY) // motion button has been pressed. activate outside x/y register capture enables
begin
init = 1'b0;
x_count_en = 1'b0;
x_up1_dwn0 = 1'b0;
y_count_en = 1'b0;
y_up1_dwn0 = 1'b0;
capt_enbl = 1'b1;
end
else if (current_state == IN_MOTION) // motion input button release. x/Y motion is now enabled
begin
init = 1'b0;
x_count_en = ((x_comp_gt) | (x_comp_lt));
x_up1_dwn0 = x_comp_lt;
y_count_en = ((y_comp_gt) | (y_comp_lt));
y_up1_dwn0 = y_comp_lt;
capt_enbl = 1'b0;
end
else // default case (used in AT_REST and XY_REACHED states), is to deactivate all FSM outputs.
begin
init = 1'b0;
x_count_en = 1'b0;
x_up1_dwn0 = 1'b0;
y_count_en = 1'b0;
y_up1_dwn0 = 1'b0;
capt_enbl = 1'b0;
end
end
endmodule
module input_synch
(
input wire clk,
input wire reset,
output wire sync_reset,
input wire sync_in,
output wire sync_out
);
reg [1:0] chain0, chain1;
always @ (posedge clk)
begin
chain0[1:0] <= {chain0[0], reset};
chain1[1:0] <= {chain1[0], sync_in};
end
assign sync_reset = (chain0[1]);
assign sync_out = (chain1[1]);
endmodule
module target_reg
(
input wire clk,
input wire load,
input wire [3:0] data,
input wire reset,
output reg [3:0] target_reg
);
// Reset if needed, increment or decrement if counter is not saturated
always @ (posedge clk)
begin
if (reset)
target_reg <= 4'b0000;
else if (load)
target_reg <= data ;
end
endmodule
module ud_counter
(
input wire clk,
input wire count_en,
input wire count_up1_dwn0,
input wire reset,
output reg [3:0] count
);
// Reset if needed, increment or decrement if counter is not saturated
always @ (posedge clk)
begin
if (reset)
count <= 4'b0000;
else if ((count_en & count_up1_dwn0) & (count!= 4'b1111))
count <= count + 4'd0001;
else if ((count_en & (!count_up1_dwn0)) & (count!= 4'b0000))
count <= count - 4'd0001;
end
endmodule
|
module Compx4
(
input [3:0] a_hex,
input [3:0] b_hex,
output reg a_eq_b,
output reg a_gt_b,
output reg a_lt_b
);
wire [3:0] aeqb;
wire [3:0] agtb;
wire [3:0] altb;
// connections to single bit comparators
Compx1 Bit3_COMP(.a(a_hex[3]), .b(b_hex[3]), .aeqb(aeqb[3]), .agtb(agtb[3]), .altb(altb[3]));
Compx1 Bit2_COMP(.a(a_hex[2]), .b(b_hex[2]), .aeqb(aeqb[2]), .agtb(agtb[2]), .altb(altb[2]));
Compx1 Bit1_COMP(.a(a_hex[1]), .b(b_hex[1]), .aeqb(aeqb[1]), .agtb(agtb[1]), .altb(altb[1]));
Compx1 Bit0_COMP(.a(a_hex[0]), .b(b_hex[0]), .aeqb(aeqb[0]), .agtb(agtb[0]), .altb(altb[0]));
always @(*)
begin
a_eq_b = aeqb[3] & aeqb[2] & aeqb[1] & aeqb[0];
a_gt_b = agtb[3] | (aeqb[3] & agtb[2]) | (aeqb[3] & aeqb[2] & agtb[1]) | (aeqb[3] & aeqb[2] & aeqb[1] & agtb[0]);
a_lt_b = altb[3] | (aeqb[3] & altb[2]) | (aeqb[3] & aeqb[2] & altb[1]) | (aeqb[3] & aeqb[2] & aeqb[1] & altb[0]);
end
endmodule
|
tt06-finale_0010
|
tt06-finale
|
CKPope-tt06-verilog-template
|
task_Mealy_SM
|
tt_um_CKPope_top
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
module tt_um_CKPope_top
(
input wire [7:0] ui_in, // Dedicated inputs for X and Y Target coordinates (BCD: 7:4 for X; 3:0 for Y)
output wire [7:0] uo_out, // Dedicated outputs for X Position and Y Position (BCD: 7:4 for X; 3:0 for Y)
input wire [7:0] uio_in, // IOs: Input path for FSM Control MOTION control input plus spares
output wire [7:0] uio_out, // IOs: Output path (not used)
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output) - TIED For UIO BEING INPUTS ONLY
input wire ena, // will go high when the design is enabled
input wire clk, // clock
// ---------------------------------------------------------------
//outputs for simulation diagnostics
// output wire init_regs_out,
// output wire load_xy_out,
// output wire [3:0] x_target_reg_out,
// output wire [3:0] y_target_reg_out,
// output wire x_comp_eq_out, x_comp_gt_out, x_comp_lt_out,
// output wire x_counten_out, x_count_up1_dwn0_out,
// output wire y_comp_eq_out, y_comp_gt_out, y_comp_lt_out,
// output wire y_counten_out, y_count_up1_dwn0_out,
// output wire reset_n_out, reset_out, motion_out,
//-- --------------------------------------------------------------
input wire rst_n // reset_n - low to reset
);// Quartus Prime Verilog Template
//----------------------------------------------------------------
//Local tile signal Inputs
wire clock, sync_reset, reset_n;
//FSM Initialization of external registers
wire init_regs;
//FSM control inputs;
wire motion_inp,sync_motion;
// x-y target data inputs
wire [3:0] x_target;
wire [3:0] y_target;
// x-y target_register signals
wire [3:0] x_target_reg;
wire [3:0] y_target_reg;
wire load_xy;
// x-y counter signals
wire x_counten, x_count_up1_dwn0, y_counten, y_count_up1_dwn0;
wire [3:0] x_pos;
wire [3:0] y_pos;
// X-Y Counter comparator signals
wire x_comp_eq, x_comp_gt, x_comp_lt;
wire y_comp_eq, y_comp_gt, y_comp_lt;
//----------------------------------------------------------------
// make Connections to infrastructure signals. clock can only run when the module is enabled (selected)
assign clock = clk;
assign reset_n = rst_n;
//----------------------------------------------------------------
// make Connections to uio, ui, uo ports
assign motion_inp = (uio_in[0]);
assign x_target = ui_in[7:4];
assign y_target = ui_in[3:0];
assign uo_out[7:4] = x_pos[3:0];
assign uo_out[3:0] = y_pos[3:0];
// TIE OFF Unused uio ports
assign uio_oe = 8'b0;
assign uio_out = 8'b0;
//----------------------------------------------------------------
// module instantiation
// Input Synchronizer
input_synch buttons
(.clk (clock), .reset(!reset_n), .sync_reset(sync_reset), .sync_in(motion_inp), .sync_out (sync_motion));
//FSM:
Mealy_SM xycontroller
(.clk(clock), .reset(!reset_n | sync_reset), .motion(sync_motion), .init(init_regs),
.x_comp_eq(x_comp_eq), .x_comp_gt(x_comp_gt), .x_comp_lt(x_comp_lt), .x_count_en(x_counten), .x_up1_dwn0(x_count_up1_dwn0),
.y_comp_eq(y_comp_eq), .y_comp_gt(y_comp_gt), .y_comp_lt(y_comp_lt), .y_count_en(y_counten), .y_up1_dwn0(y_count_up1_dwn0),
.capt_enbl(load_xy));
//X, Y Target Capture Registers
target_reg x_treg (.clk (clock), .load (load_xy), .data (x_target), .reset ((sync_reset | init_regs)), .target_reg (x_target_reg));
target_reg y_treg (.clk (clock), .load (load_xy), .data (y_target), .reset ((sync_reset | init_regs)), .target_reg (y_target_reg));
//X, Y Counters:
ud_counter x_counter (.clk (clock), .count_en (x_counten), .count_up1_dwn0 (x_count_up1_dwn0), .reset ((sync_reset | init_regs)), .count (x_pos[3:0]));
ud_counter y_counter (.clk (clock), .count_en (y_counten), .count_up1_dwn0 (y_count_up1_dwn0), .reset ((sync_reset | init_regs)), .count (y_pos[3:0]));
// X, Y Comparators
Compx4 x_comp (.a_hex(x_pos), .b_hex(x_target_reg), .a_eq_b(x_comp_eq), .a_gt_b(x_comp_gt), .a_lt_b(x_comp_lt));
Compx4 y_comp (.a_hex(y_pos), .b_hex(y_target_reg), .a_eq_b(y_comp_eq), .a_gt_b(y_comp_gt), .a_lt_b(y_comp_lt));
//----------------------------------------------------------------
// temporary connections for diagnostics outputs
//assign x_target_reg_out = x_target_reg;
//assign y_target_reg_out = y_target_reg;
//assign load_xy_out = load_xy;
//assign x_counten_out = x_counten;
//assign x_comp_eq_out = x_comp_eq;
//assign x_comp_gt_out = x_comp_gt;
//assign x_comp_lt_out = x_comp_lt;
//assign x_count_up1_dwn0_out = x_count_up1_dwn0;
//assign y_counten_out = y_counten;
//assign y_comp_eq_out = y_comp_eq;
//assign y_comp_gt_out = y_comp_gt;
//assign y_comp_lt_out = y_comp_lt;
//assign y_count_up1_dwn0_out = y_count_up1_dwn0;
//assign reset_out = sync_reset;
//assign reset_n_out = reset_n;
//assign init_regs_out = init_regs;
//assign motion_out= sync_motion;
endmodule
module Compx1
(
input a,
input b,
output reg aeqb,
output reg agtb,
output reg altb
);
always @(*)
begin
aeqb = (a & b) | ((!(a)) & (!(b)));
agtb = a & (!(b));
altb = (!(a)) & b ;
end
endmodule
module Compx4
(
input [3:0] a_hex,
input [3:0] b_hex,
output reg a_eq_b,
output reg a_gt_b,
output reg a_lt_b
);
wire [3:0] aeqb;
wire [3:0] agtb;
wire [3:0] altb;
// connections to single bit comparators
Compx1 Bit3_COMP(.a(a_hex[3]), .b(b_hex[3]), .aeqb(aeqb[3]), .agtb(agtb[3]), .altb(altb[3]));
Compx1 Bit2_COMP(.a(a_hex[2]), .b(b_hex[2]), .aeqb(aeqb[2]), .agtb(agtb[2]), .altb(altb[2]));
Compx1 Bit1_COMP(.a(a_hex[1]), .b(b_hex[1]), .aeqb(aeqb[1]), .agtb(agtb[1]), .altb(altb[1]));
Compx1 Bit0_COMP(.a(a_hex[0]), .b(b_hex[0]), .aeqb(aeqb[0]), .agtb(agtb[0]), .altb(altb[0]));
always @(*)
begin
a_eq_b = aeqb[3] & aeqb[2] & aeqb[1] & aeqb[0];
a_gt_b = agtb[3] | (aeqb[3] & agtb[2]) | (aeqb[3] & aeqb[2] & agtb[1]) | (aeqb[3] & aeqb[2] & aeqb[1] & agtb[0]);
a_lt_b = altb[3] | (aeqb[3] & altb[2]) | (aeqb[3] & aeqb[2] & altb[1]) | (aeqb[3] & aeqb[2] & aeqb[1] & altb[0]);
end
endmodule
module Mealy_SM
(
input clk,
input reset,
input motion,
input x_comp_eq,
input x_comp_gt,
input x_comp_lt,
input y_comp_eq,
input y_comp_gt,
input y_comp_lt,
output reg init,
output reg x_count_en,
output reg x_up1_dwn0,
output reg y_count_en,
output reg y_up1_dwn0,
output reg capt_enbl
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module input_synch
(
input wire clk,
input wire reset,
output wire sync_reset,
input wire sync_in,
output wire sync_out
);
reg [1:0] chain0, chain1;
always @ (posedge clk)
begin
chain0[1:0] <= {chain0[0], reset};
chain1[1:0] <= {chain1[0], sync_in};
end
assign sync_reset = (chain0[1]);
assign sync_out = (chain1[1]);
endmodule
module target_reg
(
input wire clk,
input wire load,
input wire [3:0] data,
input wire reset,
output reg [3:0] target_reg
);
// Reset if needed, increment or decrement if counter is not saturated
always @ (posedge clk)
begin
if (reset)
target_reg <= 4'b0000;
else if (load)
target_reg <= data ;
end
endmodule
module ud_counter
(
input wire clk,
input wire count_en,
input wire count_up1_dwn0,
input wire reset,
output reg [3:0] count
);
// Reset if needed, increment or decrement if counter is not saturated
always @ (posedge clk)
begin
if (reset)
count <= 4'b0000;
else if ((count_en & count_up1_dwn0) & (count!= 4'b1111))
count <= count + 4'd0001;
else if ((count_en & (!count_up1_dwn0)) & (count!= 4'b0000))
count <= count - 4'd0001;
end
endmodule
|
module Mealy_SM
(
input clk,
input reset,
input motion,
input x_comp_eq,
input x_comp_gt,
input x_comp_lt,
input y_comp_eq,
input y_comp_gt,
input y_comp_lt,
output reg init,
output reg x_count_en,
output reg x_up1_dwn0,
output reg y_count_en,
output reg y_up1_dwn0,
output reg capt_enbl
);
parameter INITIALIZE1 =3'b000,
INITIALIZE2 =3'b001,
AT_REST =3'b010,
CAPTURE_XY =3'b011,
IN_MOTION =3'b100,
XY_REACHED =3'b101;
// RANGE of STATE VALUES (INITIALIZE, AT_REST, CAPTURE_XY, IN_MOTION, XY_REACHED);
reg [2:0] current_state, next_state; // current_state, next_state registers of type STATES
// STATE MACHINE: MEALY Type
//REGISTER SECTION OF STATE MACHINE
always @(posedge clk, posedge reset) // sequential logic to latch the FSM state (FSM REGISTER SECTION)
begin
if (reset==1)
current_state <= INITIALIZE1;
else
current_state <= next_state; // on the rising edge of clock the current state is updated with next state value
end
//TRANSITION SECTION OF STATE MACHINE
always @(*) // logic to determine next state. (FSM TRANSITION SECTION)
begin
case (current_state)
INITIALIZE1:
begin
next_state = INITIALIZE2;
end
INITIALIZE2:
begin
next_state = AT_REST;
end
AT_REST:
begin
if (motion)
next_state = CAPTURE_XY;
else
next_state = AT_REST;
end
CAPTURE_XY:
begin
if (motion)
next_state = CAPTURE_XY; // stay here until MOTION goes off. Then go to IN_MOTION
else
next_state = IN_MOTION;
end
IN_MOTION:
begin
if ((x_comp_eq) & (y_comp_eq))
next_state = XY_REACHED;
else
next_state = IN_MOTION;
end
XY_REACHED:
begin
next_state = AT_REST;
end
default:
next_state = AT_REST;
endcase
end
//DECODER SECTION OF STATE MACHINE
always @(*) // logic to drive MEALY FSM outputs (FSM DECODER SECTION)
begin
if (current_state == INITIALIZE1) // force outside counters to be initialized to zero for first state
begin
init = 1'b1;
x_count_en = 1'b0;
x_up1_dwn0 = 1'b0;
y_count_en = 1'b0;
y_up1_dwn0 = 1'b0;
capt_enbl = 1'b0;
end
else if (current_state == INITIALIZE2) // keep outside counters initialized to zero for another state
begin
init = 1'b0;
x_count_en = 1'b0;
x_up1_dwn0 = 1'b0;
y_count_en = 1'b0;
y_up1_dwn0 = 1'b0;
capt_enbl = 1'b0;
end
else if (current_state == CAPTURE_XY) // motion button has been pressed. activate outside x/y register capture enables
begin
init = 1'b0;
x_count_en = 1'b0;
x_up1_dwn0 = 1'b0;
y_count_en = 1'b0;
y_up1_dwn0 = 1'b0;
capt_enbl = 1'b1;
end
else if (current_state == IN_MOTION) // motion input button release. x/Y motion is now enabled
begin
init = 1'b0;
x_count_en = ((x_comp_gt) | (x_comp_lt));
x_up1_dwn0 = x_comp_lt;
y_count_en = ((y_comp_gt) | (y_comp_lt));
y_up1_dwn0 = y_comp_lt;
capt_enbl = 1'b0;
end
else // default case (used in AT_REST and XY_REACHED states), is to deactivate all FSM outputs.
begin
init = 1'b0;
x_count_en = 1'b0;
x_up1_dwn0 = 1'b0;
y_count_en = 1'b0;
y_up1_dwn0 = 1'b0;
capt_enbl = 1'b0;
end
end
endmodule
|
tt06-finale_0011
|
tt06-finale
|
CKPope-tt06-verilog-template
|
task_input_synch
|
tt_um_CKPope_top
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
module tt_um_CKPope_top
(
input wire [7:0] ui_in, // Dedicated inputs for X and Y Target coordinates (BCD: 7:4 for X; 3:0 for Y)
output wire [7:0] uo_out, // Dedicated outputs for X Position and Y Position (BCD: 7:4 for X; 3:0 for Y)
input wire [7:0] uio_in, // IOs: Input path for FSM Control MOTION control input plus spares
output wire [7:0] uio_out, // IOs: Output path (not used)
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output) - TIED For UIO BEING INPUTS ONLY
input wire ena, // will go high when the design is enabled
input wire clk, // clock
// ---------------------------------------------------------------
//outputs for simulation diagnostics
// output wire init_regs_out,
// output wire load_xy_out,
// output wire [3:0] x_target_reg_out,
// output wire [3:0] y_target_reg_out,
// output wire x_comp_eq_out, x_comp_gt_out, x_comp_lt_out,
// output wire x_counten_out, x_count_up1_dwn0_out,
// output wire y_comp_eq_out, y_comp_gt_out, y_comp_lt_out,
// output wire y_counten_out, y_count_up1_dwn0_out,
// output wire reset_n_out, reset_out, motion_out,
//-- --------------------------------------------------------------
input wire rst_n // reset_n - low to reset
);// Quartus Prime Verilog Template
//----------------------------------------------------------------
//Local tile signal Inputs
wire clock, sync_reset, reset_n;
//FSM Initialization of external registers
wire init_regs;
//FSM control inputs;
wire motion_inp,sync_motion;
// x-y target data inputs
wire [3:0] x_target;
wire [3:0] y_target;
// x-y target_register signals
wire [3:0] x_target_reg;
wire [3:0] y_target_reg;
wire load_xy;
// x-y counter signals
wire x_counten, x_count_up1_dwn0, y_counten, y_count_up1_dwn0;
wire [3:0] x_pos;
wire [3:0] y_pos;
// X-Y Counter comparator signals
wire x_comp_eq, x_comp_gt, x_comp_lt;
wire y_comp_eq, y_comp_gt, y_comp_lt;
//----------------------------------------------------------------
// make Connections to infrastructure signals. clock can only run when the module is enabled (selected)
assign clock = clk;
assign reset_n = rst_n;
//----------------------------------------------------------------
// make Connections to uio, ui, uo ports
assign motion_inp = (uio_in[0]);
assign x_target = ui_in[7:4];
assign y_target = ui_in[3:0];
assign uo_out[7:4] = x_pos[3:0];
assign uo_out[3:0] = y_pos[3:0];
// TIE OFF Unused uio ports
assign uio_oe = 8'b0;
assign uio_out = 8'b0;
//----------------------------------------------------------------
// module instantiation
// Input Synchronizer
input_synch buttons
(.clk (clock), .reset(!reset_n), .sync_reset(sync_reset), .sync_in(motion_inp), .sync_out (sync_motion));
//FSM:
Mealy_SM xycontroller
(.clk(clock), .reset(!reset_n | sync_reset), .motion(sync_motion), .init(init_regs),
.x_comp_eq(x_comp_eq), .x_comp_gt(x_comp_gt), .x_comp_lt(x_comp_lt), .x_count_en(x_counten), .x_up1_dwn0(x_count_up1_dwn0),
.y_comp_eq(y_comp_eq), .y_comp_gt(y_comp_gt), .y_comp_lt(y_comp_lt), .y_count_en(y_counten), .y_up1_dwn0(y_count_up1_dwn0),
.capt_enbl(load_xy));
//X, Y Target Capture Registers
target_reg x_treg (.clk (clock), .load (load_xy), .data (x_target), .reset ((sync_reset | init_regs)), .target_reg (x_target_reg));
target_reg y_treg (.clk (clock), .load (load_xy), .data (y_target), .reset ((sync_reset | init_regs)), .target_reg (y_target_reg));
//X, Y Counters:
ud_counter x_counter (.clk (clock), .count_en (x_counten), .count_up1_dwn0 (x_count_up1_dwn0), .reset ((sync_reset | init_regs)), .count (x_pos[3:0]));
ud_counter y_counter (.clk (clock), .count_en (y_counten), .count_up1_dwn0 (y_count_up1_dwn0), .reset ((sync_reset | init_regs)), .count (y_pos[3:0]));
// X, Y Comparators
Compx4 x_comp (.a_hex(x_pos), .b_hex(x_target_reg), .a_eq_b(x_comp_eq), .a_gt_b(x_comp_gt), .a_lt_b(x_comp_lt));
Compx4 y_comp (.a_hex(y_pos), .b_hex(y_target_reg), .a_eq_b(y_comp_eq), .a_gt_b(y_comp_gt), .a_lt_b(y_comp_lt));
//----------------------------------------------------------------
// temporary connections for diagnostics outputs
//assign x_target_reg_out = x_target_reg;
//assign y_target_reg_out = y_target_reg;
//assign load_xy_out = load_xy;
//assign x_counten_out = x_counten;
//assign x_comp_eq_out = x_comp_eq;
//assign x_comp_gt_out = x_comp_gt;
//assign x_comp_lt_out = x_comp_lt;
//assign x_count_up1_dwn0_out = x_count_up1_dwn0;
//assign y_counten_out = y_counten;
//assign y_comp_eq_out = y_comp_eq;
//assign y_comp_gt_out = y_comp_gt;
//assign y_comp_lt_out = y_comp_lt;
//assign y_count_up1_dwn0_out = y_count_up1_dwn0;
//assign reset_out = sync_reset;
//assign reset_n_out = reset_n;
//assign init_regs_out = init_regs;
//assign motion_out= sync_motion;
endmodule
module Compx1
(
input a,
input b,
output reg aeqb,
output reg agtb,
output reg altb
);
always @(*)
begin
aeqb = (a & b) | ((!(a)) & (!(b)));
agtb = a & (!(b));
altb = (!(a)) & b ;
end
endmodule
module Compx4
(
input [3:0] a_hex,
input [3:0] b_hex,
output reg a_eq_b,
output reg a_gt_b,
output reg a_lt_b
);
wire [3:0] aeqb;
wire [3:0] agtb;
wire [3:0] altb;
// connections to single bit comparators
Compx1 Bit3_COMP(.a(a_hex[3]), .b(b_hex[3]), .aeqb(aeqb[3]), .agtb(agtb[3]), .altb(altb[3]));
Compx1 Bit2_COMP(.a(a_hex[2]), .b(b_hex[2]), .aeqb(aeqb[2]), .agtb(agtb[2]), .altb(altb[2]));
Compx1 Bit1_COMP(.a(a_hex[1]), .b(b_hex[1]), .aeqb(aeqb[1]), .agtb(agtb[1]), .altb(altb[1]));
Compx1 Bit0_COMP(.a(a_hex[0]), .b(b_hex[0]), .aeqb(aeqb[0]), .agtb(agtb[0]), .altb(altb[0]));
always @(*)
begin
a_eq_b = aeqb[3] & aeqb[2] & aeqb[1] & aeqb[0];
a_gt_b = agtb[3] | (aeqb[3] & agtb[2]) | (aeqb[3] & aeqb[2] & agtb[1]) | (aeqb[3] & aeqb[2] & aeqb[1] & agtb[0]);
a_lt_b = altb[3] | (aeqb[3] & altb[2]) | (aeqb[3] & aeqb[2] & altb[1]) | (aeqb[3] & aeqb[2] & aeqb[1] & altb[0]);
end
endmodule
module Mealy_SM
(
input clk,
input reset,
input motion,
input x_comp_eq,
input x_comp_gt,
input x_comp_lt,
input y_comp_eq,
input y_comp_gt,
input y_comp_lt,
output reg init,
output reg x_count_en,
output reg x_up1_dwn0,
output reg y_count_en,
output reg y_up1_dwn0,
output reg capt_enbl
);
parameter INITIALIZE1 =3'b000,
INITIALIZE2 =3'b001,
AT_REST =3'b010,
CAPTURE_XY =3'b011,
IN_MOTION =3'b100,
XY_REACHED =3'b101;
// RANGE of STATE VALUES (INITIALIZE, AT_REST, CAPTURE_XY, IN_MOTION, XY_REACHED);
reg [2:0] current_state, next_state; // current_state, next_state registers of type STATES
// STATE MACHINE: MEALY Type
//REGISTER SECTION OF STATE MACHINE
always @(posedge clk, posedge reset) // sequential logic to latch the FSM state (FSM REGISTER SECTION)
begin
if (reset==1)
current_state <= INITIALIZE1;
else
current_state <= next_state; // on the rising edge of clock the current state is updated with next state value
end
//TRANSITION SECTION OF STATE MACHINE
always @(*) // logic to determine next state. (FSM TRANSITION SECTION)
begin
case (current_state)
INITIALIZE1:
begin
next_state = INITIALIZE2;
end
INITIALIZE2:
begin
next_state = AT_REST;
end
AT_REST:
begin
if (motion)
next_state = CAPTURE_XY;
else
next_state = AT_REST;
end
CAPTURE_XY:
begin
if (motion)
next_state = CAPTURE_XY; // stay here until MOTION goes off. Then go to IN_MOTION
else
next_state = IN_MOTION;
end
IN_MOTION:
begin
if ((x_comp_eq) & (y_comp_eq))
next_state = XY_REACHED;
else
next_state = IN_MOTION;
end
XY_REACHED:
begin
next_state = AT_REST;
end
default:
next_state = AT_REST;
endcase
end
//DECODER SECTION OF STATE MACHINE
always @(*) // logic to drive MEALY FSM outputs (FSM DECODER SECTION)
begin
if (current_state == INITIALIZE1) // force outside counters to be initialized to zero for first state
begin
init = 1'b1;
x_count_en = 1'b0;
x_up1_dwn0 = 1'b0;
y_count_en = 1'b0;
y_up1_dwn0 = 1'b0;
capt_enbl = 1'b0;
end
else if (current_state == INITIALIZE2) // keep outside counters initialized to zero for another state
begin
init = 1'b0;
x_count_en = 1'b0;
x_up1_dwn0 = 1'b0;
y_count_en = 1'b0;
y_up1_dwn0 = 1'b0;
capt_enbl = 1'b0;
end
else if (current_state == CAPTURE_XY) // motion button has been pressed. activate outside x/y register capture enables
begin
init = 1'b0;
x_count_en = 1'b0;
x_up1_dwn0 = 1'b0;
y_count_en = 1'b0;
y_up1_dwn0 = 1'b0;
capt_enbl = 1'b1;
end
else if (current_state == IN_MOTION) // motion input button release. x/Y motion is now enabled
begin
init = 1'b0;
x_count_en = ((x_comp_gt) | (x_comp_lt));
x_up1_dwn0 = x_comp_lt;
y_count_en = ((y_comp_gt) | (y_comp_lt));
y_up1_dwn0 = y_comp_lt;
capt_enbl = 1'b0;
end
else // default case (used in AT_REST and XY_REACHED states), is to deactivate all FSM outputs.
begin
init = 1'b0;
x_count_en = 1'b0;
x_up1_dwn0 = 1'b0;
y_count_en = 1'b0;
y_up1_dwn0 = 1'b0;
capt_enbl = 1'b0;
end
end
endmodule
module input_synch
(
input wire clk,
input wire reset,
output wire sync_reset,
input wire sync_in,
output wire sync_out
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module target_reg
(
input wire clk,
input wire load,
input wire [3:0] data,
input wire reset,
output reg [3:0] target_reg
);
// Reset if needed, increment or decrement if counter is not saturated
always @ (posedge clk)
begin
if (reset)
target_reg <= 4'b0000;
else if (load)
target_reg <= data ;
end
endmodule
module ud_counter
(
input wire clk,
input wire count_en,
input wire count_up1_dwn0,
input wire reset,
output reg [3:0] count
);
// Reset if needed, increment or decrement if counter is not saturated
always @ (posedge clk)
begin
if (reset)
count <= 4'b0000;
else if ((count_en & count_up1_dwn0) & (count!= 4'b1111))
count <= count + 4'd0001;
else if ((count_en & (!count_up1_dwn0)) & (count!= 4'b0000))
count <= count - 4'd0001;
end
endmodule
|
module input_synch
(
input wire clk,
input wire reset,
output wire sync_reset,
input wire sync_in,
output wire sync_out
);
reg [1:0] chain0, chain1;
always @ (posedge clk)
begin
chain0[1:0] <= {chain0[0], reset};
chain1[1:0] <= {chain1[0], sync_in};
end
assign sync_reset = (chain0[1]);
assign sync_out = (chain1[1]);
endmodule
|
tt06-finale_0012
|
tt06-finale
|
CKPope-tt06-verilog-template
|
task_target_reg
|
tt_um_CKPope_top
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
module tt_um_CKPope_top
(
input wire [7:0] ui_in, // Dedicated inputs for X and Y Target coordinates (BCD: 7:4 for X; 3:0 for Y)
output wire [7:0] uo_out, // Dedicated outputs for X Position and Y Position (BCD: 7:4 for X; 3:0 for Y)
input wire [7:0] uio_in, // IOs: Input path for FSM Control MOTION control input plus spares
output wire [7:0] uio_out, // IOs: Output path (not used)
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output) - TIED For UIO BEING INPUTS ONLY
input wire ena, // will go high when the design is enabled
input wire clk, // clock
// ---------------------------------------------------------------
//outputs for simulation diagnostics
// output wire init_regs_out,
// output wire load_xy_out,
// output wire [3:0] x_target_reg_out,
// output wire [3:0] y_target_reg_out,
// output wire x_comp_eq_out, x_comp_gt_out, x_comp_lt_out,
// output wire x_counten_out, x_count_up1_dwn0_out,
// output wire y_comp_eq_out, y_comp_gt_out, y_comp_lt_out,
// output wire y_counten_out, y_count_up1_dwn0_out,
// output wire reset_n_out, reset_out, motion_out,
//-- --------------------------------------------------------------
input wire rst_n // reset_n - low to reset
);// Quartus Prime Verilog Template
//----------------------------------------------------------------
//Local tile signal Inputs
wire clock, sync_reset, reset_n;
//FSM Initialization of external registers
wire init_regs;
//FSM control inputs;
wire motion_inp,sync_motion;
// x-y target data inputs
wire [3:0] x_target;
wire [3:0] y_target;
// x-y target_register signals
wire [3:0] x_target_reg;
wire [3:0] y_target_reg;
wire load_xy;
// x-y counter signals
wire x_counten, x_count_up1_dwn0, y_counten, y_count_up1_dwn0;
wire [3:0] x_pos;
wire [3:0] y_pos;
// X-Y Counter comparator signals
wire x_comp_eq, x_comp_gt, x_comp_lt;
wire y_comp_eq, y_comp_gt, y_comp_lt;
//----------------------------------------------------------------
// make Connections to infrastructure signals. clock can only run when the module is enabled (selected)
assign clock = clk;
assign reset_n = rst_n;
//----------------------------------------------------------------
// make Connections to uio, ui, uo ports
assign motion_inp = (uio_in[0]);
assign x_target = ui_in[7:4];
assign y_target = ui_in[3:0];
assign uo_out[7:4] = x_pos[3:0];
assign uo_out[3:0] = y_pos[3:0];
// TIE OFF Unused uio ports
assign uio_oe = 8'b0;
assign uio_out = 8'b0;
//----------------------------------------------------------------
// module instantiation
// Input Synchronizer
input_synch buttons
(.clk (clock), .reset(!reset_n), .sync_reset(sync_reset), .sync_in(motion_inp), .sync_out (sync_motion));
//FSM:
Mealy_SM xycontroller
(.clk(clock), .reset(!reset_n | sync_reset), .motion(sync_motion), .init(init_regs),
.x_comp_eq(x_comp_eq), .x_comp_gt(x_comp_gt), .x_comp_lt(x_comp_lt), .x_count_en(x_counten), .x_up1_dwn0(x_count_up1_dwn0),
.y_comp_eq(y_comp_eq), .y_comp_gt(y_comp_gt), .y_comp_lt(y_comp_lt), .y_count_en(y_counten), .y_up1_dwn0(y_count_up1_dwn0),
.capt_enbl(load_xy));
//X, Y Target Capture Registers
target_reg x_treg (.clk (clock), .load (load_xy), .data (x_target), .reset ((sync_reset | init_regs)), .target_reg (x_target_reg));
target_reg y_treg (.clk (clock), .load (load_xy), .data (y_target), .reset ((sync_reset | init_regs)), .target_reg (y_target_reg));
//X, Y Counters:
ud_counter x_counter (.clk (clock), .count_en (x_counten), .count_up1_dwn0 (x_count_up1_dwn0), .reset ((sync_reset | init_regs)), .count (x_pos[3:0]));
ud_counter y_counter (.clk (clock), .count_en (y_counten), .count_up1_dwn0 (y_count_up1_dwn0), .reset ((sync_reset | init_regs)), .count (y_pos[3:0]));
// X, Y Comparators
Compx4 x_comp (.a_hex(x_pos), .b_hex(x_target_reg), .a_eq_b(x_comp_eq), .a_gt_b(x_comp_gt), .a_lt_b(x_comp_lt));
Compx4 y_comp (.a_hex(y_pos), .b_hex(y_target_reg), .a_eq_b(y_comp_eq), .a_gt_b(y_comp_gt), .a_lt_b(y_comp_lt));
//----------------------------------------------------------------
// temporary connections for diagnostics outputs
//assign x_target_reg_out = x_target_reg;
//assign y_target_reg_out = y_target_reg;
//assign load_xy_out = load_xy;
//assign x_counten_out = x_counten;
//assign x_comp_eq_out = x_comp_eq;
//assign x_comp_gt_out = x_comp_gt;
//assign x_comp_lt_out = x_comp_lt;
//assign x_count_up1_dwn0_out = x_count_up1_dwn0;
//assign y_counten_out = y_counten;
//assign y_comp_eq_out = y_comp_eq;
//assign y_comp_gt_out = y_comp_gt;
//assign y_comp_lt_out = y_comp_lt;
//assign y_count_up1_dwn0_out = y_count_up1_dwn0;
//assign reset_out = sync_reset;
//assign reset_n_out = reset_n;
//assign init_regs_out = init_regs;
//assign motion_out= sync_motion;
endmodule
module Compx1
(
input a,
input b,
output reg aeqb,
output reg agtb,
output reg altb
);
always @(*)
begin
aeqb = (a & b) | ((!(a)) & (!(b)));
agtb = a & (!(b));
altb = (!(a)) & b ;
end
endmodule
module Compx4
(
input [3:0] a_hex,
input [3:0] b_hex,
output reg a_eq_b,
output reg a_gt_b,
output reg a_lt_b
);
wire [3:0] aeqb;
wire [3:0] agtb;
wire [3:0] altb;
// connections to single bit comparators
Compx1 Bit3_COMP(.a(a_hex[3]), .b(b_hex[3]), .aeqb(aeqb[3]), .agtb(agtb[3]), .altb(altb[3]));
Compx1 Bit2_COMP(.a(a_hex[2]), .b(b_hex[2]), .aeqb(aeqb[2]), .agtb(agtb[2]), .altb(altb[2]));
Compx1 Bit1_COMP(.a(a_hex[1]), .b(b_hex[1]), .aeqb(aeqb[1]), .agtb(agtb[1]), .altb(altb[1]));
Compx1 Bit0_COMP(.a(a_hex[0]), .b(b_hex[0]), .aeqb(aeqb[0]), .agtb(agtb[0]), .altb(altb[0]));
always @(*)
begin
a_eq_b = aeqb[3] & aeqb[2] & aeqb[1] & aeqb[0];
a_gt_b = agtb[3] | (aeqb[3] & agtb[2]) | (aeqb[3] & aeqb[2] & agtb[1]) | (aeqb[3] & aeqb[2] & aeqb[1] & agtb[0]);
a_lt_b = altb[3] | (aeqb[3] & altb[2]) | (aeqb[3] & aeqb[2] & altb[1]) | (aeqb[3] & aeqb[2] & aeqb[1] & altb[0]);
end
endmodule
module Mealy_SM
(
input clk,
input reset,
input motion,
input x_comp_eq,
input x_comp_gt,
input x_comp_lt,
input y_comp_eq,
input y_comp_gt,
input y_comp_lt,
output reg init,
output reg x_count_en,
output reg x_up1_dwn0,
output reg y_count_en,
output reg y_up1_dwn0,
output reg capt_enbl
);
parameter INITIALIZE1 =3'b000,
INITIALIZE2 =3'b001,
AT_REST =3'b010,
CAPTURE_XY =3'b011,
IN_MOTION =3'b100,
XY_REACHED =3'b101;
// RANGE of STATE VALUES (INITIALIZE, AT_REST, CAPTURE_XY, IN_MOTION, XY_REACHED);
reg [2:0] current_state, next_state; // current_state, next_state registers of type STATES
// STATE MACHINE: MEALY Type
//REGISTER SECTION OF STATE MACHINE
always @(posedge clk, posedge reset) // sequential logic to latch the FSM state (FSM REGISTER SECTION)
begin
if (reset==1)
current_state <= INITIALIZE1;
else
current_state <= next_state; // on the rising edge of clock the current state is updated with next state value
end
//TRANSITION SECTION OF STATE MACHINE
always @(*) // logic to determine next state. (FSM TRANSITION SECTION)
begin
case (current_state)
INITIALIZE1:
begin
next_state = INITIALIZE2;
end
INITIALIZE2:
begin
next_state = AT_REST;
end
AT_REST:
begin
if (motion)
next_state = CAPTURE_XY;
else
next_state = AT_REST;
end
CAPTURE_XY:
begin
if (motion)
next_state = CAPTURE_XY; // stay here until MOTION goes off. Then go to IN_MOTION
else
next_state = IN_MOTION;
end
IN_MOTION:
begin
if ((x_comp_eq) & (y_comp_eq))
next_state = XY_REACHED;
else
next_state = IN_MOTION;
end
XY_REACHED:
begin
next_state = AT_REST;
end
default:
next_state = AT_REST;
endcase
end
//DECODER SECTION OF STATE MACHINE
always @(*) // logic to drive MEALY FSM outputs (FSM DECODER SECTION)
begin
if (current_state == INITIALIZE1) // force outside counters to be initialized to zero for first state
begin
init = 1'b1;
x_count_en = 1'b0;
x_up1_dwn0 = 1'b0;
y_count_en = 1'b0;
y_up1_dwn0 = 1'b0;
capt_enbl = 1'b0;
end
else if (current_state == INITIALIZE2) // keep outside counters initialized to zero for another state
begin
init = 1'b0;
x_count_en = 1'b0;
x_up1_dwn0 = 1'b0;
y_count_en = 1'b0;
y_up1_dwn0 = 1'b0;
capt_enbl = 1'b0;
end
else if (current_state == CAPTURE_XY) // motion button has been pressed. activate outside x/y register capture enables
begin
init = 1'b0;
x_count_en = 1'b0;
x_up1_dwn0 = 1'b0;
y_count_en = 1'b0;
y_up1_dwn0 = 1'b0;
capt_enbl = 1'b1;
end
else if (current_state == IN_MOTION) // motion input button release. x/Y motion is now enabled
begin
init = 1'b0;
x_count_en = ((x_comp_gt) | (x_comp_lt));
x_up1_dwn0 = x_comp_lt;
y_count_en = ((y_comp_gt) | (y_comp_lt));
y_up1_dwn0 = y_comp_lt;
capt_enbl = 1'b0;
end
else // default case (used in AT_REST and XY_REACHED states), is to deactivate all FSM outputs.
begin
init = 1'b0;
x_count_en = 1'b0;
x_up1_dwn0 = 1'b0;
y_count_en = 1'b0;
y_up1_dwn0 = 1'b0;
capt_enbl = 1'b0;
end
end
endmodule
module input_synch
(
input wire clk,
input wire reset,
output wire sync_reset,
input wire sync_in,
output wire sync_out
);
reg [1:0] chain0, chain1;
always @ (posedge clk)
begin
chain0[1:0] <= {chain0[0], reset};
chain1[1:0] <= {chain1[0], sync_in};
end
assign sync_reset = (chain0[1]);
assign sync_out = (chain1[1]);
endmodule
module target_reg
(
input wire clk,
input wire load,
input wire [3:0] data,
input wire reset,
output reg [3:0] target_reg
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module ud_counter
(
input wire clk,
input wire count_en,
input wire count_up1_dwn0,
input wire reset,
output reg [3:0] count
);
// Reset if needed, increment or decrement if counter is not saturated
always @ (posedge clk)
begin
if (reset)
count <= 4'b0000;
else if ((count_en & count_up1_dwn0) & (count!= 4'b1111))
count <= count + 4'd0001;
else if ((count_en & (!count_up1_dwn0)) & (count!= 4'b0000))
count <= count - 4'd0001;
end
endmodule
|
module target_reg
(
input wire clk,
input wire load,
input wire [3:0] data,
input wire reset,
output reg [3:0] target_reg
);
// Reset if needed, increment or decrement if counter is not saturated
always @ (posedge clk)
begin
if (reset)
target_reg <= 4'b0000;
else if (load)
target_reg <= data ;
end
endmodule
|
tt06-finale_0013
|
tt06-finale
|
CKPope-tt06-verilog-template
|
task_ud_counter
|
tt_um_CKPope_top
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
module tt_um_CKPope_top
(
input wire [7:0] ui_in, // Dedicated inputs for X and Y Target coordinates (BCD: 7:4 for X; 3:0 for Y)
output wire [7:0] uo_out, // Dedicated outputs for X Position and Y Position (BCD: 7:4 for X; 3:0 for Y)
input wire [7:0] uio_in, // IOs: Input path for FSM Control MOTION control input plus spares
output wire [7:0] uio_out, // IOs: Output path (not used)
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output) - TIED For UIO BEING INPUTS ONLY
input wire ena, // will go high when the design is enabled
input wire clk, // clock
// ---------------------------------------------------------------
//outputs for simulation diagnostics
// output wire init_regs_out,
// output wire load_xy_out,
// output wire [3:0] x_target_reg_out,
// output wire [3:0] y_target_reg_out,
// output wire x_comp_eq_out, x_comp_gt_out, x_comp_lt_out,
// output wire x_counten_out, x_count_up1_dwn0_out,
// output wire y_comp_eq_out, y_comp_gt_out, y_comp_lt_out,
// output wire y_counten_out, y_count_up1_dwn0_out,
// output wire reset_n_out, reset_out, motion_out,
//-- --------------------------------------------------------------
input wire rst_n // reset_n - low to reset
);// Quartus Prime Verilog Template
//----------------------------------------------------------------
//Local tile signal Inputs
wire clock, sync_reset, reset_n;
//FSM Initialization of external registers
wire init_regs;
//FSM control inputs;
wire motion_inp,sync_motion;
// x-y target data inputs
wire [3:0] x_target;
wire [3:0] y_target;
// x-y target_register signals
wire [3:0] x_target_reg;
wire [3:0] y_target_reg;
wire load_xy;
// x-y counter signals
wire x_counten, x_count_up1_dwn0, y_counten, y_count_up1_dwn0;
wire [3:0] x_pos;
wire [3:0] y_pos;
// X-Y Counter comparator signals
wire x_comp_eq, x_comp_gt, x_comp_lt;
wire y_comp_eq, y_comp_gt, y_comp_lt;
//----------------------------------------------------------------
// make Connections to infrastructure signals. clock can only run when the module is enabled (selected)
assign clock = clk;
assign reset_n = rst_n;
//----------------------------------------------------------------
// make Connections to uio, ui, uo ports
assign motion_inp = (uio_in[0]);
assign x_target = ui_in[7:4];
assign y_target = ui_in[3:0];
assign uo_out[7:4] = x_pos[3:0];
assign uo_out[3:0] = y_pos[3:0];
// TIE OFF Unused uio ports
assign uio_oe = 8'b0;
assign uio_out = 8'b0;
//----------------------------------------------------------------
// module instantiation
// Input Synchronizer
input_synch buttons
(.clk (clock), .reset(!reset_n), .sync_reset(sync_reset), .sync_in(motion_inp), .sync_out (sync_motion));
//FSM:
Mealy_SM xycontroller
(.clk(clock), .reset(!reset_n | sync_reset), .motion(sync_motion), .init(init_regs),
.x_comp_eq(x_comp_eq), .x_comp_gt(x_comp_gt), .x_comp_lt(x_comp_lt), .x_count_en(x_counten), .x_up1_dwn0(x_count_up1_dwn0),
.y_comp_eq(y_comp_eq), .y_comp_gt(y_comp_gt), .y_comp_lt(y_comp_lt), .y_count_en(y_counten), .y_up1_dwn0(y_count_up1_dwn0),
.capt_enbl(load_xy));
//X, Y Target Capture Registers
target_reg x_treg (.clk (clock), .load (load_xy), .data (x_target), .reset ((sync_reset | init_regs)), .target_reg (x_target_reg));
target_reg y_treg (.clk (clock), .load (load_xy), .data (y_target), .reset ((sync_reset | init_regs)), .target_reg (y_target_reg));
//X, Y Counters:
ud_counter x_counter (.clk (clock), .count_en (x_counten), .count_up1_dwn0 (x_count_up1_dwn0), .reset ((sync_reset | init_regs)), .count (x_pos[3:0]));
ud_counter y_counter (.clk (clock), .count_en (y_counten), .count_up1_dwn0 (y_count_up1_dwn0), .reset ((sync_reset | init_regs)), .count (y_pos[3:0]));
// X, Y Comparators
Compx4 x_comp (.a_hex(x_pos), .b_hex(x_target_reg), .a_eq_b(x_comp_eq), .a_gt_b(x_comp_gt), .a_lt_b(x_comp_lt));
Compx4 y_comp (.a_hex(y_pos), .b_hex(y_target_reg), .a_eq_b(y_comp_eq), .a_gt_b(y_comp_gt), .a_lt_b(y_comp_lt));
//----------------------------------------------------------------
// temporary connections for diagnostics outputs
//assign x_target_reg_out = x_target_reg;
//assign y_target_reg_out = y_target_reg;
//assign load_xy_out = load_xy;
//assign x_counten_out = x_counten;
//assign x_comp_eq_out = x_comp_eq;
//assign x_comp_gt_out = x_comp_gt;
//assign x_comp_lt_out = x_comp_lt;
//assign x_count_up1_dwn0_out = x_count_up1_dwn0;
//assign y_counten_out = y_counten;
//assign y_comp_eq_out = y_comp_eq;
//assign y_comp_gt_out = y_comp_gt;
//assign y_comp_lt_out = y_comp_lt;
//assign y_count_up1_dwn0_out = y_count_up1_dwn0;
//assign reset_out = sync_reset;
//assign reset_n_out = reset_n;
//assign init_regs_out = init_regs;
//assign motion_out= sync_motion;
endmodule
module Compx1
(
input a,
input b,
output reg aeqb,
output reg agtb,
output reg altb
);
always @(*)
begin
aeqb = (a & b) | ((!(a)) & (!(b)));
agtb = a & (!(b));
altb = (!(a)) & b ;
end
endmodule
module Compx4
(
input [3:0] a_hex,
input [3:0] b_hex,
output reg a_eq_b,
output reg a_gt_b,
output reg a_lt_b
);
wire [3:0] aeqb;
wire [3:0] agtb;
wire [3:0] altb;
// connections to single bit comparators
Compx1 Bit3_COMP(.a(a_hex[3]), .b(b_hex[3]), .aeqb(aeqb[3]), .agtb(agtb[3]), .altb(altb[3]));
Compx1 Bit2_COMP(.a(a_hex[2]), .b(b_hex[2]), .aeqb(aeqb[2]), .agtb(agtb[2]), .altb(altb[2]));
Compx1 Bit1_COMP(.a(a_hex[1]), .b(b_hex[1]), .aeqb(aeqb[1]), .agtb(agtb[1]), .altb(altb[1]));
Compx1 Bit0_COMP(.a(a_hex[0]), .b(b_hex[0]), .aeqb(aeqb[0]), .agtb(agtb[0]), .altb(altb[0]));
always @(*)
begin
a_eq_b = aeqb[3] & aeqb[2] & aeqb[1] & aeqb[0];
a_gt_b = agtb[3] | (aeqb[3] & agtb[2]) | (aeqb[3] & aeqb[2] & agtb[1]) | (aeqb[3] & aeqb[2] & aeqb[1] & agtb[0]);
a_lt_b = altb[3] | (aeqb[3] & altb[2]) | (aeqb[3] & aeqb[2] & altb[1]) | (aeqb[3] & aeqb[2] & aeqb[1] & altb[0]);
end
endmodule
module Mealy_SM
(
input clk,
input reset,
input motion,
input x_comp_eq,
input x_comp_gt,
input x_comp_lt,
input y_comp_eq,
input y_comp_gt,
input y_comp_lt,
output reg init,
output reg x_count_en,
output reg x_up1_dwn0,
output reg y_count_en,
output reg y_up1_dwn0,
output reg capt_enbl
);
parameter INITIALIZE1 =3'b000,
INITIALIZE2 =3'b001,
AT_REST =3'b010,
CAPTURE_XY =3'b011,
IN_MOTION =3'b100,
XY_REACHED =3'b101;
// RANGE of STATE VALUES (INITIALIZE, AT_REST, CAPTURE_XY, IN_MOTION, XY_REACHED);
reg [2:0] current_state, next_state; // current_state, next_state registers of type STATES
// STATE MACHINE: MEALY Type
//REGISTER SECTION OF STATE MACHINE
always @(posedge clk, posedge reset) // sequential logic to latch the FSM state (FSM REGISTER SECTION)
begin
if (reset==1)
current_state <= INITIALIZE1;
else
current_state <= next_state; // on the rising edge of clock the current state is updated with next state value
end
//TRANSITION SECTION OF STATE MACHINE
always @(*) // logic to determine next state. (FSM TRANSITION SECTION)
begin
case (current_state)
INITIALIZE1:
begin
next_state = INITIALIZE2;
end
INITIALIZE2:
begin
next_state = AT_REST;
end
AT_REST:
begin
if (motion)
next_state = CAPTURE_XY;
else
next_state = AT_REST;
end
CAPTURE_XY:
begin
if (motion)
next_state = CAPTURE_XY; // stay here until MOTION goes off. Then go to IN_MOTION
else
next_state = IN_MOTION;
end
IN_MOTION:
begin
if ((x_comp_eq) & (y_comp_eq))
next_state = XY_REACHED;
else
next_state = IN_MOTION;
end
XY_REACHED:
begin
next_state = AT_REST;
end
default:
next_state = AT_REST;
endcase
end
//DECODER SECTION OF STATE MACHINE
always @(*) // logic to drive MEALY FSM outputs (FSM DECODER SECTION)
begin
if (current_state == INITIALIZE1) // force outside counters to be initialized to zero for first state
begin
init = 1'b1;
x_count_en = 1'b0;
x_up1_dwn0 = 1'b0;
y_count_en = 1'b0;
y_up1_dwn0 = 1'b0;
capt_enbl = 1'b0;
end
else if (current_state == INITIALIZE2) // keep outside counters initialized to zero for another state
begin
init = 1'b0;
x_count_en = 1'b0;
x_up1_dwn0 = 1'b0;
y_count_en = 1'b0;
y_up1_dwn0 = 1'b0;
capt_enbl = 1'b0;
end
else if (current_state == CAPTURE_XY) // motion button has been pressed. activate outside x/y register capture enables
begin
init = 1'b0;
x_count_en = 1'b0;
x_up1_dwn0 = 1'b0;
y_count_en = 1'b0;
y_up1_dwn0 = 1'b0;
capt_enbl = 1'b1;
end
else if (current_state == IN_MOTION) // motion input button release. x/Y motion is now enabled
begin
init = 1'b0;
x_count_en = ((x_comp_gt) | (x_comp_lt));
x_up1_dwn0 = x_comp_lt;
y_count_en = ((y_comp_gt) | (y_comp_lt));
y_up1_dwn0 = y_comp_lt;
capt_enbl = 1'b0;
end
else // default case (used in AT_REST and XY_REACHED states), is to deactivate all FSM outputs.
begin
init = 1'b0;
x_count_en = 1'b0;
x_up1_dwn0 = 1'b0;
y_count_en = 1'b0;
y_up1_dwn0 = 1'b0;
capt_enbl = 1'b0;
end
end
endmodule
module input_synch
(
input wire clk,
input wire reset,
output wire sync_reset,
input wire sync_in,
output wire sync_out
);
reg [1:0] chain0, chain1;
always @ (posedge clk)
begin
chain0[1:0] <= {chain0[0], reset};
chain1[1:0] <= {chain1[0], sync_in};
end
assign sync_reset = (chain0[1]);
assign sync_out = (chain1[1]);
endmodule
module target_reg
(
input wire clk,
input wire load,
input wire [3:0] data,
input wire reset,
output reg [3:0] target_reg
);
// Reset if needed, increment or decrement if counter is not saturated
always @ (posedge clk)
begin
if (reset)
target_reg <= 4'b0000;
else if (load)
target_reg <= data ;
end
endmodule
module ud_counter
(
input wire clk,
input wire count_en,
input wire count_up1_dwn0,
input wire reset,
output reg [3:0] count
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
|
module ud_counter
(
input wire clk,
input wire count_en,
input wire count_up1_dwn0,
input wire reset,
output reg [3:0] count
);
// Reset if needed, increment or decrement if counter is not saturated
always @ (posedge clk)
begin
if (reset)
count <= 4'b0000;
else if ((count_en & count_up1_dwn0) & (count!= 4'b1111))
count <= count + 4'd0001;
else if ((count_en & (!count_up1_dwn0)) & (count!= 4'b0000))
count <= count - 4'd0001;
end
endmodule
|
tt06-finale_0014
|
tt06-finale
|
EduHolg-FDC_chip
|
task_chip
|
tt_um_fdc_chip
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//`include "chip.v"
module tt_um_fdc_chip (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
assign uio_oe = 8'b0;
assign uio_out = 8'b0;
assign uo_out[7:5] = 3'b0;
wire reset = !rst_n; // Consistent use of reset signal
/* verilator lint_off UNUSEDSIGNAL */
wire dummy0 = ena;
wire dummy2 = |uio_in[7:0];
/* verilator lint_on UNUSEDSIGNAL */
chip chip(
.reset(ui_in[3]),
.selec(ui_in[0]),
.clk_ref(ui_in[1]),
.VCO(ui_in[2]),
.out(uo_out[4:0])
);
endmodule
module chip (
input wire reset,selec,clk_ref,VCO,
output wire [4:0] out
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module fdc_sincronico(
input wire VCO, clk, reset,
output reg [4:0] D_out
);
wire [4:0] count, q1, q2;
counter counter_1(.clk(VCO), .reset(reset), .count(count));
register register_1(.clk(clk), .reset(reset), .d(count), .q(q1));
register register_2(.clk(clk), .reset(reset), .d(q1), .q(q2));
always @*
D_out = q1 - q2;
endmodule
module fdc_asincrono #(parameter ref_N = 2, ptat_N = 5)(
input wire reset, FPTAT, FREF,
output wire [ptat_N-1:0] data
);
wire [ptat_N-1:0] data_prev;
wire [ref_N-1:0] ref_data;
assign done = ref_data[ref_N-1];
ripple_counter #(ref_N) REF_COUNT (
.clk(~done&FREF),
.reset(reset),
.count(ref_data)
);
ripple_counter #(ptat_N) PTAT_COUNT (
.clk(~done&FPTAT),
.reset((ref_data == 0) ? 1'b1 : 1'b0),
.count(data_prev)
);
reg_file #(ptat_N) Reg_Data (
.clk(done),
.reset(reset),
.D(data_prev),
.Q(data)
);
endmodule
module demux (
input wire selec,
input wire a,
output wire x,
output wire y
);
assign {x,y} = selec? {a,1'b0}:{1'b0,a};
endmodule
module ripple_counter#(parameter N=8)(
input wire clk, reset,
output wire [N-1:0] count
);
wire qclk[N-1:0];
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : counter_gen
ff_d_fdc dff_instance (
.clk((i == 0) ? clk:qclk[i-1]),
.reset(reset),
.D(count[i]),
.Q(qclk[i]),
.not_Q(count[i])
);
end
endgenerate
endmodule
module reg_file #(parameter N = 5)(
input wire clk, reset,
input wire [N-1:0]D,
output reg [N-1:0]Q
);
always@(posedge clk or posedge reset)
begin
if(reset)
Q <= 0;
else
Q <= D;
end
endmodule
module ff_d_fdc(
input wire clk, reset,
input wire D,
output reg Q,
output wire not_Q
);
always @(posedge clk or posedge reset) begin
if (reset) begin
Q <= 1'b1;
end
else begin
Q <= D;
end
end
assign not_Q = ~Q;
endmodule
module counter(
input wire clk, reset,
output reg [4:0] count
);
always @(posedge clk) begin
if (reset)
count <= 5'd0;
else
count <= count + 1;
end
endmodule
module register(
input wire clk, reset,
input wire [4:0] d,
output reg [4:0] q
);
always @(posedge clk) begin
if (reset)
q <= 5'd0;
else
q <= d;
end
endmodule
|
module chip (
input wire reset,selec,clk_ref,VCO,
output wire [4:0] out
);
wire VCO_S, VCO_A, CLK_S, CLK_A;
wire [4:0] S;
wire [4:0] A;
demux dmx1(
.selec(selec),
.a(VCO),
.x(VCO_S),
.y(VCO_A));
demux dmx2(
.selec(selec),
.a(clk_ref),
.x(CLK_S),
.y(CLK_A));
fdc_sincronico sfdc(
.VCO(VCO_S),
.clk(CLK_S),
.reset(reset),
.D_out(S));
fdc_asincrono asfdc(
.reset(reset),
.FPTAT(VCO_A),
.FREF(CLK_A),
.data(A));
assign out = (selec)? S:A;
endmodule
|
tt06-finale_0015
|
tt06-finale
|
EduHolg-FDC_chip
|
task_counter
|
tt_um_fdc_chip
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//`include "chip.v"
module tt_um_fdc_chip (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
assign uio_oe = 8'b0;
assign uio_out = 8'b0;
assign uo_out[7:5] = 3'b0;
wire reset = !rst_n; // Consistent use of reset signal
/* verilator lint_off UNUSEDSIGNAL */
wire dummy0 = ena;
wire dummy2 = |uio_in[7:0];
/* verilator lint_on UNUSEDSIGNAL */
chip chip(
.reset(ui_in[3]),
.selec(ui_in[0]),
.clk_ref(ui_in[1]),
.VCO(ui_in[2]),
.out(uo_out[4:0])
);
endmodule
module chip (
input wire reset,selec,clk_ref,VCO,
output wire [4:0] out
);
wire VCO_S, VCO_A, CLK_S, CLK_A;
wire [4:0] S;
wire [4:0] A;
demux dmx1(
.selec(selec),
.a(VCO),
.x(VCO_S),
.y(VCO_A));
demux dmx2(
.selec(selec),
.a(clk_ref),
.x(CLK_S),
.y(CLK_A));
fdc_sincronico sfdc(
.VCO(VCO_S),
.clk(CLK_S),
.reset(reset),
.D_out(S));
fdc_asincrono asfdc(
.reset(reset),
.FPTAT(VCO_A),
.FREF(CLK_A),
.data(A));
assign out = (selec)? S:A;
endmodule
module fdc_sincronico(
input wire VCO, clk, reset,
output reg [4:0] D_out
);
wire [4:0] count, q1, q2;
counter counter_1(.clk(VCO), .reset(reset), .count(count));
register register_1(.clk(clk), .reset(reset), .d(count), .q(q1));
register register_2(.clk(clk), .reset(reset), .d(q1), .q(q2));
always @*
D_out = q1 - q2;
endmodule
module fdc_asincrono #(parameter ref_N = 2, ptat_N = 5)(
input wire reset, FPTAT, FREF,
output wire [ptat_N-1:0] data
);
wire [ptat_N-1:0] data_prev;
wire [ref_N-1:0] ref_data;
assign done = ref_data[ref_N-1];
ripple_counter #(ref_N) REF_COUNT (
.clk(~done&FREF),
.reset(reset),
.count(ref_data)
);
ripple_counter #(ptat_N) PTAT_COUNT (
.clk(~done&FPTAT),
.reset((ref_data == 0) ? 1'b1 : 1'b0),
.count(data_prev)
);
reg_file #(ptat_N) Reg_Data (
.clk(done),
.reset(reset),
.D(data_prev),
.Q(data)
);
endmodule
module demux (
input wire selec,
input wire a,
output wire x,
output wire y
);
assign {x,y} = selec? {a,1'b0}:{1'b0,a};
endmodule
module ripple_counter#(parameter N=8)(
input wire clk, reset,
output wire [N-1:0] count
);
wire qclk[N-1:0];
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : counter_gen
ff_d_fdc dff_instance (
.clk((i == 0) ? clk:qclk[i-1]),
.reset(reset),
.D(count[i]),
.Q(qclk[i]),
.not_Q(count[i])
);
end
endgenerate
endmodule
module reg_file #(parameter N = 5)(
input wire clk, reset,
input wire [N-1:0]D,
output reg [N-1:0]Q
);
always@(posedge clk or posedge reset)
begin
if(reset)
Q <= 0;
else
Q <= D;
end
endmodule
module ff_d_fdc(
input wire clk, reset,
input wire D,
output reg Q,
output wire not_Q
);
always @(posedge clk or posedge reset) begin
if (reset) begin
Q <= 1'b1;
end
else begin
Q <= D;
end
end
assign not_Q = ~Q;
endmodule
module counter(
input wire clk, reset,
output reg [4:0] count
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module register(
input wire clk, reset,
input wire [4:0] d,
output reg [4:0] q
);
always @(posedge clk) begin
if (reset)
q <= 5'd0;
else
q <= d;
end
endmodule
|
module counter(
input wire clk, reset,
output reg [4:0] count
);
always @(posedge clk) begin
if (reset)
count <= 5'd0;
else
count <= count + 1;
end
endmodule
|
tt06-finale_0016
|
tt06-finale
|
EduHolg-FDC_chip
|
task_demux
|
tt_um_fdc_chip
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//`include "chip.v"
module tt_um_fdc_chip (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
assign uio_oe = 8'b0;
assign uio_out = 8'b0;
assign uo_out[7:5] = 3'b0;
wire reset = !rst_n; // Consistent use of reset signal
/* verilator lint_off UNUSEDSIGNAL */
wire dummy0 = ena;
wire dummy2 = |uio_in[7:0];
/* verilator lint_on UNUSEDSIGNAL */
chip chip(
.reset(ui_in[3]),
.selec(ui_in[0]),
.clk_ref(ui_in[1]),
.VCO(ui_in[2]),
.out(uo_out[4:0])
);
endmodule
module chip (
input wire reset,selec,clk_ref,VCO,
output wire [4:0] out
);
wire VCO_S, VCO_A, CLK_S, CLK_A;
wire [4:0] S;
wire [4:0] A;
demux dmx1(
.selec(selec),
.a(VCO),
.x(VCO_S),
.y(VCO_A));
demux dmx2(
.selec(selec),
.a(clk_ref),
.x(CLK_S),
.y(CLK_A));
fdc_sincronico sfdc(
.VCO(VCO_S),
.clk(CLK_S),
.reset(reset),
.D_out(S));
fdc_asincrono asfdc(
.reset(reset),
.FPTAT(VCO_A),
.FREF(CLK_A),
.data(A));
assign out = (selec)? S:A;
endmodule
module fdc_sincronico(
input wire VCO, clk, reset,
output reg [4:0] D_out
);
wire [4:0] count, q1, q2;
counter counter_1(.clk(VCO), .reset(reset), .count(count));
register register_1(.clk(clk), .reset(reset), .d(count), .q(q1));
register register_2(.clk(clk), .reset(reset), .d(q1), .q(q2));
always @*
D_out = q1 - q2;
endmodule
module fdc_asincrono #(parameter ref_N = 2, ptat_N = 5)(
input wire reset, FPTAT, FREF,
output wire [ptat_N-1:0] data
);
wire [ptat_N-1:0] data_prev;
wire [ref_N-1:0] ref_data;
assign done = ref_data[ref_N-1];
ripple_counter #(ref_N) REF_COUNT (
.clk(~done&FREF),
.reset(reset),
.count(ref_data)
);
ripple_counter #(ptat_N) PTAT_COUNT (
.clk(~done&FPTAT),
.reset((ref_data == 0) ? 1'b1 : 1'b0),
.count(data_prev)
);
reg_file #(ptat_N) Reg_Data (
.clk(done),
.reset(reset),
.D(data_prev),
.Q(data)
);
endmodule
module demux (
input wire selec,
input wire a,
output wire x,
output wire y
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module ripple_counter#(parameter N=8)(
input wire clk, reset,
output wire [N-1:0] count
);
wire qclk[N-1:0];
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : counter_gen
ff_d_fdc dff_instance (
.clk((i == 0) ? clk:qclk[i-1]),
.reset(reset),
.D(count[i]),
.Q(qclk[i]),
.not_Q(count[i])
);
end
endgenerate
endmodule
module reg_file #(parameter N = 5)(
input wire clk, reset,
input wire [N-1:0]D,
output reg [N-1:0]Q
);
always@(posedge clk or posedge reset)
begin
if(reset)
Q <= 0;
else
Q <= D;
end
endmodule
module ff_d_fdc(
input wire clk, reset,
input wire D,
output reg Q,
output wire not_Q
);
always @(posedge clk or posedge reset) begin
if (reset) begin
Q <= 1'b1;
end
else begin
Q <= D;
end
end
assign not_Q = ~Q;
endmodule
module counter(
input wire clk, reset,
output reg [4:0] count
);
always @(posedge clk) begin
if (reset)
count <= 5'd0;
else
count <= count + 1;
end
endmodule
module register(
input wire clk, reset,
input wire [4:0] d,
output reg [4:0] q
);
always @(posedge clk) begin
if (reset)
q <= 5'd0;
else
q <= d;
end
endmodule
|
module demux (
input wire selec,
input wire a,
output wire x,
output wire y
);
assign {x,y} = selec? {a,1'b0}:{1'b0,a};
endmodule
|
tt06-finale_0017
|
tt06-finale
|
EduHolg-FDC_chip
|
task_fdc_sincronico
|
tt_um_fdc_chip
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//`include "chip.v"
module tt_um_fdc_chip (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
assign uio_oe = 8'b0;
assign uio_out = 8'b0;
assign uo_out[7:5] = 3'b0;
wire reset = !rst_n; // Consistent use of reset signal
/* verilator lint_off UNUSEDSIGNAL */
wire dummy0 = ena;
wire dummy2 = |uio_in[7:0];
/* verilator lint_on UNUSEDSIGNAL */
chip chip(
.reset(ui_in[3]),
.selec(ui_in[0]),
.clk_ref(ui_in[1]),
.VCO(ui_in[2]),
.out(uo_out[4:0])
);
endmodule
module chip (
input wire reset,selec,clk_ref,VCO,
output wire [4:0] out
);
wire VCO_S, VCO_A, CLK_S, CLK_A;
wire [4:0] S;
wire [4:0] A;
demux dmx1(
.selec(selec),
.a(VCO),
.x(VCO_S),
.y(VCO_A));
demux dmx2(
.selec(selec),
.a(clk_ref),
.x(CLK_S),
.y(CLK_A));
fdc_sincronico sfdc(
.VCO(VCO_S),
.clk(CLK_S),
.reset(reset),
.D_out(S));
fdc_asincrono asfdc(
.reset(reset),
.FPTAT(VCO_A),
.FREF(CLK_A),
.data(A));
assign out = (selec)? S:A;
endmodule
module fdc_sincronico(
input wire VCO, clk, reset,
output reg [4:0] D_out
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module fdc_asincrono #(parameter ref_N = 2, ptat_N = 5)(
input wire reset, FPTAT, FREF,
output wire [ptat_N-1:0] data
);
wire [ptat_N-1:0] data_prev;
wire [ref_N-1:0] ref_data;
assign done = ref_data[ref_N-1];
ripple_counter #(ref_N) REF_COUNT (
.clk(~done&FREF),
.reset(reset),
.count(ref_data)
);
ripple_counter #(ptat_N) PTAT_COUNT (
.clk(~done&FPTAT),
.reset((ref_data == 0) ? 1'b1 : 1'b0),
.count(data_prev)
);
reg_file #(ptat_N) Reg_Data (
.clk(done),
.reset(reset),
.D(data_prev),
.Q(data)
);
endmodule
module demux (
input wire selec,
input wire a,
output wire x,
output wire y
);
assign {x,y} = selec? {a,1'b0}:{1'b0,a};
endmodule
module ripple_counter#(parameter N=8)(
input wire clk, reset,
output wire [N-1:0] count
);
wire qclk[N-1:0];
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : counter_gen
ff_d_fdc dff_instance (
.clk((i == 0) ? clk:qclk[i-1]),
.reset(reset),
.D(count[i]),
.Q(qclk[i]),
.not_Q(count[i])
);
end
endgenerate
endmodule
module reg_file #(parameter N = 5)(
input wire clk, reset,
input wire [N-1:0]D,
output reg [N-1:0]Q
);
always@(posedge clk or posedge reset)
begin
if(reset)
Q <= 0;
else
Q <= D;
end
endmodule
module ff_d_fdc(
input wire clk, reset,
input wire D,
output reg Q,
output wire not_Q
);
always @(posedge clk or posedge reset) begin
if (reset) begin
Q <= 1'b1;
end
else begin
Q <= D;
end
end
assign not_Q = ~Q;
endmodule
module counter(
input wire clk, reset,
output reg [4:0] count
);
always @(posedge clk) begin
if (reset)
count <= 5'd0;
else
count <= count + 1;
end
endmodule
module register(
input wire clk, reset,
input wire [4:0] d,
output reg [4:0] q
);
always @(posedge clk) begin
if (reset)
q <= 5'd0;
else
q <= d;
end
endmodule
|
module fdc_sincronico(
input wire VCO, clk, reset,
output reg [4:0] D_out
);
wire [4:0] count, q1, q2;
counter counter_1(.clk(VCO), .reset(reset), .count(count));
register register_1(.clk(clk), .reset(reset), .d(count), .q(q1));
register register_2(.clk(clk), .reset(reset), .d(q1), .q(q2));
always @*
D_out = q1 - q2;
endmodule
|
tt06-finale_0018
|
tt06-finale
|
EduHolg-FDC_chip
|
task_ff_d_fdc
|
tt_um_fdc_chip
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//`include "chip.v"
module tt_um_fdc_chip (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
assign uio_oe = 8'b0;
assign uio_out = 8'b0;
assign uo_out[7:5] = 3'b0;
wire reset = !rst_n; // Consistent use of reset signal
/* verilator lint_off UNUSEDSIGNAL */
wire dummy0 = ena;
wire dummy2 = |uio_in[7:0];
/* verilator lint_on UNUSEDSIGNAL */
chip chip(
.reset(ui_in[3]),
.selec(ui_in[0]),
.clk_ref(ui_in[1]),
.VCO(ui_in[2]),
.out(uo_out[4:0])
);
endmodule
module chip (
input wire reset,selec,clk_ref,VCO,
output wire [4:0] out
);
wire VCO_S, VCO_A, CLK_S, CLK_A;
wire [4:0] S;
wire [4:0] A;
demux dmx1(
.selec(selec),
.a(VCO),
.x(VCO_S),
.y(VCO_A));
demux dmx2(
.selec(selec),
.a(clk_ref),
.x(CLK_S),
.y(CLK_A));
fdc_sincronico sfdc(
.VCO(VCO_S),
.clk(CLK_S),
.reset(reset),
.D_out(S));
fdc_asincrono asfdc(
.reset(reset),
.FPTAT(VCO_A),
.FREF(CLK_A),
.data(A));
assign out = (selec)? S:A;
endmodule
module fdc_sincronico(
input wire VCO, clk, reset,
output reg [4:0] D_out
);
wire [4:0] count, q1, q2;
counter counter_1(.clk(VCO), .reset(reset), .count(count));
register register_1(.clk(clk), .reset(reset), .d(count), .q(q1));
register register_2(.clk(clk), .reset(reset), .d(q1), .q(q2));
always @*
D_out = q1 - q2;
endmodule
module fdc_asincrono #(parameter ref_N = 2, ptat_N = 5)(
input wire reset, FPTAT, FREF,
output wire [ptat_N-1:0] data
);
wire [ptat_N-1:0] data_prev;
wire [ref_N-1:0] ref_data;
assign done = ref_data[ref_N-1];
ripple_counter #(ref_N) REF_COUNT (
.clk(~done&FREF),
.reset(reset),
.count(ref_data)
);
ripple_counter #(ptat_N) PTAT_COUNT (
.clk(~done&FPTAT),
.reset((ref_data == 0) ? 1'b1 : 1'b0),
.count(data_prev)
);
reg_file #(ptat_N) Reg_Data (
.clk(done),
.reset(reset),
.D(data_prev),
.Q(data)
);
endmodule
module demux (
input wire selec,
input wire a,
output wire x,
output wire y
);
assign {x,y} = selec? {a,1'b0}:{1'b0,a};
endmodule
module ripple_counter#(parameter N=8)(
input wire clk, reset,
output wire [N-1:0] count
);
wire qclk[N-1:0];
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : counter_gen
ff_d_fdc dff_instance (
.clk((i == 0) ? clk:qclk[i-1]),
.reset(reset),
.D(count[i]),
.Q(qclk[i]),
.not_Q(count[i])
);
end
endgenerate
endmodule
module reg_file #(parameter N = 5)(
input wire clk, reset,
input wire [N-1:0]D,
output reg [N-1:0]Q
);
always@(posedge clk or posedge reset)
begin
if(reset)
Q <= 0;
else
Q <= D;
end
endmodule
module ff_d_fdc(
input wire clk, reset,
input wire D,
output reg Q,
output wire not_Q
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module counter(
input wire clk, reset,
output reg [4:0] count
);
always @(posedge clk) begin
if (reset)
count <= 5'd0;
else
count <= count + 1;
end
endmodule
module register(
input wire clk, reset,
input wire [4:0] d,
output reg [4:0] q
);
always @(posedge clk) begin
if (reset)
q <= 5'd0;
else
q <= d;
end
endmodule
|
module ff_d_fdc(
input wire clk, reset,
input wire D,
output reg Q,
output wire not_Q
);
always @(posedge clk or posedge reset) begin
if (reset) begin
Q <= 1'b1;
end
else begin
Q <= D;
end
end
assign not_Q = ~Q;
endmodule
|
tt06-finale_0019
|
tt06-finale
|
EduHolg-FDC_chip
|
task_register
|
tt_um_fdc_chip
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//`include "chip.v"
module tt_um_fdc_chip (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
assign uio_oe = 8'b0;
assign uio_out = 8'b0;
assign uo_out[7:5] = 3'b0;
wire reset = !rst_n; // Consistent use of reset signal
/* verilator lint_off UNUSEDSIGNAL */
wire dummy0 = ena;
wire dummy2 = |uio_in[7:0];
/* verilator lint_on UNUSEDSIGNAL */
chip chip(
.reset(ui_in[3]),
.selec(ui_in[0]),
.clk_ref(ui_in[1]),
.VCO(ui_in[2]),
.out(uo_out[4:0])
);
endmodule
module chip (
input wire reset,selec,clk_ref,VCO,
output wire [4:0] out
);
wire VCO_S, VCO_A, CLK_S, CLK_A;
wire [4:0] S;
wire [4:0] A;
demux dmx1(
.selec(selec),
.a(VCO),
.x(VCO_S),
.y(VCO_A));
demux dmx2(
.selec(selec),
.a(clk_ref),
.x(CLK_S),
.y(CLK_A));
fdc_sincronico sfdc(
.VCO(VCO_S),
.clk(CLK_S),
.reset(reset),
.D_out(S));
fdc_asincrono asfdc(
.reset(reset),
.FPTAT(VCO_A),
.FREF(CLK_A),
.data(A));
assign out = (selec)? S:A;
endmodule
module fdc_sincronico(
input wire VCO, clk, reset,
output reg [4:0] D_out
);
wire [4:0] count, q1, q2;
counter counter_1(.clk(VCO), .reset(reset), .count(count));
register register_1(.clk(clk), .reset(reset), .d(count), .q(q1));
register register_2(.clk(clk), .reset(reset), .d(q1), .q(q2));
always @*
D_out = q1 - q2;
endmodule
module fdc_asincrono #(parameter ref_N = 2, ptat_N = 5)(
input wire reset, FPTAT, FREF,
output wire [ptat_N-1:0] data
);
wire [ptat_N-1:0] data_prev;
wire [ref_N-1:0] ref_data;
assign done = ref_data[ref_N-1];
ripple_counter #(ref_N) REF_COUNT (
.clk(~done&FREF),
.reset(reset),
.count(ref_data)
);
ripple_counter #(ptat_N) PTAT_COUNT (
.clk(~done&FPTAT),
.reset((ref_data == 0) ? 1'b1 : 1'b0),
.count(data_prev)
);
reg_file #(ptat_N) Reg_Data (
.clk(done),
.reset(reset),
.D(data_prev),
.Q(data)
);
endmodule
module demux (
input wire selec,
input wire a,
output wire x,
output wire y
);
assign {x,y} = selec? {a,1'b0}:{1'b0,a};
endmodule
module ripple_counter#(parameter N=8)(
input wire clk, reset,
output wire [N-1:0] count
);
wire qclk[N-1:0];
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : counter_gen
ff_d_fdc dff_instance (
.clk((i == 0) ? clk:qclk[i-1]),
.reset(reset),
.D(count[i]),
.Q(qclk[i]),
.not_Q(count[i])
);
end
endgenerate
endmodule
module reg_file #(parameter N = 5)(
input wire clk, reset,
input wire [N-1:0]D,
output reg [N-1:0]Q
);
always@(posedge clk or posedge reset)
begin
if(reset)
Q <= 0;
else
Q <= D;
end
endmodule
module ff_d_fdc(
input wire clk, reset,
input wire D,
output reg Q,
output wire not_Q
);
always @(posedge clk or posedge reset) begin
if (reset) begin
Q <= 1'b1;
end
else begin
Q <= D;
end
end
assign not_Q = ~Q;
endmodule
module counter(
input wire clk, reset,
output reg [4:0] count
);
always @(posedge clk) begin
if (reset)
count <= 5'd0;
else
count <= count + 1;
end
endmodule
module register(
input wire clk, reset,
input wire [4:0] d,
output reg [4:0] q
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
|
module register(
input wire clk, reset,
input wire [4:0] d,
output reg [4:0] q
);
always @(posedge clk) begin
if (reset)
q <= 5'd0;
else
q <= d;
end
endmodule
|
tt06-finale_0020
|
tt06-finale
|
EduHolg-FDC_chip
|
task_tt_um_fdc_chip
|
tt_um_fdc_chip
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//`include "chip.v"
module tt_um_fdc_chip (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module chip (
input wire reset,selec,clk_ref,VCO,
output wire [4:0] out
);
wire VCO_S, VCO_A, CLK_S, CLK_A;
wire [4:0] S;
wire [4:0] A;
demux dmx1(
.selec(selec),
.a(VCO),
.x(VCO_S),
.y(VCO_A));
demux dmx2(
.selec(selec),
.a(clk_ref),
.x(CLK_S),
.y(CLK_A));
fdc_sincronico sfdc(
.VCO(VCO_S),
.clk(CLK_S),
.reset(reset),
.D_out(S));
fdc_asincrono asfdc(
.reset(reset),
.FPTAT(VCO_A),
.FREF(CLK_A),
.data(A));
assign out = (selec)? S:A;
endmodule
module fdc_sincronico(
input wire VCO, clk, reset,
output reg [4:0] D_out
);
wire [4:0] count, q1, q2;
counter counter_1(.clk(VCO), .reset(reset), .count(count));
register register_1(.clk(clk), .reset(reset), .d(count), .q(q1));
register register_2(.clk(clk), .reset(reset), .d(q1), .q(q2));
always @*
D_out = q1 - q2;
endmodule
module fdc_asincrono #(parameter ref_N = 2, ptat_N = 5)(
input wire reset, FPTAT, FREF,
output wire [ptat_N-1:0] data
);
wire [ptat_N-1:0] data_prev;
wire [ref_N-1:0] ref_data;
assign done = ref_data[ref_N-1];
ripple_counter #(ref_N) REF_COUNT (
.clk(~done&FREF),
.reset(reset),
.count(ref_data)
);
ripple_counter #(ptat_N) PTAT_COUNT (
.clk(~done&FPTAT),
.reset((ref_data == 0) ? 1'b1 : 1'b0),
.count(data_prev)
);
reg_file #(ptat_N) Reg_Data (
.clk(done),
.reset(reset),
.D(data_prev),
.Q(data)
);
endmodule
module demux (
input wire selec,
input wire a,
output wire x,
output wire y
);
assign {x,y} = selec? {a,1'b0}:{1'b0,a};
endmodule
module ripple_counter#(parameter N=8)(
input wire clk, reset,
output wire [N-1:0] count
);
wire qclk[N-1:0];
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : counter_gen
ff_d_fdc dff_instance (
.clk((i == 0) ? clk:qclk[i-1]),
.reset(reset),
.D(count[i]),
.Q(qclk[i]),
.not_Q(count[i])
);
end
endgenerate
endmodule
module reg_file #(parameter N = 5)(
input wire clk, reset,
input wire [N-1:0]D,
output reg [N-1:0]Q
);
always@(posedge clk or posedge reset)
begin
if(reset)
Q <= 0;
else
Q <= D;
end
endmodule
module ff_d_fdc(
input wire clk, reset,
input wire D,
output reg Q,
output wire not_Q
);
always @(posedge clk or posedge reset) begin
if (reset) begin
Q <= 1'b1;
end
else begin
Q <= D;
end
end
assign not_Q = ~Q;
endmodule
module counter(
input wire clk, reset,
output reg [4:0] count
);
always @(posedge clk) begin
if (reset)
count <= 5'd0;
else
count <= count + 1;
end
endmodule
module register(
input wire clk, reset,
input wire [4:0] d,
output reg [4:0] q
);
always @(posedge clk) begin
if (reset)
q <= 5'd0;
else
q <= d;
end
endmodule
|
module tt_um_fdc_chip (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
assign uio_oe = 8'b0;
assign uio_out = 8'b0;
assign uo_out[7:5] = 3'b0;
wire reset = !rst_n; // Consistent use of reset signal
/* verilator lint_off UNUSEDSIGNAL */
wire dummy0 = ena;
wire dummy2 = |uio_in[7:0];
/* verilator lint_on UNUSEDSIGNAL */
chip chip(
.reset(ui_in[3]),
.selec(ui_in[0]),
.clk_ref(ui_in[1]),
.VCO(ui_in[2]),
.out(uo_out[4:0])
);
endmodule
|
tt06-finale_0021
|
tt06-finale
|
Fountaincoder-multimac
|
task_DMADD
|
tt_um_fountaincoder_top
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Jonny Edwards
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_fountaincoder_top (
input wire clk, // clock
input wire ena, // will go high when the design is enabled
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
assign uio_out[3:0] = 4'b0;
/* verilator lint_off UNUSED */
wire [3:0] dummy1 = uio_in[7:4];
wire dummy2 = ena;
assign uio_oe = 8'b11110000;
//assign all the loose ports
wire [7:0] out;
wire [3:0] out_top;
assign uo_out = out;
assign uio_out[7:4] = out_top;
DMADD madd(
.clk (clk),
.run (uio_in[3]),
.load (uio_in[2]),
.insn (uio_in[1:0]),
.index (ui_in[7:4]),
.data (ui_in[3:0]),
.out (out),
.out_top (out_top),
.rst_n (rst_n)
);
endmodule
/*
* Copyright (c) 2024 Jonny Edwards
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module DMADD(
input wire clk,
input wire rst_n, // reset_n - low to reset
input wire [3:0] index,
input wire [3:0] data,
input wire [1:0] insn,
input wire load,
input wire run,
output [7:0] out,
output [3:0] out_top
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
|
module DMADD(
input wire clk,
input wire rst_n, // reset_n - low to reset
input wire [3:0] index,
input wire [3:0] data,
input wire [1:0] insn,
input wire load,
input wire run,
output [7:0] out,
output [3:0] out_top
);
reg [4:0] j; //j=0 ;
reg [3:0] i; // i = 4'b1111;
reg signed [3:0] i_d;
reg [3:0] i_e;// = 4'b0;
reg signed [5:0] mem[15:0];
reg bad_pattern;// = 0;
reg signed [5:0] delta;// =6'b0;
reg [7:0] count;// = 8'b0;
reg [9:0] total;// = 10'b0;
reg [11:0] out_reg;// = 0;
reg set; // = 0;
always @(posedge clk) begin
casez ({rst_n, run,load,insn})
//Reset
5'b0_?_?_??: begin out_reg<=0; set<=0; i<= 4'b1111; i_d<= 1; i_e<=4'b0; delta<=6'b0; count<=8'b0;total<=10'b0; bad_pattern<=0; for (j=0;j<16;j=j+1) begin mem[j]<=0; end end
//Initialise
5'b1_0_0_00: begin i<= 4'b0; i_e <= 4'b1111; end // Initialise MIN
5'b1_0_0_01: begin i<= 4'b1111; i_e <= 4'b0; end // Initialise MAX
5'b1_0_1_00,
5'b1_0_1_01: mem[index] <= 6'b1; // Load Data MIN
5'b1_0_1_10: {mem[index], mem[index-1]} <= {mem[index] + {2'b0,data}, mem[index-1] - {2'b0,data}} ; //MADD
5'b1_1_0_00: i <= i + i_d; // Run MIN
5'b1_1_0_01: i <= i - i_d; // Run MAX
5'b1_1_0_10: begin i <= i - i_d; delta <= delta + mem[i-1]; count <= count+{2'b0,delta}; total <= total + {2'b0,count}; end //MADD
default: bad_pattern <= 1;
endcase
if (i == i_e && insn[1]==1) begin
out_reg <= {2'b0,total} + {4'b0,count};
i_d <= 0 ;
end
if ((mem[i] != 6'b0) && !set && insn[1]!=1) begin
out_reg <= {8'b0,i};
i_d <= 0;
set <= 1;
end
// $display("%d r %d run %d load %d isn %d bad %d i_d %d i_e %d index %d data %d out_reg %d", i ,rst_n, run, load,insn, bad_pattern,i_d,i_e, index, data,out);
// $display("d %d c %d t %d m %d",delta,count,total,mem[i]);
end
assign out = out_reg[7:0];
//assign out_top = out_reg[11:8];
assign out_top = i_d;
endmodule
|
tt06-finale_0022
|
tt06-finale
|
Fountaincoder-multimac
|
task_tt_um_fountaincoder_top
|
tt_um_fountaincoder_top
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Jonny Edwards
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_fountaincoder_top (
input wire clk, // clock
input wire ena, // will go high when the design is enabled
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire rst_n // reset_n - low to reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
/*
* Copyright (c) 2024 Jonny Edwards
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module DMADD(
input wire clk,
input wire rst_n, // reset_n - low to reset
input wire [3:0] index,
input wire [3:0] data,
input wire [1:0] insn,
input wire load,
input wire run,
output [7:0] out,
output [3:0] out_top
);
reg [4:0] j; //j=0 ;
reg [3:0] i; // i = 4'b1111;
reg signed [3:0] i_d;
reg [3:0] i_e;// = 4'b0;
reg signed [5:0] mem[15:0];
reg bad_pattern;// = 0;
reg signed [5:0] delta;// =6'b0;
reg [7:0] count;// = 8'b0;
reg [9:0] total;// = 10'b0;
reg [11:0] out_reg;// = 0;
reg set; // = 0;
always @(posedge clk) begin
casez ({rst_n, run,load,insn})
//Reset
5'b0_?_?_??: begin out_reg<=0; set<=0; i<= 4'b1111; i_d<= 1; i_e<=4'b0; delta<=6'b0; count<=8'b0;total<=10'b0; bad_pattern<=0; for (j=0;j<16;j=j+1) begin mem[j]<=0; end end
//Initialise
5'b1_0_0_00: begin i<= 4'b0; i_e <= 4'b1111; end // Initialise MIN
5'b1_0_0_01: begin i<= 4'b1111; i_e <= 4'b0; end // Initialise MAX
5'b1_0_1_00,
5'b1_0_1_01: mem[index] <= 6'b1; // Load Data MIN
5'b1_0_1_10: {mem[index], mem[index-1]} <= {mem[index] + {2'b0,data}, mem[index-1] - {2'b0,data}} ; //MADD
5'b1_1_0_00: i <= i + i_d; // Run MIN
5'b1_1_0_01: i <= i - i_d; // Run MAX
5'b1_1_0_10: begin i <= i - i_d; delta <= delta + mem[i-1]; count <= count+{2'b0,delta}; total <= total + {2'b0,count}; end //MADD
default: bad_pattern <= 1;
endcase
if (i == i_e && insn[1]==1) begin
out_reg <= {2'b0,total} + {4'b0,count};
i_d <= 0 ;
end
if ((mem[i] != 6'b0) && !set && insn[1]!=1) begin
out_reg <= {8'b0,i};
i_d <= 0;
set <= 1;
end
// $display("%d r %d run %d load %d isn %d bad %d i_d %d i_e %d index %d data %d out_reg %d", i ,rst_n, run, load,insn, bad_pattern,i_d,i_e, index, data,out);
// $display("d %d c %d t %d m %d",delta,count,total,mem[i]);
end
assign out = out_reg[7:0];
//assign out_top = out_reg[11:8];
assign out_top = i_d;
endmodule
|
module tt_um_fountaincoder_top (
input wire clk, // clock
input wire ena, // will go high when the design is enabled
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
assign uio_out[3:0] = 4'b0;
/* verilator lint_off UNUSED */
wire [3:0] dummy1 = uio_in[7:4];
wire dummy2 = ena;
assign uio_oe = 8'b11110000;
//assign all the loose ports
wire [7:0] out;
wire [3:0] out_top;
assign uo_out = out;
assign uio_out[7:4] = out_top;
DMADD madd(
.clk (clk),
.run (uio_in[3]),
.load (uio_in[2]),
.insn (uio_in[1:0]),
.index (ui_in[7:4]),
.data (ui_in[3:0]),
.out (out),
.out_top (out_top),
.rst_n (rst_n)
);
endmodule
|
tt06-finale_0023
|
tt06-finale
|
JoseKaisen-ALU_3bits
|
task_ALU
|
tt_um_ALU
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_ALU (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
ALU U3 (.A(ui_in[2:0]), .B(ui_in[5:3]), .ctrl(uio_in[2:0]), .Leds(uo_out[5:0]));
assign uio_oe= 8'b 00111111;
assign uo_out[7:6]= 2'b00;
assign uio_out[7:0]= 8'b00000000;
endmodule
`timescale 1ns / 1ps
module ALU (input [2:0] ctrl, input [2:0] A,B, output [5:0] Leds);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
`timescale 1ns / 1ps
module arithmetic_operators (input [2:0]A,B, output reg [3:0]Y1_ADD, output reg[5:0]Y3_MULT,
output reg[2:0]Y2_MIN, Y4_DIV, Y5_MOD);
always@(A,B)
begin
Y1_ADD = A + B;
Y2_MIN = A - B;
Y3_MULT = A * B;
Y4_DIV = A / B;
Y5_MOD = A % B;
end
endmodule
|
module ALU (input [2:0] ctrl, input [2:0] A,B, output [5:0] Leds);
wire [5:0] Y3_MULT;
wire [3:0] Y1_ADD;
wire [2:0] Y2_MIN,Y4_DIV, Y5_MOD;
reg [5:0] aux;
arithmetic_operators U2 (.A(A), .B(B), .Y1_ADD(Y1_ADD),
.Y2_MIN(Y2_MIN), .Y3_MULT(Y3_MULT), .Y4_DIV(Y4_DIV), .Y5_MOD(Y5_MOD));
assign Leds= aux;
always@(*)
begin
case(ctrl)
0:aux= Y1_ADD;
1:aux= Y2_MIN;
2:aux= Y3_MULT;
3:aux= Y4_DIV;
4:aux= Y5_MOD;
default:aux=0;
endcase
end
endmodule
|
tt06-finale_0024
|
tt06-finale
|
JoseKaisen-ALU_3bits
|
task_arithmetic_operators
|
tt_um_ALU
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_ALU (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
ALU U3 (.A(ui_in[2:0]), .B(ui_in[5:3]), .ctrl(uio_in[2:0]), .Leds(uo_out[5:0]));
assign uio_oe= 8'b 00111111;
assign uo_out[7:6]= 2'b00;
assign uio_out[7:0]= 8'b00000000;
endmodule
`timescale 1ns / 1ps
module ALU (input [2:0] ctrl, input [2:0] A,B, output [5:0] Leds);
wire [5:0] Y3_MULT;
wire [3:0] Y1_ADD;
wire [2:0] Y2_MIN,Y4_DIV, Y5_MOD;
reg [5:0] aux;
arithmetic_operators U2 (.A(A), .B(B), .Y1_ADD(Y1_ADD),
.Y2_MIN(Y2_MIN), .Y3_MULT(Y3_MULT), .Y4_DIV(Y4_DIV), .Y5_MOD(Y5_MOD));
assign Leds= aux;
always@(*)
begin
case(ctrl)
0:aux= Y1_ADD;
1:aux= Y2_MIN;
2:aux= Y3_MULT;
3:aux= Y4_DIV;
4:aux= Y5_MOD;
default:aux=0;
endcase
end
endmodule
`timescale 1ns / 1ps
module arithmetic_operators (input [2:0]A,B, output reg [3:0]Y1_ADD, output reg[5:0]Y3_MULT,
output reg[2:0]Y2_MIN, Y4_DIV, Y5_MOD);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
|
module arithmetic_operators (input [2:0]A,B, output reg [3:0]Y1_ADD, output reg[5:0]Y3_MULT,
output reg[2:0]Y2_MIN, Y4_DIV, Y5_MOD);
always@(A,B)
begin
Y1_ADD = A + B;
Y2_MIN = A - B;
Y3_MULT = A * B;
Y4_DIV = A / B;
Y5_MOD = A % B;
end
endmodule
|
tt06-finale_0025
|
tt06-finale
|
JoseKaisen-ALU_3bits
|
task_tt_um_ALU
|
tt_um_ALU
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_ALU (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
`timescale 1ns / 1ps
module ALU (input [2:0] ctrl, input [2:0] A,B, output [5:0] Leds);
wire [5:0] Y3_MULT;
wire [3:0] Y1_ADD;
wire [2:0] Y2_MIN,Y4_DIV, Y5_MOD;
reg [5:0] aux;
arithmetic_operators U2 (.A(A), .B(B), .Y1_ADD(Y1_ADD),
.Y2_MIN(Y2_MIN), .Y3_MULT(Y3_MULT), .Y4_DIV(Y4_DIV), .Y5_MOD(Y5_MOD));
assign Leds= aux;
always@(*)
begin
case(ctrl)
0:aux= Y1_ADD;
1:aux= Y2_MIN;
2:aux= Y3_MULT;
3:aux= Y4_DIV;
4:aux= Y5_MOD;
default:aux=0;
endcase
end
endmodule
`timescale 1ns / 1ps
module arithmetic_operators (input [2:0]A,B, output reg [3:0]Y1_ADD, output reg[5:0]Y3_MULT,
output reg[2:0]Y2_MIN, Y4_DIV, Y5_MOD);
always@(A,B)
begin
Y1_ADD = A + B;
Y2_MIN = A - B;
Y3_MULT = A * B;
Y4_DIV = A / B;
Y5_MOD = A % B;
end
endmodule
|
module tt_um_ALU (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
ALU U3 (.A(ui_in[2:0]), .B(ui_in[5:3]), .ctrl(uio_in[2:0]), .Leds(uo_out[5:0]));
assign uio_oe= 8'b 00111111;
assign uo_out[7:6]= 2'b00;
assign uio_out[7:0]= 8'b00000000;
endmodule
|
tt06-finale_0026
|
tt06-finale
|
Lefteris-B-i_tree
|
task_IsolationTreeStateMachine
|
tt_um_i_tree_batzolislefteris
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_i_tree_batzolislefteris(
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
assign uio_oe = 8'b0000_0000;
assign uio_out = 8'b0000_0000;
assign uo_out[7:1] = 7'b0000_000;
i_tree i_tree_inst(
.clk(clk),
.reset(rst_n),
.sensor_data(ui_in[0]),
.anomaly_detected(uo_out[0])
);
endmodule
module i_tree(
input wire clk,
input wire reset,
input wire sensor_data, // Incoming sensor data bit
output wire anomaly_detected // Output indicating if an anomaly was detected
);
// Internal signal declarations
wire [7:0] data_from_buffer;
wire data_ready;
wire data_processed;
// Instantiate the InputBuffer module
InputBuffer #(.DATA_WIDTH(8)) input_buffer_inst (
.clk(clk),
.reset(reset),
.sensor_data(sensor_data),
.data_processed(data_processed),
.data_output(data_from_buffer),
.data_ready(data_ready)
);
// Instantiate the IsolationTreeStateMachine module
IsolationTreeStateMachine isolation_tree_state_machine_inst (
.clk(clk),
.reset(reset),
.data_input(data_from_buffer),
.data_valid(data_ready),
.anomaly_detected(anomaly_detected),
.data_processed(data_processed)
);
endmodule
module IsolationTreeStateMachine(
input wire clk,
input wire reset,
input wire [7:0] data_input,
input wire data_valid,
output reg anomaly_detected,
output reg data_processed
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module InputBuffer #(
parameter DATA_WIDTH = 8 // Default parameter for data width
)(
input wire clk,
input wire reset,
input wire sensor_data,
input wire data_processed, // Signal from state machine indicating data has been processed
output reg [DATA_WIDTH-1:0] data_output,
output reg data_ready
);
// Internal signals and registers
reg [DATA_WIDTH-1:0] buffer;
reg [DATA_WIDTH-1:0] data_temp;
reg [DATA_WIDTH-1:0] bit_count = 0; // Bit count for data collection
// Always block for handling the shift register and outputting data
always @(posedge clk or posedge reset) begin
if (reset) begin
// Reset all outputs and internal registers
buffer <= 0;
data_temp <= 0;
data_output <= 0;
data_ready <= 0;
bit_count <= 0;
end else begin
// Handle data collection and output
if (bit_count < DATA_WIDTH) begin
buffer <= (buffer << 1) | sensor_data;
bit_count <= bit_count + 1;
end
// Check if data has been processed and ready to be output
if (data_processed && (bit_count == DATA_WIDTH)) begin
data_temp <= buffer; // Save data temporarily
data_ready <= 1;
end
// Output data after ensuring it has been processed and ready
if (data_ready) begin
data_output <= data_temp;
data_ready <= 0;
buffer <= 0; // Reset buffer for new data collection
bit_count <= 0; // Reset bit count
end
end
end
endmodule
|
module IsolationTreeStateMachine(
input wire clk,
input wire reset,
input wire [7:0] data_input,
input wire data_valid,
output reg anomaly_detected,
output reg data_processed
);
// Define state constants
localparam [1:0] IDLE = 2'b00,
CHECK_ANOMALY = 2'b01,
PROCESS_DONE = 2'b10;
// State variables
reg [1:0] current_state = IDLE;
reg [1:0] next_state = IDLE;
reg [7:0] anomaly_pattern; // Internal register to hold the anomaly pattern
always @(posedge clk or negedge reset) begin
if (!reset) begin
// Reset logic
anomaly_detected <= 0;
data_processed <= 0;
current_state <= IDLE;
next_state <= IDLE;
anomaly_pattern <= 8'h00; // Reset anomaly pattern register
end else begin
current_state <= next_state; // Transition to the next state
case (current_state)
IDLE: begin
anomaly_detected <= 0; // Reset anomaly_detected each cycle
if (data_valid) begin
next_state <= CHECK_ANOMALY; // Transition to check anomaly if data is valid
anomaly_pattern <= data_input; // Store the first 8-bit value as the anomaly pattern
end
end
CHECK_ANOMALY: begin
// Perform anomaly check
anomaly_detected <= (data_input == anomaly_pattern); // Check if data matches anomaly pattern
next_state <= PROCESS_DONE; // Move to process done state
end
PROCESS_DONE: begin
// Indicate processing is done
data_processed <= 1;
next_state <= IDLE; // Return to IDLE state
end
default: begin
next_state <= IDLE; // Default fallback to IDLE
end
endcase
end
end
endmodule
|
tt06-finale_0027
|
tt06-finale
|
Lefteris-B-i_tree
|
task_i_tree
|
tt_um_i_tree_batzolislefteris
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_i_tree_batzolislefteris(
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
assign uio_oe = 8'b0000_0000;
assign uio_out = 8'b0000_0000;
assign uo_out[7:1] = 7'b0000_000;
i_tree i_tree_inst(
.clk(clk),
.reset(rst_n),
.sensor_data(ui_in[0]),
.anomaly_detected(uo_out[0])
);
endmodule
module i_tree(
input wire clk,
input wire reset,
input wire sensor_data, // Incoming sensor data bit
output wire anomaly_detected // Output indicating if an anomaly was detected
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module IsolationTreeStateMachine(
input wire clk,
input wire reset,
input wire [7:0] data_input,
input wire data_valid,
output reg anomaly_detected,
output reg data_processed
);
// Define state constants
localparam [1:0] IDLE = 2'b00,
CHECK_ANOMALY = 2'b01,
PROCESS_DONE = 2'b10;
// State variables
reg [1:0] current_state = IDLE;
reg [1:0] next_state = IDLE;
reg [7:0] anomaly_pattern; // Internal register to hold the anomaly pattern
always @(posedge clk or negedge reset) begin
if (!reset) begin
// Reset logic
anomaly_detected <= 0;
data_processed <= 0;
current_state <= IDLE;
next_state <= IDLE;
anomaly_pattern <= 8'h00; // Reset anomaly pattern register
end else begin
current_state <= next_state; // Transition to the next state
case (current_state)
IDLE: begin
anomaly_detected <= 0; // Reset anomaly_detected each cycle
if (data_valid) begin
next_state <= CHECK_ANOMALY; // Transition to check anomaly if data is valid
anomaly_pattern <= data_input; // Store the first 8-bit value as the anomaly pattern
end
end
CHECK_ANOMALY: begin
// Perform anomaly check
anomaly_detected <= (data_input == anomaly_pattern); // Check if data matches anomaly pattern
next_state <= PROCESS_DONE; // Move to process done state
end
PROCESS_DONE: begin
// Indicate processing is done
data_processed <= 1;
next_state <= IDLE; // Return to IDLE state
end
default: begin
next_state <= IDLE; // Default fallback to IDLE
end
endcase
end
end
endmodule
module InputBuffer #(
parameter DATA_WIDTH = 8 // Default parameter for data width
)(
input wire clk,
input wire reset,
input wire sensor_data,
input wire data_processed, // Signal from state machine indicating data has been processed
output reg [DATA_WIDTH-1:0] data_output,
output reg data_ready
);
// Internal signals and registers
reg [DATA_WIDTH-1:0] buffer;
reg [DATA_WIDTH-1:0] data_temp;
reg [DATA_WIDTH-1:0] bit_count = 0; // Bit count for data collection
// Always block for handling the shift register and outputting data
always @(posedge clk or posedge reset) begin
if (reset) begin
// Reset all outputs and internal registers
buffer <= 0;
data_temp <= 0;
data_output <= 0;
data_ready <= 0;
bit_count <= 0;
end else begin
// Handle data collection and output
if (bit_count < DATA_WIDTH) begin
buffer <= (buffer << 1) | sensor_data;
bit_count <= bit_count + 1;
end
// Check if data has been processed and ready to be output
if (data_processed && (bit_count == DATA_WIDTH)) begin
data_temp <= buffer; // Save data temporarily
data_ready <= 1;
end
// Output data after ensuring it has been processed and ready
if (data_ready) begin
data_output <= data_temp;
data_ready <= 0;
buffer <= 0; // Reset buffer for new data collection
bit_count <= 0; // Reset bit count
end
end
end
endmodule
|
module i_tree(
input wire clk,
input wire reset,
input wire sensor_data, // Incoming sensor data bit
output wire anomaly_detected // Output indicating if an anomaly was detected
);
// Internal signal declarations
wire [7:0] data_from_buffer;
wire data_ready;
wire data_processed;
// Instantiate the InputBuffer module
InputBuffer #(.DATA_WIDTH(8)) input_buffer_inst (
.clk(clk),
.reset(reset),
.sensor_data(sensor_data),
.data_processed(data_processed),
.data_output(data_from_buffer),
.data_ready(data_ready)
);
// Instantiate the IsolationTreeStateMachine module
IsolationTreeStateMachine isolation_tree_state_machine_inst (
.clk(clk),
.reset(reset),
.data_input(data_from_buffer),
.data_valid(data_ready),
.anomaly_detected(anomaly_detected),
.data_processed(data_processed)
);
endmodule
|
tt06-finale_0028
|
tt06-finale
|
Lefteris-B-i_tree
|
task_tt_um_i_tree_batzolislefteris
|
tt_um_i_tree_batzolislefteris
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_i_tree_batzolislefteris(
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module i_tree(
input wire clk,
input wire reset,
input wire sensor_data, // Incoming sensor data bit
output wire anomaly_detected // Output indicating if an anomaly was detected
);
// Internal signal declarations
wire [7:0] data_from_buffer;
wire data_ready;
wire data_processed;
// Instantiate the InputBuffer module
InputBuffer #(.DATA_WIDTH(8)) input_buffer_inst (
.clk(clk),
.reset(reset),
.sensor_data(sensor_data),
.data_processed(data_processed),
.data_output(data_from_buffer),
.data_ready(data_ready)
);
// Instantiate the IsolationTreeStateMachine module
IsolationTreeStateMachine isolation_tree_state_machine_inst (
.clk(clk),
.reset(reset),
.data_input(data_from_buffer),
.data_valid(data_ready),
.anomaly_detected(anomaly_detected),
.data_processed(data_processed)
);
endmodule
module IsolationTreeStateMachine(
input wire clk,
input wire reset,
input wire [7:0] data_input,
input wire data_valid,
output reg anomaly_detected,
output reg data_processed
);
// Define state constants
localparam [1:0] IDLE = 2'b00,
CHECK_ANOMALY = 2'b01,
PROCESS_DONE = 2'b10;
// State variables
reg [1:0] current_state = IDLE;
reg [1:0] next_state = IDLE;
reg [7:0] anomaly_pattern; // Internal register to hold the anomaly pattern
always @(posedge clk or negedge reset) begin
if (!reset) begin
// Reset logic
anomaly_detected <= 0;
data_processed <= 0;
current_state <= IDLE;
next_state <= IDLE;
anomaly_pattern <= 8'h00; // Reset anomaly pattern register
end else begin
current_state <= next_state; // Transition to the next state
case (current_state)
IDLE: begin
anomaly_detected <= 0; // Reset anomaly_detected each cycle
if (data_valid) begin
next_state <= CHECK_ANOMALY; // Transition to check anomaly if data is valid
anomaly_pattern <= data_input; // Store the first 8-bit value as the anomaly pattern
end
end
CHECK_ANOMALY: begin
// Perform anomaly check
anomaly_detected <= (data_input == anomaly_pattern); // Check if data matches anomaly pattern
next_state <= PROCESS_DONE; // Move to process done state
end
PROCESS_DONE: begin
// Indicate processing is done
data_processed <= 1;
next_state <= IDLE; // Return to IDLE state
end
default: begin
next_state <= IDLE; // Default fallback to IDLE
end
endcase
end
end
endmodule
module InputBuffer #(
parameter DATA_WIDTH = 8 // Default parameter for data width
)(
input wire clk,
input wire reset,
input wire sensor_data,
input wire data_processed, // Signal from state machine indicating data has been processed
output reg [DATA_WIDTH-1:0] data_output,
output reg data_ready
);
// Internal signals and registers
reg [DATA_WIDTH-1:0] buffer;
reg [DATA_WIDTH-1:0] data_temp;
reg [DATA_WIDTH-1:0] bit_count = 0; // Bit count for data collection
// Always block for handling the shift register and outputting data
always @(posedge clk or posedge reset) begin
if (reset) begin
// Reset all outputs and internal registers
buffer <= 0;
data_temp <= 0;
data_output <= 0;
data_ready <= 0;
bit_count <= 0;
end else begin
// Handle data collection and output
if (bit_count < DATA_WIDTH) begin
buffer <= (buffer << 1) | sensor_data;
bit_count <= bit_count + 1;
end
// Check if data has been processed and ready to be output
if (data_processed && (bit_count == DATA_WIDTH)) begin
data_temp <= buffer; // Save data temporarily
data_ready <= 1;
end
// Output data after ensuring it has been processed and ready
if (data_ready) begin
data_output <= data_temp;
data_ready <= 0;
buffer <= 0; // Reset buffer for new data collection
bit_count <= 0; // Reset bit count
end
end
end
endmodule
|
module tt_um_i_tree_batzolislefteris(
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
assign uio_oe = 8'b0000_0000;
assign uio_out = 8'b0000_0000;
assign uo_out[7:1] = 7'b0000_000;
i_tree i_tree_inst(
.clk(clk),
.reset(rst_n),
.sensor_data(ui_in[0]),
.anomaly_detected(uo_out[0])
);
endmodule
|
tt06-finale_0029
|
tt06-finale
|
OnSachinSharma-tt06-verilog-PWM
|
task_DFF_PWM
|
tt_um_shivam
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_shivam (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
//assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in
assign uio_out = 0;
assign uio_oe = 0;
assign uo_out = PWM_OUT;
wire slow_clk_enable; // slow clock enable signal for debouncing FFs
reg[27:0] counter_debounce=0;// counter for creating slow clock enable signals
wire tmp1,tmp2,duty_inc;// temporary flip-flop signals for debouncing the increasing button
wire tmp3,tmp4,duty_dec;// temporary flip-flop signals for debouncing the decreasing button
reg[3:0] counter_PWM=0;// counter for creating 10Mhz PWM signal
reg[3:0] DUTY_CYCLE=5; // initial duty cycle is 50%
// Debouncing 2 buttons for inc/dec duty cycle
// Firstly generate slow clock enable for debouncing flip-flop (4Hz)
always @(posedge clk)
begin
counter_debounce <= counter_debounce + 1;
//if(counter_debounce>=25000000) then
// for running on FPGA -- comment when running simulation
if(counter_debounce>=1)
// for running simulation -- comment when running on FPGA
counter_debounce <= 0;
end
// assign slow_clk_enable = counter_debounce == 25000000 ?1:0;
// for running on FPGA -- comment when running simulation
assign slow_clk_enable = counter_debounce == 1 ?1:0;
// for running simulation -- comment when running on FPGA
// debouncing FFs for increasing button
DFF_PWM PWM_DFF1(clk,slow_clk_enable,ui_in[0],tmp1);
DFF_PWM PWM_DFF2(clk,slow_clk_enable,tmp1, tmp2);
assign duty_inc = tmp1 & (~ tmp2) & slow_clk_enable;
// debouncing FFs for decreasing button
DFF_PWM PWM_DFF3(clk,slow_clk_enable,ui_in[1], tmp3);
DFF_PWM PWM_DFF4(clk,slow_clk_enable,tmp3, tmp4);
assign duty_dec = tmp3 & (~ tmp4) & slow_clk_enable;
// vary the duty cycle using the debounced buttons above
always @(posedge clk)
begin
if(duty_inc==1 && DUTY_CYCLE <= 9)
DUTY_CYCLE <= DUTY_CYCLE + 1;// increase duty cycle by 10%
else if(duty_dec==1 && DUTY_CYCLE>=1)
DUTY_CYCLE <= DUTY_CYCLE - 1;//decrease duty cycle by 10%
end
// Create 10MHz PWM signal with variable duty cycle controlled by 2 buttons
always @(posedge clk)
begin
counter_PWM <= counter_PWM + 1;
if(counter_PWM>=9)
counter_PWM <= 0;
end
assign PWM_OUT = counter_PWM < DUTY_CYCLE ? 1:0;
endmodule
// Debouncing DFFs for push buttons on FPGA
module DFF_PWM(clk,en,D,Q);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
|
module DFF_PWM(clk,en,D,Q);
input clk,en,D;
output reg Q;
always @(posedge clk)
begin
if(en==1) // slow clock enable signal
Q <= D;
end
endmodule
|
tt06-finale_0030
|
tt06-finale
|
OnSachinSharma-tt06-verilog-PWM
|
task_tt_um_shivam
|
tt_um_shivam
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_shivam (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
// Debouncing DFFs for push buttons on FPGA
module DFF_PWM(clk,en,D,Q);
input clk,en,D;
output reg Q;
always @(posedge clk)
begin
if(en==1) // slow clock enable signal
Q <= D;
end
endmodule
|
module tt_um_shivam (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
//assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in
assign uio_out = 0;
assign uio_oe = 0;
assign uo_out = PWM_OUT;
wire slow_clk_enable; // slow clock enable signal for debouncing FFs
reg[27:0] counter_debounce=0;// counter for creating slow clock enable signals
wire tmp1,tmp2,duty_inc;// temporary flip-flop signals for debouncing the increasing button
wire tmp3,tmp4,duty_dec;// temporary flip-flop signals for debouncing the decreasing button
reg[3:0] counter_PWM=0;// counter for creating 10Mhz PWM signal
reg[3:0] DUTY_CYCLE=5; // initial duty cycle is 50%
// Debouncing 2 buttons for inc/dec duty cycle
// Firstly generate slow clock enable for debouncing flip-flop (4Hz)
always @(posedge clk)
begin
counter_debounce <= counter_debounce + 1;
//if(counter_debounce>=25000000) then
// for running on FPGA -- comment when running simulation
if(counter_debounce>=1)
// for running simulation -- comment when running on FPGA
counter_debounce <= 0;
end
// assign slow_clk_enable = counter_debounce == 25000000 ?1:0;
// for running on FPGA -- comment when running simulation
assign slow_clk_enable = counter_debounce == 1 ?1:0;
// for running simulation -- comment when running on FPGA
// debouncing FFs for increasing button
DFF_PWM PWM_DFF1(clk,slow_clk_enable,ui_in[0],tmp1);
DFF_PWM PWM_DFF2(clk,slow_clk_enable,tmp1, tmp2);
assign duty_inc = tmp1 & (~ tmp2) & slow_clk_enable;
// debouncing FFs for decreasing button
DFF_PWM PWM_DFF3(clk,slow_clk_enable,ui_in[1], tmp3);
DFF_PWM PWM_DFF4(clk,slow_clk_enable,tmp3, tmp4);
assign duty_dec = tmp3 & (~ tmp4) & slow_clk_enable;
// vary the duty cycle using the debounced buttons above
always @(posedge clk)
begin
if(duty_inc==1 && DUTY_CYCLE <= 9)
DUTY_CYCLE <= DUTY_CYCLE + 1;// increase duty cycle by 10%
else if(duty_dec==1 && DUTY_CYCLE>=1)
DUTY_CYCLE <= DUTY_CYCLE - 1;//decrease duty cycle by 10%
end
// Create 10MHz PWM signal with variable duty cycle controlled by 2 buttons
always @(posedge clk)
begin
counter_PWM <= counter_PWM + 1;
if(counter_PWM>=9)
counter_PWM <= 0;
end
assign PWM_OUT = counter_PWM < DUTY_CYCLE ? 1:0;
endmodule
|
tt06-finale_0031
|
tt06-finale
|
SteffenReith-TT06_ASG
|
task_ASG
|
tt_um_SteffenReith_ASGTop
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Steffen Reith
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_SteffenReith_ASGTop (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// A reset signal for the ASG
wire reset = !(rst_n && ena);
// Don't use the IOs as outputs
assign uio_out = 8'b0000_0000;
// Set the directions for the IOs (unused at all)
assign uio_oe = 8'bZZZZ_ZZZZ;
// Set unused outputs to Z
assign uo_out[7:1] = 7'bZZZZ_ZZZ;
//Instantiate the ASG and connect the signals
ASG asg (
.loadIt(ui_in[1:0]),
.load(ui_in[2]),
.enable(ui_in[3]),
.newBit(uo_out[0]),
.reset(reset),
.clk(clk)
);
endmodule
// Generator : SpinalHDL v1.10.1 git head : 2527c7c6b0fb0f95e5e1a5722a0be732b364ce43
// Component : ASG
// Git hash : ddaf840b8cb4ff1c649e316de111050773741fb0
`timescale 1ns/1ps
module ASG (
input wire [1:0] loadIt,
input wire load,
input wire enable,
output wire newBit,
input wire clk,
input wire reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module LSFR_2 (
input wire load,
input wire loadIt,
input wire enable,
output wire newBit,
input wire clk,
input wire reset
);
wire [88:0] fsRegN;
reg [88:0] fsReg;
wire taps_0;
wire taps_1;
reg genBit;
assign taps_0 = fsReg[0];
assign taps_1 = fsReg[51];
always @(*) begin
genBit = (taps_0 ^ taps_1);
if(loadIt) begin
genBit = load;
end
end
assign newBit = fsReg[0];
assign fsRegN = {genBit,fsReg[88 : 1]};
always @(posedge clk) begin
if(reset) begin
fsReg <= 89'h00000000000000000000000;
end else begin
if(enable) begin
fsReg <= fsRegN;
end
end
end
endmodule
module LSFR_1 (
input wire load,
input wire loadIt,
input wire enable,
output wire newBit,
input wire clk,
input wire reset
);
wire [62:0] fsRegN;
reg [62:0] fsReg;
wire taps_0;
wire taps_1;
reg genBit;
assign taps_0 = fsReg[0];
assign taps_1 = fsReg[62];
always @(*) begin
genBit = (taps_0 ^ taps_1);
if(loadIt) begin
genBit = load;
end
end
assign newBit = fsReg[0];
assign fsRegN = {genBit,fsReg[62 : 1]};
always @(posedge clk) begin
if(reset) begin
fsReg <= 63'h0000000000000000;
end else begin
if(enable) begin
fsReg <= fsRegN;
end
end
end
endmodule
module LSFR (
input wire load,
input wire loadIt,
input wire enable,
output wire newBit,
input wire clk,
input wire reset
);
wire [30:0] fsRegN;
reg [30:0] fsReg;
wire taps_0;
wire taps_1;
reg genBit;
assign taps_0 = fsReg[0];
assign taps_1 = fsReg[28];
always @(*) begin
genBit = (taps_0 ^ taps_1);
if(loadIt) begin
genBit = load;
end
end
assign newBit = fsReg[0];
assign fsRegN = {genBit,fsReg[30 : 1]};
always @(posedge clk) begin
if(reset) begin
fsReg <= 31'h00000000;
end else begin
if(enable) begin
fsReg <= fsRegN;
end
end
end
endmodule
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_example (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in
assign uio_out = 0;
assign uio_oe = 0;
endmodule
|
module ASG (
input wire [1:0] loadIt,
input wire load,
input wire enable,
output wire newBit,
input wire clk,
input wire reset
);
wire R1_enable;
wire R2_enable;
wire R3_enable;
wire R1_newBit;
wire R2_newBit;
wire R3_newBit;
wire loadR1;
wire loadR2;
wire loadR3;
LSFR R1 (
.load (load ), //i
.loadIt (loadR1 ), //i
.enable (R1_enable), //i
.newBit (R1_newBit), //o
.clk (clk ), //i
.reset (reset ) //i
);
LSFR_1 R2 (
.load (load ), //i
.loadIt (loadR2 ), //i
.enable (R2_enable), //i
.newBit (R2_newBit), //o
.clk (clk ), //i
.reset (reset ) //i
);
LSFR_2 R3 (
.load (load ), //i
.loadIt (loadR3 ), //i
.enable (R3_enable), //i
.newBit (R3_newBit), //o
.clk (clk ), //i
.reset (reset ) //i
);
assign loadR1 = (loadIt == 2'b01);
assign loadR2 = (loadIt == 2'b10);
assign loadR3 = (loadIt == 2'b11);
assign R1_enable = (enable || loadR1);
assign R2_enable = ((enable && R1_newBit) || loadR2);
assign R3_enable = ((enable && (! R1_newBit)) || loadR3);
assign newBit = (R2_newBit ^ R3_newBit);
endmodule
|
tt06-finale_0032
|
tt06-finale
|
SteffenReith-TT06_ASG
|
task_LSFR
|
tt_um_SteffenReith_ASGTop
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Steffen Reith
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_SteffenReith_ASGTop (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// A reset signal for the ASG
wire reset = !(rst_n && ena);
// Don't use the IOs as outputs
assign uio_out = 8'b0000_0000;
// Set the directions for the IOs (unused at all)
assign uio_oe = 8'bZZZZ_ZZZZ;
// Set unused outputs to Z
assign uo_out[7:1] = 7'bZZZZ_ZZZ;
//Instantiate the ASG and connect the signals
ASG asg (
.loadIt(ui_in[1:0]),
.load(ui_in[2]),
.enable(ui_in[3]),
.newBit(uo_out[0]),
.reset(reset),
.clk(clk)
);
endmodule
// Generator : SpinalHDL v1.10.1 git head : 2527c7c6b0fb0f95e5e1a5722a0be732b364ce43
// Component : ASG
// Git hash : ddaf840b8cb4ff1c649e316de111050773741fb0
`timescale 1ns/1ps
module ASG (
input wire [1:0] loadIt,
input wire load,
input wire enable,
output wire newBit,
input wire clk,
input wire reset
);
wire R1_enable;
wire R2_enable;
wire R3_enable;
wire R1_newBit;
wire R2_newBit;
wire R3_newBit;
wire loadR1;
wire loadR2;
wire loadR3;
LSFR R1 (
.load (load ), //i
.loadIt (loadR1 ), //i
.enable (R1_enable), //i
.newBit (R1_newBit), //o
.clk (clk ), //i
.reset (reset ) //i
);
LSFR_1 R2 (
.load (load ), //i
.loadIt (loadR2 ), //i
.enable (R2_enable), //i
.newBit (R2_newBit), //o
.clk (clk ), //i
.reset (reset ) //i
);
LSFR_2 R3 (
.load (load ), //i
.loadIt (loadR3 ), //i
.enable (R3_enable), //i
.newBit (R3_newBit), //o
.clk (clk ), //i
.reset (reset ) //i
);
assign loadR1 = (loadIt == 2'b01);
assign loadR2 = (loadIt == 2'b10);
assign loadR3 = (loadIt == 2'b11);
assign R1_enable = (enable || loadR1);
assign R2_enable = ((enable && R1_newBit) || loadR2);
assign R3_enable = ((enable && (! R1_newBit)) || loadR3);
assign newBit = (R2_newBit ^ R3_newBit);
endmodule
module LSFR_2 (
input wire load,
input wire loadIt,
input wire enable,
output wire newBit,
input wire clk,
input wire reset
);
wire [88:0] fsRegN;
reg [88:0] fsReg;
wire taps_0;
wire taps_1;
reg genBit;
assign taps_0 = fsReg[0];
assign taps_1 = fsReg[51];
always @(*) begin
genBit = (taps_0 ^ taps_1);
if(loadIt) begin
genBit = load;
end
end
assign newBit = fsReg[0];
assign fsRegN = {genBit,fsReg[88 : 1]};
always @(posedge clk) begin
if(reset) begin
fsReg <= 89'h00000000000000000000000;
end else begin
if(enable) begin
fsReg <= fsRegN;
end
end
end
endmodule
module LSFR_1 (
input wire load,
input wire loadIt,
input wire enable,
output wire newBit,
input wire clk,
input wire reset
);
wire [62:0] fsRegN;
reg [62:0] fsReg;
wire taps_0;
wire taps_1;
reg genBit;
assign taps_0 = fsReg[0];
assign taps_1 = fsReg[62];
always @(*) begin
genBit = (taps_0 ^ taps_1);
if(loadIt) begin
genBit = load;
end
end
assign newBit = fsReg[0];
assign fsRegN = {genBit,fsReg[62 : 1]};
always @(posedge clk) begin
if(reset) begin
fsReg <= 63'h0000000000000000;
end else begin
if(enable) begin
fsReg <= fsRegN;
end
end
end
endmodule
module LSFR (
input wire load,
input wire loadIt,
input wire enable,
output wire newBit,
input wire clk,
input wire reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_example (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in
assign uio_out = 0;
assign uio_oe = 0;
endmodule
|
module LSFR (
input wire load,
input wire loadIt,
input wire enable,
output wire newBit,
input wire clk,
input wire reset
);
wire [30:0] fsRegN;
reg [30:0] fsReg;
wire taps_0;
wire taps_1;
reg genBit;
assign taps_0 = fsReg[0];
assign taps_1 = fsReg[28];
always @(*) begin
genBit = (taps_0 ^ taps_1);
if(loadIt) begin
genBit = load;
end
end
assign newBit = fsReg[0];
assign fsRegN = {genBit,fsReg[30 : 1]};
always @(posedge clk) begin
if(reset) begin
fsReg <= 31'h00000000;
end else begin
if(enable) begin
fsReg <= fsRegN;
end
end
end
endmodule
|
tt06-finale_0033
|
tt06-finale
|
SteffenReith-TT06_ASG
|
task_LSFR_1
|
tt_um_SteffenReith_ASGTop
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Steffen Reith
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_SteffenReith_ASGTop (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// A reset signal for the ASG
wire reset = !(rst_n && ena);
// Don't use the IOs as outputs
assign uio_out = 8'b0000_0000;
// Set the directions for the IOs (unused at all)
assign uio_oe = 8'bZZZZ_ZZZZ;
// Set unused outputs to Z
assign uo_out[7:1] = 7'bZZZZ_ZZZ;
//Instantiate the ASG and connect the signals
ASG asg (
.loadIt(ui_in[1:0]),
.load(ui_in[2]),
.enable(ui_in[3]),
.newBit(uo_out[0]),
.reset(reset),
.clk(clk)
);
endmodule
// Generator : SpinalHDL v1.10.1 git head : 2527c7c6b0fb0f95e5e1a5722a0be732b364ce43
// Component : ASG
// Git hash : ddaf840b8cb4ff1c649e316de111050773741fb0
`timescale 1ns/1ps
module ASG (
input wire [1:0] loadIt,
input wire load,
input wire enable,
output wire newBit,
input wire clk,
input wire reset
);
wire R1_enable;
wire R2_enable;
wire R3_enable;
wire R1_newBit;
wire R2_newBit;
wire R3_newBit;
wire loadR1;
wire loadR2;
wire loadR3;
LSFR R1 (
.load (load ), //i
.loadIt (loadR1 ), //i
.enable (R1_enable), //i
.newBit (R1_newBit), //o
.clk (clk ), //i
.reset (reset ) //i
);
LSFR_1 R2 (
.load (load ), //i
.loadIt (loadR2 ), //i
.enable (R2_enable), //i
.newBit (R2_newBit), //o
.clk (clk ), //i
.reset (reset ) //i
);
LSFR_2 R3 (
.load (load ), //i
.loadIt (loadR3 ), //i
.enable (R3_enable), //i
.newBit (R3_newBit), //o
.clk (clk ), //i
.reset (reset ) //i
);
assign loadR1 = (loadIt == 2'b01);
assign loadR2 = (loadIt == 2'b10);
assign loadR3 = (loadIt == 2'b11);
assign R1_enable = (enable || loadR1);
assign R2_enable = ((enable && R1_newBit) || loadR2);
assign R3_enable = ((enable && (! R1_newBit)) || loadR3);
assign newBit = (R2_newBit ^ R3_newBit);
endmodule
module LSFR_2 (
input wire load,
input wire loadIt,
input wire enable,
output wire newBit,
input wire clk,
input wire reset
);
wire [88:0] fsRegN;
reg [88:0] fsReg;
wire taps_0;
wire taps_1;
reg genBit;
assign taps_0 = fsReg[0];
assign taps_1 = fsReg[51];
always @(*) begin
genBit = (taps_0 ^ taps_1);
if(loadIt) begin
genBit = load;
end
end
assign newBit = fsReg[0];
assign fsRegN = {genBit,fsReg[88 : 1]};
always @(posedge clk) begin
if(reset) begin
fsReg <= 89'h00000000000000000000000;
end else begin
if(enable) begin
fsReg <= fsRegN;
end
end
end
endmodule
module LSFR_1 (
input wire load,
input wire loadIt,
input wire enable,
output wire newBit,
input wire clk,
input wire reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module LSFR (
input wire load,
input wire loadIt,
input wire enable,
output wire newBit,
input wire clk,
input wire reset
);
wire [30:0] fsRegN;
reg [30:0] fsReg;
wire taps_0;
wire taps_1;
reg genBit;
assign taps_0 = fsReg[0];
assign taps_1 = fsReg[28];
always @(*) begin
genBit = (taps_0 ^ taps_1);
if(loadIt) begin
genBit = load;
end
end
assign newBit = fsReg[0];
assign fsRegN = {genBit,fsReg[30 : 1]};
always @(posedge clk) begin
if(reset) begin
fsReg <= 31'h00000000;
end else begin
if(enable) begin
fsReg <= fsRegN;
end
end
end
endmodule
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_example (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in
assign uio_out = 0;
assign uio_oe = 0;
endmodule
|
module LSFR_1 (
input wire load,
input wire loadIt,
input wire enable,
output wire newBit,
input wire clk,
input wire reset
);
wire [62:0] fsRegN;
reg [62:0] fsReg;
wire taps_0;
wire taps_1;
reg genBit;
assign taps_0 = fsReg[0];
assign taps_1 = fsReg[62];
always @(*) begin
genBit = (taps_0 ^ taps_1);
if(loadIt) begin
genBit = load;
end
end
assign newBit = fsReg[0];
assign fsRegN = {genBit,fsReg[62 : 1]};
always @(posedge clk) begin
if(reset) begin
fsReg <= 63'h0000000000000000;
end else begin
if(enable) begin
fsReg <= fsRegN;
end
end
end
endmodule
|
tt06-finale_0034
|
tt06-finale
|
SteffenReith-TT06_ASG
|
task_LSFR_2
|
tt_um_SteffenReith_ASGTop
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Steffen Reith
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_SteffenReith_ASGTop (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// A reset signal for the ASG
wire reset = !(rst_n && ena);
// Don't use the IOs as outputs
assign uio_out = 8'b0000_0000;
// Set the directions for the IOs (unused at all)
assign uio_oe = 8'bZZZZ_ZZZZ;
// Set unused outputs to Z
assign uo_out[7:1] = 7'bZZZZ_ZZZ;
//Instantiate the ASG and connect the signals
ASG asg (
.loadIt(ui_in[1:0]),
.load(ui_in[2]),
.enable(ui_in[3]),
.newBit(uo_out[0]),
.reset(reset),
.clk(clk)
);
endmodule
// Generator : SpinalHDL v1.10.1 git head : 2527c7c6b0fb0f95e5e1a5722a0be732b364ce43
// Component : ASG
// Git hash : ddaf840b8cb4ff1c649e316de111050773741fb0
`timescale 1ns/1ps
module ASG (
input wire [1:0] loadIt,
input wire load,
input wire enable,
output wire newBit,
input wire clk,
input wire reset
);
wire R1_enable;
wire R2_enable;
wire R3_enable;
wire R1_newBit;
wire R2_newBit;
wire R3_newBit;
wire loadR1;
wire loadR2;
wire loadR3;
LSFR R1 (
.load (load ), //i
.loadIt (loadR1 ), //i
.enable (R1_enable), //i
.newBit (R1_newBit), //o
.clk (clk ), //i
.reset (reset ) //i
);
LSFR_1 R2 (
.load (load ), //i
.loadIt (loadR2 ), //i
.enable (R2_enable), //i
.newBit (R2_newBit), //o
.clk (clk ), //i
.reset (reset ) //i
);
LSFR_2 R3 (
.load (load ), //i
.loadIt (loadR3 ), //i
.enable (R3_enable), //i
.newBit (R3_newBit), //o
.clk (clk ), //i
.reset (reset ) //i
);
assign loadR1 = (loadIt == 2'b01);
assign loadR2 = (loadIt == 2'b10);
assign loadR3 = (loadIt == 2'b11);
assign R1_enable = (enable || loadR1);
assign R2_enable = ((enable && R1_newBit) || loadR2);
assign R3_enable = ((enable && (! R1_newBit)) || loadR3);
assign newBit = (R2_newBit ^ R3_newBit);
endmodule
module LSFR_2 (
input wire load,
input wire loadIt,
input wire enable,
output wire newBit,
input wire clk,
input wire reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module LSFR_1 (
input wire load,
input wire loadIt,
input wire enable,
output wire newBit,
input wire clk,
input wire reset
);
wire [62:0] fsRegN;
reg [62:0] fsReg;
wire taps_0;
wire taps_1;
reg genBit;
assign taps_0 = fsReg[0];
assign taps_1 = fsReg[62];
always @(*) begin
genBit = (taps_0 ^ taps_1);
if(loadIt) begin
genBit = load;
end
end
assign newBit = fsReg[0];
assign fsRegN = {genBit,fsReg[62 : 1]};
always @(posedge clk) begin
if(reset) begin
fsReg <= 63'h0000000000000000;
end else begin
if(enable) begin
fsReg <= fsRegN;
end
end
end
endmodule
module LSFR (
input wire load,
input wire loadIt,
input wire enable,
output wire newBit,
input wire clk,
input wire reset
);
wire [30:0] fsRegN;
reg [30:0] fsReg;
wire taps_0;
wire taps_1;
reg genBit;
assign taps_0 = fsReg[0];
assign taps_1 = fsReg[28];
always @(*) begin
genBit = (taps_0 ^ taps_1);
if(loadIt) begin
genBit = load;
end
end
assign newBit = fsReg[0];
assign fsRegN = {genBit,fsReg[30 : 1]};
always @(posedge clk) begin
if(reset) begin
fsReg <= 31'h00000000;
end else begin
if(enable) begin
fsReg <= fsRegN;
end
end
end
endmodule
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_example (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in
assign uio_out = 0;
assign uio_oe = 0;
endmodule
|
module LSFR_2 (
input wire load,
input wire loadIt,
input wire enable,
output wire newBit,
input wire clk,
input wire reset
);
wire [88:0] fsRegN;
reg [88:0] fsReg;
wire taps_0;
wire taps_1;
reg genBit;
assign taps_0 = fsReg[0];
assign taps_1 = fsReg[51];
always @(*) begin
genBit = (taps_0 ^ taps_1);
if(loadIt) begin
genBit = load;
end
end
assign newBit = fsReg[0];
assign fsRegN = {genBit,fsReg[88 : 1]};
always @(posedge clk) begin
if(reset) begin
fsReg <= 89'h00000000000000000000000;
end else begin
if(enable) begin
fsReg <= fsRegN;
end
end
end
endmodule
|
tt06-finale_0035
|
tt06-finale
|
SteffenReith-TT06_ASG
|
task_tt_um_SteffenReith_ASGTop
|
tt_um_SteffenReith_ASGTop
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Steffen Reith
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_SteffenReith_ASGTop (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
// Generator : SpinalHDL v1.10.1 git head : 2527c7c6b0fb0f95e5e1a5722a0be732b364ce43
// Component : ASG
// Git hash : ddaf840b8cb4ff1c649e316de111050773741fb0
`timescale 1ns/1ps
module ASG (
input wire [1:0] loadIt,
input wire load,
input wire enable,
output wire newBit,
input wire clk,
input wire reset
);
wire R1_enable;
wire R2_enable;
wire R3_enable;
wire R1_newBit;
wire R2_newBit;
wire R3_newBit;
wire loadR1;
wire loadR2;
wire loadR3;
LSFR R1 (
.load (load ), //i
.loadIt (loadR1 ), //i
.enable (R1_enable), //i
.newBit (R1_newBit), //o
.clk (clk ), //i
.reset (reset ) //i
);
LSFR_1 R2 (
.load (load ), //i
.loadIt (loadR2 ), //i
.enable (R2_enable), //i
.newBit (R2_newBit), //o
.clk (clk ), //i
.reset (reset ) //i
);
LSFR_2 R3 (
.load (load ), //i
.loadIt (loadR3 ), //i
.enable (R3_enable), //i
.newBit (R3_newBit), //o
.clk (clk ), //i
.reset (reset ) //i
);
assign loadR1 = (loadIt == 2'b01);
assign loadR2 = (loadIt == 2'b10);
assign loadR3 = (loadIt == 2'b11);
assign R1_enable = (enable || loadR1);
assign R2_enable = ((enable && R1_newBit) || loadR2);
assign R3_enable = ((enable && (! R1_newBit)) || loadR3);
assign newBit = (R2_newBit ^ R3_newBit);
endmodule
module LSFR_2 (
input wire load,
input wire loadIt,
input wire enable,
output wire newBit,
input wire clk,
input wire reset
);
wire [88:0] fsRegN;
reg [88:0] fsReg;
wire taps_0;
wire taps_1;
reg genBit;
assign taps_0 = fsReg[0];
assign taps_1 = fsReg[51];
always @(*) begin
genBit = (taps_0 ^ taps_1);
if(loadIt) begin
genBit = load;
end
end
assign newBit = fsReg[0];
assign fsRegN = {genBit,fsReg[88 : 1]};
always @(posedge clk) begin
if(reset) begin
fsReg <= 89'h00000000000000000000000;
end else begin
if(enable) begin
fsReg <= fsRegN;
end
end
end
endmodule
module LSFR_1 (
input wire load,
input wire loadIt,
input wire enable,
output wire newBit,
input wire clk,
input wire reset
);
wire [62:0] fsRegN;
reg [62:0] fsReg;
wire taps_0;
wire taps_1;
reg genBit;
assign taps_0 = fsReg[0];
assign taps_1 = fsReg[62];
always @(*) begin
genBit = (taps_0 ^ taps_1);
if(loadIt) begin
genBit = load;
end
end
assign newBit = fsReg[0];
assign fsRegN = {genBit,fsReg[62 : 1]};
always @(posedge clk) begin
if(reset) begin
fsReg <= 63'h0000000000000000;
end else begin
if(enable) begin
fsReg <= fsRegN;
end
end
end
endmodule
module LSFR (
input wire load,
input wire loadIt,
input wire enable,
output wire newBit,
input wire clk,
input wire reset
);
wire [30:0] fsRegN;
reg [30:0] fsReg;
wire taps_0;
wire taps_1;
reg genBit;
assign taps_0 = fsReg[0];
assign taps_1 = fsReg[28];
always @(*) begin
genBit = (taps_0 ^ taps_1);
if(loadIt) begin
genBit = load;
end
end
assign newBit = fsReg[0];
assign fsRegN = {genBit,fsReg[30 : 1]};
always @(posedge clk) begin
if(reset) begin
fsReg <= 31'h00000000;
end else begin
if(enable) begin
fsReg <= fsRegN;
end
end
end
endmodule
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_example (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in
assign uio_out = 0;
assign uio_oe = 0;
endmodule
|
module tt_um_SteffenReith_ASGTop (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// A reset signal for the ASG
wire reset = !(rst_n && ena);
// Don't use the IOs as outputs
assign uio_out = 8'b0000_0000;
// Set the directions for the IOs (unused at all)
assign uio_oe = 8'bZZZZ_ZZZZ;
// Set unused outputs to Z
assign uo_out[7:1] = 7'bZZZZ_ZZZ;
//Instantiate the ASG and connect the signals
ASG asg (
.loadIt(ui_in[1:0]),
.load(ui_in[2]),
.enable(ui_in[3]),
.newBit(uo_out[0]),
.reset(reset),
.clk(clk)
);
endmodule
|
tt06-finale_0036
|
tt06-finale
|
SteffenReith-TT06_PiMac
|
task_PiMAC
|
tt_um_SteffenReith_PiMACTop
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
// Generator : SpinalHDL v1.10.1 git head : 2527c7c6b0fb0f95e5e1a5722a0be732b364ce43
// Component : PiMAC
// Git hash : 82e1b4b4426cb20a6f387f1686876bda014c9247
`timescale 1ns/1ps
module PiMAC (
input wire [3:0] a,
input wire [3:0] b,
input wire [3:0] c,
output wire [7:0] result,
input wire clk,
input wire reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
/*
* Copyright (c) 2024 Steffen Reith
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_SteffenReith_PiMACTop (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// A reset signal for the MAC-unit
wire reset = !(rst_n && ena);
// Don't use the IOs as outputs
assign uio_out = 8'b0000_0000;
// Set the directions for the IOs
assign uio_oe = 8'bZZZZ_0000;
//Instantiate the PiMAC and connect the signals
PiMAC piMAC (
.a(ui_in[3:0]),
.b(ui_in[7:4]),
.c(uio_in[3:0]),
.result(uo_out),
.reset(reset),
.clk(clk)
);
endmodule
|
module PiMAC (
input wire [3:0] a,
input wire [3:0] b,
input wire [3:0] c,
output wire [7:0] result,
input wire clk,
input wire reset
);
wire [4:0] _zz_nodes_1_ACC_1;
wire [5:0] _zz_nodes_2_ACC_2;
wire [6:0] _zz_nodes_3_ACC_3;
reg [3:0] nodes_3_B;
reg [3:0] nodes_3_A;
reg [6:0] nodes_3_ACC_2;
wire [7:0] nodes_3_ACC_3;
reg [3:0] nodes_2_B;
reg [3:0] nodes_2_A;
reg [5:0] nodes_2_ACC_1;
wire [6:0] nodes_2_ACC_2;
reg [3:0] nodes_1_B;
reg [3:0] nodes_1_A;
reg [4:0] nodes_1_ACC_0;
wire [5:0] nodes_1_ACC_1;
wire [4:0] nodes_0_ACC_0;
wire [3:0] nodes_0_C;
wire [3:0] nodes_0_B;
wire [3:0] nodes_0_A;
assign _zz_nodes_1_ACC_1 = ({1'd0,nodes_1_A} <<< 1'd1);
assign _zz_nodes_2_ACC_2 = ({2'd0,nodes_2_A} <<< 2'd2);
assign _zz_nodes_3_ACC_3 = ({3'd0,nodes_3_A} <<< 2'd3);
assign nodes_0_A = a;
assign nodes_0_B = b;
assign nodes_0_C = c;
assign nodes_0_ACC_0 = ({1'b0,nodes_0_C} + {1'b0,(nodes_0_B[0] ? nodes_0_A : 4'b0000)});
assign nodes_1_ACC_1 = ({1'b0,nodes_1_ACC_0} + {1'b0,(nodes_1_B[1] ? _zz_nodes_1_ACC_1 : 5'h00)});
assign nodes_2_ACC_2 = ({1'b0,nodes_2_ACC_1} + {1'b0,(nodes_2_B[2] ? _zz_nodes_2_ACC_2 : 6'h00)});
assign nodes_3_ACC_3 = ({1'b0,nodes_3_ACC_2} + {1'b0,(nodes_3_B[3] ? _zz_nodes_3_ACC_3 : 7'h00)});
assign result = nodes_3_ACC_3;
always @(posedge clk) begin
nodes_1_A <= nodes_0_A;
nodes_1_B <= nodes_0_B;
nodes_1_ACC_0 <= nodes_0_ACC_0;
nodes_2_A <= nodes_1_A;
nodes_2_B <= nodes_1_B;
nodes_2_ACC_1 <= nodes_1_ACC_1;
nodes_3_A <= nodes_2_A;
nodes_3_B <= nodes_2_B;
nodes_3_ACC_2 <= nodes_2_ACC_2;
end
endmodule
|
tt06-finale_0037
|
tt06-finale
|
SteffenReith-TT06_PiMac
|
task_tt_um_SteffenReith_PiMACTop
|
tt_um_SteffenReith_PiMACTop
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
// Generator : SpinalHDL v1.10.1 git head : 2527c7c6b0fb0f95e5e1a5722a0be732b364ce43
// Component : PiMAC
// Git hash : 82e1b4b4426cb20a6f387f1686876bda014c9247
`timescale 1ns/1ps
module PiMAC (
input wire [3:0] a,
input wire [3:0] b,
input wire [3:0] c,
output wire [7:0] result,
input wire clk,
input wire reset
);
wire [4:0] _zz_nodes_1_ACC_1;
wire [5:0] _zz_nodes_2_ACC_2;
wire [6:0] _zz_nodes_3_ACC_3;
reg [3:0] nodes_3_B;
reg [3:0] nodes_3_A;
reg [6:0] nodes_3_ACC_2;
wire [7:0] nodes_3_ACC_3;
reg [3:0] nodes_2_B;
reg [3:0] nodes_2_A;
reg [5:0] nodes_2_ACC_1;
wire [6:0] nodes_2_ACC_2;
reg [3:0] nodes_1_B;
reg [3:0] nodes_1_A;
reg [4:0] nodes_1_ACC_0;
wire [5:0] nodes_1_ACC_1;
wire [4:0] nodes_0_ACC_0;
wire [3:0] nodes_0_C;
wire [3:0] nodes_0_B;
wire [3:0] nodes_0_A;
assign _zz_nodes_1_ACC_1 = ({1'd0,nodes_1_A} <<< 1'd1);
assign _zz_nodes_2_ACC_2 = ({2'd0,nodes_2_A} <<< 2'd2);
assign _zz_nodes_3_ACC_3 = ({3'd0,nodes_3_A} <<< 2'd3);
assign nodes_0_A = a;
assign nodes_0_B = b;
assign nodes_0_C = c;
assign nodes_0_ACC_0 = ({1'b0,nodes_0_C} + {1'b0,(nodes_0_B[0] ? nodes_0_A : 4'b0000)});
assign nodes_1_ACC_1 = ({1'b0,nodes_1_ACC_0} + {1'b0,(nodes_1_B[1] ? _zz_nodes_1_ACC_1 : 5'h00)});
assign nodes_2_ACC_2 = ({1'b0,nodes_2_ACC_1} + {1'b0,(nodes_2_B[2] ? _zz_nodes_2_ACC_2 : 6'h00)});
assign nodes_3_ACC_3 = ({1'b0,nodes_3_ACC_2} + {1'b0,(nodes_3_B[3] ? _zz_nodes_3_ACC_3 : 7'h00)});
assign result = nodes_3_ACC_3;
always @(posedge clk) begin
nodes_1_A <= nodes_0_A;
nodes_1_B <= nodes_0_B;
nodes_1_ACC_0 <= nodes_0_ACC_0;
nodes_2_A <= nodes_1_A;
nodes_2_B <= nodes_1_B;
nodes_2_ACC_1 <= nodes_1_ACC_1;
nodes_3_A <= nodes_2_A;
nodes_3_B <= nodes_2_B;
nodes_3_ACC_2 <= nodes_2_ACC_2;
end
endmodule
/*
* Copyright (c) 2024 Steffen Reith
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_SteffenReith_PiMACTop (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
|
module tt_um_SteffenReith_PiMACTop (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// A reset signal for the MAC-unit
wire reset = !(rst_n && ena);
// Don't use the IOs as outputs
assign uio_out = 8'b0000_0000;
// Set the directions for the IOs
assign uio_oe = 8'bZZZZ_0000;
//Instantiate the PiMAC and connect the signals
PiMAC piMAC (
.a(ui_in[3:0]),
.b(ui_in[7:4]),
.c(uio_in[3:0]),
.result(uo_out),
.reset(reset),
.clk(clk)
);
endmodule
|
tt06-finale_0038
|
tt06-finale
|
ThorKn-TT06_AudioChip_V2
|
task_PWMaudio
|
tt_um_thorkn_audiochip_v2
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Thorsten Knoll
* SPDX-License-Identifier: Apache-2.0
*/
`timescale 1ns/1ps
`define default_netname none
module tt_um_thorkn_audiochip_v2 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
wire pwm_1_out;
wire pwm_2_out;
wire [11:0] frequency;
wire reset;
assign reset = !rst_n;
assign frequency = {uio_in[7:4],ui_in[7:0]};
PWMaudio pwm_audio (
.io_pwm_1 (pwm_1_out ), //o
.io_pwm_2 (pwm_2_out ), //o
.io_frequency (frequency ), //i
.io_adsr_switch (uio_in[3] ), //i
.io_adsr_choice (uio_in[2:0] ), //i
.clk (clk ), //i
.reset (reset ) //i
);
// All output pins must be assigned. If not used, assign to 0.
assign uo_out = {6'b0000_00, pwm_2_out, pwm_1_out};
assign uio_out = 8'b0000_0000;
assign uio_oe = 8'b0000_0000;
endmodule
module PWMaudio (
output io_pwm_1,
output io_pwm_2,
input [11:0] io_frequency,
input io_adsr_switch,
input [2:0] io_adsr_choice,
input clk,
input reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module PWMctrl (
input [11:0] io_freq,
input [7:0] io_level,
output io_pwm_1,
output io_pwm_2,
input clk,
input reset
);
wire pwmdriver_1_1_io_pwm;
wire pwmdriver_2_io_pwm;
wire [11:0] _zz_freq_counter_valueNext;
wire [0:0] _zz_freq_counter_valueNext_1;
wire [7:0] _zz_pwm_steps_counter_valueNext;
wire [0:0] _zz_pwm_steps_counter_valueNext_1;
reg freq_counter_willIncrement;
reg freq_counter_willClear;
reg [11:0] freq_counter_valueNext;
reg [11:0] freq_counter_value;
wire freq_counter_willOverflowIfInc;
wire freq_counter_willOverflow;
reg pwm_steps_counter_willIncrement;
wire pwm_steps_counter_willClear;
reg [7:0] pwm_steps_counter_valueNext;
reg [7:0] pwm_steps_counter_value;
wire pwm_steps_counter_willOverflowIfInc;
wire pwm_steps_counter_willOverflow;
reg [7:0] duty_cycle_1;
wire when_PWMctrl_l23;
wire when_PWMctrl_l29;
function zz_freq_counter_willIncrement(input dummy);
begin
zz_freq_counter_willIncrement = 1'b0;
zz_freq_counter_willIncrement = 1'b1;
end
endfunction
wire _zz_1;
assign _zz_freq_counter_valueNext_1 = freq_counter_willIncrement;
assign _zz_freq_counter_valueNext = {11'd0, _zz_freq_counter_valueNext_1};
assign _zz_pwm_steps_counter_valueNext_1 = pwm_steps_counter_willIncrement;
assign _zz_pwm_steps_counter_valueNext = {7'd0, _zz_pwm_steps_counter_valueNext_1};
PWMdriver pwmdriver_1_1 (
.io_dutyCycle (duty_cycle_1[7:0] ), //i
.io_pwm (pwmdriver_1_1_io_pwm ), //o
.clk (clk ), //i
.reset (reset ) //i
);
PWMdriver pwmdriver_2 (
.io_dutyCycle (pwm_steps_counter_value[7:0] ), //i
.io_pwm (pwmdriver_2_io_pwm ), //o
.clk (clk ), //i
.reset (reset ) //i
);
assign _zz_1 = zz_freq_counter_willIncrement(1'b0);
always @(*) freq_counter_willIncrement = _zz_1;
always @(*) begin
freq_counter_willClear = 1'b0;
if(when_PWMctrl_l23) begin
freq_counter_willClear = 1'b1;
end
end
assign freq_counter_willOverflowIfInc = (freq_counter_value == 12'hfff);
assign freq_counter_willOverflow = (freq_counter_willOverflowIfInc && freq_counter_willIncrement);
always @(*) begin
freq_counter_valueNext = (freq_counter_value + _zz_freq_counter_valueNext);
if(freq_counter_willClear) begin
freq_counter_valueNext = 12'h0;
end
end
always @(*) begin
pwm_steps_counter_willIncrement = 1'b0;
if(when_PWMctrl_l23) begin
pwm_steps_counter_willIncrement = 1'b1;
end
end
assign pwm_steps_counter_willClear = 1'b0;
assign pwm_steps_counter_willOverflowIfInc = (pwm_steps_counter_value == 8'hff);
assign pwm_steps_counter_willOverflow = (pwm_steps_counter_willOverflowIfInc && pwm_steps_counter_willIncrement);
always @(*) begin
pwm_steps_counter_valueNext = (pwm_steps_counter_value + _zz_pwm_steps_counter_valueNext);
if(pwm_steps_counter_willClear) begin
pwm_steps_counter_valueNext = 8'h0;
end
end
assign io_pwm_1 = pwmdriver_1_1_io_pwm;
assign when_PWMctrl_l23 = (freq_counter_value == io_freq);
assign when_PWMctrl_l29 = (pwm_steps_counter_value < 8'h7f);
always @(*) begin
if(when_PWMctrl_l29) begin
duty_cycle_1 = 8'h0;
end else begin
duty_cycle_1 = io_level;
end
end
assign io_pwm_2 = pwmdriver_2_io_pwm;
always @(posedge clk or posedge reset) begin
if(reset) begin
freq_counter_value <= 12'h0;
pwm_steps_counter_value <= 8'h0;
end else begin
freq_counter_value <= freq_counter_valueNext;
pwm_steps_counter_value <= pwm_steps_counter_valueNext;
end
end
endmodule
//PWMdriver replaced by PWMdriver
module PWMdriver (
input [7:0] io_dutyCycle,
output io_pwm,
input clk,
input reset
);
wire [7:0] _zz_counter_valueNext;
wire [0:0] _zz_counter_valueNext_1;
reg counter_willIncrement;
wire counter_willClear;
reg [7:0] counter_valueNext;
reg [7:0] counter_value;
wire counter_willOverflowIfInc;
wire counter_willOverflow;
function zz_counter_willIncrement(input dummy);
begin
zz_counter_willIncrement = 1'b0;
zz_counter_willIncrement = 1'b1;
end
endfunction
wire _zz_1;
assign _zz_counter_valueNext_1 = counter_willIncrement;
assign _zz_counter_valueNext = {7'd0, _zz_counter_valueNext_1};
assign _zz_1 = zz_counter_willIncrement(1'b0);
always @(*) counter_willIncrement = _zz_1;
assign counter_willClear = 1'b0;
assign counter_willOverflowIfInc = (counter_value == 8'hff);
assign counter_willOverflow = (counter_willOverflowIfInc && counter_willIncrement);
always @(*) begin
counter_valueNext = (counter_value + _zz_counter_valueNext);
if(counter_willClear) begin
counter_valueNext = 8'h0;
end
end
assign io_pwm = (counter_value < io_dutyCycle);
always @(posedge clk or posedge reset) begin
if(reset) begin
counter_value <= 8'h0;
end else begin
counter_value <= counter_valueNext;
end
end
endmodule
|
module PWMaudio (
output io_pwm_1,
output io_pwm_2,
input [11:0] io_frequency,
input io_adsr_switch,
input [2:0] io_adsr_choice,
input clk,
input reset
);
localparam fsm_adsr_enumDef_BOOT = 3'd0;
localparam fsm_adsr_enumDef_stateEntry = 3'd1;
localparam fsm_adsr_enumDef_stateAttack = 3'd2;
localparam fsm_adsr_enumDef_stateDelay = 3'd3;
localparam fsm_adsr_enumDef_stateSustain = 3'd4;
localparam fsm_adsr_enumDef_stateRelease = 3'd5;
wire [11:0] pwm_ctrl_io_freq;
reg [7:0] pwm_ctrl_io_level;
wire pwm_ctrl_io_pwm_1;
wire pwm_ctrl_io_pwm_2;
reg [23:0] adsr1;
reg [23:0] adsr2;
reg [23:0] adsr3;
reg [23:0] adsr4;
wire [2:0] switch_PWMaudio_l25;
wire fsm_adsr_wantExit;
reg fsm_adsr_wantStart;
wire fsm_adsr_wantKill;
reg [23:0] fsm_adsr_counter;
reg [7:0] fsm_adsr_level_adsr;
reg [2:0] fsm_adsr_stateReg;
reg [2:0] fsm_adsr_stateNext;
wire when_PWMaudio_l110;
wire when_PWMaudio_l114;
wire when_PWMaudio_l124;
wire when_PWMaudio_l128;
wire when_PWMaudio_l139;
wire when_PWMaudio_l149;
wire when_PWMaudio_l153;
wire when_StateMachine_l238;
wire when_StateMachine_l238_1;
wire when_StateMachine_l238_2;
wire when_StateMachine_l238_3;
`ifndef SYNTHESIS
reg [95:0] fsm_adsr_stateReg_string;
reg [95:0] fsm_adsr_stateNext_string;
`endif
PWMctrl pwm_ctrl (
.io_freq (pwm_ctrl_io_freq[11:0] ), //i
.io_level (pwm_ctrl_io_level[7:0] ), //i
.io_pwm_1 (pwm_ctrl_io_pwm_1 ), //o
.io_pwm_2 (pwm_ctrl_io_pwm_2 ), //o
.clk (clk ), //i
.reset (reset ) //i
);
`ifndef SYNTHESIS
always @(*) begin
case(fsm_adsr_stateReg)
fsm_adsr_enumDef_BOOT : fsm_adsr_stateReg_string = "BOOT ";
fsm_adsr_enumDef_stateEntry : fsm_adsr_stateReg_string = "stateEntry ";
fsm_adsr_enumDef_stateAttack : fsm_adsr_stateReg_string = "stateAttack ";
fsm_adsr_enumDef_stateDelay : fsm_adsr_stateReg_string = "stateDelay ";
fsm_adsr_enumDef_stateSustain : fsm_adsr_stateReg_string = "stateSustain";
fsm_adsr_enumDef_stateRelease : fsm_adsr_stateReg_string = "stateRelease";
default : fsm_adsr_stateReg_string = "????????????";
endcase
end
always @(*) begin
case(fsm_adsr_stateNext)
fsm_adsr_enumDef_BOOT : fsm_adsr_stateNext_string = "BOOT ";
fsm_adsr_enumDef_stateEntry : fsm_adsr_stateNext_string = "stateEntry ";
fsm_adsr_enumDef_stateAttack : fsm_adsr_stateNext_string = "stateAttack ";
fsm_adsr_enumDef_stateDelay : fsm_adsr_stateNext_string = "stateDelay ";
fsm_adsr_enumDef_stateSustain : fsm_adsr_stateNext_string = "stateSustain";
fsm_adsr_enumDef_stateRelease : fsm_adsr_stateNext_string = "stateRelease";
default : fsm_adsr_stateNext_string = "????????????";
endcase
end
`endif
assign switch_PWMaudio_l25 = io_adsr_choice;
always @(*) begin
case(switch_PWMaudio_l25)
3'b000 : begin
adsr1 = 24'h000032;
end
3'b001 : begin
adsr1 = 24'h000032;
end
3'b010 : begin
adsr1 = 24'h00000a;
end
3'b011 : begin
adsr1 = 24'h00000a;
end
3'b100 : begin
adsr1 = 24'h0003e8;
end
3'b101 : begin
adsr1 = 24'h0003e8;
end
3'b110 : begin
adsr1 = 24'h001388;
end
default : begin
adsr1 = 24'h001388;
end
endcase
end
always @(*) begin
case(switch_PWMaudio_l25)
3'b000 : begin
adsr2 = 24'h000064;
end
3'b001 : begin
adsr2 = 24'h0001f4;
end
3'b010 : begin
adsr2 = 24'h0005dc;
end
3'b011 : begin
adsr2 = 24'h0007d0;
end
3'b100 : begin
adsr2 = 24'h000064;
end
3'b101 : begin
adsr2 = 24'h0007d0;
end
3'b110 : begin
adsr2 = 24'h0003e8;
end
default : begin
adsr2 = 24'h001388;
end
endcase
end
always @(*) begin
case(switch_PWMaudio_l25)
3'b000 : begin
adsr3 = 24'h0001f4;
end
3'b001 : begin
adsr3 = 24'h0001f4;
end
3'b010 : begin
adsr3 = 24'h0003e8;
end
3'b011 : begin
adsr3 = 24'h0005dc;
end
3'b100 : begin
adsr3 = 24'h0007d0;
end
3'b101 : begin
adsr3 = 24'h0007d0;
end
3'b110 : begin
adsr3 = 24'h0001f4;
end
default : begin
adsr3 = 24'h0003e8;
end
endcase
end
always @(*) begin
case(switch_PWMaudio_l25)
3'b000 : begin
adsr4 = 24'h000064;
end
3'b001 : begin
adsr4 = 24'h000064;
end
3'b010 : begin
adsr4 = 24'h000190;
end
3'b011 : begin
adsr4 = 24'h000190;
end
3'b100 : begin
adsr4 = 24'h000190;
end
3'b101 : begin
adsr4 = 24'h0003e8;
end
3'b110 : begin
adsr4 = 24'h000190;
end
default : begin
adsr4 = 24'h002710;
end
endcase
end
assign io_pwm_1 = pwm_ctrl_io_pwm_1;
assign io_pwm_2 = pwm_ctrl_io_pwm_2;
assign pwm_ctrl_io_freq = io_frequency;
assign fsm_adsr_wantExit = 1'b0;
always @(*) begin
fsm_adsr_wantStart = 1'b0;
case(fsm_adsr_stateReg)
fsm_adsr_enumDef_stateEntry : begin
end
fsm_adsr_enumDef_stateAttack : begin
end
fsm_adsr_enumDef_stateDelay : begin
end
fsm_adsr_enumDef_stateSustain : begin
end
fsm_adsr_enumDef_stateRelease : begin
end
default : begin
fsm_adsr_wantStart = 1'b1;
end
endcase
end
assign fsm_adsr_wantKill = 1'b0;
always @(*) begin
if(io_adsr_switch) begin
pwm_ctrl_io_level = fsm_adsr_level_adsr;
end else begin
pwm_ctrl_io_level = 8'hff;
end
end
always @(*) begin
fsm_adsr_stateNext = fsm_adsr_stateReg;
case(fsm_adsr_stateReg)
fsm_adsr_enumDef_stateEntry : begin
fsm_adsr_stateNext = fsm_adsr_enumDef_stateAttack;
end
fsm_adsr_enumDef_stateAttack : begin
if(when_PWMaudio_l114) begin
fsm_adsr_stateNext = fsm_adsr_enumDef_stateDelay;
end
end
fsm_adsr_enumDef_stateDelay : begin
if(when_PWMaudio_l128) begin
fsm_adsr_stateNext = fsm_adsr_enumDef_stateSustain;
end
end
fsm_adsr_enumDef_stateSustain : begin
if(when_PWMaudio_l139) begin
fsm_adsr_stateNext = fsm_adsr_enumDef_stateRelease;
end
end
fsm_adsr_enumDef_stateRelease : begin
if(when_PWMaudio_l153) begin
fsm_adsr_stateNext = fsm_adsr_enumDef_stateEntry;
end
end
default : begin
end
endcase
if(fsm_adsr_wantStart) begin
fsm_adsr_stateNext = fsm_adsr_enumDef_stateEntry;
end
if(fsm_adsr_wantKill) begin
fsm_adsr_stateNext = fsm_adsr_enumDef_BOOT;
end
end
assign when_PWMaudio_l110 = (adsr1 <= fsm_adsr_counter);
assign when_PWMaudio_l114 = (fsm_adsr_level_adsr == 8'hff);
assign when_PWMaudio_l124 = (adsr2 <= fsm_adsr_counter);
assign when_PWMaudio_l128 = (fsm_adsr_level_adsr == 8'h7f);
assign when_PWMaudio_l139 = (adsr3 <= fsm_adsr_counter);
assign when_PWMaudio_l149 = (adsr4 <= fsm_adsr_counter);
assign when_PWMaudio_l153 = (fsm_adsr_level_adsr == 8'h0);
assign when_StateMachine_l238 = ((! (fsm_adsr_stateReg == fsm_adsr_enumDef_stateAttack)) && (fsm_adsr_stateNext == fsm_adsr_enumDef_stateAttack));
assign when_StateMachine_l238_1 = ((! (fsm_adsr_stateReg == fsm_adsr_enumDef_stateDelay)) && (fsm_adsr_stateNext == fsm_adsr_enumDef_stateDelay));
assign when_StateMachine_l238_2 = ((! (fsm_adsr_stateReg == fsm_adsr_enumDef_stateSustain)) && (fsm_adsr_stateNext == fsm_adsr_enumDef_stateSustain));
assign when_StateMachine_l238_3 = ((! (fsm_adsr_stateReg == fsm_adsr_enumDef_stateRelease)) && (fsm_adsr_stateNext == fsm_adsr_enumDef_stateRelease));
always @(posedge clk or posedge reset) begin
if(reset) begin
fsm_adsr_counter <= 24'h0;
fsm_adsr_level_adsr <= 8'h0;
fsm_adsr_stateReg <= fsm_adsr_enumDef_BOOT;
end else begin
fsm_adsr_stateReg <= fsm_adsr_stateNext;
case(fsm_adsr_stateReg)
fsm_adsr_enumDef_stateEntry : begin
end
fsm_adsr_enumDef_stateAttack : begin
fsm_adsr_counter <= (fsm_adsr_counter + 24'h000001);
if(when_PWMaudio_l110) begin
fsm_adsr_level_adsr <= (fsm_adsr_level_adsr + 8'h01);
fsm_adsr_counter <= 24'h0;
end
end
fsm_adsr_enumDef_stateDelay : begin
fsm_adsr_counter <= (fsm_adsr_counter + 24'h000001);
if(when_PWMaudio_l124) begin
fsm_adsr_level_adsr <= (fsm_adsr_level_adsr - 8'h01);
fsm_adsr_counter <= 24'h0;
end
end
fsm_adsr_enumDef_stateSustain : begin
fsm_adsr_counter <= (fsm_adsr_counter + 24'h000001);
fsm_adsr_level_adsr <= 8'h7f;
end
fsm_adsr_enumDef_stateRelease : begin
fsm_adsr_counter <= (fsm_adsr_counter + 24'h000001);
if(when_PWMaudio_l149) begin
fsm_adsr_level_adsr <= (fsm_adsr_level_adsr - 8'h01);
fsm_adsr_counter <= 24'h0;
end
end
default : begin
end
endcase
if(when_StateMachine_l238) begin
fsm_adsr_counter <= 24'h0;
end
if(when_StateMachine_l238_1) begin
fsm_adsr_counter <= 24'h0;
end
if(when_StateMachine_l238_2) begin
fsm_adsr_counter <= 24'h0;
end
if(when_StateMachine_l238_3) begin
fsm_adsr_counter <= 24'h0;
end
end
end
endmodule
|
tt06-finale_0039
|
tt06-finale
|
ThorKn-TT06_AudioChip_V2
|
task_PWMctrl
|
tt_um_thorkn_audiochip_v2
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Thorsten Knoll
* SPDX-License-Identifier: Apache-2.0
*/
`timescale 1ns/1ps
`define default_netname none
module tt_um_thorkn_audiochip_v2 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
wire pwm_1_out;
wire pwm_2_out;
wire [11:0] frequency;
wire reset;
assign reset = !rst_n;
assign frequency = {uio_in[7:4],ui_in[7:0]};
PWMaudio pwm_audio (
.io_pwm_1 (pwm_1_out ), //o
.io_pwm_2 (pwm_2_out ), //o
.io_frequency (frequency ), //i
.io_adsr_switch (uio_in[3] ), //i
.io_adsr_choice (uio_in[2:0] ), //i
.clk (clk ), //i
.reset (reset ) //i
);
// All output pins must be assigned. If not used, assign to 0.
assign uo_out = {6'b0000_00, pwm_2_out, pwm_1_out};
assign uio_out = 8'b0000_0000;
assign uio_oe = 8'b0000_0000;
endmodule
module PWMaudio (
output io_pwm_1,
output io_pwm_2,
input [11:0] io_frequency,
input io_adsr_switch,
input [2:0] io_adsr_choice,
input clk,
input reset
);
localparam fsm_adsr_enumDef_BOOT = 3'd0;
localparam fsm_adsr_enumDef_stateEntry = 3'd1;
localparam fsm_adsr_enumDef_stateAttack = 3'd2;
localparam fsm_adsr_enumDef_stateDelay = 3'd3;
localparam fsm_adsr_enumDef_stateSustain = 3'd4;
localparam fsm_adsr_enumDef_stateRelease = 3'd5;
wire [11:0] pwm_ctrl_io_freq;
reg [7:0] pwm_ctrl_io_level;
wire pwm_ctrl_io_pwm_1;
wire pwm_ctrl_io_pwm_2;
reg [23:0] adsr1;
reg [23:0] adsr2;
reg [23:0] adsr3;
reg [23:0] adsr4;
wire [2:0] switch_PWMaudio_l25;
wire fsm_adsr_wantExit;
reg fsm_adsr_wantStart;
wire fsm_adsr_wantKill;
reg [23:0] fsm_adsr_counter;
reg [7:0] fsm_adsr_level_adsr;
reg [2:0] fsm_adsr_stateReg;
reg [2:0] fsm_adsr_stateNext;
wire when_PWMaudio_l110;
wire when_PWMaudio_l114;
wire when_PWMaudio_l124;
wire when_PWMaudio_l128;
wire when_PWMaudio_l139;
wire when_PWMaudio_l149;
wire when_PWMaudio_l153;
wire when_StateMachine_l238;
wire when_StateMachine_l238_1;
wire when_StateMachine_l238_2;
wire when_StateMachine_l238_3;
`ifndef SYNTHESIS
reg [95:0] fsm_adsr_stateReg_string;
reg [95:0] fsm_adsr_stateNext_string;
`endif
PWMctrl pwm_ctrl (
.io_freq (pwm_ctrl_io_freq[11:0] ), //i
.io_level (pwm_ctrl_io_level[7:0] ), //i
.io_pwm_1 (pwm_ctrl_io_pwm_1 ), //o
.io_pwm_2 (pwm_ctrl_io_pwm_2 ), //o
.clk (clk ), //i
.reset (reset ) //i
);
`ifndef SYNTHESIS
always @(*) begin
case(fsm_adsr_stateReg)
fsm_adsr_enumDef_BOOT : fsm_adsr_stateReg_string = "BOOT ";
fsm_adsr_enumDef_stateEntry : fsm_adsr_stateReg_string = "stateEntry ";
fsm_adsr_enumDef_stateAttack : fsm_adsr_stateReg_string = "stateAttack ";
fsm_adsr_enumDef_stateDelay : fsm_adsr_stateReg_string = "stateDelay ";
fsm_adsr_enumDef_stateSustain : fsm_adsr_stateReg_string = "stateSustain";
fsm_adsr_enumDef_stateRelease : fsm_adsr_stateReg_string = "stateRelease";
default : fsm_adsr_stateReg_string = "????????????";
endcase
end
always @(*) begin
case(fsm_adsr_stateNext)
fsm_adsr_enumDef_BOOT : fsm_adsr_stateNext_string = "BOOT ";
fsm_adsr_enumDef_stateEntry : fsm_adsr_stateNext_string = "stateEntry ";
fsm_adsr_enumDef_stateAttack : fsm_adsr_stateNext_string = "stateAttack ";
fsm_adsr_enumDef_stateDelay : fsm_adsr_stateNext_string = "stateDelay ";
fsm_adsr_enumDef_stateSustain : fsm_adsr_stateNext_string = "stateSustain";
fsm_adsr_enumDef_stateRelease : fsm_adsr_stateNext_string = "stateRelease";
default : fsm_adsr_stateNext_string = "????????????";
endcase
end
`endif
assign switch_PWMaudio_l25 = io_adsr_choice;
always @(*) begin
case(switch_PWMaudio_l25)
3'b000 : begin
adsr1 = 24'h000032;
end
3'b001 : begin
adsr1 = 24'h000032;
end
3'b010 : begin
adsr1 = 24'h00000a;
end
3'b011 : begin
adsr1 = 24'h00000a;
end
3'b100 : begin
adsr1 = 24'h0003e8;
end
3'b101 : begin
adsr1 = 24'h0003e8;
end
3'b110 : begin
adsr1 = 24'h001388;
end
default : begin
adsr1 = 24'h001388;
end
endcase
end
always @(*) begin
case(switch_PWMaudio_l25)
3'b000 : begin
adsr2 = 24'h000064;
end
3'b001 : begin
adsr2 = 24'h0001f4;
end
3'b010 : begin
adsr2 = 24'h0005dc;
end
3'b011 : begin
adsr2 = 24'h0007d0;
end
3'b100 : begin
adsr2 = 24'h000064;
end
3'b101 : begin
adsr2 = 24'h0007d0;
end
3'b110 : begin
adsr2 = 24'h0003e8;
end
default : begin
adsr2 = 24'h001388;
end
endcase
end
always @(*) begin
case(switch_PWMaudio_l25)
3'b000 : begin
adsr3 = 24'h0001f4;
end
3'b001 : begin
adsr3 = 24'h0001f4;
end
3'b010 : begin
adsr3 = 24'h0003e8;
end
3'b011 : begin
adsr3 = 24'h0005dc;
end
3'b100 : begin
adsr3 = 24'h0007d0;
end
3'b101 : begin
adsr3 = 24'h0007d0;
end
3'b110 : begin
adsr3 = 24'h0001f4;
end
default : begin
adsr3 = 24'h0003e8;
end
endcase
end
always @(*) begin
case(switch_PWMaudio_l25)
3'b000 : begin
adsr4 = 24'h000064;
end
3'b001 : begin
adsr4 = 24'h000064;
end
3'b010 : begin
adsr4 = 24'h000190;
end
3'b011 : begin
adsr4 = 24'h000190;
end
3'b100 : begin
adsr4 = 24'h000190;
end
3'b101 : begin
adsr4 = 24'h0003e8;
end
3'b110 : begin
adsr4 = 24'h000190;
end
default : begin
adsr4 = 24'h002710;
end
endcase
end
assign io_pwm_1 = pwm_ctrl_io_pwm_1;
assign io_pwm_2 = pwm_ctrl_io_pwm_2;
assign pwm_ctrl_io_freq = io_frequency;
assign fsm_adsr_wantExit = 1'b0;
always @(*) begin
fsm_adsr_wantStart = 1'b0;
case(fsm_adsr_stateReg)
fsm_adsr_enumDef_stateEntry : begin
end
fsm_adsr_enumDef_stateAttack : begin
end
fsm_adsr_enumDef_stateDelay : begin
end
fsm_adsr_enumDef_stateSustain : begin
end
fsm_adsr_enumDef_stateRelease : begin
end
default : begin
fsm_adsr_wantStart = 1'b1;
end
endcase
end
assign fsm_adsr_wantKill = 1'b0;
always @(*) begin
if(io_adsr_switch) begin
pwm_ctrl_io_level = fsm_adsr_level_adsr;
end else begin
pwm_ctrl_io_level = 8'hff;
end
end
always @(*) begin
fsm_adsr_stateNext = fsm_adsr_stateReg;
case(fsm_adsr_stateReg)
fsm_adsr_enumDef_stateEntry : begin
fsm_adsr_stateNext = fsm_adsr_enumDef_stateAttack;
end
fsm_adsr_enumDef_stateAttack : begin
if(when_PWMaudio_l114) begin
fsm_adsr_stateNext = fsm_adsr_enumDef_stateDelay;
end
end
fsm_adsr_enumDef_stateDelay : begin
if(when_PWMaudio_l128) begin
fsm_adsr_stateNext = fsm_adsr_enumDef_stateSustain;
end
end
fsm_adsr_enumDef_stateSustain : begin
if(when_PWMaudio_l139) begin
fsm_adsr_stateNext = fsm_adsr_enumDef_stateRelease;
end
end
fsm_adsr_enumDef_stateRelease : begin
if(when_PWMaudio_l153) begin
fsm_adsr_stateNext = fsm_adsr_enumDef_stateEntry;
end
end
default : begin
end
endcase
if(fsm_adsr_wantStart) begin
fsm_adsr_stateNext = fsm_adsr_enumDef_stateEntry;
end
if(fsm_adsr_wantKill) begin
fsm_adsr_stateNext = fsm_adsr_enumDef_BOOT;
end
end
assign when_PWMaudio_l110 = (adsr1 <= fsm_adsr_counter);
assign when_PWMaudio_l114 = (fsm_adsr_level_adsr == 8'hff);
assign when_PWMaudio_l124 = (adsr2 <= fsm_adsr_counter);
assign when_PWMaudio_l128 = (fsm_adsr_level_adsr == 8'h7f);
assign when_PWMaudio_l139 = (adsr3 <= fsm_adsr_counter);
assign when_PWMaudio_l149 = (adsr4 <= fsm_adsr_counter);
assign when_PWMaudio_l153 = (fsm_adsr_level_adsr == 8'h0);
assign when_StateMachine_l238 = ((! (fsm_adsr_stateReg == fsm_adsr_enumDef_stateAttack)) && (fsm_adsr_stateNext == fsm_adsr_enumDef_stateAttack));
assign when_StateMachine_l238_1 = ((! (fsm_adsr_stateReg == fsm_adsr_enumDef_stateDelay)) && (fsm_adsr_stateNext == fsm_adsr_enumDef_stateDelay));
assign when_StateMachine_l238_2 = ((! (fsm_adsr_stateReg == fsm_adsr_enumDef_stateSustain)) && (fsm_adsr_stateNext == fsm_adsr_enumDef_stateSustain));
assign when_StateMachine_l238_3 = ((! (fsm_adsr_stateReg == fsm_adsr_enumDef_stateRelease)) && (fsm_adsr_stateNext == fsm_adsr_enumDef_stateRelease));
always @(posedge clk or posedge reset) begin
if(reset) begin
fsm_adsr_counter <= 24'h0;
fsm_adsr_level_adsr <= 8'h0;
fsm_adsr_stateReg <= fsm_adsr_enumDef_BOOT;
end else begin
fsm_adsr_stateReg <= fsm_adsr_stateNext;
case(fsm_adsr_stateReg)
fsm_adsr_enumDef_stateEntry : begin
end
fsm_adsr_enumDef_stateAttack : begin
fsm_adsr_counter <= (fsm_adsr_counter + 24'h000001);
if(when_PWMaudio_l110) begin
fsm_adsr_level_adsr <= (fsm_adsr_level_adsr + 8'h01);
fsm_adsr_counter <= 24'h0;
end
end
fsm_adsr_enumDef_stateDelay : begin
fsm_adsr_counter <= (fsm_adsr_counter + 24'h000001);
if(when_PWMaudio_l124) begin
fsm_adsr_level_adsr <= (fsm_adsr_level_adsr - 8'h01);
fsm_adsr_counter <= 24'h0;
end
end
fsm_adsr_enumDef_stateSustain : begin
fsm_adsr_counter <= (fsm_adsr_counter + 24'h000001);
fsm_adsr_level_adsr <= 8'h7f;
end
fsm_adsr_enumDef_stateRelease : begin
fsm_adsr_counter <= (fsm_adsr_counter + 24'h000001);
if(when_PWMaudio_l149) begin
fsm_adsr_level_adsr <= (fsm_adsr_level_adsr - 8'h01);
fsm_adsr_counter <= 24'h0;
end
end
default : begin
end
endcase
if(when_StateMachine_l238) begin
fsm_adsr_counter <= 24'h0;
end
if(when_StateMachine_l238_1) begin
fsm_adsr_counter <= 24'h0;
end
if(when_StateMachine_l238_2) begin
fsm_adsr_counter <= 24'h0;
end
if(when_StateMachine_l238_3) begin
fsm_adsr_counter <= 24'h0;
end
end
end
endmodule
module PWMctrl (
input [11:0] io_freq,
input [7:0] io_level,
output io_pwm_1,
output io_pwm_2,
input clk,
input reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
//PWMdriver replaced by PWMdriver
module PWMdriver (
input [7:0] io_dutyCycle,
output io_pwm,
input clk,
input reset
);
wire [7:0] _zz_counter_valueNext;
wire [0:0] _zz_counter_valueNext_1;
reg counter_willIncrement;
wire counter_willClear;
reg [7:0] counter_valueNext;
reg [7:0] counter_value;
wire counter_willOverflowIfInc;
wire counter_willOverflow;
function zz_counter_willIncrement(input dummy);
begin
zz_counter_willIncrement = 1'b0;
zz_counter_willIncrement = 1'b1;
end
endfunction
wire _zz_1;
assign _zz_counter_valueNext_1 = counter_willIncrement;
assign _zz_counter_valueNext = {7'd0, _zz_counter_valueNext_1};
assign _zz_1 = zz_counter_willIncrement(1'b0);
always @(*) counter_willIncrement = _zz_1;
assign counter_willClear = 1'b0;
assign counter_willOverflowIfInc = (counter_value == 8'hff);
assign counter_willOverflow = (counter_willOverflowIfInc && counter_willIncrement);
always @(*) begin
counter_valueNext = (counter_value + _zz_counter_valueNext);
if(counter_willClear) begin
counter_valueNext = 8'h0;
end
end
assign io_pwm = (counter_value < io_dutyCycle);
always @(posedge clk or posedge reset) begin
if(reset) begin
counter_value <= 8'h0;
end else begin
counter_value <= counter_valueNext;
end
end
endmodule
|
module PWMctrl (
input [11:0] io_freq,
input [7:0] io_level,
output io_pwm_1,
output io_pwm_2,
input clk,
input reset
);
wire pwmdriver_1_1_io_pwm;
wire pwmdriver_2_io_pwm;
wire [11:0] _zz_freq_counter_valueNext;
wire [0:0] _zz_freq_counter_valueNext_1;
wire [7:0] _zz_pwm_steps_counter_valueNext;
wire [0:0] _zz_pwm_steps_counter_valueNext_1;
reg freq_counter_willIncrement;
reg freq_counter_willClear;
reg [11:0] freq_counter_valueNext;
reg [11:0] freq_counter_value;
wire freq_counter_willOverflowIfInc;
wire freq_counter_willOverflow;
reg pwm_steps_counter_willIncrement;
wire pwm_steps_counter_willClear;
reg [7:0] pwm_steps_counter_valueNext;
reg [7:0] pwm_steps_counter_value;
wire pwm_steps_counter_willOverflowIfInc;
wire pwm_steps_counter_willOverflow;
reg [7:0] duty_cycle_1;
wire when_PWMctrl_l23;
wire when_PWMctrl_l29;
function zz_freq_counter_willIncrement(input dummy);
begin
zz_freq_counter_willIncrement = 1'b0;
zz_freq_counter_willIncrement = 1'b1;
end
endfunction
wire _zz_1;
assign _zz_freq_counter_valueNext_1 = freq_counter_willIncrement;
assign _zz_freq_counter_valueNext = {11'd0, _zz_freq_counter_valueNext_1};
assign _zz_pwm_steps_counter_valueNext_1 = pwm_steps_counter_willIncrement;
assign _zz_pwm_steps_counter_valueNext = {7'd0, _zz_pwm_steps_counter_valueNext_1};
PWMdriver pwmdriver_1_1 (
.io_dutyCycle (duty_cycle_1[7:0] ), //i
.io_pwm (pwmdriver_1_1_io_pwm ), //o
.clk (clk ), //i
.reset (reset ) //i
);
PWMdriver pwmdriver_2 (
.io_dutyCycle (pwm_steps_counter_value[7:0] ), //i
.io_pwm (pwmdriver_2_io_pwm ), //o
.clk (clk ), //i
.reset (reset ) //i
);
assign _zz_1 = zz_freq_counter_willIncrement(1'b0);
always @(*) freq_counter_willIncrement = _zz_1;
always @(*) begin
freq_counter_willClear = 1'b0;
if(when_PWMctrl_l23) begin
freq_counter_willClear = 1'b1;
end
end
assign freq_counter_willOverflowIfInc = (freq_counter_value == 12'hfff);
assign freq_counter_willOverflow = (freq_counter_willOverflowIfInc && freq_counter_willIncrement);
always @(*) begin
freq_counter_valueNext = (freq_counter_value + _zz_freq_counter_valueNext);
if(freq_counter_willClear) begin
freq_counter_valueNext = 12'h0;
end
end
always @(*) begin
pwm_steps_counter_willIncrement = 1'b0;
if(when_PWMctrl_l23) begin
pwm_steps_counter_willIncrement = 1'b1;
end
end
assign pwm_steps_counter_willClear = 1'b0;
assign pwm_steps_counter_willOverflowIfInc = (pwm_steps_counter_value == 8'hff);
assign pwm_steps_counter_willOverflow = (pwm_steps_counter_willOverflowIfInc && pwm_steps_counter_willIncrement);
always @(*) begin
pwm_steps_counter_valueNext = (pwm_steps_counter_value + _zz_pwm_steps_counter_valueNext);
if(pwm_steps_counter_willClear) begin
pwm_steps_counter_valueNext = 8'h0;
end
end
assign io_pwm_1 = pwmdriver_1_1_io_pwm;
assign when_PWMctrl_l23 = (freq_counter_value == io_freq);
assign when_PWMctrl_l29 = (pwm_steps_counter_value < 8'h7f);
always @(*) begin
if(when_PWMctrl_l29) begin
duty_cycle_1 = 8'h0;
end else begin
duty_cycle_1 = io_level;
end
end
assign io_pwm_2 = pwmdriver_2_io_pwm;
always @(posedge clk or posedge reset) begin
if(reset) begin
freq_counter_value <= 12'h0;
pwm_steps_counter_value <= 8'h0;
end else begin
freq_counter_value <= freq_counter_valueNext;
pwm_steps_counter_value <= pwm_steps_counter_valueNext;
end
end
endmodule
|
tt06-finale_0040
|
tt06-finale
|
ThorKn-TT06_AudioChip_V2
|
task_PWMdriver
|
tt_um_thorkn_audiochip_v2
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Thorsten Knoll
* SPDX-License-Identifier: Apache-2.0
*/
`timescale 1ns/1ps
`define default_netname none
module tt_um_thorkn_audiochip_v2 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
wire pwm_1_out;
wire pwm_2_out;
wire [11:0] frequency;
wire reset;
assign reset = !rst_n;
assign frequency = {uio_in[7:4],ui_in[7:0]};
PWMaudio pwm_audio (
.io_pwm_1 (pwm_1_out ), //o
.io_pwm_2 (pwm_2_out ), //o
.io_frequency (frequency ), //i
.io_adsr_switch (uio_in[3] ), //i
.io_adsr_choice (uio_in[2:0] ), //i
.clk (clk ), //i
.reset (reset ) //i
);
// All output pins must be assigned. If not used, assign to 0.
assign uo_out = {6'b0000_00, pwm_2_out, pwm_1_out};
assign uio_out = 8'b0000_0000;
assign uio_oe = 8'b0000_0000;
endmodule
module PWMaudio (
output io_pwm_1,
output io_pwm_2,
input [11:0] io_frequency,
input io_adsr_switch,
input [2:0] io_adsr_choice,
input clk,
input reset
);
localparam fsm_adsr_enumDef_BOOT = 3'd0;
localparam fsm_adsr_enumDef_stateEntry = 3'd1;
localparam fsm_adsr_enumDef_stateAttack = 3'd2;
localparam fsm_adsr_enumDef_stateDelay = 3'd3;
localparam fsm_adsr_enumDef_stateSustain = 3'd4;
localparam fsm_adsr_enumDef_stateRelease = 3'd5;
wire [11:0] pwm_ctrl_io_freq;
reg [7:0] pwm_ctrl_io_level;
wire pwm_ctrl_io_pwm_1;
wire pwm_ctrl_io_pwm_2;
reg [23:0] adsr1;
reg [23:0] adsr2;
reg [23:0] adsr3;
reg [23:0] adsr4;
wire [2:0] switch_PWMaudio_l25;
wire fsm_adsr_wantExit;
reg fsm_adsr_wantStart;
wire fsm_adsr_wantKill;
reg [23:0] fsm_adsr_counter;
reg [7:0] fsm_adsr_level_adsr;
reg [2:0] fsm_adsr_stateReg;
reg [2:0] fsm_adsr_stateNext;
wire when_PWMaudio_l110;
wire when_PWMaudio_l114;
wire when_PWMaudio_l124;
wire when_PWMaudio_l128;
wire when_PWMaudio_l139;
wire when_PWMaudio_l149;
wire when_PWMaudio_l153;
wire when_StateMachine_l238;
wire when_StateMachine_l238_1;
wire when_StateMachine_l238_2;
wire when_StateMachine_l238_3;
`ifndef SYNTHESIS
reg [95:0] fsm_adsr_stateReg_string;
reg [95:0] fsm_adsr_stateNext_string;
`endif
PWMctrl pwm_ctrl (
.io_freq (pwm_ctrl_io_freq[11:0] ), //i
.io_level (pwm_ctrl_io_level[7:0] ), //i
.io_pwm_1 (pwm_ctrl_io_pwm_1 ), //o
.io_pwm_2 (pwm_ctrl_io_pwm_2 ), //o
.clk (clk ), //i
.reset (reset ) //i
);
`ifndef SYNTHESIS
always @(*) begin
case(fsm_adsr_stateReg)
fsm_adsr_enumDef_BOOT : fsm_adsr_stateReg_string = "BOOT ";
fsm_adsr_enumDef_stateEntry : fsm_adsr_stateReg_string = "stateEntry ";
fsm_adsr_enumDef_stateAttack : fsm_adsr_stateReg_string = "stateAttack ";
fsm_adsr_enumDef_stateDelay : fsm_adsr_stateReg_string = "stateDelay ";
fsm_adsr_enumDef_stateSustain : fsm_adsr_stateReg_string = "stateSustain";
fsm_adsr_enumDef_stateRelease : fsm_adsr_stateReg_string = "stateRelease";
default : fsm_adsr_stateReg_string = "????????????";
endcase
end
always @(*) begin
case(fsm_adsr_stateNext)
fsm_adsr_enumDef_BOOT : fsm_adsr_stateNext_string = "BOOT ";
fsm_adsr_enumDef_stateEntry : fsm_adsr_stateNext_string = "stateEntry ";
fsm_adsr_enumDef_stateAttack : fsm_adsr_stateNext_string = "stateAttack ";
fsm_adsr_enumDef_stateDelay : fsm_adsr_stateNext_string = "stateDelay ";
fsm_adsr_enumDef_stateSustain : fsm_adsr_stateNext_string = "stateSustain";
fsm_adsr_enumDef_stateRelease : fsm_adsr_stateNext_string = "stateRelease";
default : fsm_adsr_stateNext_string = "????????????";
endcase
end
`endif
assign switch_PWMaudio_l25 = io_adsr_choice;
always @(*) begin
case(switch_PWMaudio_l25)
3'b000 : begin
adsr1 = 24'h000032;
end
3'b001 : begin
adsr1 = 24'h000032;
end
3'b010 : begin
adsr1 = 24'h00000a;
end
3'b011 : begin
adsr1 = 24'h00000a;
end
3'b100 : begin
adsr1 = 24'h0003e8;
end
3'b101 : begin
adsr1 = 24'h0003e8;
end
3'b110 : begin
adsr1 = 24'h001388;
end
default : begin
adsr1 = 24'h001388;
end
endcase
end
always @(*) begin
case(switch_PWMaudio_l25)
3'b000 : begin
adsr2 = 24'h000064;
end
3'b001 : begin
adsr2 = 24'h0001f4;
end
3'b010 : begin
adsr2 = 24'h0005dc;
end
3'b011 : begin
adsr2 = 24'h0007d0;
end
3'b100 : begin
adsr2 = 24'h000064;
end
3'b101 : begin
adsr2 = 24'h0007d0;
end
3'b110 : begin
adsr2 = 24'h0003e8;
end
default : begin
adsr2 = 24'h001388;
end
endcase
end
always @(*) begin
case(switch_PWMaudio_l25)
3'b000 : begin
adsr3 = 24'h0001f4;
end
3'b001 : begin
adsr3 = 24'h0001f4;
end
3'b010 : begin
adsr3 = 24'h0003e8;
end
3'b011 : begin
adsr3 = 24'h0005dc;
end
3'b100 : begin
adsr3 = 24'h0007d0;
end
3'b101 : begin
adsr3 = 24'h0007d0;
end
3'b110 : begin
adsr3 = 24'h0001f4;
end
default : begin
adsr3 = 24'h0003e8;
end
endcase
end
always @(*) begin
case(switch_PWMaudio_l25)
3'b000 : begin
adsr4 = 24'h000064;
end
3'b001 : begin
adsr4 = 24'h000064;
end
3'b010 : begin
adsr4 = 24'h000190;
end
3'b011 : begin
adsr4 = 24'h000190;
end
3'b100 : begin
adsr4 = 24'h000190;
end
3'b101 : begin
adsr4 = 24'h0003e8;
end
3'b110 : begin
adsr4 = 24'h000190;
end
default : begin
adsr4 = 24'h002710;
end
endcase
end
assign io_pwm_1 = pwm_ctrl_io_pwm_1;
assign io_pwm_2 = pwm_ctrl_io_pwm_2;
assign pwm_ctrl_io_freq = io_frequency;
assign fsm_adsr_wantExit = 1'b0;
always @(*) begin
fsm_adsr_wantStart = 1'b0;
case(fsm_adsr_stateReg)
fsm_adsr_enumDef_stateEntry : begin
end
fsm_adsr_enumDef_stateAttack : begin
end
fsm_adsr_enumDef_stateDelay : begin
end
fsm_adsr_enumDef_stateSustain : begin
end
fsm_adsr_enumDef_stateRelease : begin
end
default : begin
fsm_adsr_wantStart = 1'b1;
end
endcase
end
assign fsm_adsr_wantKill = 1'b0;
always @(*) begin
if(io_adsr_switch) begin
pwm_ctrl_io_level = fsm_adsr_level_adsr;
end else begin
pwm_ctrl_io_level = 8'hff;
end
end
always @(*) begin
fsm_adsr_stateNext = fsm_adsr_stateReg;
case(fsm_adsr_stateReg)
fsm_adsr_enumDef_stateEntry : begin
fsm_adsr_stateNext = fsm_adsr_enumDef_stateAttack;
end
fsm_adsr_enumDef_stateAttack : begin
if(when_PWMaudio_l114) begin
fsm_adsr_stateNext = fsm_adsr_enumDef_stateDelay;
end
end
fsm_adsr_enumDef_stateDelay : begin
if(when_PWMaudio_l128) begin
fsm_adsr_stateNext = fsm_adsr_enumDef_stateSustain;
end
end
fsm_adsr_enumDef_stateSustain : begin
if(when_PWMaudio_l139) begin
fsm_adsr_stateNext = fsm_adsr_enumDef_stateRelease;
end
end
fsm_adsr_enumDef_stateRelease : begin
if(when_PWMaudio_l153) begin
fsm_adsr_stateNext = fsm_adsr_enumDef_stateEntry;
end
end
default : begin
end
endcase
if(fsm_adsr_wantStart) begin
fsm_adsr_stateNext = fsm_adsr_enumDef_stateEntry;
end
if(fsm_adsr_wantKill) begin
fsm_adsr_stateNext = fsm_adsr_enumDef_BOOT;
end
end
assign when_PWMaudio_l110 = (adsr1 <= fsm_adsr_counter);
assign when_PWMaudio_l114 = (fsm_adsr_level_adsr == 8'hff);
assign when_PWMaudio_l124 = (adsr2 <= fsm_adsr_counter);
assign when_PWMaudio_l128 = (fsm_adsr_level_adsr == 8'h7f);
assign when_PWMaudio_l139 = (adsr3 <= fsm_adsr_counter);
assign when_PWMaudio_l149 = (adsr4 <= fsm_adsr_counter);
assign when_PWMaudio_l153 = (fsm_adsr_level_adsr == 8'h0);
assign when_StateMachine_l238 = ((! (fsm_adsr_stateReg == fsm_adsr_enumDef_stateAttack)) && (fsm_adsr_stateNext == fsm_adsr_enumDef_stateAttack));
assign when_StateMachine_l238_1 = ((! (fsm_adsr_stateReg == fsm_adsr_enumDef_stateDelay)) && (fsm_adsr_stateNext == fsm_adsr_enumDef_stateDelay));
assign when_StateMachine_l238_2 = ((! (fsm_adsr_stateReg == fsm_adsr_enumDef_stateSustain)) && (fsm_adsr_stateNext == fsm_adsr_enumDef_stateSustain));
assign when_StateMachine_l238_3 = ((! (fsm_adsr_stateReg == fsm_adsr_enumDef_stateRelease)) && (fsm_adsr_stateNext == fsm_adsr_enumDef_stateRelease));
always @(posedge clk or posedge reset) begin
if(reset) begin
fsm_adsr_counter <= 24'h0;
fsm_adsr_level_adsr <= 8'h0;
fsm_adsr_stateReg <= fsm_adsr_enumDef_BOOT;
end else begin
fsm_adsr_stateReg <= fsm_adsr_stateNext;
case(fsm_adsr_stateReg)
fsm_adsr_enumDef_stateEntry : begin
end
fsm_adsr_enumDef_stateAttack : begin
fsm_adsr_counter <= (fsm_adsr_counter + 24'h000001);
if(when_PWMaudio_l110) begin
fsm_adsr_level_adsr <= (fsm_adsr_level_adsr + 8'h01);
fsm_adsr_counter <= 24'h0;
end
end
fsm_adsr_enumDef_stateDelay : begin
fsm_adsr_counter <= (fsm_adsr_counter + 24'h000001);
if(when_PWMaudio_l124) begin
fsm_adsr_level_adsr <= (fsm_adsr_level_adsr - 8'h01);
fsm_adsr_counter <= 24'h0;
end
end
fsm_adsr_enumDef_stateSustain : begin
fsm_adsr_counter <= (fsm_adsr_counter + 24'h000001);
fsm_adsr_level_adsr <= 8'h7f;
end
fsm_adsr_enumDef_stateRelease : begin
fsm_adsr_counter <= (fsm_adsr_counter + 24'h000001);
if(when_PWMaudio_l149) begin
fsm_adsr_level_adsr <= (fsm_adsr_level_adsr - 8'h01);
fsm_adsr_counter <= 24'h0;
end
end
default : begin
end
endcase
if(when_StateMachine_l238) begin
fsm_adsr_counter <= 24'h0;
end
if(when_StateMachine_l238_1) begin
fsm_adsr_counter <= 24'h0;
end
if(when_StateMachine_l238_2) begin
fsm_adsr_counter <= 24'h0;
end
if(when_StateMachine_l238_3) begin
fsm_adsr_counter <= 24'h0;
end
end
end
endmodule
module PWMctrl (
input [11:0] io_freq,
input [7:0] io_level,
output io_pwm_1,
output io_pwm_2,
input clk,
input reset
);
wire pwmdriver_1_1_io_pwm;
wire pwmdriver_2_io_pwm;
wire [11:0] _zz_freq_counter_valueNext;
wire [0:0] _zz_freq_counter_valueNext_1;
wire [7:0] _zz_pwm_steps_counter_valueNext;
wire [0:0] _zz_pwm_steps_counter_valueNext_1;
reg freq_counter_willIncrement;
reg freq_counter_willClear;
reg [11:0] freq_counter_valueNext;
reg [11:0] freq_counter_value;
wire freq_counter_willOverflowIfInc;
wire freq_counter_willOverflow;
reg pwm_steps_counter_willIncrement;
wire pwm_steps_counter_willClear;
reg [7:0] pwm_steps_counter_valueNext;
reg [7:0] pwm_steps_counter_value;
wire pwm_steps_counter_willOverflowIfInc;
wire pwm_steps_counter_willOverflow;
reg [7:0] duty_cycle_1;
wire when_PWMctrl_l23;
wire when_PWMctrl_l29;
function zz_freq_counter_willIncrement(input dummy);
begin
zz_freq_counter_willIncrement = 1'b0;
zz_freq_counter_willIncrement = 1'b1;
end
endfunction
wire _zz_1;
assign _zz_freq_counter_valueNext_1 = freq_counter_willIncrement;
assign _zz_freq_counter_valueNext = {11'd0, _zz_freq_counter_valueNext_1};
assign _zz_pwm_steps_counter_valueNext_1 = pwm_steps_counter_willIncrement;
assign _zz_pwm_steps_counter_valueNext = {7'd0, _zz_pwm_steps_counter_valueNext_1};
PWMdriver pwmdriver_1_1 (
.io_dutyCycle (duty_cycle_1[7:0] ), //i
.io_pwm (pwmdriver_1_1_io_pwm ), //o
.clk (clk ), //i
.reset (reset ) //i
);
PWMdriver pwmdriver_2 (
.io_dutyCycle (pwm_steps_counter_value[7:0] ), //i
.io_pwm (pwmdriver_2_io_pwm ), //o
.clk (clk ), //i
.reset (reset ) //i
);
assign _zz_1 = zz_freq_counter_willIncrement(1'b0);
always @(*) freq_counter_willIncrement = _zz_1;
always @(*) begin
freq_counter_willClear = 1'b0;
if(when_PWMctrl_l23) begin
freq_counter_willClear = 1'b1;
end
end
assign freq_counter_willOverflowIfInc = (freq_counter_value == 12'hfff);
assign freq_counter_willOverflow = (freq_counter_willOverflowIfInc && freq_counter_willIncrement);
always @(*) begin
freq_counter_valueNext = (freq_counter_value + _zz_freq_counter_valueNext);
if(freq_counter_willClear) begin
freq_counter_valueNext = 12'h0;
end
end
always @(*) begin
pwm_steps_counter_willIncrement = 1'b0;
if(when_PWMctrl_l23) begin
pwm_steps_counter_willIncrement = 1'b1;
end
end
assign pwm_steps_counter_willClear = 1'b0;
assign pwm_steps_counter_willOverflowIfInc = (pwm_steps_counter_value == 8'hff);
assign pwm_steps_counter_willOverflow = (pwm_steps_counter_willOverflowIfInc && pwm_steps_counter_willIncrement);
always @(*) begin
pwm_steps_counter_valueNext = (pwm_steps_counter_value + _zz_pwm_steps_counter_valueNext);
if(pwm_steps_counter_willClear) begin
pwm_steps_counter_valueNext = 8'h0;
end
end
assign io_pwm_1 = pwmdriver_1_1_io_pwm;
assign when_PWMctrl_l23 = (freq_counter_value == io_freq);
assign when_PWMctrl_l29 = (pwm_steps_counter_value < 8'h7f);
always @(*) begin
if(when_PWMctrl_l29) begin
duty_cycle_1 = 8'h0;
end else begin
duty_cycle_1 = io_level;
end
end
assign io_pwm_2 = pwmdriver_2_io_pwm;
always @(posedge clk or posedge reset) begin
if(reset) begin
freq_counter_value <= 12'h0;
pwm_steps_counter_value <= 8'h0;
end else begin
freq_counter_value <= freq_counter_valueNext;
pwm_steps_counter_value <= pwm_steps_counter_valueNext;
end
end
endmodule
//PWMdriver replaced by PWMdriver
module PWMdriver (
input [7:0] io_dutyCycle,
output io_pwm,
input clk,
input reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
|
module PWMdriver (
input [7:0] io_dutyCycle,
output io_pwm,
input clk,
input reset
);
wire [7:0] _zz_counter_valueNext;
wire [0:0] _zz_counter_valueNext_1;
reg counter_willIncrement;
wire counter_willClear;
reg [7:0] counter_valueNext;
reg [7:0] counter_value;
wire counter_willOverflowIfInc;
wire counter_willOverflow;
function zz_counter_willIncrement(input dummy);
begin
zz_counter_willIncrement = 1'b0;
zz_counter_willIncrement = 1'b1;
end
endfunction
wire _zz_1;
assign _zz_counter_valueNext_1 = counter_willIncrement;
assign _zz_counter_valueNext = {7'd0, _zz_counter_valueNext_1};
assign _zz_1 = zz_counter_willIncrement(1'b0);
always @(*) counter_willIncrement = _zz_1;
assign counter_willClear = 1'b0;
assign counter_willOverflowIfInc = (counter_value == 8'hff);
assign counter_willOverflow = (counter_willOverflowIfInc && counter_willIncrement);
always @(*) begin
counter_valueNext = (counter_value + _zz_counter_valueNext);
if(counter_willClear) begin
counter_valueNext = 8'h0;
end
end
assign io_pwm = (counter_value < io_dutyCycle);
always @(posedge clk or posedge reset) begin
if(reset) begin
counter_value <= 8'h0;
end else begin
counter_value <= counter_valueNext;
end
end
endmodule
|
tt06-finale_0041
|
tt06-finale
|
ThorKn-TT06_AudioChip_V2
|
task_tt_um_thorkn_audiochip_v2
|
tt_um_thorkn_audiochip_v2
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Thorsten Knoll
* SPDX-License-Identifier: Apache-2.0
*/
`timescale 1ns/1ps
`define default_netname none
module tt_um_thorkn_audiochip_v2 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module PWMaudio (
output io_pwm_1,
output io_pwm_2,
input [11:0] io_frequency,
input io_adsr_switch,
input [2:0] io_adsr_choice,
input clk,
input reset
);
localparam fsm_adsr_enumDef_BOOT = 3'd0;
localparam fsm_adsr_enumDef_stateEntry = 3'd1;
localparam fsm_adsr_enumDef_stateAttack = 3'd2;
localparam fsm_adsr_enumDef_stateDelay = 3'd3;
localparam fsm_adsr_enumDef_stateSustain = 3'd4;
localparam fsm_adsr_enumDef_stateRelease = 3'd5;
wire [11:0] pwm_ctrl_io_freq;
reg [7:0] pwm_ctrl_io_level;
wire pwm_ctrl_io_pwm_1;
wire pwm_ctrl_io_pwm_2;
reg [23:0] adsr1;
reg [23:0] adsr2;
reg [23:0] adsr3;
reg [23:0] adsr4;
wire [2:0] switch_PWMaudio_l25;
wire fsm_adsr_wantExit;
reg fsm_adsr_wantStart;
wire fsm_adsr_wantKill;
reg [23:0] fsm_adsr_counter;
reg [7:0] fsm_adsr_level_adsr;
reg [2:0] fsm_adsr_stateReg;
reg [2:0] fsm_adsr_stateNext;
wire when_PWMaudio_l110;
wire when_PWMaudio_l114;
wire when_PWMaudio_l124;
wire when_PWMaudio_l128;
wire when_PWMaudio_l139;
wire when_PWMaudio_l149;
wire when_PWMaudio_l153;
wire when_StateMachine_l238;
wire when_StateMachine_l238_1;
wire when_StateMachine_l238_2;
wire when_StateMachine_l238_3;
`ifndef SYNTHESIS
reg [95:0] fsm_adsr_stateReg_string;
reg [95:0] fsm_adsr_stateNext_string;
`endif
PWMctrl pwm_ctrl (
.io_freq (pwm_ctrl_io_freq[11:0] ), //i
.io_level (pwm_ctrl_io_level[7:0] ), //i
.io_pwm_1 (pwm_ctrl_io_pwm_1 ), //o
.io_pwm_2 (pwm_ctrl_io_pwm_2 ), //o
.clk (clk ), //i
.reset (reset ) //i
);
`ifndef SYNTHESIS
always @(*) begin
case(fsm_adsr_stateReg)
fsm_adsr_enumDef_BOOT : fsm_adsr_stateReg_string = "BOOT ";
fsm_adsr_enumDef_stateEntry : fsm_adsr_stateReg_string = "stateEntry ";
fsm_adsr_enumDef_stateAttack : fsm_adsr_stateReg_string = "stateAttack ";
fsm_adsr_enumDef_stateDelay : fsm_adsr_stateReg_string = "stateDelay ";
fsm_adsr_enumDef_stateSustain : fsm_adsr_stateReg_string = "stateSustain";
fsm_adsr_enumDef_stateRelease : fsm_adsr_stateReg_string = "stateRelease";
default : fsm_adsr_stateReg_string = "????????????";
endcase
end
always @(*) begin
case(fsm_adsr_stateNext)
fsm_adsr_enumDef_BOOT : fsm_adsr_stateNext_string = "BOOT ";
fsm_adsr_enumDef_stateEntry : fsm_adsr_stateNext_string = "stateEntry ";
fsm_adsr_enumDef_stateAttack : fsm_adsr_stateNext_string = "stateAttack ";
fsm_adsr_enumDef_stateDelay : fsm_adsr_stateNext_string = "stateDelay ";
fsm_adsr_enumDef_stateSustain : fsm_adsr_stateNext_string = "stateSustain";
fsm_adsr_enumDef_stateRelease : fsm_adsr_stateNext_string = "stateRelease";
default : fsm_adsr_stateNext_string = "????????????";
endcase
end
`endif
assign switch_PWMaudio_l25 = io_adsr_choice;
always @(*) begin
case(switch_PWMaudio_l25)
3'b000 : begin
adsr1 = 24'h000032;
end
3'b001 : begin
adsr1 = 24'h000032;
end
3'b010 : begin
adsr1 = 24'h00000a;
end
3'b011 : begin
adsr1 = 24'h00000a;
end
3'b100 : begin
adsr1 = 24'h0003e8;
end
3'b101 : begin
adsr1 = 24'h0003e8;
end
3'b110 : begin
adsr1 = 24'h001388;
end
default : begin
adsr1 = 24'h001388;
end
endcase
end
always @(*) begin
case(switch_PWMaudio_l25)
3'b000 : begin
adsr2 = 24'h000064;
end
3'b001 : begin
adsr2 = 24'h0001f4;
end
3'b010 : begin
adsr2 = 24'h0005dc;
end
3'b011 : begin
adsr2 = 24'h0007d0;
end
3'b100 : begin
adsr2 = 24'h000064;
end
3'b101 : begin
adsr2 = 24'h0007d0;
end
3'b110 : begin
adsr2 = 24'h0003e8;
end
default : begin
adsr2 = 24'h001388;
end
endcase
end
always @(*) begin
case(switch_PWMaudio_l25)
3'b000 : begin
adsr3 = 24'h0001f4;
end
3'b001 : begin
adsr3 = 24'h0001f4;
end
3'b010 : begin
adsr3 = 24'h0003e8;
end
3'b011 : begin
adsr3 = 24'h0005dc;
end
3'b100 : begin
adsr3 = 24'h0007d0;
end
3'b101 : begin
adsr3 = 24'h0007d0;
end
3'b110 : begin
adsr3 = 24'h0001f4;
end
default : begin
adsr3 = 24'h0003e8;
end
endcase
end
always @(*) begin
case(switch_PWMaudio_l25)
3'b000 : begin
adsr4 = 24'h000064;
end
3'b001 : begin
adsr4 = 24'h000064;
end
3'b010 : begin
adsr4 = 24'h000190;
end
3'b011 : begin
adsr4 = 24'h000190;
end
3'b100 : begin
adsr4 = 24'h000190;
end
3'b101 : begin
adsr4 = 24'h0003e8;
end
3'b110 : begin
adsr4 = 24'h000190;
end
default : begin
adsr4 = 24'h002710;
end
endcase
end
assign io_pwm_1 = pwm_ctrl_io_pwm_1;
assign io_pwm_2 = pwm_ctrl_io_pwm_2;
assign pwm_ctrl_io_freq = io_frequency;
assign fsm_adsr_wantExit = 1'b0;
always @(*) begin
fsm_adsr_wantStart = 1'b0;
case(fsm_adsr_stateReg)
fsm_adsr_enumDef_stateEntry : begin
end
fsm_adsr_enumDef_stateAttack : begin
end
fsm_adsr_enumDef_stateDelay : begin
end
fsm_adsr_enumDef_stateSustain : begin
end
fsm_adsr_enumDef_stateRelease : begin
end
default : begin
fsm_adsr_wantStart = 1'b1;
end
endcase
end
assign fsm_adsr_wantKill = 1'b0;
always @(*) begin
if(io_adsr_switch) begin
pwm_ctrl_io_level = fsm_adsr_level_adsr;
end else begin
pwm_ctrl_io_level = 8'hff;
end
end
always @(*) begin
fsm_adsr_stateNext = fsm_adsr_stateReg;
case(fsm_adsr_stateReg)
fsm_adsr_enumDef_stateEntry : begin
fsm_adsr_stateNext = fsm_adsr_enumDef_stateAttack;
end
fsm_adsr_enumDef_stateAttack : begin
if(when_PWMaudio_l114) begin
fsm_adsr_stateNext = fsm_adsr_enumDef_stateDelay;
end
end
fsm_adsr_enumDef_stateDelay : begin
if(when_PWMaudio_l128) begin
fsm_adsr_stateNext = fsm_adsr_enumDef_stateSustain;
end
end
fsm_adsr_enumDef_stateSustain : begin
if(when_PWMaudio_l139) begin
fsm_adsr_stateNext = fsm_adsr_enumDef_stateRelease;
end
end
fsm_adsr_enumDef_stateRelease : begin
if(when_PWMaudio_l153) begin
fsm_adsr_stateNext = fsm_adsr_enumDef_stateEntry;
end
end
default : begin
end
endcase
if(fsm_adsr_wantStart) begin
fsm_adsr_stateNext = fsm_adsr_enumDef_stateEntry;
end
if(fsm_adsr_wantKill) begin
fsm_adsr_stateNext = fsm_adsr_enumDef_BOOT;
end
end
assign when_PWMaudio_l110 = (adsr1 <= fsm_adsr_counter);
assign when_PWMaudio_l114 = (fsm_adsr_level_adsr == 8'hff);
assign when_PWMaudio_l124 = (adsr2 <= fsm_adsr_counter);
assign when_PWMaudio_l128 = (fsm_adsr_level_adsr == 8'h7f);
assign when_PWMaudio_l139 = (adsr3 <= fsm_adsr_counter);
assign when_PWMaudio_l149 = (adsr4 <= fsm_adsr_counter);
assign when_PWMaudio_l153 = (fsm_adsr_level_adsr == 8'h0);
assign when_StateMachine_l238 = ((! (fsm_adsr_stateReg == fsm_adsr_enumDef_stateAttack)) && (fsm_adsr_stateNext == fsm_adsr_enumDef_stateAttack));
assign when_StateMachine_l238_1 = ((! (fsm_adsr_stateReg == fsm_adsr_enumDef_stateDelay)) && (fsm_adsr_stateNext == fsm_adsr_enumDef_stateDelay));
assign when_StateMachine_l238_2 = ((! (fsm_adsr_stateReg == fsm_adsr_enumDef_stateSustain)) && (fsm_adsr_stateNext == fsm_adsr_enumDef_stateSustain));
assign when_StateMachine_l238_3 = ((! (fsm_adsr_stateReg == fsm_adsr_enumDef_stateRelease)) && (fsm_adsr_stateNext == fsm_adsr_enumDef_stateRelease));
always @(posedge clk or posedge reset) begin
if(reset) begin
fsm_adsr_counter <= 24'h0;
fsm_adsr_level_adsr <= 8'h0;
fsm_adsr_stateReg <= fsm_adsr_enumDef_BOOT;
end else begin
fsm_adsr_stateReg <= fsm_adsr_stateNext;
case(fsm_adsr_stateReg)
fsm_adsr_enumDef_stateEntry : begin
end
fsm_adsr_enumDef_stateAttack : begin
fsm_adsr_counter <= (fsm_adsr_counter + 24'h000001);
if(when_PWMaudio_l110) begin
fsm_adsr_level_adsr <= (fsm_adsr_level_adsr + 8'h01);
fsm_adsr_counter <= 24'h0;
end
end
fsm_adsr_enumDef_stateDelay : begin
fsm_adsr_counter <= (fsm_adsr_counter + 24'h000001);
if(when_PWMaudio_l124) begin
fsm_adsr_level_adsr <= (fsm_adsr_level_adsr - 8'h01);
fsm_adsr_counter <= 24'h0;
end
end
fsm_adsr_enumDef_stateSustain : begin
fsm_adsr_counter <= (fsm_adsr_counter + 24'h000001);
fsm_adsr_level_adsr <= 8'h7f;
end
fsm_adsr_enumDef_stateRelease : begin
fsm_adsr_counter <= (fsm_adsr_counter + 24'h000001);
if(when_PWMaudio_l149) begin
fsm_adsr_level_adsr <= (fsm_adsr_level_adsr - 8'h01);
fsm_adsr_counter <= 24'h0;
end
end
default : begin
end
endcase
if(when_StateMachine_l238) begin
fsm_adsr_counter <= 24'h0;
end
if(when_StateMachine_l238_1) begin
fsm_adsr_counter <= 24'h0;
end
if(when_StateMachine_l238_2) begin
fsm_adsr_counter <= 24'h0;
end
if(when_StateMachine_l238_3) begin
fsm_adsr_counter <= 24'h0;
end
end
end
endmodule
module PWMctrl (
input [11:0] io_freq,
input [7:0] io_level,
output io_pwm_1,
output io_pwm_2,
input clk,
input reset
);
wire pwmdriver_1_1_io_pwm;
wire pwmdriver_2_io_pwm;
wire [11:0] _zz_freq_counter_valueNext;
wire [0:0] _zz_freq_counter_valueNext_1;
wire [7:0] _zz_pwm_steps_counter_valueNext;
wire [0:0] _zz_pwm_steps_counter_valueNext_1;
reg freq_counter_willIncrement;
reg freq_counter_willClear;
reg [11:0] freq_counter_valueNext;
reg [11:0] freq_counter_value;
wire freq_counter_willOverflowIfInc;
wire freq_counter_willOverflow;
reg pwm_steps_counter_willIncrement;
wire pwm_steps_counter_willClear;
reg [7:0] pwm_steps_counter_valueNext;
reg [7:0] pwm_steps_counter_value;
wire pwm_steps_counter_willOverflowIfInc;
wire pwm_steps_counter_willOverflow;
reg [7:0] duty_cycle_1;
wire when_PWMctrl_l23;
wire when_PWMctrl_l29;
function zz_freq_counter_willIncrement(input dummy);
begin
zz_freq_counter_willIncrement = 1'b0;
zz_freq_counter_willIncrement = 1'b1;
end
endfunction
wire _zz_1;
assign _zz_freq_counter_valueNext_1 = freq_counter_willIncrement;
assign _zz_freq_counter_valueNext = {11'd0, _zz_freq_counter_valueNext_1};
assign _zz_pwm_steps_counter_valueNext_1 = pwm_steps_counter_willIncrement;
assign _zz_pwm_steps_counter_valueNext = {7'd0, _zz_pwm_steps_counter_valueNext_1};
PWMdriver pwmdriver_1_1 (
.io_dutyCycle (duty_cycle_1[7:0] ), //i
.io_pwm (pwmdriver_1_1_io_pwm ), //o
.clk (clk ), //i
.reset (reset ) //i
);
PWMdriver pwmdriver_2 (
.io_dutyCycle (pwm_steps_counter_value[7:0] ), //i
.io_pwm (pwmdriver_2_io_pwm ), //o
.clk (clk ), //i
.reset (reset ) //i
);
assign _zz_1 = zz_freq_counter_willIncrement(1'b0);
always @(*) freq_counter_willIncrement = _zz_1;
always @(*) begin
freq_counter_willClear = 1'b0;
if(when_PWMctrl_l23) begin
freq_counter_willClear = 1'b1;
end
end
assign freq_counter_willOverflowIfInc = (freq_counter_value == 12'hfff);
assign freq_counter_willOverflow = (freq_counter_willOverflowIfInc && freq_counter_willIncrement);
always @(*) begin
freq_counter_valueNext = (freq_counter_value + _zz_freq_counter_valueNext);
if(freq_counter_willClear) begin
freq_counter_valueNext = 12'h0;
end
end
always @(*) begin
pwm_steps_counter_willIncrement = 1'b0;
if(when_PWMctrl_l23) begin
pwm_steps_counter_willIncrement = 1'b1;
end
end
assign pwm_steps_counter_willClear = 1'b0;
assign pwm_steps_counter_willOverflowIfInc = (pwm_steps_counter_value == 8'hff);
assign pwm_steps_counter_willOverflow = (pwm_steps_counter_willOverflowIfInc && pwm_steps_counter_willIncrement);
always @(*) begin
pwm_steps_counter_valueNext = (pwm_steps_counter_value + _zz_pwm_steps_counter_valueNext);
if(pwm_steps_counter_willClear) begin
pwm_steps_counter_valueNext = 8'h0;
end
end
assign io_pwm_1 = pwmdriver_1_1_io_pwm;
assign when_PWMctrl_l23 = (freq_counter_value == io_freq);
assign when_PWMctrl_l29 = (pwm_steps_counter_value < 8'h7f);
always @(*) begin
if(when_PWMctrl_l29) begin
duty_cycle_1 = 8'h0;
end else begin
duty_cycle_1 = io_level;
end
end
assign io_pwm_2 = pwmdriver_2_io_pwm;
always @(posedge clk or posedge reset) begin
if(reset) begin
freq_counter_value <= 12'h0;
pwm_steps_counter_value <= 8'h0;
end else begin
freq_counter_value <= freq_counter_valueNext;
pwm_steps_counter_value <= pwm_steps_counter_valueNext;
end
end
endmodule
//PWMdriver replaced by PWMdriver
module PWMdriver (
input [7:0] io_dutyCycle,
output io_pwm,
input clk,
input reset
);
wire [7:0] _zz_counter_valueNext;
wire [0:0] _zz_counter_valueNext_1;
reg counter_willIncrement;
wire counter_willClear;
reg [7:0] counter_valueNext;
reg [7:0] counter_value;
wire counter_willOverflowIfInc;
wire counter_willOverflow;
function zz_counter_willIncrement(input dummy);
begin
zz_counter_willIncrement = 1'b0;
zz_counter_willIncrement = 1'b1;
end
endfunction
wire _zz_1;
assign _zz_counter_valueNext_1 = counter_willIncrement;
assign _zz_counter_valueNext = {7'd0, _zz_counter_valueNext_1};
assign _zz_1 = zz_counter_willIncrement(1'b0);
always @(*) counter_willIncrement = _zz_1;
assign counter_willClear = 1'b0;
assign counter_willOverflowIfInc = (counter_value == 8'hff);
assign counter_willOverflow = (counter_willOverflowIfInc && counter_willIncrement);
always @(*) begin
counter_valueNext = (counter_value + _zz_counter_valueNext);
if(counter_willClear) begin
counter_valueNext = 8'h0;
end
end
assign io_pwm = (counter_value < io_dutyCycle);
always @(posedge clk or posedge reset) begin
if(reset) begin
counter_value <= 8'h0;
end else begin
counter_value <= counter_valueNext;
end
end
endmodule
|
module tt_um_thorkn_audiochip_v2 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
wire pwm_1_out;
wire pwm_2_out;
wire [11:0] frequency;
wire reset;
assign reset = !rst_n;
assign frequency = {uio_in[7:4],ui_in[7:0]};
PWMaudio pwm_audio (
.io_pwm_1 (pwm_1_out ), //o
.io_pwm_2 (pwm_2_out ), //o
.io_frequency (frequency ), //i
.io_adsr_switch (uio_in[3] ), //i
.io_adsr_choice (uio_in[2:0] ), //i
.clk (clk ), //i
.reset (reset ) //i
);
// All output pins must be assigned. If not used, assign to 0.
assign uo_out = {6'b0000_00, pwm_2_out, pwm_1_out};
assign uio_out = 8'b0000_0000;
assign uio_oe = 8'b0000_0000;
endmodule
|
tt06-finale_0042
|
tt06-finale
|
adennen-tt06-arond-project
|
task_clock_divider
|
tt_um_7seg_animated
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Aron Dennen
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_7seg_animated (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
reg reset;
// *** Clock divider vars
wire clkPwm;
wire clk60;
clock_divider clk_divider (
.clk(clk),
.reset(reset),
.clkPwm(clkPwm),
.clk60(clk60)
);
// *** PWM module vars
reg pwmOut;
pwm pwm (
.enable(ena),
.clk(clkPwm),
.reset(reset),
.pwmValue( { uio_in[6:0], 1'b0 } ),
.pwmOut(pwmOut)
);
// *** Segment animator vars
reg [6:0] charInput;
wire [6:0] displayOut;
segment_animator animator (
.enable(ena),
.clk(clk),
.clk60(clk60),
.reset(reset),
.charAvailable(ui_in[7]),
.charInput(charInput),
.out(displayOut)
);
// *** Main program
reg [7:0] out;
assign uo_out = out;
always @(posedge clk) begin
reset <= ~rst_n;
charInput <= ui_in[6:0];
if (uio_in[7]) begin
out[6:0] <= (pwmOut) ? displayOut : 7'b0000000;
end
else out[6:0] <= displayOut;
out[7] <= ui_in[7];
end
// All output pins must be assigned. If not used, assign to 0.
//assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in
assign uio_out = 0;
assign uio_oe = 0;
endmodule
/*
* Copyright (c) 2024 Aron Dennen
* SPDX-License-Identifier: Apache-2.0
*/
// Iterates over the bits of a 7-segment character, sets the output segments individually with a delay period
module segment_animator (
// Inputs
input wire reset,
input wire enable,
input wire clk,
input wire clk60, // 60Hz clock input for timing
input wire charAvailable, // A character is available to be read
input wire [6:0] charInput, // The next character to read
// Outputs
output wire [6:0] out // 7-segment out
);
reg [6:0] segsOut;
reg [6:0] currentChar; // Current 7-segment character to be displayed
reg [6:0] segChecked; // Flags whether the segment has been evaluated for display
reg [2:0] segIndex; // Debug for displaying segments sequentially
reg [5:0] timerCount; // 6-bit segment animation timer (64 ticks)
// Registers used for rising edge detection while avoiding multidriven errors
reg charAvailable_prev;
reg clk60_prev;
// States
reg [1:0] state;
localparam idle_state = 2'b00;
localparam getChar_state = 2'b01;
localparam getSeg_state = 2'b10;
assign out = segsOut;
always @(posedge clk) begin
if (reset) begin
segsOut <= 0;
currentChar <= 0;
segChecked <= 0;
segIndex <= 0;
timerCount <= 0;
state <= idle_state;
charAvailable_prev <= 0;
clk60_prev <= 0;
end
else if (enable) begin
// Check for rising edges
// Read the character from charInput on the rising edge of charAvailable
if (charAvailable == 1 && charAvailable_prev == 0) begin
state <= getChar_state;
end
// Update the timer on the rising edge of clk60
else if (clk60 == 1 && clk60_prev == 0) begin
if (timerCount > 0) begin
timerCount <= timerCount - 1;
if (timerCount == 1) state <= getSeg_state; // Get the next segment after the timer expires
end
end
// If there are no rising edges then process the current state
else begin
case(state)
getSeg_state: begin
// Find the next valid segment, one clock at a time
// If the current segment index is a valid segment,
// display it and start the timer
if (currentChar[segIndex] == 1) begin
segsOut[segIndex] <= 1;
// Start the timer and move to idle state
timerCount <= 7; // delay for 7 timer ticks = 7/60 or 0.117 seconds
state <= idle_state;
end
// Mark that the segment has been checked
segChecked[segIndex] <= 1;
// Move to the next segment to check (debug)
segIndex <= segIndex + 1;
// 3. If all the segments have been checked, idle
if (segChecked == 7'b1111111) begin
state <= idle_state;
end
end
getChar_state: begin
// *** Reset variables ***
segsOut <= 0; // Reset the display
currentChar <= charInput; // Get the next input character here
segChecked <= 0;
segIndex <= 0;
timerCount <= 0;
// Done getting the new character
// Start displaying the segments
state <= getSeg_state;
end
default:;
endcase
end
// Update the signal status registers used for edge detection
charAvailable_prev <= charAvailable;
clk60_prev <= clk60;
end /* end else if (enable) */
end /* end always block */
endmodule
/*
* Copyright (c) 2024 Aron Dennen
* SPDX-License-Identifier: Apache-2.0
*/
// Inputs a 12.5 MHz signal and outputs a 122400 Hz (480Hz * 255 Pwm periods/clock) and 60 Hz clock signal
// Outputs toggle at twice the output frequency to maintin N rising edges per second
module clock_divider (
// Inputs
input wire clk,
input wire reset,
// Outputs
output wire clkPwm,
output wire clk60
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
/*
* Copyright (c) 2024 Aron Dennen
* SPDX-License-Identifier: Apache-2.0
*/
// 8-bit pwm, pwmValue 0 = fully off, pwmValue 255 = fully on
// rolls the count over at 254 to prevent the off-by-one error
// which prevents 255 from being fully on
module pwm (
// Inputs
input wire enable,
input wire clk,
input wire reset,
input wire [7:0] pwmValue,
// Outputs
output wire pwmOut
);
reg [7:0] pwmCount;
reg out;
assign pwmOut = out;
always @(posedge clk) begin
if (enable) begin
if (reset) begin
pwmCount <= 0;
out <= 0;
end
else if (enable) begin
out <= (pwmCount < pwmValue) ? 1 : 0;
pwmCount <= pwmCount + 1;
if (pwmCount == 254) pwmCount <= 0; // Off-by-one error fix
end
end
end
endmodule
|
module clock_divider (
// Inputs
input wire clk,
input wire reset,
// Outputs
output wire clkPwm,
output wire clk60
);
reg [5:0] count; // 6-bit counter for 12.5 MHz -> 122,400 Hz signal (51 counts per transition)
reg [9:0] count2; // 10-bit counter for 122,400 Hz -> 60 Hz signal (1020 counts per transition)
reg outPwm;
reg out60;
assign clkPwm = outPwm;
assign clk60 = out60;
always @(posedge clk) begin
if (reset) begin
count <= 0;
outPwm <= 0;
end
else begin
count <= count + 1;
if (count == 51) begin
// reset the main counter
count <= 0;
outPwm <= ~outPwm;
end
end
end
always @(posedge outPwm) begin
if (reset) begin
count2 <= 0;
out60 <= 0;
end
else begin
count2 <= count2 + 1;
if (count2 == 1020) begin
count2 <= 0;
out60 <= ~out60;
end
end
end
endmodule
|
tt06-finale_0043
|
tt06-finale
|
adennen-tt06-arond-project
|
task_pwm
|
tt_um_7seg_animated
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Aron Dennen
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_7seg_animated (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
reg reset;
// *** Clock divider vars
wire clkPwm;
wire clk60;
clock_divider clk_divider (
.clk(clk),
.reset(reset),
.clkPwm(clkPwm),
.clk60(clk60)
);
// *** PWM module vars
reg pwmOut;
pwm pwm (
.enable(ena),
.clk(clkPwm),
.reset(reset),
.pwmValue( { uio_in[6:0], 1'b0 } ),
.pwmOut(pwmOut)
);
// *** Segment animator vars
reg [6:0] charInput;
wire [6:0] displayOut;
segment_animator animator (
.enable(ena),
.clk(clk),
.clk60(clk60),
.reset(reset),
.charAvailable(ui_in[7]),
.charInput(charInput),
.out(displayOut)
);
// *** Main program
reg [7:0] out;
assign uo_out = out;
always @(posedge clk) begin
reset <= ~rst_n;
charInput <= ui_in[6:0];
if (uio_in[7]) begin
out[6:0] <= (pwmOut) ? displayOut : 7'b0000000;
end
else out[6:0] <= displayOut;
out[7] <= ui_in[7];
end
// All output pins must be assigned. If not used, assign to 0.
//assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in
assign uio_out = 0;
assign uio_oe = 0;
endmodule
/*
* Copyright (c) 2024 Aron Dennen
* SPDX-License-Identifier: Apache-2.0
*/
// Iterates over the bits of a 7-segment character, sets the output segments individually with a delay period
module segment_animator (
// Inputs
input wire reset,
input wire enable,
input wire clk,
input wire clk60, // 60Hz clock input for timing
input wire charAvailable, // A character is available to be read
input wire [6:0] charInput, // The next character to read
// Outputs
output wire [6:0] out // 7-segment out
);
reg [6:0] segsOut;
reg [6:0] currentChar; // Current 7-segment character to be displayed
reg [6:0] segChecked; // Flags whether the segment has been evaluated for display
reg [2:0] segIndex; // Debug for displaying segments sequentially
reg [5:0] timerCount; // 6-bit segment animation timer (64 ticks)
// Registers used for rising edge detection while avoiding multidriven errors
reg charAvailable_prev;
reg clk60_prev;
// States
reg [1:0] state;
localparam idle_state = 2'b00;
localparam getChar_state = 2'b01;
localparam getSeg_state = 2'b10;
assign out = segsOut;
always @(posedge clk) begin
if (reset) begin
segsOut <= 0;
currentChar <= 0;
segChecked <= 0;
segIndex <= 0;
timerCount <= 0;
state <= idle_state;
charAvailable_prev <= 0;
clk60_prev <= 0;
end
else if (enable) begin
// Check for rising edges
// Read the character from charInput on the rising edge of charAvailable
if (charAvailable == 1 && charAvailable_prev == 0) begin
state <= getChar_state;
end
// Update the timer on the rising edge of clk60
else if (clk60 == 1 && clk60_prev == 0) begin
if (timerCount > 0) begin
timerCount <= timerCount - 1;
if (timerCount == 1) state <= getSeg_state; // Get the next segment after the timer expires
end
end
// If there are no rising edges then process the current state
else begin
case(state)
getSeg_state: begin
// Find the next valid segment, one clock at a time
// If the current segment index is a valid segment,
// display it and start the timer
if (currentChar[segIndex] == 1) begin
segsOut[segIndex] <= 1;
// Start the timer and move to idle state
timerCount <= 7; // delay for 7 timer ticks = 7/60 or 0.117 seconds
state <= idle_state;
end
// Mark that the segment has been checked
segChecked[segIndex] <= 1;
// Move to the next segment to check (debug)
segIndex <= segIndex + 1;
// 3. If all the segments have been checked, idle
if (segChecked == 7'b1111111) begin
state <= idle_state;
end
end
getChar_state: begin
// *** Reset variables ***
segsOut <= 0; // Reset the display
currentChar <= charInput; // Get the next input character here
segChecked <= 0;
segIndex <= 0;
timerCount <= 0;
// Done getting the new character
// Start displaying the segments
state <= getSeg_state;
end
default:;
endcase
end
// Update the signal status registers used for edge detection
charAvailable_prev <= charAvailable;
clk60_prev <= clk60;
end /* end else if (enable) */
end /* end always block */
endmodule
/*
* Copyright (c) 2024 Aron Dennen
* SPDX-License-Identifier: Apache-2.0
*/
// Inputs a 12.5 MHz signal and outputs a 122400 Hz (480Hz * 255 Pwm periods/clock) and 60 Hz clock signal
// Outputs toggle at twice the output frequency to maintin N rising edges per second
module clock_divider (
// Inputs
input wire clk,
input wire reset,
// Outputs
output wire clkPwm,
output wire clk60
);
reg [5:0] count; // 6-bit counter for 12.5 MHz -> 122,400 Hz signal (51 counts per transition)
reg [9:0] count2; // 10-bit counter for 122,400 Hz -> 60 Hz signal (1020 counts per transition)
reg outPwm;
reg out60;
assign clkPwm = outPwm;
assign clk60 = out60;
always @(posedge clk) begin
if (reset) begin
count <= 0;
outPwm <= 0;
end
else begin
count <= count + 1;
if (count == 51) begin
// reset the main counter
count <= 0;
outPwm <= ~outPwm;
end
end
end
always @(posedge outPwm) begin
if (reset) begin
count2 <= 0;
out60 <= 0;
end
else begin
count2 <= count2 + 1;
if (count2 == 1020) begin
count2 <= 0;
out60 <= ~out60;
end
end
end
endmodule
/*
* Copyright (c) 2024 Aron Dennen
* SPDX-License-Identifier: Apache-2.0
*/
// 8-bit pwm, pwmValue 0 = fully off, pwmValue 255 = fully on
// rolls the count over at 254 to prevent the off-by-one error
// which prevents 255 from being fully on
module pwm (
// Inputs
input wire enable,
input wire clk,
input wire reset,
input wire [7:0] pwmValue,
// Outputs
output wire pwmOut
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
|
module pwm (
// Inputs
input wire enable,
input wire clk,
input wire reset,
input wire [7:0] pwmValue,
// Outputs
output wire pwmOut
);
reg [7:0] pwmCount;
reg out;
assign pwmOut = out;
always @(posedge clk) begin
if (enable) begin
if (reset) begin
pwmCount <= 0;
out <= 0;
end
else if (enable) begin
out <= (pwmCount < pwmValue) ? 1 : 0;
pwmCount <= pwmCount + 1;
if (pwmCount == 254) pwmCount <= 0; // Off-by-one error fix
end
end
end
endmodule
|
tt06-finale_0044
|
tt06-finale
|
adennen-tt06-arond-project
|
task_segment_animator
|
tt_um_7seg_animated
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Aron Dennen
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_7seg_animated (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
reg reset;
// *** Clock divider vars
wire clkPwm;
wire clk60;
clock_divider clk_divider (
.clk(clk),
.reset(reset),
.clkPwm(clkPwm),
.clk60(clk60)
);
// *** PWM module vars
reg pwmOut;
pwm pwm (
.enable(ena),
.clk(clkPwm),
.reset(reset),
.pwmValue( { uio_in[6:0], 1'b0 } ),
.pwmOut(pwmOut)
);
// *** Segment animator vars
reg [6:0] charInput;
wire [6:0] displayOut;
segment_animator animator (
.enable(ena),
.clk(clk),
.clk60(clk60),
.reset(reset),
.charAvailable(ui_in[7]),
.charInput(charInput),
.out(displayOut)
);
// *** Main program
reg [7:0] out;
assign uo_out = out;
always @(posedge clk) begin
reset <= ~rst_n;
charInput <= ui_in[6:0];
if (uio_in[7]) begin
out[6:0] <= (pwmOut) ? displayOut : 7'b0000000;
end
else out[6:0] <= displayOut;
out[7] <= ui_in[7];
end
// All output pins must be assigned. If not used, assign to 0.
//assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in
assign uio_out = 0;
assign uio_oe = 0;
endmodule
/*
* Copyright (c) 2024 Aron Dennen
* SPDX-License-Identifier: Apache-2.0
*/
// Iterates over the bits of a 7-segment character, sets the output segments individually with a delay period
module segment_animator (
// Inputs
input wire reset,
input wire enable,
input wire clk,
input wire clk60, // 60Hz clock input for timing
input wire charAvailable, // A character is available to be read
input wire [6:0] charInput, // The next character to read
// Outputs
output wire [6:0] out // 7-segment out
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
/*
* Copyright (c) 2024 Aron Dennen
* SPDX-License-Identifier: Apache-2.0
*/
// Inputs a 12.5 MHz signal and outputs a 122400 Hz (480Hz * 255 Pwm periods/clock) and 60 Hz clock signal
// Outputs toggle at twice the output frequency to maintin N rising edges per second
module clock_divider (
// Inputs
input wire clk,
input wire reset,
// Outputs
output wire clkPwm,
output wire clk60
);
reg [5:0] count; // 6-bit counter for 12.5 MHz -> 122,400 Hz signal (51 counts per transition)
reg [9:0] count2; // 10-bit counter for 122,400 Hz -> 60 Hz signal (1020 counts per transition)
reg outPwm;
reg out60;
assign clkPwm = outPwm;
assign clk60 = out60;
always @(posedge clk) begin
if (reset) begin
count <= 0;
outPwm <= 0;
end
else begin
count <= count + 1;
if (count == 51) begin
// reset the main counter
count <= 0;
outPwm <= ~outPwm;
end
end
end
always @(posedge outPwm) begin
if (reset) begin
count2 <= 0;
out60 <= 0;
end
else begin
count2 <= count2 + 1;
if (count2 == 1020) begin
count2 <= 0;
out60 <= ~out60;
end
end
end
endmodule
/*
* Copyright (c) 2024 Aron Dennen
* SPDX-License-Identifier: Apache-2.0
*/
// 8-bit pwm, pwmValue 0 = fully off, pwmValue 255 = fully on
// rolls the count over at 254 to prevent the off-by-one error
// which prevents 255 from being fully on
module pwm (
// Inputs
input wire enable,
input wire clk,
input wire reset,
input wire [7:0] pwmValue,
// Outputs
output wire pwmOut
);
reg [7:0] pwmCount;
reg out;
assign pwmOut = out;
always @(posedge clk) begin
if (enable) begin
if (reset) begin
pwmCount <= 0;
out <= 0;
end
else if (enable) begin
out <= (pwmCount < pwmValue) ? 1 : 0;
pwmCount <= pwmCount + 1;
if (pwmCount == 254) pwmCount <= 0; // Off-by-one error fix
end
end
end
endmodule
|
module segment_animator (
// Inputs
input wire reset,
input wire enable,
input wire clk,
input wire clk60, // 60Hz clock input for timing
input wire charAvailable, // A character is available to be read
input wire [6:0] charInput, // The next character to read
// Outputs
output wire [6:0] out // 7-segment out
);
reg [6:0] segsOut;
reg [6:0] currentChar; // Current 7-segment character to be displayed
reg [6:0] segChecked; // Flags whether the segment has been evaluated for display
reg [2:0] segIndex; // Debug for displaying segments sequentially
reg [5:0] timerCount; // 6-bit segment animation timer (64 ticks)
// Registers used for rising edge detection while avoiding multidriven errors
reg charAvailable_prev;
reg clk60_prev;
// States
reg [1:0] state;
localparam idle_state = 2'b00;
localparam getChar_state = 2'b01;
localparam getSeg_state = 2'b10;
assign out = segsOut;
always @(posedge clk) begin
if (reset) begin
segsOut <= 0;
currentChar <= 0;
segChecked <= 0;
segIndex <= 0;
timerCount <= 0;
state <= idle_state;
charAvailable_prev <= 0;
clk60_prev <= 0;
end
else if (enable) begin
// Check for rising edges
// Read the character from charInput on the rising edge of charAvailable
if (charAvailable == 1 && charAvailable_prev == 0) begin
state <= getChar_state;
end
// Update the timer on the rising edge of clk60
else if (clk60 == 1 && clk60_prev == 0) begin
if (timerCount > 0) begin
timerCount <= timerCount - 1;
if (timerCount == 1) state <= getSeg_state; // Get the next segment after the timer expires
end
end
// If there are no rising edges then process the current state
else begin
case(state)
getSeg_state: begin
// Find the next valid segment, one clock at a time
// If the current segment index is a valid segment,
// display it and start the timer
if (currentChar[segIndex] == 1) begin
segsOut[segIndex] <= 1;
// Start the timer and move to idle state
timerCount <= 7; // delay for 7 timer ticks = 7/60 or 0.117 seconds
state <= idle_state;
end
// Mark that the segment has been checked
segChecked[segIndex] <= 1;
// Move to the next segment to check (debug)
segIndex <= segIndex + 1;
// 3. If all the segments have been checked, idle
if (segChecked == 7'b1111111) begin
state <= idle_state;
end
end
getChar_state: begin
// *** Reset variables ***
segsOut <= 0; // Reset the display
currentChar <= charInput; // Get the next input character here
segChecked <= 0;
segIndex <= 0;
timerCount <= 0;
// Done getting the new character
// Start displaying the segments
state <= getSeg_state;
end
default:;
endcase
end
// Update the signal status registers used for edge detection
charAvailable_prev <= charAvailable;
clk60_prev <= clk60;
end /* end else if (enable) */
end /* end always block */
endmodule
|
tt06-finale_0045
|
tt06-finale
|
adennen-tt06-arond-project
|
task_tt_um_7seg_animated
|
tt_um_7seg_animated
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Aron Dennen
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_7seg_animated (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
/*
* Copyright (c) 2024 Aron Dennen
* SPDX-License-Identifier: Apache-2.0
*/
// Iterates over the bits of a 7-segment character, sets the output segments individually with a delay period
module segment_animator (
// Inputs
input wire reset,
input wire enable,
input wire clk,
input wire clk60, // 60Hz clock input for timing
input wire charAvailable, // A character is available to be read
input wire [6:0] charInput, // The next character to read
// Outputs
output wire [6:0] out // 7-segment out
);
reg [6:0] segsOut;
reg [6:0] currentChar; // Current 7-segment character to be displayed
reg [6:0] segChecked; // Flags whether the segment has been evaluated for display
reg [2:0] segIndex; // Debug for displaying segments sequentially
reg [5:0] timerCount; // 6-bit segment animation timer (64 ticks)
// Registers used for rising edge detection while avoiding multidriven errors
reg charAvailable_prev;
reg clk60_prev;
// States
reg [1:0] state;
localparam idle_state = 2'b00;
localparam getChar_state = 2'b01;
localparam getSeg_state = 2'b10;
assign out = segsOut;
always @(posedge clk) begin
if (reset) begin
segsOut <= 0;
currentChar <= 0;
segChecked <= 0;
segIndex <= 0;
timerCount <= 0;
state <= idle_state;
charAvailable_prev <= 0;
clk60_prev <= 0;
end
else if (enable) begin
// Check for rising edges
// Read the character from charInput on the rising edge of charAvailable
if (charAvailable == 1 && charAvailable_prev == 0) begin
state <= getChar_state;
end
// Update the timer on the rising edge of clk60
else if (clk60 == 1 && clk60_prev == 0) begin
if (timerCount > 0) begin
timerCount <= timerCount - 1;
if (timerCount == 1) state <= getSeg_state; // Get the next segment after the timer expires
end
end
// If there are no rising edges then process the current state
else begin
case(state)
getSeg_state: begin
// Find the next valid segment, one clock at a time
// If the current segment index is a valid segment,
// display it and start the timer
if (currentChar[segIndex] == 1) begin
segsOut[segIndex] <= 1;
// Start the timer and move to idle state
timerCount <= 7; // delay for 7 timer ticks = 7/60 or 0.117 seconds
state <= idle_state;
end
// Mark that the segment has been checked
segChecked[segIndex] <= 1;
// Move to the next segment to check (debug)
segIndex <= segIndex + 1;
// 3. If all the segments have been checked, idle
if (segChecked == 7'b1111111) begin
state <= idle_state;
end
end
getChar_state: begin
// *** Reset variables ***
segsOut <= 0; // Reset the display
currentChar <= charInput; // Get the next input character here
segChecked <= 0;
segIndex <= 0;
timerCount <= 0;
// Done getting the new character
// Start displaying the segments
state <= getSeg_state;
end
default:;
endcase
end
// Update the signal status registers used for edge detection
charAvailable_prev <= charAvailable;
clk60_prev <= clk60;
end /* end else if (enable) */
end /* end always block */
endmodule
/*
* Copyright (c) 2024 Aron Dennen
* SPDX-License-Identifier: Apache-2.0
*/
// Inputs a 12.5 MHz signal and outputs a 122400 Hz (480Hz * 255 Pwm periods/clock) and 60 Hz clock signal
// Outputs toggle at twice the output frequency to maintin N rising edges per second
module clock_divider (
// Inputs
input wire clk,
input wire reset,
// Outputs
output wire clkPwm,
output wire clk60
);
reg [5:0] count; // 6-bit counter for 12.5 MHz -> 122,400 Hz signal (51 counts per transition)
reg [9:0] count2; // 10-bit counter for 122,400 Hz -> 60 Hz signal (1020 counts per transition)
reg outPwm;
reg out60;
assign clkPwm = outPwm;
assign clk60 = out60;
always @(posedge clk) begin
if (reset) begin
count <= 0;
outPwm <= 0;
end
else begin
count <= count + 1;
if (count == 51) begin
// reset the main counter
count <= 0;
outPwm <= ~outPwm;
end
end
end
always @(posedge outPwm) begin
if (reset) begin
count2 <= 0;
out60 <= 0;
end
else begin
count2 <= count2 + 1;
if (count2 == 1020) begin
count2 <= 0;
out60 <= ~out60;
end
end
end
endmodule
/*
* Copyright (c) 2024 Aron Dennen
* SPDX-License-Identifier: Apache-2.0
*/
// 8-bit pwm, pwmValue 0 = fully off, pwmValue 255 = fully on
// rolls the count over at 254 to prevent the off-by-one error
// which prevents 255 from being fully on
module pwm (
// Inputs
input wire enable,
input wire clk,
input wire reset,
input wire [7:0] pwmValue,
// Outputs
output wire pwmOut
);
reg [7:0] pwmCount;
reg out;
assign pwmOut = out;
always @(posedge clk) begin
if (enable) begin
if (reset) begin
pwmCount <= 0;
out <= 0;
end
else if (enable) begin
out <= (pwmCount < pwmValue) ? 1 : 0;
pwmCount <= pwmCount + 1;
if (pwmCount == 254) pwmCount <= 0; // Off-by-one error fix
end
end
end
endmodule
|
module tt_um_7seg_animated (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
reg reset;
// *** Clock divider vars
wire clkPwm;
wire clk60;
clock_divider clk_divider (
.clk(clk),
.reset(reset),
.clkPwm(clkPwm),
.clk60(clk60)
);
// *** PWM module vars
reg pwmOut;
pwm pwm (
.enable(ena),
.clk(clkPwm),
.reset(reset),
.pwmValue( { uio_in[6:0], 1'b0 } ),
.pwmOut(pwmOut)
);
// *** Segment animator vars
reg [6:0] charInput;
wire [6:0] displayOut;
segment_animator animator (
.enable(ena),
.clk(clk),
.clk60(clk60),
.reset(reset),
.charAvailable(ui_in[7]),
.charInput(charInput),
.out(displayOut)
);
// *** Main program
reg [7:0] out;
assign uo_out = out;
always @(posedge clk) begin
reset <= ~rst_n;
charInput <= ui_in[6:0];
if (uio_in[7]) begin
out[6:0] <= (pwmOut) ? displayOut : 7'b0000000;
end
else out[6:0] <= displayOut;
out[7] <= ui_in[7];
end
// All output pins must be assigned. If not used, assign to 0.
//assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in
assign uio_out = 0;
assign uio_oe = 0;
endmodule
|
tt06-finale_0046
|
tt06-finale
|
aiju-tt06-aiju-8080
|
task_bus_if
|
tt_um_aiju_8080
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_aiju_8080 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] bus_data_out; // From bus_if_i of bus_if.v
wire bus_handshake_req; // From bus_if_i of bus_if.v
wire bus_io; // From bus_if_i of bus_if.v
wire bus_output_enable; // From bus_if_i of bus_if.v
wire [1:0] bus_state; // From bus_if_i of bus_if.v
wire cpu_fetch; // From cpu_i of cpu.v
wire cpu_halted; // From cpu_i of cpu.v
wire cpu_in_debug; // From cpu_i of cpu.v
wire cpu_int_ack; // From cpu_i of cpu.v
wire [15:0] memory_addr; // From cpu_i of cpu.v
wire memory_done; // From bus_if_i of bus_if.v
wire memory_io; // From cpu_i of cpu.v
wire [7:0] memory_rdata; // From bus_if_i of bus_if.v
wire memory_read; // From cpu_i of cpu.v
wire [7:0] memory_wdata; // From cpu_i of cpu.v
wire memory_write; // From cpu_i of cpu.v
// End of automatics
assign uo_out[0] = bus_handshake_req;
assign uo_out[1] = bus_state[0];
assign uo_out[2] = bus_state[1];
assign uo_out[3] = bus_io;
assign uo_out[4] = cpu_fetch;
assign uo_out[5] = cpu_in_debug;
assign uo_out[6] = cpu_halted;
assign uo_out[7] = cpu_int_ack;
wire ext_bus_handshake_ack = ui_in[0];
wire ext_debug_req = ui_in[1];
wire ext_int_req = ui_in[2];
wire bus_handshake_ack;
(*keep_hierarchy*) sync bus_handshake_ack_sync(
.clk(clk),
.rst_n(rst_n),
.in(ext_bus_handshake_ack),
.out(bus_handshake_ack)
);
wire debug_req;
(*keep_hierarchy*) sync debug_req_sync(
.clk(clk),
.rst_n(rst_n),
.in(ext_debug_req),
.out(debug_req)
);
wire int_req;
(*keep_hierarchy*) sync int_req_sync(
.clk(clk),
.rst_n(rst_n),
.in(ext_int_req),
.out(int_req)
);
wire [7:0] bus_data_in = uio_in;
assign uio_out = bus_data_out;
assign uio_oe = {8{bus_output_enable}};
bus_if bus_if_i(/*AUTOINST*/
// Outputs
.bus_handshake_req(bus_handshake_req),
.bus_state (bus_state[1:0]),
.bus_data_out (bus_data_out[7:0]),
.bus_output_enable(bus_output_enable),
.bus_io (bus_io),
.memory_rdata (memory_rdata[7:0]),
.memory_done (memory_done),
// Inputs
.clk (clk),
.rst_n (rst_n),
.bus_handshake_ack(bus_handshake_ack),
.bus_data_in (bus_data_in[7:0]),
.memory_read (memory_read),
.memory_write (memory_write),
.memory_addr (memory_addr[15:0]),
.memory_io (memory_io),
.memory_wdata (memory_wdata[7:0]));
cpu cpu_i(/*AUTOINST*/
// Outputs
.memory_read (memory_read),
.memory_write (memory_write),
.memory_addr (memory_addr[15:0]),
.memory_io (memory_io),
.memory_wdata (memory_wdata[7:0]),
.cpu_fetch (cpu_fetch),
.cpu_halted (cpu_halted),
.cpu_in_debug (cpu_in_debug),
.cpu_int_ack (cpu_int_ack),
// Inputs
.clk (clk),
.rst_n (rst_n),
.memory_rdata (memory_rdata[7:0]),
.memory_done (memory_done),
.debug_req (debug_req),
.int_req (int_req));
endmodule
module sync(
input wire clk,
input wire rst_n,
input wire in,
output wire out
);
(* keep *) reg a;
(* keep *) reg b;
assign out = b;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
a <= 1'b0;
b <= 1'b0;
end else begin
a <= in;
b <= a;
end
end
endmodule
`default_nettype none
module bus_if(
input wire clk,
input wire rst_n,
input wire bus_handshake_ack,
output reg bus_handshake_req,
output reg [1:0] bus_state,
input wire [7:0] bus_data_in,
output reg [7:0] bus_data_out,
output reg bus_output_enable,
output wire bus_io,
input wire memory_read,
input wire memory_write,
input wire [15:0] memory_addr,
input wire memory_io,
input wire [7:0] memory_wdata,
output reg [7:0] memory_rdata,
output reg memory_done
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
`default_nettype none
module cpu(
input wire clk,
input wire rst_n,
output reg memory_read,
output reg memory_write,
output reg [15:0] memory_addr,
output reg memory_io,
output reg [7:0] memory_wdata,
input wire [7:0] memory_rdata,
input wire memory_done,
input wire debug_req,
input wire int_req,
output wire cpu_fetch,
output wire cpu_halted,
output wire cpu_in_debug,
output wire cpu_int_ack
);
reg [15:0] AL;
reg [15:0] rPC;
reg [15:0] rSP;
reg [7:0] rA, rB, rC, rD, rE, rH, rL;
reg [7:0] rPSR;
reg [7:0] rIR;
reg [5:0] state;
localparam CPU_FETCH = 0;
localparam CPU_DECODE = 1;
localparam CPU_MVI0 = 2;
localparam CPU_MVI1 = 3;
localparam CPU_ALU0 = 4;
localparam CPU_ALU1 = 5;
localparam CPU_MOV = 6;
localparam CPU_JMP0 = 7;
localparam CPU_JMP1 = 8;
localparam CPU_PUSH0 = 9;
localparam CPU_PUSH1 = 10;
localparam CPU_PUSH2 = 11;
localparam CPU_POP0 = 12;
localparam CPU_POP1 = 13;
localparam CPU_HALT = 14;
localparam CPU_LXI0 = 15;
localparam CPU_LXI1 = 16;
localparam CPU_DIRECT0 = 17;
localparam CPU_DIRECT1 = 18;
localparam CPU_DIRECT2 = 19;
localparam CPU_DIRECT3 = 20;
localparam CPU_UNARY = 21;
localparam CPU_CALL0 = 22;
localparam CPU_CALL1 = 23;
localparam CPU_CALL2 = 24;
localparam CPU_CALL3 = 25;
localparam CPU_RET0 = 26;
localparam CPU_RET1 = 27;
localparam CPU_PCHL0 = 28;
localparam CPU_PCHL1 = 29;
localparam CPU_PCHL2 = 30;
localparam CPU_SPHL0 = 31;
localparam CPU_SPHL1 = 32;
localparam CPU_INRDCR0 = 33;
localparam CPU_INRDCR1 = 34;
localparam CPU_INXDCX0 = 35;
localparam CPU_INXDCX1 = 36;
localparam CPU_INXDCX2 = 37;
localparam CPU_INXDCX3 = 38;
localparam CPU_LDAXSTAX0 = 39;
localparam CPU_LDAXSTAX1 = 40;
localparam CPU_LDAXSTAX2 = 41;
localparam CPU_XCHG0 = 42;
localparam CPU_XCHG1 = 43;
localparam CPU_XCHG2 = 44;
localparam CPU_XCHG3 = 45;
localparam CPU_XCHG4 = 46;
localparam CPU_XCHG5 = 47;
localparam CPU_DAD0 = 48;
localparam CPU_DAD1 = 49;
localparam CPU_DAD2 = 50;
localparam CPU_DAD3 = 51;
localparam CPU_DAD4 = 52;
localparam CPU_DAD5 = 53;
localparam CPU_DAD6 = 54;
localparam CPU_DAD7 = 55;
localparam CPU_IO0 = 56;
localparam CPU_IO1 = 57;
localparam CPU_EIDI = 58;
localparam CPU_DEBUG0 = 62;
localparam CPU_DEBUG1 = 63;
wire iMOV = rIR[7:6] == 1 && rIR != 8'b01110110;
wire iALU = rIR[7:6] == 2;
wire iALUI = (rIR & ~8'h38) == 8'b1100_0110;
wire iMVI = rIR[7:6] == 0 && rIR[2:0] == 3'b110;
wire iJMP = rIR == 8'b1100_0011;
wire iPUSH = (rIR & ~8'h30) == 8'b1100_0101;
wire iPOP = (rIR & ~8'h30) == 8'b1100_0001;
wire iHALT = rIR == 8'h76;
wire iLXI = (rIR & ~8'h30) == 8'b0000_0001;
wire iLDA = rIR == 8'h3A;
wire iSTA = rIR == 8'h32;
wire iLHLD = rIR == 8'h2A;
wire iSHLD = rIR == 8'h22;
wire iUNARY = (rIR & ~8'h38) == 8'b0000_0111;
wire iCALL = rIR == 8'hCD;
wire iCALLcc = (rIR & ~8'h38) == 8'b1100_0100;
wire iRST = (rIR & ~8'h38) == 8'b1100_0111;
wire iRET = rIR == 8'hC9;
wire iRETcc = (rIR & ~8'h38) == 8'b1100_0000;
wire iJMPcc = (rIR & ~8'h38) == 8'b1100_0010;
wire iPCHL = rIR == 8'hE9;
wire iSPHL = rIR == 8'hF9;
wire iINR = (rIR & ~8'h38) == 8'b0000_0100;
wire iDCR = (rIR & ~8'h38) == 8'b0000_0101;
wire iINX = (rIR & ~8'h30) == 8'b0000_0011;
wire iDCX = (rIR & ~8'h30) == 8'b0000_1011;
wire iINX_SP = rIR == 8'b0011_0011;
wire iDCX_SP = rIR == 8'b0011_1011;
wire iLDAX = (rIR & ~8'h10) == 8'b0000_1010;
wire iSTAX = (rIR & ~8'h10) == 8'b0000_0010;
wire iXCHG = rIR == 8'b1110_1011;
wire iXTHL = rIR == 8'b1110_0011;
wire iDAD = (rIR & ~8'h30) == 8'b0000_1001;
wire iIN = rIR == 8'b1101_1011;
wire iOUT = rIR == 8'b1101_0011;
wire iNOP = rIR == 8'b0000_0000;
wire iEI = rIR == 8'b1111_1011;
wire iDI = rIR == 8'b1111_0011;
wire undefined =
(rIR & ~8'h38) == 8'b0000_0000 && !iNOP
|| rIR == 8'b1101_1001
|| (rIR & ~8'h30) == 8'b1100_1101 && !iCALL
|| rIR == 8'b1100_1011;
wire memory_operand =
iMOV && (rIR[5:3] == 3'b110 || rIR[2:0] == 3'b110)
|| iALU && rIR[2:0] == 3'b110
|| (iINR || iDCR || iMVI) && rIR[5:3] == 3'b110;
wire dbgEXIT = rIR[6];
wire dbgREAD = !rIR[7] && !dbgEXIT;
wire dbgWRITE = rIR[7];
reg condition;
always @(*) begin
case(rIR[5:3])
3'b000: condition = !rPSR[6];
3'b001: condition = rPSR[6];
3'b010: condition = !rPSR[0];
3'b011: condition = rPSR[0];
3'b100: condition = !rPSR[2];
3'b101: condition = rPSR[2];
3'b110: condition = !rPSR[7];
3'b111: condition = rPSR[7];
endcase
end
reg int_enabled;
reg int_latch;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
int_enabled <= 1'b0;
int_latch <= 1'b0;
end else begin
if(state == CPU_EIDI) begin
if(iEI)
int_enabled <= 1'b1;
if(iDI)
int_enabled <= 1'b0;
end
if(cpu_int_ack)
int_enabled <= 1'b0;
if(cycle_done)
int_latch <= int_req && int_enabled && !(state == CPU_EIDI && iDI || cpu_int_ack);
end
end
assign cpu_int_ack = state == CPU_FETCH && int_latch;
reg [5:0] decode_goto;
reg missing_decoder_case;
always @(*) begin
decode_goto = CPU_FETCH;
missing_decoder_case = 1'b0;
case(1'b1)
iMOV: decode_goto = CPU_MOV;
iALU, iALUI: decode_goto = CPU_ALU0;
iMVI: decode_goto = CPU_MVI0;
iJMP, iJMPcc: decode_goto = CPU_JMP0;
iPUSH: decode_goto = CPU_PUSH0;
iPOP: decode_goto = CPU_POP0;
iHALT: decode_goto = CPU_HALT;
iLXI: decode_goto = CPU_LXI0;
iLDA, iSTA, iLHLD, iSHLD: decode_goto = CPU_DIRECT0;
iUNARY: decode_goto = CPU_UNARY;
iCALL, iCALLcc, iRST: decode_goto = CPU_CALL0;
iRET: decode_goto = CPU_RET0;
iRETcc: decode_goto = condition ? CPU_RET0 : CPU_FETCH;
iPCHL: decode_goto = CPU_PCHL0;
iSPHL: decode_goto = CPU_SPHL0;
iINR, iDCR: decode_goto = CPU_INRDCR0;
iINX, iDCX: decode_goto = CPU_INXDCX0;
iLDAX, iSTAX: decode_goto = CPU_LDAXSTAX0;
iXCHG, iXTHL: decode_goto = CPU_XCHG0;
iDAD: decode_goto = CPU_DAD0;
iIN, iOUT: decode_goto = CPU_IO0;
iNOP, undefined: decode_goto = CPU_FETCH;
iEI, iDI: decode_goto = CPU_EIDI;
default: missing_decoder_case = 1'b1;
endcase
end
always @(posedge clk) begin
if(state == CPU_DECODE && undefined)
$display("undefined opcode %x", rIR);
end
reg [7:0] aluIn;
reg [7:0] aluOut;
reg alu_carry_out, alu_aux_carry_out;
reg [4:0] alu_op;
reg [7:0] set_flags;
localparam ALU_ADD = 0;
localparam ALU_ADC = 1;
localparam ALU_SUB = 2;
localparam ALU_SBB = 3;
localparam ALU_AND = 4;
localparam ALU_XOR = 5;
localparam ALU_OR = 6;
localparam ALU_CMP = 7;
localparam ALU_RLC = 8;
localparam ALU_RRC = 9;
localparam ALU_RAL = 10;
localparam ALU_RAR = 11;
localparam ALU_DAA = 12;
localparam ALU_CMA = 13;
localparam ALU_STC = 14;
localparam ALU_CMC = 15;
localparam ALU_INC = 16;
localparam ALU_DEC = 17;
localparam ALU_NOP = 31;
reg [7:0] daa_operand;
always @(*) begin
daa_operand = 8'h00;
if(rA[3:0] > 9 || rPSR[4])
daa_operand[3:0] = 6;
if(rA >= 8'h9a || rPSR[0])
daa_operand[7:4] = 6;
end
always @(*) begin
alu_carry_out = 1'b0;
alu_aux_carry_out = 1'b0;
aluOut = aluIn;
case(alu_op)
ALU_ADD, ALU_ADC: begin
{alu_carry_out, aluOut} = rA + aluIn + (rPSR[0] & (alu_op == ALU_ADC));
alu_aux_carry_out = (((rA & 15) + (aluIn & 15) + (rPSR[0] & (alu_op == ALU_ADC))) & 16) != 0;
end
ALU_SUB, ALU_SBB, ALU_CMP: begin
{alu_carry_out, aluOut} = rA - aluIn - (rPSR[0] & (alu_op == ALU_SBB));
alu_aux_carry_out = (((rA & 15) - (aluIn & 15) - (rPSR[0] & (alu_op == ALU_SBB))) & 16) == 0;
end
ALU_AND: begin
aluOut = rA & aluIn;
alu_aux_carry_out = rA[3] | aluIn[3];
end
ALU_OR:
aluOut = rA | aluIn;
ALU_XOR:
aluOut = rA ^ aluIn;
ALU_RLC: begin
aluOut = {rA[6:0], rA[7]};
alu_carry_out = rA[7];
end
ALU_RRC: begin
aluOut = {rA[0], rA[7:1]};
alu_carry_out = rA[0];
end
ALU_RAL: begin
{alu_carry_out, aluOut} = {rA, rPSR[0]};
end
ALU_RAR: begin
{aluOut, alu_carry_out} = {rPSR[0], rA};
end
ALU_CMA: aluOut = ~rA;
ALU_CMC: begin
aluOut = rA;
alu_carry_out = ~rPSR[0];
end
ALU_STC: begin
aluOut = rA;
alu_carry_out = 1'b1;
end
ALU_DAA: begin
{alu_carry_out, aluOut} = (rA + daa_operand) | (rPSR[0] ? 9'h100 : 9'h000);
alu_aux_carry_out = (((rA & 15) + (daa_operand & 15)) & 16) != 0;
end
ALU_INC: begin
{alu_carry_out, aluOut} = aluIn + 1;
alu_aux_carry_out = (aluIn & 15) == 15;
end
ALU_DEC: begin
{alu_carry_out, aluOut} = aluIn - 1;
alu_aux_carry_out = (aluIn & 15) != 0;
end
endcase
end
wire alu_zero = aluOut == 0;
wire alu_parity = ~^aluOut;
wire alu_sign = aluOut[7];
wire [7:0] alu_flags = {alu_sign, alu_zero, 1'b0, alu_aux_carry_out, 1'b0, alu_parity, 1'b1, alu_carry_out};
wire cycle_done = !memory_read && !memory_write || memory_done;
wire pc_increment =
state == CPU_FETCH && !debug_req && !cpu_int_ack
|| state == CPU_MVI0 || state == CPU_JMP0 || state == CPU_JMP1 && iJMPcc && !condition
|| state == CPU_ALU0 && iALUI
|| state == CPU_LXI0 || state == CPU_LXI1
|| state == CPU_DIRECT0 || state == CPU_DIRECT1
|| (state == CPU_CALL0 || state == CPU_CALL1) && !iRST
|| state == CPU_IO0;
wire al_increment = state == CPU_DIRECT2;
wire sp_decrement =
state == CPU_PUSH0 || state == CPU_PUSH1
|| state == CPU_CALL1 && (!iCALLcc || condition)
|| state == CPU_CALL2
|| state == CPU_INXDCX0 && iDCX_SP
|| state == CPU_XCHG5 && iXTHL;
wire sp_increment =
state == CPU_POP0 || state == CPU_POP1
|| state == CPU_RET0 || state == CPU_RET1
|| state == CPU_INXDCX0 && iINX_SP
|| state == CPU_XCHG2 && iXTHL;
wire pc_jmp =
state == CPU_JMP1 && (!iJMPcc || condition)
|| state == CPU_RET1;
wire pc_jmp_al = state == CPU_CALL3 && !iRST || state == CPU_PCHL2;
wire pc_rst_jmp = state == CPU_CALL3 && iRST;
wire ir_load = state == CPU_FETCH || state == CPU_DEBUG0;
assign cpu_fetch = state == CPU_FETCH;
assign cpu_halted = state == CPU_HALT;
assign cpu_in_debug = state == CPU_DEBUG0 || state == CPU_DEBUG1;
reg [4:0] db_dst;
reg [4:0] db_src;
localparam DB_ALL = 5'b00010;
localparam DB_ALH = 5'b00011;
localparam DB_SPL = 5'b00100;
localparam DB_SPH = 5'b00101;
localparam DB_PSR = 5'b00110;
localparam DB_ALU = 5'b00111;
localparam DB_B = 5'b01000;
localparam DB_C = 5'b01001;
localparam DB_D = 5'b01010;
localparam DB_E = 5'b01011;
localparam DB_H = 5'b01100;
localparam DB_L = 5'b01101;
localparam DB_MEM = 5'b01110;
localparam DB_A = 5'b01111;
localparam DB_PCL = 5'b10000;
localparam DB_PCH = 5'b10001;
reg [7:0] DB;
always @(*) begin
DB = 8'bx;
case(db_src)
DB_PSR: DB = rPSR;
DB_ALU: DB = aluOut;
DB_B: DB = rB;
DB_C: DB = rC;
DB_D: DB = rD;
DB_E: DB = rE;
DB_H: DB = rH;
DB_L: DB = rL;
DB_MEM: DB = memory_rdata;
DB_A: DB = rA;
DB_SPL: DB = rSP[7:0];
DB_SPH: DB = rSP[15:8];
DB_PCL: DB = rPC[7:0];
DB_PCH: DB = rPC[15:8];
DB_ALL: DB = AL[7:0];
DB_ALH: DB = AL[15:8];
endcase
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
rPC <= 0;
rIR <= 0;
rSP <= 0;
AL <= 0;
end else begin
if(cycle_done) begin
if(pc_increment)
rPC <= rPC + 1;
if(pc_jmp)
rPC <= {memory_rdata, aluIn};
if(pc_jmp_al)
rPC <= AL;
if(pc_rst_jmp)
rPC <= rIR & 8'h38;
if(ir_load)
rIR <= memory_rdata;
if(db_dst == DB_SPH)
rSP[15:8] <= DB;
if(db_dst == DB_SPL)
rSP[7:0] <= DB;
if(sp_increment)
rSP <= rSP + 1;
if(sp_decrement)
rSP <= rSP - 1;
if(db_dst == DB_ALH)
AL[15:8] <= DB;
if(db_dst == DB_ALL)
AL[7:0] <= DB;
if(al_increment)
AL <= AL + 1;
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
rPSR <= 2;
end else begin
if(cycle_done) begin
if(db_dst == DB_PSR)
rPSR <= DB & ~8'h28 | 2;
else
rPSR <= (rPSR & ~set_flags | alu_flags & set_flags) & ~8'h28 | 2;
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
{rA, rB, rC, rD, rE, rH, rL} <= 0;
aluIn <= 0;
end else begin
if(cycle_done) begin
case(db_dst)
DB_ALU: aluIn <= DB;
DB_B: rB <= DB;
DB_C: rC <= DB;
DB_D: rD <= DB;
DB_E: rE <= DB;
DB_H: rH <= DB;
DB_L: rL <= DB;
DB_A: rA <= DB;
endcase
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
state <= CPU_FETCH;
end else begin
if(cycle_done) begin
case(state)
CPU_FETCH:
if(debug_req)
state <= CPU_DEBUG0;
else
state <= CPU_DECODE;
CPU_DECODE:
state <= decode_goto;
CPU_HALT:
if(debug_req)
state <= CPU_DEBUG0;
else if(int_latch)
state <= CPU_FETCH;
CPU_MVI0:
state <= memory_operand ? CPU_MVI1 : CPU_FETCH;
CPU_MVI1:
state <= CPU_FETCH;
CPU_MOV:
state <= CPU_FETCH;
CPU_ALU0:
state <= CPU_ALU1;
CPU_ALU1:
state <= CPU_FETCH;
CPU_JMP0:
state <= CPU_JMP1;
CPU_JMP1:
state <= CPU_FETCH;
CPU_PUSH0:
state <= CPU_PUSH1;
CPU_PUSH1:
state <= CPU_PUSH2;
CPU_PUSH2:
state <= CPU_FETCH;
CPU_POP0:
state <= CPU_POP1;
CPU_POP1:
state <= CPU_FETCH;
CPU_LXI0:
state <= CPU_LXI1;
CPU_LXI1:
state <= CPU_FETCH;
CPU_DIRECT0:
state <= CPU_DIRECT1;
CPU_DIRECT1:
state <= CPU_DIRECT2;
CPU_DIRECT2:
if(iLHLD || iSHLD)
state <= CPU_DIRECT3;
else
state <= CPU_FETCH;
CPU_DIRECT3:
state <= CPU_FETCH;
CPU_UNARY:
state <= CPU_FETCH;
CPU_CALL0:
state <= CPU_CALL1;
CPU_CALL1:
if(!iCALLcc || condition)
state <= CPU_CALL2;
else
state <= CPU_FETCH;
CPU_CALL2:
state <= CPU_CALL3;
CPU_CALL3:
state <= CPU_FETCH;
CPU_RET0:
state <= CPU_RET1;
CPU_RET1:
state <= CPU_FETCH;
CPU_PCHL0:
state <= CPU_PCHL1;
CPU_PCHL1:
state <= CPU_PCHL2;
CPU_PCHL2:
state <= CPU_FETCH;
CPU_SPHL0:
state <= CPU_SPHL1;
CPU_SPHL1:
state <= CPU_FETCH;
CPU_INRDCR0:
state <= CPU_INRDCR1;
CPU_INRDCR1:
state <= CPU_FETCH;
CPU_INXDCX0:
state <= iINX_SP || iDCX_SP ? CPU_FETCH : CPU_INXDCX1;
CPU_INXDCX1:
state <= alu_carry_out ? CPU_INXDCX2 : CPU_FETCH;
CPU_INXDCX2:
state <= CPU_INXDCX3;
CPU_INXDCX3:
state <= CPU_FETCH;
CPU_LDAXSTAX0:
state <= CPU_LDAXSTAX1;
CPU_LDAXSTAX1:
state <= CPU_LDAXSTAX2;
CPU_LDAXSTAX2:
state <= CPU_FETCH;
CPU_DEBUG0:
state <= CPU_DEBUG1;
CPU_DEBUG1:
if(dbgEXIT)
state <= CPU_FETCH;
else
state <= CPU_DEBUG0;
CPU_XCHG0:
state <= CPU_XCHG1;
CPU_XCHG1:
state <= CPU_XCHG2;
CPU_XCHG2:
state <= CPU_XCHG3;
CPU_XCHG3:
state <= CPU_XCHG4;
CPU_XCHG4:
state <= CPU_XCHG5;
CPU_XCHG5:
state <= CPU_FETCH;
CPU_DAD0:
state <= CPU_DAD1;
CPU_DAD1:
state <= CPU_DAD2;
CPU_DAD2:
state <= CPU_DAD3;
CPU_DAD3:
state <= CPU_DAD4;
CPU_DAD4:
state <= CPU_DAD5;
CPU_DAD5:
state <= CPU_DAD6;
CPU_DAD6:
state <= CPU_DAD7;
CPU_DAD7:
state <= CPU_FETCH;
CPU_IO0:
state <= CPU_IO1;
CPU_IO1:
state <= CPU_FETCH;
CPU_EIDI:
state <= CPU_FETCH;
`ifndef SYNTHESIS
default:
assert(0);
`endif
endcase
end
end
end
always @(*) begin
memory_addr = 16'bx;
memory_wdata = 8'bx;
memory_read = 1'b0;
memory_write = 1'b0;
memory_io = 1'b0;
case(state)
CPU_FETCH, CPU_MVI0, CPU_JMP0, CPU_JMP1, CPU_LXI0, CPU_LXI1, CPU_DIRECT0, CPU_DIRECT1, CPU_IO0: begin
memory_addr = rPC;
memory_read = 1'b1;
end
CPU_CALL0, CPU_CALL1: begin
memory_addr = rPC;
memory_read = !iRST;
end
CPU_MVI1: begin
memory_addr = {rH, rL};
memory_wdata = DB;
memory_write = 1'b1;
end
CPU_MOV: begin
memory_addr = {rH, rL};
if(rIR[5:3] == 6) begin
memory_wdata = DB;
memory_write = 1'b1;
end else if(rIR[2:0] == 6)
memory_read = 1'b1;
end
CPU_ALU0: begin
if(iALUI) begin
memory_addr = rPC;
memory_read = 1'b1;
end else if(memory_operand) begin
memory_addr = {rH, rL};
memory_read = 1'b1;
end
end
CPU_PUSH1, CPU_PUSH2: begin
memory_addr = rSP;
memory_wdata = DB;
memory_write = 1'b1;
end
CPU_POP0, CPU_POP1, CPU_RET0, CPU_RET1: begin
memory_addr = rSP;
memory_read = 1'b1;
end
CPU_DIRECT2, CPU_DIRECT3: begin
memory_addr = AL;
memory_read = iLDA || iLHLD;
memory_write = iSTA || iSHLD;
memory_wdata = DB;
end
CPU_CALL2, CPU_CALL3: begin
memory_addr = rSP;
memory_wdata = DB;
memory_write = 1'b1;
end
CPU_INRDCR0, CPU_INRDCR1: begin
if(memory_operand) begin
memory_addr = {rH, rL};
memory_wdata = DB;
memory_read = state == CPU_INRDCR0;
memory_write = state == CPU_INRDCR1;
end
end
CPU_LDAXSTAX2: begin
memory_addr = AL;
memory_read = iLDAX;
memory_write = iSTAX;
memory_wdata = DB;
end
CPU_XCHG1, CPU_XCHG4: begin
if(iXTHL) begin
memory_read = 1'b1;
memory_addr = rSP;
end
end
CPU_XCHG2, CPU_XCHG5: begin
if(iXTHL) begin
memory_write = 1'b1;
memory_wdata = DB;
memory_addr = rSP;
end
end
CPU_IO1: begin
memory_addr = {8'b0, AL[7:0]};
memory_wdata = DB;
memory_read = iIN;
memory_write = iOUT;
memory_io = 1'b1;
end
CPU_DEBUG0: begin
memory_addr = 16'hCAFE;
memory_read = 1'b1;
memory_io = 1'b1;
end
CPU_DEBUG1: begin
memory_io = 1'b1;
if(dbgREAD) begin
memory_addr = 16'hCAFF;
memory_write = 1'b1;
memory_wdata = DB;
end
if(dbgWRITE) begin
memory_addr = 16'hCAFF;
memory_read = 1'b1;
end
end
endcase
end
always @(*) begin
db_src = 4'b0000;
db_dst = 4'b0000;
alu_op = ALU_NOP;
set_flags = 0;
case(state)
CPU_MOV: begin
db_src = {1'b1, rIR[2:0]};
db_dst = {1'b1, rIR[5:3]};
end
CPU_MVI0: begin
db_src = DB_MEM;
db_dst = memory_operand ? DB_ALU : {1'b1, rIR[5:3]};
end
CPU_MVI1: begin
db_src = DB_ALU;
end
CPU_ALU0: begin
db_src = iALUI ? DB_MEM : {1'b1, rIR[2:0]};
db_dst = DB_ALU;
end
CPU_ALU1: begin
db_src = DB_ALU;
if(rIR[5:3] != 3'b111)
db_dst = DB_A;
alu_op = rIR[5:3];
set_flags = 8'hff;
end
CPU_JMP0, CPU_RET0: begin
db_src = DB_MEM;
db_dst = DB_ALU;
end
CPU_PUSH1, CPU_PUSH2: begin
if(rIR[5:4] == 3)
db_src = state == CPU_PUSH1 ? DB_A : DB_PSR;
else
db_src = {1'b1, rIR[5:4], state == CPU_PUSH2};
end
CPU_POP0, CPU_POP1: begin
db_src = DB_MEM;
if(rIR[5:4] == 3)
db_dst = state == CPU_POP1 ? DB_A : DB_PSR;
else
db_dst = {1'b1, rIR[5:4], state == CPU_POP0};
end
CPU_LXI0, CPU_LXI1: begin
db_src = DB_MEM;
if(rIR[5:4] == 3)
db_dst = state == CPU_LXI1 ? DB_SPH : DB_SPL;
else
db_dst = {1'b1, rIR[5:4], state != CPU_LXI1};
end
CPU_DIRECT0, CPU_DIRECT1: begin
db_src = DB_MEM;
db_dst = state == CPU_DIRECT1 ? DB_ALH : DB_ALL;
end
CPU_DIRECT2: begin
case(1'b1)
iSTA:
db_src = DB_A;
iLDA: begin
db_src = DB_MEM;
db_dst = DB_A;
end
iSHLD:
db_src = DB_L;
iLHLD: begin
db_src = DB_MEM;
db_dst = DB_L;
end
endcase
end
CPU_DIRECT3: begin
if(iSHLD)
db_src = DB_H;
else begin
db_src = DB_MEM;
db_dst = DB_H;
end
end
CPU_UNARY: begin
db_src = DB_ALU;
db_dst = DB_A;
alu_op = {1'b1, rIR[5:3]};
case(rIR[5:3])
4: set_flags = 8'hff;
5: set_flags = 0;
default: set_flags = 1;
endcase
end
CPU_CALL0: begin
db_src = DB_MEM;
db_dst = DB_ALL;
end
CPU_CALL1: begin
db_src = DB_MEM;
db_dst = DB_ALH;
end
CPU_CALL2:
db_src = DB_PCH;
CPU_CALL3:
db_src = DB_PCL;
CPU_PCHL0: begin
db_src = DB_L;
db_dst = DB_ALL;
end
CPU_PCHL1: begin
db_src = DB_H;
db_dst = DB_ALH;
end
CPU_SPHL0: begin
db_src = DB_L;
db_dst = DB_SPL;
end
CPU_SPHL1: begin
db_src = DB_H;
db_dst = DB_SPH;
end
CPU_INRDCR0: begin
db_src = {1'b1, rIR[5:3]};
db_dst = DB_ALU;
end
CPU_INRDCR1: begin
db_src = DB_ALU;
db_dst = {1'b1, rIR[5:3]};
alu_op = iDCR ? ALU_DEC : ALU_INC;
set_flags = 8'hfe;
end
CPU_INXDCX0, CPU_INXDCX2: begin
db_src = {1'b1, rIR[5:4], state == CPU_INXDCX0};
db_dst = DB_ALU;
end
CPU_INXDCX1, CPU_INXDCX3: begin
db_src = DB_ALU;
db_dst = {1'b1, rIR[5:4], state == CPU_INXDCX1};
alu_op = iDCX ? ALU_DEC : ALU_INC;
end
CPU_LDAXSTAX0, CPU_LDAXSTAX1: begin
db_src = {1'b1, 1'b0, rIR[4], state == CPU_LDAXSTAX0};
db_dst = state == CPU_LDAXSTAX1 ? DB_ALH : DB_ALL;
end
CPU_LDAXSTAX2: begin
if(iLDAX) begin
db_src = DB_MEM;
db_dst = DB_A;
end else
db_src = DB_A;
end
CPU_DEBUG1: begin
if(dbgREAD) begin
db_src = rIR[4:0];
end
if(dbgWRITE) begin
db_src = DB_MEM;
db_dst = rIR[4:0];
end
end
CPU_XCHG0: begin
db_src = DB_L;
db_dst = DB_ALL;
end
CPU_XCHG1: begin
db_src = iXTHL ? DB_MEM : DB_E;
db_dst = DB_L;
end
CPU_XCHG2: begin
db_src = DB_ALL;
if(iXCHG)
db_dst = DB_E;
end
CPU_XCHG3: begin
db_src = DB_H;
db_dst = DB_ALL;
end
CPU_XCHG4: begin
db_src = iXTHL ? DB_MEM : DB_D;
db_dst = DB_H;
end
CPU_XCHG5: begin
db_src = DB_ALL;
if(iXCHG)
db_dst = DB_D;
end
CPU_DAD0: begin
db_src = DB_A;
db_dst = DB_ALL;
end
CPU_DAD1: begin
db_src = DB_L;
db_dst = DB_A;
end
CPU_DAD2: begin
db_src = rIR[5:4] == 3 ? DB_SPL : {1'b1, rIR[5:4], 1'b1};
db_dst = DB_ALU;
end
CPU_DAD3: begin
alu_op = ALU_ADD;
db_src = DB_ALU;
db_dst = DB_L;
set_flags = 8'h01;
end
CPU_DAD4: begin
db_src = DB_H;
db_dst = DB_A;
end
CPU_DAD5: begin
db_src = rIR[5:4] == 3 ? DB_SPH : {1'b1, rIR[5:4], 1'b0};
db_dst = DB_ALU;
end
CPU_DAD6: begin
alu_op = ALU_ADC;
db_src = DB_ALU;
db_dst = DB_H;
set_flags = 8'h01;
end
CPU_DAD7: begin
db_src = DB_ALL;
db_dst = DB_A;
end
CPU_IO0: begin
db_src = DB_MEM;
db_dst = DB_ALL;
end
CPU_IO1: begin
if(iIN) begin
db_src = DB_MEM;
db_dst = DB_A;
end
if(iOUT)
db_src = DB_A;
end
endcase
end
`ifdef FORMAL
initial state = CPU_FETCH;
default clocking
@(posedge clk);
endclocking
default disable iff(!rst_n);
assume property (memory_done |=> !memory_done);
assume property (debug_req && !cpu_in_debug |=> debug_req);
read_until_done: assert property (memory_read && !memory_done |=> memory_read);
write_until_done: assert property (memory_write && !memory_done |=> memory_write);
not_read_and_write: assert property (!memory_read || !memory_write);
stable_memory_addr: assert property (!$initstate && (memory_read && $past(memory_read) || memory_write && $past(memory_write)) && !$past(memory_done) |-> $stable(memory_addr) && $stable(memory_io));
stable_memory_wdata: assert property (!$initstate && memory_write && $past(memory_write) && !$past(memory_done) && state != CPU_DEBUG1 |-> $stable(memory_wdata));
assert property (state == CPU_ALU0 || state == CPU_ALU1 |-> iALU || iALUI);
assert property (state == CPU_HALT |-> iHALT);
assert property (state == CPU_POP0 || state == CPU_POP1 |-> iPOP);
assert property (state == CPU_PUSH0 || state == CPU_PUSH1 || state == CPU_PUSH2 |-> iPUSH);
assert property (state == CPU_PCHL0 || state == CPU_PCHL1 || state == CPU_PCHL2 |-> iPCHL);
assert property (state == CPU_RET0 || state == CPU_RET1 |-> iRET || iRETcc);
assert property (state == CPU_UNARY |-> iUNARY);
assert property (state == CPU_INRDCR0 || state == CPU_INRDCR1 |-> iINR || iDCR);
assert property (state == CPU_DAD0 || state == CPU_DAD1 || state == CPU_DAD2 || state == CPU_DAD3 || state == CPU_DAD4 || state == CPU_DAD5 || state == CPU_DAD6 || state == CPU_DAD7 |-> iDAD);
assert property (state == CPU_JMP0 || state == CPU_JMP1 |-> iJMP || iJMPcc);
assert property (state == CPU_INXDCX0 || state == CPU_INXDCX1 || state == CPU_INXDCX2 || state == CPU_INXDCX3 |-> iINX || iDCX);
assert property (state == CPU_MOV |-> iMOV);
assert property (state == CPU_DIRECT0 || state == CPU_DIRECT1 || state == CPU_DIRECT2 |-> iLDA || iSTA || iLHLD || iSHLD);
assert property (state == CPU_DIRECT3 |-> iLHLD || iSHLD);
assert property (state == CPU_MVI0 || state == CPU_MVI1 |-> iMVI);
assert property (state == CPU_LXI0 || state == CPU_LXI1 |-> iLXI);
assert property (state == CPU_LDAXSTAX0 || state == CPU_LDAXSTAX1 || state == CPU_LDAXSTAX2 |-> iLDAX || iSTAX);
assert property (state == CPU_SPHL0 || state == CPU_SPHL1 |-> iSPHL);
assert property (state == CPU_IO0 || state == CPU_IO1 |-> iIN || iOUT);
assert property (state == CPU_CALL0 || state == CPU_CALL1 || state == CPU_CALL2 || state == CPU_CALL3 |-> iCALL || iCALLcc || iRST);
assert property (state == CPU_XCHG0 || state == CPU_XCHG1 || state == CPU_XCHG2 || state == CPU_XCHG3 || state == CPU_XCHG4 || state == CPU_XCHG5 |-> iXCHG || iXTHL);
assert property (state == CPU_EIDI |-> iEI || iDI);
exactly_one_decode: assert property ($onehot({
iMOV, iALU, iALUI, iMVI, iJMP, iPUSH, iPOP, iHALT, iLXI, iLDA, iSTA, iLHLD, iSHLD,
iUNARY, iCALL, iCALLcc, iRST, iRET, iRETcc, iJMPcc, iPCHL, iSPHL, iINR, iDCR,
iINX, iDCX, iLDAX, iSTAX, iXCHG, iXTHL, iDAD, iIN, iOUT, iNOP, iEI, iDI,
undefined}));
inx_sp_dcx_sp: assert property ((!iINX_SP || iINX) && (!iDCX_SP || iDCX));
no_missing_cases: assert property (!missing_decoder_case);
`ifdef LIVENESS
assume property (memory_read |-> ##[1:3] memory_done);
assume property (memory_write |-> ##[1:3] memory_done);
assert property (state != CPU_FETCH |-> ##[1:40] state == CPU_FETCH || state == CPU_HALT || state == CPU_DEBUG0 || state == CPU_DEBUG1);
assert property (debug_req && !cpu_in_debug |-> ##[1:40] cpu_in_debug);
`endif
`endif
endmodule
|
module bus_if(
input wire clk,
input wire rst_n,
input wire bus_handshake_ack,
output reg bus_handshake_req,
output reg [1:0] bus_state,
input wire [7:0] bus_data_in,
output reg [7:0] bus_data_out,
output reg bus_output_enable,
output wire bus_io,
input wire memory_read,
input wire memory_write,
input wire [15:0] memory_addr,
input wire memory_io,
input wire [7:0] memory_wdata,
output reg [7:0] memory_rdata,
output reg memory_done
);
reg [1:0] memory_state;
localparam MEMORY_IDLE = 0;
localparam MEMORY_ADDR_LOW = 1;
localparam MEMORY_ADDR_HIGH = 2;
localparam MEMORY_DATA = 3;
wire want_output_enable = memory_state != MEMORY_IDLE && (memory_state != MEMORY_DATA || memory_write);
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
memory_state <= MEMORY_IDLE;
memory_rdata <= 8'bx;
bus_handshake_req <= 1'b0;
memory_done <= 1'b0;
bus_output_enable <= 1'b0;
end else begin
memory_done <= 1'b0;
if(memory_state == MEMORY_IDLE && !memory_done && (memory_read || memory_write))
memory_state <= MEMORY_ADDR_LOW;
if(memory_state != MEMORY_IDLE && !bus_handshake_ack)
bus_output_enable <= want_output_enable;
if(memory_state != MEMORY_IDLE && !bus_handshake_ack && want_output_enable == bus_output_enable)
bus_handshake_req <= 1'b1;
if(bus_handshake_req && bus_handshake_ack) begin
bus_handshake_req <= 1'b0;
case(memory_state)
MEMORY_ADDR_LOW:
memory_state <= MEMORY_ADDR_HIGH;
MEMORY_ADDR_HIGH: begin
memory_state <= MEMORY_DATA;
if(memory_read)
bus_output_enable <= 1'b0;
end
MEMORY_DATA: begin
memory_state <= MEMORY_IDLE;
bus_output_enable <= 1'b0;
memory_done <= 1'b1;
if(memory_read)
memory_rdata <= bus_data_in;
end
endcase
end
end
end
assign bus_io = memory_io;
always @(*) begin
bus_data_out = 8'bx;
bus_state = 2'b00;
case(memory_state)
MEMORY_ADDR_LOW: begin
bus_data_out = memory_addr[7:0];
bus_state = 2'b00;
end
MEMORY_ADDR_HIGH: begin
bus_data_out = memory_addr[15:8];
bus_state = 2'b01;
end
MEMORY_DATA: begin
bus_state = {1'b1, memory_write};
if(memory_write) begin
bus_data_out = memory_wdata;
end
end
endcase
end
`ifdef FORMAL
initial begin
memory_state = MEMORY_IDLE;
memory_done = 1'b0;
bus_handshake_req = 1'b0;
bus_output_enable = 1'b0;
end
default clocking
@(posedge clk);
endclocking
default disable iff(!rst_n);
assume property (!(memory_read && memory_write));
assume property (memory_read && !memory_done |=> memory_read);
assume property (memory_write && !memory_done |=> memory_write);
assume property ($rose(bus_handshake_ack) |-> $past(bus_handshake_req));
assume property ($fell(bus_handshake_ack) |-> $past(!bus_handshake_req));
assume property ((memory_read && $past(memory_read)) || (memory_write && $past(memory_write)) |-> $stable(memory_addr) && $stable(memory_wdata));
state_invariant: assert property (memory_state != MEMORY_IDLE |-> (memory_read || memory_write) && !memory_done);
done_one_cycle: assert property (memory_done |=> !memory_done);
done_only_if_active: assert property (memory_done |-> memory_read || memory_write);
req_only_when_active: assert property (memory_state == MEMORY_IDLE |-> !bus_handshake_req);
req_when_no_ack: assert property ($rose(bus_handshake_req) |-> !bus_handshake_ack);
req_falls_when_ack: assert property (!$initstate && $fell(bus_handshake_req) |-> bus_handshake_ack);
stable_bus_state: assert property (bus_handshake_req |-> $stable(bus_state));
no_bus_contention: assert property (bus_handshake_req && bus_state == 2'b10 |-> !bus_output_enable && !$past(bus_output_enable));
stable_bus_data_out: assert property (bus_handshake_req && bus_state != 2'b10 |-> bus_output_enable && $past(bus_output_enable) && $stable(bus_data_out));
latch_bus_data: assert property (memory_done && memory_read |-> memory_rdata == $past(bus_data_in));
stable_bus_output: assert property ((bus_handshake_req || bus_handshake_ack) && !bus_output_enable |=> !bus_output_enable);
stable_bus_output2: assert property (bus_handshake_req && !bus_output_enable |-> !$past(bus_output_enable));
`ifdef LIVENESS
assume property(bus_handshake_req |-> ##[1:5] bus_handshake_ack);
assume property(!bus_handshake_req |-> ##[1:5] !bus_handshake_ack);
liveness: assert property ((memory_read || memory_write) && !memory_done |-> ##[1:40] memory_done);
`endif
`endif
endmodule
|
tt06-finale_0047
|
tt06-finale
|
aiju-tt06-aiju-8080
|
task_cpu
|
tt_um_aiju_8080
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_aiju_8080 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] bus_data_out; // From bus_if_i of bus_if.v
wire bus_handshake_req; // From bus_if_i of bus_if.v
wire bus_io; // From bus_if_i of bus_if.v
wire bus_output_enable; // From bus_if_i of bus_if.v
wire [1:0] bus_state; // From bus_if_i of bus_if.v
wire cpu_fetch; // From cpu_i of cpu.v
wire cpu_halted; // From cpu_i of cpu.v
wire cpu_in_debug; // From cpu_i of cpu.v
wire cpu_int_ack; // From cpu_i of cpu.v
wire [15:0] memory_addr; // From cpu_i of cpu.v
wire memory_done; // From bus_if_i of bus_if.v
wire memory_io; // From cpu_i of cpu.v
wire [7:0] memory_rdata; // From bus_if_i of bus_if.v
wire memory_read; // From cpu_i of cpu.v
wire [7:0] memory_wdata; // From cpu_i of cpu.v
wire memory_write; // From cpu_i of cpu.v
// End of automatics
assign uo_out[0] = bus_handshake_req;
assign uo_out[1] = bus_state[0];
assign uo_out[2] = bus_state[1];
assign uo_out[3] = bus_io;
assign uo_out[4] = cpu_fetch;
assign uo_out[5] = cpu_in_debug;
assign uo_out[6] = cpu_halted;
assign uo_out[7] = cpu_int_ack;
wire ext_bus_handshake_ack = ui_in[0];
wire ext_debug_req = ui_in[1];
wire ext_int_req = ui_in[2];
wire bus_handshake_ack;
(*keep_hierarchy*) sync bus_handshake_ack_sync(
.clk(clk),
.rst_n(rst_n),
.in(ext_bus_handshake_ack),
.out(bus_handshake_ack)
);
wire debug_req;
(*keep_hierarchy*) sync debug_req_sync(
.clk(clk),
.rst_n(rst_n),
.in(ext_debug_req),
.out(debug_req)
);
wire int_req;
(*keep_hierarchy*) sync int_req_sync(
.clk(clk),
.rst_n(rst_n),
.in(ext_int_req),
.out(int_req)
);
wire [7:0] bus_data_in = uio_in;
assign uio_out = bus_data_out;
assign uio_oe = {8{bus_output_enable}};
bus_if bus_if_i(/*AUTOINST*/
// Outputs
.bus_handshake_req(bus_handshake_req),
.bus_state (bus_state[1:0]),
.bus_data_out (bus_data_out[7:0]),
.bus_output_enable(bus_output_enable),
.bus_io (bus_io),
.memory_rdata (memory_rdata[7:0]),
.memory_done (memory_done),
// Inputs
.clk (clk),
.rst_n (rst_n),
.bus_handshake_ack(bus_handshake_ack),
.bus_data_in (bus_data_in[7:0]),
.memory_read (memory_read),
.memory_write (memory_write),
.memory_addr (memory_addr[15:0]),
.memory_io (memory_io),
.memory_wdata (memory_wdata[7:0]));
cpu cpu_i(/*AUTOINST*/
// Outputs
.memory_read (memory_read),
.memory_write (memory_write),
.memory_addr (memory_addr[15:0]),
.memory_io (memory_io),
.memory_wdata (memory_wdata[7:0]),
.cpu_fetch (cpu_fetch),
.cpu_halted (cpu_halted),
.cpu_in_debug (cpu_in_debug),
.cpu_int_ack (cpu_int_ack),
// Inputs
.clk (clk),
.rst_n (rst_n),
.memory_rdata (memory_rdata[7:0]),
.memory_done (memory_done),
.debug_req (debug_req),
.int_req (int_req));
endmodule
module sync(
input wire clk,
input wire rst_n,
input wire in,
output wire out
);
(* keep *) reg a;
(* keep *) reg b;
assign out = b;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
a <= 1'b0;
b <= 1'b0;
end else begin
a <= in;
b <= a;
end
end
endmodule
`default_nettype none
module bus_if(
input wire clk,
input wire rst_n,
input wire bus_handshake_ack,
output reg bus_handshake_req,
output reg [1:0] bus_state,
input wire [7:0] bus_data_in,
output reg [7:0] bus_data_out,
output reg bus_output_enable,
output wire bus_io,
input wire memory_read,
input wire memory_write,
input wire [15:0] memory_addr,
input wire memory_io,
input wire [7:0] memory_wdata,
output reg [7:0] memory_rdata,
output reg memory_done
);
reg [1:0] memory_state;
localparam MEMORY_IDLE = 0;
localparam MEMORY_ADDR_LOW = 1;
localparam MEMORY_ADDR_HIGH = 2;
localparam MEMORY_DATA = 3;
wire want_output_enable = memory_state != MEMORY_IDLE && (memory_state != MEMORY_DATA || memory_write);
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
memory_state <= MEMORY_IDLE;
memory_rdata <= 8'bx;
bus_handshake_req <= 1'b0;
memory_done <= 1'b0;
bus_output_enable <= 1'b0;
end else begin
memory_done <= 1'b0;
if(memory_state == MEMORY_IDLE && !memory_done && (memory_read || memory_write))
memory_state <= MEMORY_ADDR_LOW;
if(memory_state != MEMORY_IDLE && !bus_handshake_ack)
bus_output_enable <= want_output_enable;
if(memory_state != MEMORY_IDLE && !bus_handshake_ack && want_output_enable == bus_output_enable)
bus_handshake_req <= 1'b1;
if(bus_handshake_req && bus_handshake_ack) begin
bus_handshake_req <= 1'b0;
case(memory_state)
MEMORY_ADDR_LOW:
memory_state <= MEMORY_ADDR_HIGH;
MEMORY_ADDR_HIGH: begin
memory_state <= MEMORY_DATA;
if(memory_read)
bus_output_enable <= 1'b0;
end
MEMORY_DATA: begin
memory_state <= MEMORY_IDLE;
bus_output_enable <= 1'b0;
memory_done <= 1'b1;
if(memory_read)
memory_rdata <= bus_data_in;
end
endcase
end
end
end
assign bus_io = memory_io;
always @(*) begin
bus_data_out = 8'bx;
bus_state = 2'b00;
case(memory_state)
MEMORY_ADDR_LOW: begin
bus_data_out = memory_addr[7:0];
bus_state = 2'b00;
end
MEMORY_ADDR_HIGH: begin
bus_data_out = memory_addr[15:8];
bus_state = 2'b01;
end
MEMORY_DATA: begin
bus_state = {1'b1, memory_write};
if(memory_write) begin
bus_data_out = memory_wdata;
end
end
endcase
end
`ifdef FORMAL
initial begin
memory_state = MEMORY_IDLE;
memory_done = 1'b0;
bus_handshake_req = 1'b0;
bus_output_enable = 1'b0;
end
default clocking
@(posedge clk);
endclocking
default disable iff(!rst_n);
assume property (!(memory_read && memory_write));
assume property (memory_read && !memory_done |=> memory_read);
assume property (memory_write && !memory_done |=> memory_write);
assume property ($rose(bus_handshake_ack) |-> $past(bus_handshake_req));
assume property ($fell(bus_handshake_ack) |-> $past(!bus_handshake_req));
assume property ((memory_read && $past(memory_read)) || (memory_write && $past(memory_write)) |-> $stable(memory_addr) && $stable(memory_wdata));
state_invariant: assert property (memory_state != MEMORY_IDLE |-> (memory_read || memory_write) && !memory_done);
done_one_cycle: assert property (memory_done |=> !memory_done);
done_only_if_active: assert property (memory_done |-> memory_read || memory_write);
req_only_when_active: assert property (memory_state == MEMORY_IDLE |-> !bus_handshake_req);
req_when_no_ack: assert property ($rose(bus_handshake_req) |-> !bus_handshake_ack);
req_falls_when_ack: assert property (!$initstate && $fell(bus_handshake_req) |-> bus_handshake_ack);
stable_bus_state: assert property (bus_handshake_req |-> $stable(bus_state));
no_bus_contention: assert property (bus_handshake_req && bus_state == 2'b10 |-> !bus_output_enable && !$past(bus_output_enable));
stable_bus_data_out: assert property (bus_handshake_req && bus_state != 2'b10 |-> bus_output_enable && $past(bus_output_enable) && $stable(bus_data_out));
latch_bus_data: assert property (memory_done && memory_read |-> memory_rdata == $past(bus_data_in));
stable_bus_output: assert property ((bus_handshake_req || bus_handshake_ack) && !bus_output_enable |=> !bus_output_enable);
stable_bus_output2: assert property (bus_handshake_req && !bus_output_enable |-> !$past(bus_output_enable));
`ifdef LIVENESS
assume property(bus_handshake_req |-> ##[1:5] bus_handshake_ack);
assume property(!bus_handshake_req |-> ##[1:5] !bus_handshake_ack);
liveness: assert property ((memory_read || memory_write) && !memory_done |-> ##[1:40] memory_done);
`endif
`endif
endmodule
`default_nettype none
module cpu(
input wire clk,
input wire rst_n,
output reg memory_read,
output reg memory_write,
output reg [15:0] memory_addr,
output reg memory_io,
output reg [7:0] memory_wdata,
input wire [7:0] memory_rdata,
input wire memory_done,
input wire debug_req,
input wire int_req,
output wire cpu_fetch,
output wire cpu_halted,
output wire cpu_in_debug,
output wire cpu_int_ack
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
|
module cpu(
input wire clk,
input wire rst_n,
output reg memory_read,
output reg memory_write,
output reg [15:0] memory_addr,
output reg memory_io,
output reg [7:0] memory_wdata,
input wire [7:0] memory_rdata,
input wire memory_done,
input wire debug_req,
input wire int_req,
output wire cpu_fetch,
output wire cpu_halted,
output wire cpu_in_debug,
output wire cpu_int_ack
);
reg [15:0] AL;
reg [15:0] rPC;
reg [15:0] rSP;
reg [7:0] rA, rB, rC, rD, rE, rH, rL;
reg [7:0] rPSR;
reg [7:0] rIR;
reg [5:0] state;
localparam CPU_FETCH = 0;
localparam CPU_DECODE = 1;
localparam CPU_MVI0 = 2;
localparam CPU_MVI1 = 3;
localparam CPU_ALU0 = 4;
localparam CPU_ALU1 = 5;
localparam CPU_MOV = 6;
localparam CPU_JMP0 = 7;
localparam CPU_JMP1 = 8;
localparam CPU_PUSH0 = 9;
localparam CPU_PUSH1 = 10;
localparam CPU_PUSH2 = 11;
localparam CPU_POP0 = 12;
localparam CPU_POP1 = 13;
localparam CPU_HALT = 14;
localparam CPU_LXI0 = 15;
localparam CPU_LXI1 = 16;
localparam CPU_DIRECT0 = 17;
localparam CPU_DIRECT1 = 18;
localparam CPU_DIRECT2 = 19;
localparam CPU_DIRECT3 = 20;
localparam CPU_UNARY = 21;
localparam CPU_CALL0 = 22;
localparam CPU_CALL1 = 23;
localparam CPU_CALL2 = 24;
localparam CPU_CALL3 = 25;
localparam CPU_RET0 = 26;
localparam CPU_RET1 = 27;
localparam CPU_PCHL0 = 28;
localparam CPU_PCHL1 = 29;
localparam CPU_PCHL2 = 30;
localparam CPU_SPHL0 = 31;
localparam CPU_SPHL1 = 32;
localparam CPU_INRDCR0 = 33;
localparam CPU_INRDCR1 = 34;
localparam CPU_INXDCX0 = 35;
localparam CPU_INXDCX1 = 36;
localparam CPU_INXDCX2 = 37;
localparam CPU_INXDCX3 = 38;
localparam CPU_LDAXSTAX0 = 39;
localparam CPU_LDAXSTAX1 = 40;
localparam CPU_LDAXSTAX2 = 41;
localparam CPU_XCHG0 = 42;
localparam CPU_XCHG1 = 43;
localparam CPU_XCHG2 = 44;
localparam CPU_XCHG3 = 45;
localparam CPU_XCHG4 = 46;
localparam CPU_XCHG5 = 47;
localparam CPU_DAD0 = 48;
localparam CPU_DAD1 = 49;
localparam CPU_DAD2 = 50;
localparam CPU_DAD3 = 51;
localparam CPU_DAD4 = 52;
localparam CPU_DAD5 = 53;
localparam CPU_DAD6 = 54;
localparam CPU_DAD7 = 55;
localparam CPU_IO0 = 56;
localparam CPU_IO1 = 57;
localparam CPU_EIDI = 58;
localparam CPU_DEBUG0 = 62;
localparam CPU_DEBUG1 = 63;
wire iMOV = rIR[7:6] == 1 && rIR != 8'b01110110;
wire iALU = rIR[7:6] == 2;
wire iALUI = (rIR & ~8'h38) == 8'b1100_0110;
wire iMVI = rIR[7:6] == 0 && rIR[2:0] == 3'b110;
wire iJMP = rIR == 8'b1100_0011;
wire iPUSH = (rIR & ~8'h30) == 8'b1100_0101;
wire iPOP = (rIR & ~8'h30) == 8'b1100_0001;
wire iHALT = rIR == 8'h76;
wire iLXI = (rIR & ~8'h30) == 8'b0000_0001;
wire iLDA = rIR == 8'h3A;
wire iSTA = rIR == 8'h32;
wire iLHLD = rIR == 8'h2A;
wire iSHLD = rIR == 8'h22;
wire iUNARY = (rIR & ~8'h38) == 8'b0000_0111;
wire iCALL = rIR == 8'hCD;
wire iCALLcc = (rIR & ~8'h38) == 8'b1100_0100;
wire iRST = (rIR & ~8'h38) == 8'b1100_0111;
wire iRET = rIR == 8'hC9;
wire iRETcc = (rIR & ~8'h38) == 8'b1100_0000;
wire iJMPcc = (rIR & ~8'h38) == 8'b1100_0010;
wire iPCHL = rIR == 8'hE9;
wire iSPHL = rIR == 8'hF9;
wire iINR = (rIR & ~8'h38) == 8'b0000_0100;
wire iDCR = (rIR & ~8'h38) == 8'b0000_0101;
wire iINX = (rIR & ~8'h30) == 8'b0000_0011;
wire iDCX = (rIR & ~8'h30) == 8'b0000_1011;
wire iINX_SP = rIR == 8'b0011_0011;
wire iDCX_SP = rIR == 8'b0011_1011;
wire iLDAX = (rIR & ~8'h10) == 8'b0000_1010;
wire iSTAX = (rIR & ~8'h10) == 8'b0000_0010;
wire iXCHG = rIR == 8'b1110_1011;
wire iXTHL = rIR == 8'b1110_0011;
wire iDAD = (rIR & ~8'h30) == 8'b0000_1001;
wire iIN = rIR == 8'b1101_1011;
wire iOUT = rIR == 8'b1101_0011;
wire iNOP = rIR == 8'b0000_0000;
wire iEI = rIR == 8'b1111_1011;
wire iDI = rIR == 8'b1111_0011;
wire undefined =
(rIR & ~8'h38) == 8'b0000_0000 && !iNOP
|| rIR == 8'b1101_1001
|| (rIR & ~8'h30) == 8'b1100_1101 && !iCALL
|| rIR == 8'b1100_1011;
wire memory_operand =
iMOV && (rIR[5:3] == 3'b110 || rIR[2:0] == 3'b110)
|| iALU && rIR[2:0] == 3'b110
|| (iINR || iDCR || iMVI) && rIR[5:3] == 3'b110;
wire dbgEXIT = rIR[6];
wire dbgREAD = !rIR[7] && !dbgEXIT;
wire dbgWRITE = rIR[7];
reg condition;
always @(*) begin
case(rIR[5:3])
3'b000: condition = !rPSR[6];
3'b001: condition = rPSR[6];
3'b010: condition = !rPSR[0];
3'b011: condition = rPSR[0];
3'b100: condition = !rPSR[2];
3'b101: condition = rPSR[2];
3'b110: condition = !rPSR[7];
3'b111: condition = rPSR[7];
endcase
end
reg int_enabled;
reg int_latch;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
int_enabled <= 1'b0;
int_latch <= 1'b0;
end else begin
if(state == CPU_EIDI) begin
if(iEI)
int_enabled <= 1'b1;
if(iDI)
int_enabled <= 1'b0;
end
if(cpu_int_ack)
int_enabled <= 1'b0;
if(cycle_done)
int_latch <= int_req && int_enabled && !(state == CPU_EIDI && iDI || cpu_int_ack);
end
end
assign cpu_int_ack = state == CPU_FETCH && int_latch;
reg [5:0] decode_goto;
reg missing_decoder_case;
always @(*) begin
decode_goto = CPU_FETCH;
missing_decoder_case = 1'b0;
case(1'b1)
iMOV: decode_goto = CPU_MOV;
iALU, iALUI: decode_goto = CPU_ALU0;
iMVI: decode_goto = CPU_MVI0;
iJMP, iJMPcc: decode_goto = CPU_JMP0;
iPUSH: decode_goto = CPU_PUSH0;
iPOP: decode_goto = CPU_POP0;
iHALT: decode_goto = CPU_HALT;
iLXI: decode_goto = CPU_LXI0;
iLDA, iSTA, iLHLD, iSHLD: decode_goto = CPU_DIRECT0;
iUNARY: decode_goto = CPU_UNARY;
iCALL, iCALLcc, iRST: decode_goto = CPU_CALL0;
iRET: decode_goto = CPU_RET0;
iRETcc: decode_goto = condition ? CPU_RET0 : CPU_FETCH;
iPCHL: decode_goto = CPU_PCHL0;
iSPHL: decode_goto = CPU_SPHL0;
iINR, iDCR: decode_goto = CPU_INRDCR0;
iINX, iDCX: decode_goto = CPU_INXDCX0;
iLDAX, iSTAX: decode_goto = CPU_LDAXSTAX0;
iXCHG, iXTHL: decode_goto = CPU_XCHG0;
iDAD: decode_goto = CPU_DAD0;
iIN, iOUT: decode_goto = CPU_IO0;
iNOP, undefined: decode_goto = CPU_FETCH;
iEI, iDI: decode_goto = CPU_EIDI;
default: missing_decoder_case = 1'b1;
endcase
end
always @(posedge clk) begin
if(state == CPU_DECODE && undefined)
$display("undefined opcode %x", rIR);
end
reg [7:0] aluIn;
reg [7:0] aluOut;
reg alu_carry_out, alu_aux_carry_out;
reg [4:0] alu_op;
reg [7:0] set_flags;
localparam ALU_ADD = 0;
localparam ALU_ADC = 1;
localparam ALU_SUB = 2;
localparam ALU_SBB = 3;
localparam ALU_AND = 4;
localparam ALU_XOR = 5;
localparam ALU_OR = 6;
localparam ALU_CMP = 7;
localparam ALU_RLC = 8;
localparam ALU_RRC = 9;
localparam ALU_RAL = 10;
localparam ALU_RAR = 11;
localparam ALU_DAA = 12;
localparam ALU_CMA = 13;
localparam ALU_STC = 14;
localparam ALU_CMC = 15;
localparam ALU_INC = 16;
localparam ALU_DEC = 17;
localparam ALU_NOP = 31;
reg [7:0] daa_operand;
always @(*) begin
daa_operand = 8'h00;
if(rA[3:0] > 9 || rPSR[4])
daa_operand[3:0] = 6;
if(rA >= 8'h9a || rPSR[0])
daa_operand[7:4] = 6;
end
always @(*) begin
alu_carry_out = 1'b0;
alu_aux_carry_out = 1'b0;
aluOut = aluIn;
case(alu_op)
ALU_ADD, ALU_ADC: begin
{alu_carry_out, aluOut} = rA + aluIn + (rPSR[0] & (alu_op == ALU_ADC));
alu_aux_carry_out = (((rA & 15) + (aluIn & 15) + (rPSR[0] & (alu_op == ALU_ADC))) & 16) != 0;
end
ALU_SUB, ALU_SBB, ALU_CMP: begin
{alu_carry_out, aluOut} = rA - aluIn - (rPSR[0] & (alu_op == ALU_SBB));
alu_aux_carry_out = (((rA & 15) - (aluIn & 15) - (rPSR[0] & (alu_op == ALU_SBB))) & 16) == 0;
end
ALU_AND: begin
aluOut = rA & aluIn;
alu_aux_carry_out = rA[3] | aluIn[3];
end
ALU_OR:
aluOut = rA | aluIn;
ALU_XOR:
aluOut = rA ^ aluIn;
ALU_RLC: begin
aluOut = {rA[6:0], rA[7]};
alu_carry_out = rA[7];
end
ALU_RRC: begin
aluOut = {rA[0], rA[7:1]};
alu_carry_out = rA[0];
end
ALU_RAL: begin
{alu_carry_out, aluOut} = {rA, rPSR[0]};
end
ALU_RAR: begin
{aluOut, alu_carry_out} = {rPSR[0], rA};
end
ALU_CMA: aluOut = ~rA;
ALU_CMC: begin
aluOut = rA;
alu_carry_out = ~rPSR[0];
end
ALU_STC: begin
aluOut = rA;
alu_carry_out = 1'b1;
end
ALU_DAA: begin
{alu_carry_out, aluOut} = (rA + daa_operand) | (rPSR[0] ? 9'h100 : 9'h000);
alu_aux_carry_out = (((rA & 15) + (daa_operand & 15)) & 16) != 0;
end
ALU_INC: begin
{alu_carry_out, aluOut} = aluIn + 1;
alu_aux_carry_out = (aluIn & 15) == 15;
end
ALU_DEC: begin
{alu_carry_out, aluOut} = aluIn - 1;
alu_aux_carry_out = (aluIn & 15) != 0;
end
endcase
end
wire alu_zero = aluOut == 0;
wire alu_parity = ~^aluOut;
wire alu_sign = aluOut[7];
wire [7:0] alu_flags = {alu_sign, alu_zero, 1'b0, alu_aux_carry_out, 1'b0, alu_parity, 1'b1, alu_carry_out};
wire cycle_done = !memory_read && !memory_write || memory_done;
wire pc_increment =
state == CPU_FETCH && !debug_req && !cpu_int_ack
|| state == CPU_MVI0 || state == CPU_JMP0 || state == CPU_JMP1 && iJMPcc && !condition
|| state == CPU_ALU0 && iALUI
|| state == CPU_LXI0 || state == CPU_LXI1
|| state == CPU_DIRECT0 || state == CPU_DIRECT1
|| (state == CPU_CALL0 || state == CPU_CALL1) && !iRST
|| state == CPU_IO0;
wire al_increment = state == CPU_DIRECT2;
wire sp_decrement =
state == CPU_PUSH0 || state == CPU_PUSH1
|| state == CPU_CALL1 && (!iCALLcc || condition)
|| state == CPU_CALL2
|| state == CPU_INXDCX0 && iDCX_SP
|| state == CPU_XCHG5 && iXTHL;
wire sp_increment =
state == CPU_POP0 || state == CPU_POP1
|| state == CPU_RET0 || state == CPU_RET1
|| state == CPU_INXDCX0 && iINX_SP
|| state == CPU_XCHG2 && iXTHL;
wire pc_jmp =
state == CPU_JMP1 && (!iJMPcc || condition)
|| state == CPU_RET1;
wire pc_jmp_al = state == CPU_CALL3 && !iRST || state == CPU_PCHL2;
wire pc_rst_jmp = state == CPU_CALL3 && iRST;
wire ir_load = state == CPU_FETCH || state == CPU_DEBUG0;
assign cpu_fetch = state == CPU_FETCH;
assign cpu_halted = state == CPU_HALT;
assign cpu_in_debug = state == CPU_DEBUG0 || state == CPU_DEBUG1;
reg [4:0] db_dst;
reg [4:0] db_src;
localparam DB_ALL = 5'b00010;
localparam DB_ALH = 5'b00011;
localparam DB_SPL = 5'b00100;
localparam DB_SPH = 5'b00101;
localparam DB_PSR = 5'b00110;
localparam DB_ALU = 5'b00111;
localparam DB_B = 5'b01000;
localparam DB_C = 5'b01001;
localparam DB_D = 5'b01010;
localparam DB_E = 5'b01011;
localparam DB_H = 5'b01100;
localparam DB_L = 5'b01101;
localparam DB_MEM = 5'b01110;
localparam DB_A = 5'b01111;
localparam DB_PCL = 5'b10000;
localparam DB_PCH = 5'b10001;
reg [7:0] DB;
always @(*) begin
DB = 8'bx;
case(db_src)
DB_PSR: DB = rPSR;
DB_ALU: DB = aluOut;
DB_B: DB = rB;
DB_C: DB = rC;
DB_D: DB = rD;
DB_E: DB = rE;
DB_H: DB = rH;
DB_L: DB = rL;
DB_MEM: DB = memory_rdata;
DB_A: DB = rA;
DB_SPL: DB = rSP[7:0];
DB_SPH: DB = rSP[15:8];
DB_PCL: DB = rPC[7:0];
DB_PCH: DB = rPC[15:8];
DB_ALL: DB = AL[7:0];
DB_ALH: DB = AL[15:8];
endcase
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
rPC <= 0;
rIR <= 0;
rSP <= 0;
AL <= 0;
end else begin
if(cycle_done) begin
if(pc_increment)
rPC <= rPC + 1;
if(pc_jmp)
rPC <= {memory_rdata, aluIn};
if(pc_jmp_al)
rPC <= AL;
if(pc_rst_jmp)
rPC <= rIR & 8'h38;
if(ir_load)
rIR <= memory_rdata;
if(db_dst == DB_SPH)
rSP[15:8] <= DB;
if(db_dst == DB_SPL)
rSP[7:0] <= DB;
if(sp_increment)
rSP <= rSP + 1;
if(sp_decrement)
rSP <= rSP - 1;
if(db_dst == DB_ALH)
AL[15:8] <= DB;
if(db_dst == DB_ALL)
AL[7:0] <= DB;
if(al_increment)
AL <= AL + 1;
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
rPSR <= 2;
end else begin
if(cycle_done) begin
if(db_dst == DB_PSR)
rPSR <= DB & ~8'h28 | 2;
else
rPSR <= (rPSR & ~set_flags | alu_flags & set_flags) & ~8'h28 | 2;
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
{rA, rB, rC, rD, rE, rH, rL} <= 0;
aluIn <= 0;
end else begin
if(cycle_done) begin
case(db_dst)
DB_ALU: aluIn <= DB;
DB_B: rB <= DB;
DB_C: rC <= DB;
DB_D: rD <= DB;
DB_E: rE <= DB;
DB_H: rH <= DB;
DB_L: rL <= DB;
DB_A: rA <= DB;
endcase
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
state <= CPU_FETCH;
end else begin
if(cycle_done) begin
case(state)
CPU_FETCH:
if(debug_req)
state <= CPU_DEBUG0;
else
state <= CPU_DECODE;
CPU_DECODE:
state <= decode_goto;
CPU_HALT:
if(debug_req)
state <= CPU_DEBUG0;
else if(int_latch)
state <= CPU_FETCH;
CPU_MVI0:
state <= memory_operand ? CPU_MVI1 : CPU_FETCH;
CPU_MVI1:
state <= CPU_FETCH;
CPU_MOV:
state <= CPU_FETCH;
CPU_ALU0:
state <= CPU_ALU1;
CPU_ALU1:
state <= CPU_FETCH;
CPU_JMP0:
state <= CPU_JMP1;
CPU_JMP1:
state <= CPU_FETCH;
CPU_PUSH0:
state <= CPU_PUSH1;
CPU_PUSH1:
state <= CPU_PUSH2;
CPU_PUSH2:
state <= CPU_FETCH;
CPU_POP0:
state <= CPU_POP1;
CPU_POP1:
state <= CPU_FETCH;
CPU_LXI0:
state <= CPU_LXI1;
CPU_LXI1:
state <= CPU_FETCH;
CPU_DIRECT0:
state <= CPU_DIRECT1;
CPU_DIRECT1:
state <= CPU_DIRECT2;
CPU_DIRECT2:
if(iLHLD || iSHLD)
state <= CPU_DIRECT3;
else
state <= CPU_FETCH;
CPU_DIRECT3:
state <= CPU_FETCH;
CPU_UNARY:
state <= CPU_FETCH;
CPU_CALL0:
state <= CPU_CALL1;
CPU_CALL1:
if(!iCALLcc || condition)
state <= CPU_CALL2;
else
state <= CPU_FETCH;
CPU_CALL2:
state <= CPU_CALL3;
CPU_CALL3:
state <= CPU_FETCH;
CPU_RET0:
state <= CPU_RET1;
CPU_RET1:
state <= CPU_FETCH;
CPU_PCHL0:
state <= CPU_PCHL1;
CPU_PCHL1:
state <= CPU_PCHL2;
CPU_PCHL2:
state <= CPU_FETCH;
CPU_SPHL0:
state <= CPU_SPHL1;
CPU_SPHL1:
state <= CPU_FETCH;
CPU_INRDCR0:
state <= CPU_INRDCR1;
CPU_INRDCR1:
state <= CPU_FETCH;
CPU_INXDCX0:
state <= iINX_SP || iDCX_SP ? CPU_FETCH : CPU_INXDCX1;
CPU_INXDCX1:
state <= alu_carry_out ? CPU_INXDCX2 : CPU_FETCH;
CPU_INXDCX2:
state <= CPU_INXDCX3;
CPU_INXDCX3:
state <= CPU_FETCH;
CPU_LDAXSTAX0:
state <= CPU_LDAXSTAX1;
CPU_LDAXSTAX1:
state <= CPU_LDAXSTAX2;
CPU_LDAXSTAX2:
state <= CPU_FETCH;
CPU_DEBUG0:
state <= CPU_DEBUG1;
CPU_DEBUG1:
if(dbgEXIT)
state <= CPU_FETCH;
else
state <= CPU_DEBUG0;
CPU_XCHG0:
state <= CPU_XCHG1;
CPU_XCHG1:
state <= CPU_XCHG2;
CPU_XCHG2:
state <= CPU_XCHG3;
CPU_XCHG3:
state <= CPU_XCHG4;
CPU_XCHG4:
state <= CPU_XCHG5;
CPU_XCHG5:
state <= CPU_FETCH;
CPU_DAD0:
state <= CPU_DAD1;
CPU_DAD1:
state <= CPU_DAD2;
CPU_DAD2:
state <= CPU_DAD3;
CPU_DAD3:
state <= CPU_DAD4;
CPU_DAD4:
state <= CPU_DAD5;
CPU_DAD5:
state <= CPU_DAD6;
CPU_DAD6:
state <= CPU_DAD7;
CPU_DAD7:
state <= CPU_FETCH;
CPU_IO0:
state <= CPU_IO1;
CPU_IO1:
state <= CPU_FETCH;
CPU_EIDI:
state <= CPU_FETCH;
`ifndef SYNTHESIS
default:
assert(0);
`endif
endcase
end
end
end
always @(*) begin
memory_addr = 16'bx;
memory_wdata = 8'bx;
memory_read = 1'b0;
memory_write = 1'b0;
memory_io = 1'b0;
case(state)
CPU_FETCH, CPU_MVI0, CPU_JMP0, CPU_JMP1, CPU_LXI0, CPU_LXI1, CPU_DIRECT0, CPU_DIRECT1, CPU_IO0: begin
memory_addr = rPC;
memory_read = 1'b1;
end
CPU_CALL0, CPU_CALL1: begin
memory_addr = rPC;
memory_read = !iRST;
end
CPU_MVI1: begin
memory_addr = {rH, rL};
memory_wdata = DB;
memory_write = 1'b1;
end
CPU_MOV: begin
memory_addr = {rH, rL};
if(rIR[5:3] == 6) begin
memory_wdata = DB;
memory_write = 1'b1;
end else if(rIR[2:0] == 6)
memory_read = 1'b1;
end
CPU_ALU0: begin
if(iALUI) begin
memory_addr = rPC;
memory_read = 1'b1;
end else if(memory_operand) begin
memory_addr = {rH, rL};
memory_read = 1'b1;
end
end
CPU_PUSH1, CPU_PUSH2: begin
memory_addr = rSP;
memory_wdata = DB;
memory_write = 1'b1;
end
CPU_POP0, CPU_POP1, CPU_RET0, CPU_RET1: begin
memory_addr = rSP;
memory_read = 1'b1;
end
CPU_DIRECT2, CPU_DIRECT3: begin
memory_addr = AL;
memory_read = iLDA || iLHLD;
memory_write = iSTA || iSHLD;
memory_wdata = DB;
end
CPU_CALL2, CPU_CALL3: begin
memory_addr = rSP;
memory_wdata = DB;
memory_write = 1'b1;
end
CPU_INRDCR0, CPU_INRDCR1: begin
if(memory_operand) begin
memory_addr = {rH, rL};
memory_wdata = DB;
memory_read = state == CPU_INRDCR0;
memory_write = state == CPU_INRDCR1;
end
end
CPU_LDAXSTAX2: begin
memory_addr = AL;
memory_read = iLDAX;
memory_write = iSTAX;
memory_wdata = DB;
end
CPU_XCHG1, CPU_XCHG4: begin
if(iXTHL) begin
memory_read = 1'b1;
memory_addr = rSP;
end
end
CPU_XCHG2, CPU_XCHG5: begin
if(iXTHL) begin
memory_write = 1'b1;
memory_wdata = DB;
memory_addr = rSP;
end
end
CPU_IO1: begin
memory_addr = {8'b0, AL[7:0]};
memory_wdata = DB;
memory_read = iIN;
memory_write = iOUT;
memory_io = 1'b1;
end
CPU_DEBUG0: begin
memory_addr = 16'hCAFE;
memory_read = 1'b1;
memory_io = 1'b1;
end
CPU_DEBUG1: begin
memory_io = 1'b1;
if(dbgREAD) begin
memory_addr = 16'hCAFF;
memory_write = 1'b1;
memory_wdata = DB;
end
if(dbgWRITE) begin
memory_addr = 16'hCAFF;
memory_read = 1'b1;
end
end
endcase
end
always @(*) begin
db_src = 4'b0000;
db_dst = 4'b0000;
alu_op = ALU_NOP;
set_flags = 0;
case(state)
CPU_MOV: begin
db_src = {1'b1, rIR[2:0]};
db_dst = {1'b1, rIR[5:3]};
end
CPU_MVI0: begin
db_src = DB_MEM;
db_dst = memory_operand ? DB_ALU : {1'b1, rIR[5:3]};
end
CPU_MVI1: begin
db_src = DB_ALU;
end
CPU_ALU0: begin
db_src = iALUI ? DB_MEM : {1'b1, rIR[2:0]};
db_dst = DB_ALU;
end
CPU_ALU1: begin
db_src = DB_ALU;
if(rIR[5:3] != 3'b111)
db_dst = DB_A;
alu_op = rIR[5:3];
set_flags = 8'hff;
end
CPU_JMP0, CPU_RET0: begin
db_src = DB_MEM;
db_dst = DB_ALU;
end
CPU_PUSH1, CPU_PUSH2: begin
if(rIR[5:4] == 3)
db_src = state == CPU_PUSH1 ? DB_A : DB_PSR;
else
db_src = {1'b1, rIR[5:4], state == CPU_PUSH2};
end
CPU_POP0, CPU_POP1: begin
db_src = DB_MEM;
if(rIR[5:4] == 3)
db_dst = state == CPU_POP1 ? DB_A : DB_PSR;
else
db_dst = {1'b1, rIR[5:4], state == CPU_POP0};
end
CPU_LXI0, CPU_LXI1: begin
db_src = DB_MEM;
if(rIR[5:4] == 3)
db_dst = state == CPU_LXI1 ? DB_SPH : DB_SPL;
else
db_dst = {1'b1, rIR[5:4], state != CPU_LXI1};
end
CPU_DIRECT0, CPU_DIRECT1: begin
db_src = DB_MEM;
db_dst = state == CPU_DIRECT1 ? DB_ALH : DB_ALL;
end
CPU_DIRECT2: begin
case(1'b1)
iSTA:
db_src = DB_A;
iLDA: begin
db_src = DB_MEM;
db_dst = DB_A;
end
iSHLD:
db_src = DB_L;
iLHLD: begin
db_src = DB_MEM;
db_dst = DB_L;
end
endcase
end
CPU_DIRECT3: begin
if(iSHLD)
db_src = DB_H;
else begin
db_src = DB_MEM;
db_dst = DB_H;
end
end
CPU_UNARY: begin
db_src = DB_ALU;
db_dst = DB_A;
alu_op = {1'b1, rIR[5:3]};
case(rIR[5:3])
4: set_flags = 8'hff;
5: set_flags = 0;
default: set_flags = 1;
endcase
end
CPU_CALL0: begin
db_src = DB_MEM;
db_dst = DB_ALL;
end
CPU_CALL1: begin
db_src = DB_MEM;
db_dst = DB_ALH;
end
CPU_CALL2:
db_src = DB_PCH;
CPU_CALL3:
db_src = DB_PCL;
CPU_PCHL0: begin
db_src = DB_L;
db_dst = DB_ALL;
end
CPU_PCHL1: begin
db_src = DB_H;
db_dst = DB_ALH;
end
CPU_SPHL0: begin
db_src = DB_L;
db_dst = DB_SPL;
end
CPU_SPHL1: begin
db_src = DB_H;
db_dst = DB_SPH;
end
CPU_INRDCR0: begin
db_src = {1'b1, rIR[5:3]};
db_dst = DB_ALU;
end
CPU_INRDCR1: begin
db_src = DB_ALU;
db_dst = {1'b1, rIR[5:3]};
alu_op = iDCR ? ALU_DEC : ALU_INC;
set_flags = 8'hfe;
end
CPU_INXDCX0, CPU_INXDCX2: begin
db_src = {1'b1, rIR[5:4], state == CPU_INXDCX0};
db_dst = DB_ALU;
end
CPU_INXDCX1, CPU_INXDCX3: begin
db_src = DB_ALU;
db_dst = {1'b1, rIR[5:4], state == CPU_INXDCX1};
alu_op = iDCX ? ALU_DEC : ALU_INC;
end
CPU_LDAXSTAX0, CPU_LDAXSTAX1: begin
db_src = {1'b1, 1'b0, rIR[4], state == CPU_LDAXSTAX0};
db_dst = state == CPU_LDAXSTAX1 ? DB_ALH : DB_ALL;
end
CPU_LDAXSTAX2: begin
if(iLDAX) begin
db_src = DB_MEM;
db_dst = DB_A;
end else
db_src = DB_A;
end
CPU_DEBUG1: begin
if(dbgREAD) begin
db_src = rIR[4:0];
end
if(dbgWRITE) begin
db_src = DB_MEM;
db_dst = rIR[4:0];
end
end
CPU_XCHG0: begin
db_src = DB_L;
db_dst = DB_ALL;
end
CPU_XCHG1: begin
db_src = iXTHL ? DB_MEM : DB_E;
db_dst = DB_L;
end
CPU_XCHG2: begin
db_src = DB_ALL;
if(iXCHG)
db_dst = DB_E;
end
CPU_XCHG3: begin
db_src = DB_H;
db_dst = DB_ALL;
end
CPU_XCHG4: begin
db_src = iXTHL ? DB_MEM : DB_D;
db_dst = DB_H;
end
CPU_XCHG5: begin
db_src = DB_ALL;
if(iXCHG)
db_dst = DB_D;
end
CPU_DAD0: begin
db_src = DB_A;
db_dst = DB_ALL;
end
CPU_DAD1: begin
db_src = DB_L;
db_dst = DB_A;
end
CPU_DAD2: begin
db_src = rIR[5:4] == 3 ? DB_SPL : {1'b1, rIR[5:4], 1'b1};
db_dst = DB_ALU;
end
CPU_DAD3: begin
alu_op = ALU_ADD;
db_src = DB_ALU;
db_dst = DB_L;
set_flags = 8'h01;
end
CPU_DAD4: begin
db_src = DB_H;
db_dst = DB_A;
end
CPU_DAD5: begin
db_src = rIR[5:4] == 3 ? DB_SPH : {1'b1, rIR[5:4], 1'b0};
db_dst = DB_ALU;
end
CPU_DAD6: begin
alu_op = ALU_ADC;
db_src = DB_ALU;
db_dst = DB_H;
set_flags = 8'h01;
end
CPU_DAD7: begin
db_src = DB_ALL;
db_dst = DB_A;
end
CPU_IO0: begin
db_src = DB_MEM;
db_dst = DB_ALL;
end
CPU_IO1: begin
if(iIN) begin
db_src = DB_MEM;
db_dst = DB_A;
end
if(iOUT)
db_src = DB_A;
end
endcase
end
`ifdef FORMAL
initial state = CPU_FETCH;
default clocking
@(posedge clk);
endclocking
default disable iff(!rst_n);
assume property (memory_done |=> !memory_done);
assume property (debug_req && !cpu_in_debug |=> debug_req);
read_until_done: assert property (memory_read && !memory_done |=> memory_read);
write_until_done: assert property (memory_write && !memory_done |=> memory_write);
not_read_and_write: assert property (!memory_read || !memory_write);
stable_memory_addr: assert property (!$initstate && (memory_read && $past(memory_read) || memory_write && $past(memory_write)) && !$past(memory_done) |-> $stable(memory_addr) && $stable(memory_io));
stable_memory_wdata: assert property (!$initstate && memory_write && $past(memory_write) && !$past(memory_done) && state != CPU_DEBUG1 |-> $stable(memory_wdata));
assert property (state == CPU_ALU0 || state == CPU_ALU1 |-> iALU || iALUI);
assert property (state == CPU_HALT |-> iHALT);
assert property (state == CPU_POP0 || state == CPU_POP1 |-> iPOP);
assert property (state == CPU_PUSH0 || state == CPU_PUSH1 || state == CPU_PUSH2 |-> iPUSH);
assert property (state == CPU_PCHL0 || state == CPU_PCHL1 || state == CPU_PCHL2 |-> iPCHL);
assert property (state == CPU_RET0 || state == CPU_RET1 |-> iRET || iRETcc);
assert property (state == CPU_UNARY |-> iUNARY);
assert property (state == CPU_INRDCR0 || state == CPU_INRDCR1 |-> iINR || iDCR);
assert property (state == CPU_DAD0 || state == CPU_DAD1 || state == CPU_DAD2 || state == CPU_DAD3 || state == CPU_DAD4 || state == CPU_DAD5 || state == CPU_DAD6 || state == CPU_DAD7 |-> iDAD);
assert property (state == CPU_JMP0 || state == CPU_JMP1 |-> iJMP || iJMPcc);
assert property (state == CPU_INXDCX0 || state == CPU_INXDCX1 || state == CPU_INXDCX2 || state == CPU_INXDCX3 |-> iINX || iDCX);
assert property (state == CPU_MOV |-> iMOV);
assert property (state == CPU_DIRECT0 || state == CPU_DIRECT1 || state == CPU_DIRECT2 |-> iLDA || iSTA || iLHLD || iSHLD);
assert property (state == CPU_DIRECT3 |-> iLHLD || iSHLD);
assert property (state == CPU_MVI0 || state == CPU_MVI1 |-> iMVI);
assert property (state == CPU_LXI0 || state == CPU_LXI1 |-> iLXI);
assert property (state == CPU_LDAXSTAX0 || state == CPU_LDAXSTAX1 || state == CPU_LDAXSTAX2 |-> iLDAX || iSTAX);
assert property (state == CPU_SPHL0 || state == CPU_SPHL1 |-> iSPHL);
assert property (state == CPU_IO0 || state == CPU_IO1 |-> iIN || iOUT);
assert property (state == CPU_CALL0 || state == CPU_CALL1 || state == CPU_CALL2 || state == CPU_CALL3 |-> iCALL || iCALLcc || iRST);
assert property (state == CPU_XCHG0 || state == CPU_XCHG1 || state == CPU_XCHG2 || state == CPU_XCHG3 || state == CPU_XCHG4 || state == CPU_XCHG5 |-> iXCHG || iXTHL);
assert property (state == CPU_EIDI |-> iEI || iDI);
exactly_one_decode: assert property ($onehot({
iMOV, iALU, iALUI, iMVI, iJMP, iPUSH, iPOP, iHALT, iLXI, iLDA, iSTA, iLHLD, iSHLD,
iUNARY, iCALL, iCALLcc, iRST, iRET, iRETcc, iJMPcc, iPCHL, iSPHL, iINR, iDCR,
iINX, iDCX, iLDAX, iSTAX, iXCHG, iXTHL, iDAD, iIN, iOUT, iNOP, iEI, iDI,
undefined}));
inx_sp_dcx_sp: assert property ((!iINX_SP || iINX) && (!iDCX_SP || iDCX));
no_missing_cases: assert property (!missing_decoder_case);
`ifdef LIVENESS
assume property (memory_read |-> ##[1:3] memory_done);
assume property (memory_write |-> ##[1:3] memory_done);
assert property (state != CPU_FETCH |-> ##[1:40] state == CPU_FETCH || state == CPU_HALT || state == CPU_DEBUG0 || state == CPU_DEBUG1);
assert property (debug_req && !cpu_in_debug |-> ##[1:40] cpu_in_debug);
`endif
`endif
endmodule
|
tt06-finale_0048
|
tt06-finale
|
aiju-tt06-aiju-8080
|
task_sync
|
tt_um_aiju_8080
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_aiju_8080 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] bus_data_out; // From bus_if_i of bus_if.v
wire bus_handshake_req; // From bus_if_i of bus_if.v
wire bus_io; // From bus_if_i of bus_if.v
wire bus_output_enable; // From bus_if_i of bus_if.v
wire [1:0] bus_state; // From bus_if_i of bus_if.v
wire cpu_fetch; // From cpu_i of cpu.v
wire cpu_halted; // From cpu_i of cpu.v
wire cpu_in_debug; // From cpu_i of cpu.v
wire cpu_int_ack; // From cpu_i of cpu.v
wire [15:0] memory_addr; // From cpu_i of cpu.v
wire memory_done; // From bus_if_i of bus_if.v
wire memory_io; // From cpu_i of cpu.v
wire [7:0] memory_rdata; // From bus_if_i of bus_if.v
wire memory_read; // From cpu_i of cpu.v
wire [7:0] memory_wdata; // From cpu_i of cpu.v
wire memory_write; // From cpu_i of cpu.v
// End of automatics
assign uo_out[0] = bus_handshake_req;
assign uo_out[1] = bus_state[0];
assign uo_out[2] = bus_state[1];
assign uo_out[3] = bus_io;
assign uo_out[4] = cpu_fetch;
assign uo_out[5] = cpu_in_debug;
assign uo_out[6] = cpu_halted;
assign uo_out[7] = cpu_int_ack;
wire ext_bus_handshake_ack = ui_in[0];
wire ext_debug_req = ui_in[1];
wire ext_int_req = ui_in[2];
wire bus_handshake_ack;
(*keep_hierarchy*) sync bus_handshake_ack_sync(
.clk(clk),
.rst_n(rst_n),
.in(ext_bus_handshake_ack),
.out(bus_handshake_ack)
);
wire debug_req;
(*keep_hierarchy*) sync debug_req_sync(
.clk(clk),
.rst_n(rst_n),
.in(ext_debug_req),
.out(debug_req)
);
wire int_req;
(*keep_hierarchy*) sync int_req_sync(
.clk(clk),
.rst_n(rst_n),
.in(ext_int_req),
.out(int_req)
);
wire [7:0] bus_data_in = uio_in;
assign uio_out = bus_data_out;
assign uio_oe = {8{bus_output_enable}};
bus_if bus_if_i(/*AUTOINST*/
// Outputs
.bus_handshake_req(bus_handshake_req),
.bus_state (bus_state[1:0]),
.bus_data_out (bus_data_out[7:0]),
.bus_output_enable(bus_output_enable),
.bus_io (bus_io),
.memory_rdata (memory_rdata[7:0]),
.memory_done (memory_done),
// Inputs
.clk (clk),
.rst_n (rst_n),
.bus_handshake_ack(bus_handshake_ack),
.bus_data_in (bus_data_in[7:0]),
.memory_read (memory_read),
.memory_write (memory_write),
.memory_addr (memory_addr[15:0]),
.memory_io (memory_io),
.memory_wdata (memory_wdata[7:0]));
cpu cpu_i(/*AUTOINST*/
// Outputs
.memory_read (memory_read),
.memory_write (memory_write),
.memory_addr (memory_addr[15:0]),
.memory_io (memory_io),
.memory_wdata (memory_wdata[7:0]),
.cpu_fetch (cpu_fetch),
.cpu_halted (cpu_halted),
.cpu_in_debug (cpu_in_debug),
.cpu_int_ack (cpu_int_ack),
// Inputs
.clk (clk),
.rst_n (rst_n),
.memory_rdata (memory_rdata[7:0]),
.memory_done (memory_done),
.debug_req (debug_req),
.int_req (int_req));
endmodule
module sync(
input wire clk,
input wire rst_n,
input wire in,
output wire out
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
`default_nettype none
module bus_if(
input wire clk,
input wire rst_n,
input wire bus_handshake_ack,
output reg bus_handshake_req,
output reg [1:0] bus_state,
input wire [7:0] bus_data_in,
output reg [7:0] bus_data_out,
output reg bus_output_enable,
output wire bus_io,
input wire memory_read,
input wire memory_write,
input wire [15:0] memory_addr,
input wire memory_io,
input wire [7:0] memory_wdata,
output reg [7:0] memory_rdata,
output reg memory_done
);
reg [1:0] memory_state;
localparam MEMORY_IDLE = 0;
localparam MEMORY_ADDR_LOW = 1;
localparam MEMORY_ADDR_HIGH = 2;
localparam MEMORY_DATA = 3;
wire want_output_enable = memory_state != MEMORY_IDLE && (memory_state != MEMORY_DATA || memory_write);
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
memory_state <= MEMORY_IDLE;
memory_rdata <= 8'bx;
bus_handshake_req <= 1'b0;
memory_done <= 1'b0;
bus_output_enable <= 1'b0;
end else begin
memory_done <= 1'b0;
if(memory_state == MEMORY_IDLE && !memory_done && (memory_read || memory_write))
memory_state <= MEMORY_ADDR_LOW;
if(memory_state != MEMORY_IDLE && !bus_handshake_ack)
bus_output_enable <= want_output_enable;
if(memory_state != MEMORY_IDLE && !bus_handshake_ack && want_output_enable == bus_output_enable)
bus_handshake_req <= 1'b1;
if(bus_handshake_req && bus_handshake_ack) begin
bus_handshake_req <= 1'b0;
case(memory_state)
MEMORY_ADDR_LOW:
memory_state <= MEMORY_ADDR_HIGH;
MEMORY_ADDR_HIGH: begin
memory_state <= MEMORY_DATA;
if(memory_read)
bus_output_enable <= 1'b0;
end
MEMORY_DATA: begin
memory_state <= MEMORY_IDLE;
bus_output_enable <= 1'b0;
memory_done <= 1'b1;
if(memory_read)
memory_rdata <= bus_data_in;
end
endcase
end
end
end
assign bus_io = memory_io;
always @(*) begin
bus_data_out = 8'bx;
bus_state = 2'b00;
case(memory_state)
MEMORY_ADDR_LOW: begin
bus_data_out = memory_addr[7:0];
bus_state = 2'b00;
end
MEMORY_ADDR_HIGH: begin
bus_data_out = memory_addr[15:8];
bus_state = 2'b01;
end
MEMORY_DATA: begin
bus_state = {1'b1, memory_write};
if(memory_write) begin
bus_data_out = memory_wdata;
end
end
endcase
end
`ifdef FORMAL
initial begin
memory_state = MEMORY_IDLE;
memory_done = 1'b0;
bus_handshake_req = 1'b0;
bus_output_enable = 1'b0;
end
default clocking
@(posedge clk);
endclocking
default disable iff(!rst_n);
assume property (!(memory_read && memory_write));
assume property (memory_read && !memory_done |=> memory_read);
assume property (memory_write && !memory_done |=> memory_write);
assume property ($rose(bus_handshake_ack) |-> $past(bus_handshake_req));
assume property ($fell(bus_handshake_ack) |-> $past(!bus_handshake_req));
assume property ((memory_read && $past(memory_read)) || (memory_write && $past(memory_write)) |-> $stable(memory_addr) && $stable(memory_wdata));
state_invariant: assert property (memory_state != MEMORY_IDLE |-> (memory_read || memory_write) && !memory_done);
done_one_cycle: assert property (memory_done |=> !memory_done);
done_only_if_active: assert property (memory_done |-> memory_read || memory_write);
req_only_when_active: assert property (memory_state == MEMORY_IDLE |-> !bus_handshake_req);
req_when_no_ack: assert property ($rose(bus_handshake_req) |-> !bus_handshake_ack);
req_falls_when_ack: assert property (!$initstate && $fell(bus_handshake_req) |-> bus_handshake_ack);
stable_bus_state: assert property (bus_handshake_req |-> $stable(bus_state));
no_bus_contention: assert property (bus_handshake_req && bus_state == 2'b10 |-> !bus_output_enable && !$past(bus_output_enable));
stable_bus_data_out: assert property (bus_handshake_req && bus_state != 2'b10 |-> bus_output_enable && $past(bus_output_enable) && $stable(bus_data_out));
latch_bus_data: assert property (memory_done && memory_read |-> memory_rdata == $past(bus_data_in));
stable_bus_output: assert property ((bus_handshake_req || bus_handshake_ack) && !bus_output_enable |=> !bus_output_enable);
stable_bus_output2: assert property (bus_handshake_req && !bus_output_enable |-> !$past(bus_output_enable));
`ifdef LIVENESS
assume property(bus_handshake_req |-> ##[1:5] bus_handshake_ack);
assume property(!bus_handshake_req |-> ##[1:5] !bus_handshake_ack);
liveness: assert property ((memory_read || memory_write) && !memory_done |-> ##[1:40] memory_done);
`endif
`endif
endmodule
`default_nettype none
module cpu(
input wire clk,
input wire rst_n,
output reg memory_read,
output reg memory_write,
output reg [15:0] memory_addr,
output reg memory_io,
output reg [7:0] memory_wdata,
input wire [7:0] memory_rdata,
input wire memory_done,
input wire debug_req,
input wire int_req,
output wire cpu_fetch,
output wire cpu_halted,
output wire cpu_in_debug,
output wire cpu_int_ack
);
reg [15:0] AL;
reg [15:0] rPC;
reg [15:0] rSP;
reg [7:0] rA, rB, rC, rD, rE, rH, rL;
reg [7:0] rPSR;
reg [7:0] rIR;
reg [5:0] state;
localparam CPU_FETCH = 0;
localparam CPU_DECODE = 1;
localparam CPU_MVI0 = 2;
localparam CPU_MVI1 = 3;
localparam CPU_ALU0 = 4;
localparam CPU_ALU1 = 5;
localparam CPU_MOV = 6;
localparam CPU_JMP0 = 7;
localparam CPU_JMP1 = 8;
localparam CPU_PUSH0 = 9;
localparam CPU_PUSH1 = 10;
localparam CPU_PUSH2 = 11;
localparam CPU_POP0 = 12;
localparam CPU_POP1 = 13;
localparam CPU_HALT = 14;
localparam CPU_LXI0 = 15;
localparam CPU_LXI1 = 16;
localparam CPU_DIRECT0 = 17;
localparam CPU_DIRECT1 = 18;
localparam CPU_DIRECT2 = 19;
localparam CPU_DIRECT3 = 20;
localparam CPU_UNARY = 21;
localparam CPU_CALL0 = 22;
localparam CPU_CALL1 = 23;
localparam CPU_CALL2 = 24;
localparam CPU_CALL3 = 25;
localparam CPU_RET0 = 26;
localparam CPU_RET1 = 27;
localparam CPU_PCHL0 = 28;
localparam CPU_PCHL1 = 29;
localparam CPU_PCHL2 = 30;
localparam CPU_SPHL0 = 31;
localparam CPU_SPHL1 = 32;
localparam CPU_INRDCR0 = 33;
localparam CPU_INRDCR1 = 34;
localparam CPU_INXDCX0 = 35;
localparam CPU_INXDCX1 = 36;
localparam CPU_INXDCX2 = 37;
localparam CPU_INXDCX3 = 38;
localparam CPU_LDAXSTAX0 = 39;
localparam CPU_LDAXSTAX1 = 40;
localparam CPU_LDAXSTAX2 = 41;
localparam CPU_XCHG0 = 42;
localparam CPU_XCHG1 = 43;
localparam CPU_XCHG2 = 44;
localparam CPU_XCHG3 = 45;
localparam CPU_XCHG4 = 46;
localparam CPU_XCHG5 = 47;
localparam CPU_DAD0 = 48;
localparam CPU_DAD1 = 49;
localparam CPU_DAD2 = 50;
localparam CPU_DAD3 = 51;
localparam CPU_DAD4 = 52;
localparam CPU_DAD5 = 53;
localparam CPU_DAD6 = 54;
localparam CPU_DAD7 = 55;
localparam CPU_IO0 = 56;
localparam CPU_IO1 = 57;
localparam CPU_EIDI = 58;
localparam CPU_DEBUG0 = 62;
localparam CPU_DEBUG1 = 63;
wire iMOV = rIR[7:6] == 1 && rIR != 8'b01110110;
wire iALU = rIR[7:6] == 2;
wire iALUI = (rIR & ~8'h38) == 8'b1100_0110;
wire iMVI = rIR[7:6] == 0 && rIR[2:0] == 3'b110;
wire iJMP = rIR == 8'b1100_0011;
wire iPUSH = (rIR & ~8'h30) == 8'b1100_0101;
wire iPOP = (rIR & ~8'h30) == 8'b1100_0001;
wire iHALT = rIR == 8'h76;
wire iLXI = (rIR & ~8'h30) == 8'b0000_0001;
wire iLDA = rIR == 8'h3A;
wire iSTA = rIR == 8'h32;
wire iLHLD = rIR == 8'h2A;
wire iSHLD = rIR == 8'h22;
wire iUNARY = (rIR & ~8'h38) == 8'b0000_0111;
wire iCALL = rIR == 8'hCD;
wire iCALLcc = (rIR & ~8'h38) == 8'b1100_0100;
wire iRST = (rIR & ~8'h38) == 8'b1100_0111;
wire iRET = rIR == 8'hC9;
wire iRETcc = (rIR & ~8'h38) == 8'b1100_0000;
wire iJMPcc = (rIR & ~8'h38) == 8'b1100_0010;
wire iPCHL = rIR == 8'hE9;
wire iSPHL = rIR == 8'hF9;
wire iINR = (rIR & ~8'h38) == 8'b0000_0100;
wire iDCR = (rIR & ~8'h38) == 8'b0000_0101;
wire iINX = (rIR & ~8'h30) == 8'b0000_0011;
wire iDCX = (rIR & ~8'h30) == 8'b0000_1011;
wire iINX_SP = rIR == 8'b0011_0011;
wire iDCX_SP = rIR == 8'b0011_1011;
wire iLDAX = (rIR & ~8'h10) == 8'b0000_1010;
wire iSTAX = (rIR & ~8'h10) == 8'b0000_0010;
wire iXCHG = rIR == 8'b1110_1011;
wire iXTHL = rIR == 8'b1110_0011;
wire iDAD = (rIR & ~8'h30) == 8'b0000_1001;
wire iIN = rIR == 8'b1101_1011;
wire iOUT = rIR == 8'b1101_0011;
wire iNOP = rIR == 8'b0000_0000;
wire iEI = rIR == 8'b1111_1011;
wire iDI = rIR == 8'b1111_0011;
wire undefined =
(rIR & ~8'h38) == 8'b0000_0000 && !iNOP
|| rIR == 8'b1101_1001
|| (rIR & ~8'h30) == 8'b1100_1101 && !iCALL
|| rIR == 8'b1100_1011;
wire memory_operand =
iMOV && (rIR[5:3] == 3'b110 || rIR[2:0] == 3'b110)
|| iALU && rIR[2:0] == 3'b110
|| (iINR || iDCR || iMVI) && rIR[5:3] == 3'b110;
wire dbgEXIT = rIR[6];
wire dbgREAD = !rIR[7] && !dbgEXIT;
wire dbgWRITE = rIR[7];
reg condition;
always @(*) begin
case(rIR[5:3])
3'b000: condition = !rPSR[6];
3'b001: condition = rPSR[6];
3'b010: condition = !rPSR[0];
3'b011: condition = rPSR[0];
3'b100: condition = !rPSR[2];
3'b101: condition = rPSR[2];
3'b110: condition = !rPSR[7];
3'b111: condition = rPSR[7];
endcase
end
reg int_enabled;
reg int_latch;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
int_enabled <= 1'b0;
int_latch <= 1'b0;
end else begin
if(state == CPU_EIDI) begin
if(iEI)
int_enabled <= 1'b1;
if(iDI)
int_enabled <= 1'b0;
end
if(cpu_int_ack)
int_enabled <= 1'b0;
if(cycle_done)
int_latch <= int_req && int_enabled && !(state == CPU_EIDI && iDI || cpu_int_ack);
end
end
assign cpu_int_ack = state == CPU_FETCH && int_latch;
reg [5:0] decode_goto;
reg missing_decoder_case;
always @(*) begin
decode_goto = CPU_FETCH;
missing_decoder_case = 1'b0;
case(1'b1)
iMOV: decode_goto = CPU_MOV;
iALU, iALUI: decode_goto = CPU_ALU0;
iMVI: decode_goto = CPU_MVI0;
iJMP, iJMPcc: decode_goto = CPU_JMP0;
iPUSH: decode_goto = CPU_PUSH0;
iPOP: decode_goto = CPU_POP0;
iHALT: decode_goto = CPU_HALT;
iLXI: decode_goto = CPU_LXI0;
iLDA, iSTA, iLHLD, iSHLD: decode_goto = CPU_DIRECT0;
iUNARY: decode_goto = CPU_UNARY;
iCALL, iCALLcc, iRST: decode_goto = CPU_CALL0;
iRET: decode_goto = CPU_RET0;
iRETcc: decode_goto = condition ? CPU_RET0 : CPU_FETCH;
iPCHL: decode_goto = CPU_PCHL0;
iSPHL: decode_goto = CPU_SPHL0;
iINR, iDCR: decode_goto = CPU_INRDCR0;
iINX, iDCX: decode_goto = CPU_INXDCX0;
iLDAX, iSTAX: decode_goto = CPU_LDAXSTAX0;
iXCHG, iXTHL: decode_goto = CPU_XCHG0;
iDAD: decode_goto = CPU_DAD0;
iIN, iOUT: decode_goto = CPU_IO0;
iNOP, undefined: decode_goto = CPU_FETCH;
iEI, iDI: decode_goto = CPU_EIDI;
default: missing_decoder_case = 1'b1;
endcase
end
always @(posedge clk) begin
if(state == CPU_DECODE && undefined)
$display("undefined opcode %x", rIR);
end
reg [7:0] aluIn;
reg [7:0] aluOut;
reg alu_carry_out, alu_aux_carry_out;
reg [4:0] alu_op;
reg [7:0] set_flags;
localparam ALU_ADD = 0;
localparam ALU_ADC = 1;
localparam ALU_SUB = 2;
localparam ALU_SBB = 3;
localparam ALU_AND = 4;
localparam ALU_XOR = 5;
localparam ALU_OR = 6;
localparam ALU_CMP = 7;
localparam ALU_RLC = 8;
localparam ALU_RRC = 9;
localparam ALU_RAL = 10;
localparam ALU_RAR = 11;
localparam ALU_DAA = 12;
localparam ALU_CMA = 13;
localparam ALU_STC = 14;
localparam ALU_CMC = 15;
localparam ALU_INC = 16;
localparam ALU_DEC = 17;
localparam ALU_NOP = 31;
reg [7:0] daa_operand;
always @(*) begin
daa_operand = 8'h00;
if(rA[3:0] > 9 || rPSR[4])
daa_operand[3:0] = 6;
if(rA >= 8'h9a || rPSR[0])
daa_operand[7:4] = 6;
end
always @(*) begin
alu_carry_out = 1'b0;
alu_aux_carry_out = 1'b0;
aluOut = aluIn;
case(alu_op)
ALU_ADD, ALU_ADC: begin
{alu_carry_out, aluOut} = rA + aluIn + (rPSR[0] & (alu_op == ALU_ADC));
alu_aux_carry_out = (((rA & 15) + (aluIn & 15) + (rPSR[0] & (alu_op == ALU_ADC))) & 16) != 0;
end
ALU_SUB, ALU_SBB, ALU_CMP: begin
{alu_carry_out, aluOut} = rA - aluIn - (rPSR[0] & (alu_op == ALU_SBB));
alu_aux_carry_out = (((rA & 15) - (aluIn & 15) - (rPSR[0] & (alu_op == ALU_SBB))) & 16) == 0;
end
ALU_AND: begin
aluOut = rA & aluIn;
alu_aux_carry_out = rA[3] | aluIn[3];
end
ALU_OR:
aluOut = rA | aluIn;
ALU_XOR:
aluOut = rA ^ aluIn;
ALU_RLC: begin
aluOut = {rA[6:0], rA[7]};
alu_carry_out = rA[7];
end
ALU_RRC: begin
aluOut = {rA[0], rA[7:1]};
alu_carry_out = rA[0];
end
ALU_RAL: begin
{alu_carry_out, aluOut} = {rA, rPSR[0]};
end
ALU_RAR: begin
{aluOut, alu_carry_out} = {rPSR[0], rA};
end
ALU_CMA: aluOut = ~rA;
ALU_CMC: begin
aluOut = rA;
alu_carry_out = ~rPSR[0];
end
ALU_STC: begin
aluOut = rA;
alu_carry_out = 1'b1;
end
ALU_DAA: begin
{alu_carry_out, aluOut} = (rA + daa_operand) | (rPSR[0] ? 9'h100 : 9'h000);
alu_aux_carry_out = (((rA & 15) + (daa_operand & 15)) & 16) != 0;
end
ALU_INC: begin
{alu_carry_out, aluOut} = aluIn + 1;
alu_aux_carry_out = (aluIn & 15) == 15;
end
ALU_DEC: begin
{alu_carry_out, aluOut} = aluIn - 1;
alu_aux_carry_out = (aluIn & 15) != 0;
end
endcase
end
wire alu_zero = aluOut == 0;
wire alu_parity = ~^aluOut;
wire alu_sign = aluOut[7];
wire [7:0] alu_flags = {alu_sign, alu_zero, 1'b0, alu_aux_carry_out, 1'b0, alu_parity, 1'b1, alu_carry_out};
wire cycle_done = !memory_read && !memory_write || memory_done;
wire pc_increment =
state == CPU_FETCH && !debug_req && !cpu_int_ack
|| state == CPU_MVI0 || state == CPU_JMP0 || state == CPU_JMP1 && iJMPcc && !condition
|| state == CPU_ALU0 && iALUI
|| state == CPU_LXI0 || state == CPU_LXI1
|| state == CPU_DIRECT0 || state == CPU_DIRECT1
|| (state == CPU_CALL0 || state == CPU_CALL1) && !iRST
|| state == CPU_IO0;
wire al_increment = state == CPU_DIRECT2;
wire sp_decrement =
state == CPU_PUSH0 || state == CPU_PUSH1
|| state == CPU_CALL1 && (!iCALLcc || condition)
|| state == CPU_CALL2
|| state == CPU_INXDCX0 && iDCX_SP
|| state == CPU_XCHG5 && iXTHL;
wire sp_increment =
state == CPU_POP0 || state == CPU_POP1
|| state == CPU_RET0 || state == CPU_RET1
|| state == CPU_INXDCX0 && iINX_SP
|| state == CPU_XCHG2 && iXTHL;
wire pc_jmp =
state == CPU_JMP1 && (!iJMPcc || condition)
|| state == CPU_RET1;
wire pc_jmp_al = state == CPU_CALL3 && !iRST || state == CPU_PCHL2;
wire pc_rst_jmp = state == CPU_CALL3 && iRST;
wire ir_load = state == CPU_FETCH || state == CPU_DEBUG0;
assign cpu_fetch = state == CPU_FETCH;
assign cpu_halted = state == CPU_HALT;
assign cpu_in_debug = state == CPU_DEBUG0 || state == CPU_DEBUG1;
reg [4:0] db_dst;
reg [4:0] db_src;
localparam DB_ALL = 5'b00010;
localparam DB_ALH = 5'b00011;
localparam DB_SPL = 5'b00100;
localparam DB_SPH = 5'b00101;
localparam DB_PSR = 5'b00110;
localparam DB_ALU = 5'b00111;
localparam DB_B = 5'b01000;
localparam DB_C = 5'b01001;
localparam DB_D = 5'b01010;
localparam DB_E = 5'b01011;
localparam DB_H = 5'b01100;
localparam DB_L = 5'b01101;
localparam DB_MEM = 5'b01110;
localparam DB_A = 5'b01111;
localparam DB_PCL = 5'b10000;
localparam DB_PCH = 5'b10001;
reg [7:0] DB;
always @(*) begin
DB = 8'bx;
case(db_src)
DB_PSR: DB = rPSR;
DB_ALU: DB = aluOut;
DB_B: DB = rB;
DB_C: DB = rC;
DB_D: DB = rD;
DB_E: DB = rE;
DB_H: DB = rH;
DB_L: DB = rL;
DB_MEM: DB = memory_rdata;
DB_A: DB = rA;
DB_SPL: DB = rSP[7:0];
DB_SPH: DB = rSP[15:8];
DB_PCL: DB = rPC[7:0];
DB_PCH: DB = rPC[15:8];
DB_ALL: DB = AL[7:0];
DB_ALH: DB = AL[15:8];
endcase
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
rPC <= 0;
rIR <= 0;
rSP <= 0;
AL <= 0;
end else begin
if(cycle_done) begin
if(pc_increment)
rPC <= rPC + 1;
if(pc_jmp)
rPC <= {memory_rdata, aluIn};
if(pc_jmp_al)
rPC <= AL;
if(pc_rst_jmp)
rPC <= rIR & 8'h38;
if(ir_load)
rIR <= memory_rdata;
if(db_dst == DB_SPH)
rSP[15:8] <= DB;
if(db_dst == DB_SPL)
rSP[7:0] <= DB;
if(sp_increment)
rSP <= rSP + 1;
if(sp_decrement)
rSP <= rSP - 1;
if(db_dst == DB_ALH)
AL[15:8] <= DB;
if(db_dst == DB_ALL)
AL[7:0] <= DB;
if(al_increment)
AL <= AL + 1;
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
rPSR <= 2;
end else begin
if(cycle_done) begin
if(db_dst == DB_PSR)
rPSR <= DB & ~8'h28 | 2;
else
rPSR <= (rPSR & ~set_flags | alu_flags & set_flags) & ~8'h28 | 2;
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
{rA, rB, rC, rD, rE, rH, rL} <= 0;
aluIn <= 0;
end else begin
if(cycle_done) begin
case(db_dst)
DB_ALU: aluIn <= DB;
DB_B: rB <= DB;
DB_C: rC <= DB;
DB_D: rD <= DB;
DB_E: rE <= DB;
DB_H: rH <= DB;
DB_L: rL <= DB;
DB_A: rA <= DB;
endcase
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
state <= CPU_FETCH;
end else begin
if(cycle_done) begin
case(state)
CPU_FETCH:
if(debug_req)
state <= CPU_DEBUG0;
else
state <= CPU_DECODE;
CPU_DECODE:
state <= decode_goto;
CPU_HALT:
if(debug_req)
state <= CPU_DEBUG0;
else if(int_latch)
state <= CPU_FETCH;
CPU_MVI0:
state <= memory_operand ? CPU_MVI1 : CPU_FETCH;
CPU_MVI1:
state <= CPU_FETCH;
CPU_MOV:
state <= CPU_FETCH;
CPU_ALU0:
state <= CPU_ALU1;
CPU_ALU1:
state <= CPU_FETCH;
CPU_JMP0:
state <= CPU_JMP1;
CPU_JMP1:
state <= CPU_FETCH;
CPU_PUSH0:
state <= CPU_PUSH1;
CPU_PUSH1:
state <= CPU_PUSH2;
CPU_PUSH2:
state <= CPU_FETCH;
CPU_POP0:
state <= CPU_POP1;
CPU_POP1:
state <= CPU_FETCH;
CPU_LXI0:
state <= CPU_LXI1;
CPU_LXI1:
state <= CPU_FETCH;
CPU_DIRECT0:
state <= CPU_DIRECT1;
CPU_DIRECT1:
state <= CPU_DIRECT2;
CPU_DIRECT2:
if(iLHLD || iSHLD)
state <= CPU_DIRECT3;
else
state <= CPU_FETCH;
CPU_DIRECT3:
state <= CPU_FETCH;
CPU_UNARY:
state <= CPU_FETCH;
CPU_CALL0:
state <= CPU_CALL1;
CPU_CALL1:
if(!iCALLcc || condition)
state <= CPU_CALL2;
else
state <= CPU_FETCH;
CPU_CALL2:
state <= CPU_CALL3;
CPU_CALL3:
state <= CPU_FETCH;
CPU_RET0:
state <= CPU_RET1;
CPU_RET1:
state <= CPU_FETCH;
CPU_PCHL0:
state <= CPU_PCHL1;
CPU_PCHL1:
state <= CPU_PCHL2;
CPU_PCHL2:
state <= CPU_FETCH;
CPU_SPHL0:
state <= CPU_SPHL1;
CPU_SPHL1:
state <= CPU_FETCH;
CPU_INRDCR0:
state <= CPU_INRDCR1;
CPU_INRDCR1:
state <= CPU_FETCH;
CPU_INXDCX0:
state <= iINX_SP || iDCX_SP ? CPU_FETCH : CPU_INXDCX1;
CPU_INXDCX1:
state <= alu_carry_out ? CPU_INXDCX2 : CPU_FETCH;
CPU_INXDCX2:
state <= CPU_INXDCX3;
CPU_INXDCX3:
state <= CPU_FETCH;
CPU_LDAXSTAX0:
state <= CPU_LDAXSTAX1;
CPU_LDAXSTAX1:
state <= CPU_LDAXSTAX2;
CPU_LDAXSTAX2:
state <= CPU_FETCH;
CPU_DEBUG0:
state <= CPU_DEBUG1;
CPU_DEBUG1:
if(dbgEXIT)
state <= CPU_FETCH;
else
state <= CPU_DEBUG0;
CPU_XCHG0:
state <= CPU_XCHG1;
CPU_XCHG1:
state <= CPU_XCHG2;
CPU_XCHG2:
state <= CPU_XCHG3;
CPU_XCHG3:
state <= CPU_XCHG4;
CPU_XCHG4:
state <= CPU_XCHG5;
CPU_XCHG5:
state <= CPU_FETCH;
CPU_DAD0:
state <= CPU_DAD1;
CPU_DAD1:
state <= CPU_DAD2;
CPU_DAD2:
state <= CPU_DAD3;
CPU_DAD3:
state <= CPU_DAD4;
CPU_DAD4:
state <= CPU_DAD5;
CPU_DAD5:
state <= CPU_DAD6;
CPU_DAD6:
state <= CPU_DAD7;
CPU_DAD7:
state <= CPU_FETCH;
CPU_IO0:
state <= CPU_IO1;
CPU_IO1:
state <= CPU_FETCH;
CPU_EIDI:
state <= CPU_FETCH;
`ifndef SYNTHESIS
default:
assert(0);
`endif
endcase
end
end
end
always @(*) begin
memory_addr = 16'bx;
memory_wdata = 8'bx;
memory_read = 1'b0;
memory_write = 1'b0;
memory_io = 1'b0;
case(state)
CPU_FETCH, CPU_MVI0, CPU_JMP0, CPU_JMP1, CPU_LXI0, CPU_LXI1, CPU_DIRECT0, CPU_DIRECT1, CPU_IO0: begin
memory_addr = rPC;
memory_read = 1'b1;
end
CPU_CALL0, CPU_CALL1: begin
memory_addr = rPC;
memory_read = !iRST;
end
CPU_MVI1: begin
memory_addr = {rH, rL};
memory_wdata = DB;
memory_write = 1'b1;
end
CPU_MOV: begin
memory_addr = {rH, rL};
if(rIR[5:3] == 6) begin
memory_wdata = DB;
memory_write = 1'b1;
end else if(rIR[2:0] == 6)
memory_read = 1'b1;
end
CPU_ALU0: begin
if(iALUI) begin
memory_addr = rPC;
memory_read = 1'b1;
end else if(memory_operand) begin
memory_addr = {rH, rL};
memory_read = 1'b1;
end
end
CPU_PUSH1, CPU_PUSH2: begin
memory_addr = rSP;
memory_wdata = DB;
memory_write = 1'b1;
end
CPU_POP0, CPU_POP1, CPU_RET0, CPU_RET1: begin
memory_addr = rSP;
memory_read = 1'b1;
end
CPU_DIRECT2, CPU_DIRECT3: begin
memory_addr = AL;
memory_read = iLDA || iLHLD;
memory_write = iSTA || iSHLD;
memory_wdata = DB;
end
CPU_CALL2, CPU_CALL3: begin
memory_addr = rSP;
memory_wdata = DB;
memory_write = 1'b1;
end
CPU_INRDCR0, CPU_INRDCR1: begin
if(memory_operand) begin
memory_addr = {rH, rL};
memory_wdata = DB;
memory_read = state == CPU_INRDCR0;
memory_write = state == CPU_INRDCR1;
end
end
CPU_LDAXSTAX2: begin
memory_addr = AL;
memory_read = iLDAX;
memory_write = iSTAX;
memory_wdata = DB;
end
CPU_XCHG1, CPU_XCHG4: begin
if(iXTHL) begin
memory_read = 1'b1;
memory_addr = rSP;
end
end
CPU_XCHG2, CPU_XCHG5: begin
if(iXTHL) begin
memory_write = 1'b1;
memory_wdata = DB;
memory_addr = rSP;
end
end
CPU_IO1: begin
memory_addr = {8'b0, AL[7:0]};
memory_wdata = DB;
memory_read = iIN;
memory_write = iOUT;
memory_io = 1'b1;
end
CPU_DEBUG0: begin
memory_addr = 16'hCAFE;
memory_read = 1'b1;
memory_io = 1'b1;
end
CPU_DEBUG1: begin
memory_io = 1'b1;
if(dbgREAD) begin
memory_addr = 16'hCAFF;
memory_write = 1'b1;
memory_wdata = DB;
end
if(dbgWRITE) begin
memory_addr = 16'hCAFF;
memory_read = 1'b1;
end
end
endcase
end
always @(*) begin
db_src = 4'b0000;
db_dst = 4'b0000;
alu_op = ALU_NOP;
set_flags = 0;
case(state)
CPU_MOV: begin
db_src = {1'b1, rIR[2:0]};
db_dst = {1'b1, rIR[5:3]};
end
CPU_MVI0: begin
db_src = DB_MEM;
db_dst = memory_operand ? DB_ALU : {1'b1, rIR[5:3]};
end
CPU_MVI1: begin
db_src = DB_ALU;
end
CPU_ALU0: begin
db_src = iALUI ? DB_MEM : {1'b1, rIR[2:0]};
db_dst = DB_ALU;
end
CPU_ALU1: begin
db_src = DB_ALU;
if(rIR[5:3] != 3'b111)
db_dst = DB_A;
alu_op = rIR[5:3];
set_flags = 8'hff;
end
CPU_JMP0, CPU_RET0: begin
db_src = DB_MEM;
db_dst = DB_ALU;
end
CPU_PUSH1, CPU_PUSH2: begin
if(rIR[5:4] == 3)
db_src = state == CPU_PUSH1 ? DB_A : DB_PSR;
else
db_src = {1'b1, rIR[5:4], state == CPU_PUSH2};
end
CPU_POP0, CPU_POP1: begin
db_src = DB_MEM;
if(rIR[5:4] == 3)
db_dst = state == CPU_POP1 ? DB_A : DB_PSR;
else
db_dst = {1'b1, rIR[5:4], state == CPU_POP0};
end
CPU_LXI0, CPU_LXI1: begin
db_src = DB_MEM;
if(rIR[5:4] == 3)
db_dst = state == CPU_LXI1 ? DB_SPH : DB_SPL;
else
db_dst = {1'b1, rIR[5:4], state != CPU_LXI1};
end
CPU_DIRECT0, CPU_DIRECT1: begin
db_src = DB_MEM;
db_dst = state == CPU_DIRECT1 ? DB_ALH : DB_ALL;
end
CPU_DIRECT2: begin
case(1'b1)
iSTA:
db_src = DB_A;
iLDA: begin
db_src = DB_MEM;
db_dst = DB_A;
end
iSHLD:
db_src = DB_L;
iLHLD: begin
db_src = DB_MEM;
db_dst = DB_L;
end
endcase
end
CPU_DIRECT3: begin
if(iSHLD)
db_src = DB_H;
else begin
db_src = DB_MEM;
db_dst = DB_H;
end
end
CPU_UNARY: begin
db_src = DB_ALU;
db_dst = DB_A;
alu_op = {1'b1, rIR[5:3]};
case(rIR[5:3])
4: set_flags = 8'hff;
5: set_flags = 0;
default: set_flags = 1;
endcase
end
CPU_CALL0: begin
db_src = DB_MEM;
db_dst = DB_ALL;
end
CPU_CALL1: begin
db_src = DB_MEM;
db_dst = DB_ALH;
end
CPU_CALL2:
db_src = DB_PCH;
CPU_CALL3:
db_src = DB_PCL;
CPU_PCHL0: begin
db_src = DB_L;
db_dst = DB_ALL;
end
CPU_PCHL1: begin
db_src = DB_H;
db_dst = DB_ALH;
end
CPU_SPHL0: begin
db_src = DB_L;
db_dst = DB_SPL;
end
CPU_SPHL1: begin
db_src = DB_H;
db_dst = DB_SPH;
end
CPU_INRDCR0: begin
db_src = {1'b1, rIR[5:3]};
db_dst = DB_ALU;
end
CPU_INRDCR1: begin
db_src = DB_ALU;
db_dst = {1'b1, rIR[5:3]};
alu_op = iDCR ? ALU_DEC : ALU_INC;
set_flags = 8'hfe;
end
CPU_INXDCX0, CPU_INXDCX2: begin
db_src = {1'b1, rIR[5:4], state == CPU_INXDCX0};
db_dst = DB_ALU;
end
CPU_INXDCX1, CPU_INXDCX3: begin
db_src = DB_ALU;
db_dst = {1'b1, rIR[5:4], state == CPU_INXDCX1};
alu_op = iDCX ? ALU_DEC : ALU_INC;
end
CPU_LDAXSTAX0, CPU_LDAXSTAX1: begin
db_src = {1'b1, 1'b0, rIR[4], state == CPU_LDAXSTAX0};
db_dst = state == CPU_LDAXSTAX1 ? DB_ALH : DB_ALL;
end
CPU_LDAXSTAX2: begin
if(iLDAX) begin
db_src = DB_MEM;
db_dst = DB_A;
end else
db_src = DB_A;
end
CPU_DEBUG1: begin
if(dbgREAD) begin
db_src = rIR[4:0];
end
if(dbgWRITE) begin
db_src = DB_MEM;
db_dst = rIR[4:0];
end
end
CPU_XCHG0: begin
db_src = DB_L;
db_dst = DB_ALL;
end
CPU_XCHG1: begin
db_src = iXTHL ? DB_MEM : DB_E;
db_dst = DB_L;
end
CPU_XCHG2: begin
db_src = DB_ALL;
if(iXCHG)
db_dst = DB_E;
end
CPU_XCHG3: begin
db_src = DB_H;
db_dst = DB_ALL;
end
CPU_XCHG4: begin
db_src = iXTHL ? DB_MEM : DB_D;
db_dst = DB_H;
end
CPU_XCHG5: begin
db_src = DB_ALL;
if(iXCHG)
db_dst = DB_D;
end
CPU_DAD0: begin
db_src = DB_A;
db_dst = DB_ALL;
end
CPU_DAD1: begin
db_src = DB_L;
db_dst = DB_A;
end
CPU_DAD2: begin
db_src = rIR[5:4] == 3 ? DB_SPL : {1'b1, rIR[5:4], 1'b1};
db_dst = DB_ALU;
end
CPU_DAD3: begin
alu_op = ALU_ADD;
db_src = DB_ALU;
db_dst = DB_L;
set_flags = 8'h01;
end
CPU_DAD4: begin
db_src = DB_H;
db_dst = DB_A;
end
CPU_DAD5: begin
db_src = rIR[5:4] == 3 ? DB_SPH : {1'b1, rIR[5:4], 1'b0};
db_dst = DB_ALU;
end
CPU_DAD6: begin
alu_op = ALU_ADC;
db_src = DB_ALU;
db_dst = DB_H;
set_flags = 8'h01;
end
CPU_DAD7: begin
db_src = DB_ALL;
db_dst = DB_A;
end
CPU_IO0: begin
db_src = DB_MEM;
db_dst = DB_ALL;
end
CPU_IO1: begin
if(iIN) begin
db_src = DB_MEM;
db_dst = DB_A;
end
if(iOUT)
db_src = DB_A;
end
endcase
end
`ifdef FORMAL
initial state = CPU_FETCH;
default clocking
@(posedge clk);
endclocking
default disable iff(!rst_n);
assume property (memory_done |=> !memory_done);
assume property (debug_req && !cpu_in_debug |=> debug_req);
read_until_done: assert property (memory_read && !memory_done |=> memory_read);
write_until_done: assert property (memory_write && !memory_done |=> memory_write);
not_read_and_write: assert property (!memory_read || !memory_write);
stable_memory_addr: assert property (!$initstate && (memory_read && $past(memory_read) || memory_write && $past(memory_write)) && !$past(memory_done) |-> $stable(memory_addr) && $stable(memory_io));
stable_memory_wdata: assert property (!$initstate && memory_write && $past(memory_write) && !$past(memory_done) && state != CPU_DEBUG1 |-> $stable(memory_wdata));
assert property (state == CPU_ALU0 || state == CPU_ALU1 |-> iALU || iALUI);
assert property (state == CPU_HALT |-> iHALT);
assert property (state == CPU_POP0 || state == CPU_POP1 |-> iPOP);
assert property (state == CPU_PUSH0 || state == CPU_PUSH1 || state == CPU_PUSH2 |-> iPUSH);
assert property (state == CPU_PCHL0 || state == CPU_PCHL1 || state == CPU_PCHL2 |-> iPCHL);
assert property (state == CPU_RET0 || state == CPU_RET1 |-> iRET || iRETcc);
assert property (state == CPU_UNARY |-> iUNARY);
assert property (state == CPU_INRDCR0 || state == CPU_INRDCR1 |-> iINR || iDCR);
assert property (state == CPU_DAD0 || state == CPU_DAD1 || state == CPU_DAD2 || state == CPU_DAD3 || state == CPU_DAD4 || state == CPU_DAD5 || state == CPU_DAD6 || state == CPU_DAD7 |-> iDAD);
assert property (state == CPU_JMP0 || state == CPU_JMP1 |-> iJMP || iJMPcc);
assert property (state == CPU_INXDCX0 || state == CPU_INXDCX1 || state == CPU_INXDCX2 || state == CPU_INXDCX3 |-> iINX || iDCX);
assert property (state == CPU_MOV |-> iMOV);
assert property (state == CPU_DIRECT0 || state == CPU_DIRECT1 || state == CPU_DIRECT2 |-> iLDA || iSTA || iLHLD || iSHLD);
assert property (state == CPU_DIRECT3 |-> iLHLD || iSHLD);
assert property (state == CPU_MVI0 || state == CPU_MVI1 |-> iMVI);
assert property (state == CPU_LXI0 || state == CPU_LXI1 |-> iLXI);
assert property (state == CPU_LDAXSTAX0 || state == CPU_LDAXSTAX1 || state == CPU_LDAXSTAX2 |-> iLDAX || iSTAX);
assert property (state == CPU_SPHL0 || state == CPU_SPHL1 |-> iSPHL);
assert property (state == CPU_IO0 || state == CPU_IO1 |-> iIN || iOUT);
assert property (state == CPU_CALL0 || state == CPU_CALL1 || state == CPU_CALL2 || state == CPU_CALL3 |-> iCALL || iCALLcc || iRST);
assert property (state == CPU_XCHG0 || state == CPU_XCHG1 || state == CPU_XCHG2 || state == CPU_XCHG3 || state == CPU_XCHG4 || state == CPU_XCHG5 |-> iXCHG || iXTHL);
assert property (state == CPU_EIDI |-> iEI || iDI);
exactly_one_decode: assert property ($onehot({
iMOV, iALU, iALUI, iMVI, iJMP, iPUSH, iPOP, iHALT, iLXI, iLDA, iSTA, iLHLD, iSHLD,
iUNARY, iCALL, iCALLcc, iRST, iRET, iRETcc, iJMPcc, iPCHL, iSPHL, iINR, iDCR,
iINX, iDCX, iLDAX, iSTAX, iXCHG, iXTHL, iDAD, iIN, iOUT, iNOP, iEI, iDI,
undefined}));
inx_sp_dcx_sp: assert property ((!iINX_SP || iINX) && (!iDCX_SP || iDCX));
no_missing_cases: assert property (!missing_decoder_case);
`ifdef LIVENESS
assume property (memory_read |-> ##[1:3] memory_done);
assume property (memory_write |-> ##[1:3] memory_done);
assert property (state != CPU_FETCH |-> ##[1:40] state == CPU_FETCH || state == CPU_HALT || state == CPU_DEBUG0 || state == CPU_DEBUG1);
assert property (debug_req && !cpu_in_debug |-> ##[1:40] cpu_in_debug);
`endif
`endif
endmodule
|
module sync(
input wire clk,
input wire rst_n,
input wire in,
output wire out
);
(* keep *) reg a;
(* keep *) reg b;
assign out = b;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
a <= 1'b0;
b <= 1'b0;
end else begin
a <= in;
b <= a;
end
end
endmodule
|
tt06-finale_0049
|
tt06-finale
|
aiju-tt06-aiju-8080
|
task_tt_um_aiju_8080
|
tt_um_aiju_8080
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_aiju_8080 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module sync(
input wire clk,
input wire rst_n,
input wire in,
output wire out
);
(* keep *) reg a;
(* keep *) reg b;
assign out = b;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
a <= 1'b0;
b <= 1'b0;
end else begin
a <= in;
b <= a;
end
end
endmodule
`default_nettype none
module bus_if(
input wire clk,
input wire rst_n,
input wire bus_handshake_ack,
output reg bus_handshake_req,
output reg [1:0] bus_state,
input wire [7:0] bus_data_in,
output reg [7:0] bus_data_out,
output reg bus_output_enable,
output wire bus_io,
input wire memory_read,
input wire memory_write,
input wire [15:0] memory_addr,
input wire memory_io,
input wire [7:0] memory_wdata,
output reg [7:0] memory_rdata,
output reg memory_done
);
reg [1:0] memory_state;
localparam MEMORY_IDLE = 0;
localparam MEMORY_ADDR_LOW = 1;
localparam MEMORY_ADDR_HIGH = 2;
localparam MEMORY_DATA = 3;
wire want_output_enable = memory_state != MEMORY_IDLE && (memory_state != MEMORY_DATA || memory_write);
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
memory_state <= MEMORY_IDLE;
memory_rdata <= 8'bx;
bus_handshake_req <= 1'b0;
memory_done <= 1'b0;
bus_output_enable <= 1'b0;
end else begin
memory_done <= 1'b0;
if(memory_state == MEMORY_IDLE && !memory_done && (memory_read || memory_write))
memory_state <= MEMORY_ADDR_LOW;
if(memory_state != MEMORY_IDLE && !bus_handshake_ack)
bus_output_enable <= want_output_enable;
if(memory_state != MEMORY_IDLE && !bus_handshake_ack && want_output_enable == bus_output_enable)
bus_handshake_req <= 1'b1;
if(bus_handshake_req && bus_handshake_ack) begin
bus_handshake_req <= 1'b0;
case(memory_state)
MEMORY_ADDR_LOW:
memory_state <= MEMORY_ADDR_HIGH;
MEMORY_ADDR_HIGH: begin
memory_state <= MEMORY_DATA;
if(memory_read)
bus_output_enable <= 1'b0;
end
MEMORY_DATA: begin
memory_state <= MEMORY_IDLE;
bus_output_enable <= 1'b0;
memory_done <= 1'b1;
if(memory_read)
memory_rdata <= bus_data_in;
end
endcase
end
end
end
assign bus_io = memory_io;
always @(*) begin
bus_data_out = 8'bx;
bus_state = 2'b00;
case(memory_state)
MEMORY_ADDR_LOW: begin
bus_data_out = memory_addr[7:0];
bus_state = 2'b00;
end
MEMORY_ADDR_HIGH: begin
bus_data_out = memory_addr[15:8];
bus_state = 2'b01;
end
MEMORY_DATA: begin
bus_state = {1'b1, memory_write};
if(memory_write) begin
bus_data_out = memory_wdata;
end
end
endcase
end
`ifdef FORMAL
initial begin
memory_state = MEMORY_IDLE;
memory_done = 1'b0;
bus_handshake_req = 1'b0;
bus_output_enable = 1'b0;
end
default clocking
@(posedge clk);
endclocking
default disable iff(!rst_n);
assume property (!(memory_read && memory_write));
assume property (memory_read && !memory_done |=> memory_read);
assume property (memory_write && !memory_done |=> memory_write);
assume property ($rose(bus_handshake_ack) |-> $past(bus_handshake_req));
assume property ($fell(bus_handshake_ack) |-> $past(!bus_handshake_req));
assume property ((memory_read && $past(memory_read)) || (memory_write && $past(memory_write)) |-> $stable(memory_addr) && $stable(memory_wdata));
state_invariant: assert property (memory_state != MEMORY_IDLE |-> (memory_read || memory_write) && !memory_done);
done_one_cycle: assert property (memory_done |=> !memory_done);
done_only_if_active: assert property (memory_done |-> memory_read || memory_write);
req_only_when_active: assert property (memory_state == MEMORY_IDLE |-> !bus_handshake_req);
req_when_no_ack: assert property ($rose(bus_handshake_req) |-> !bus_handshake_ack);
req_falls_when_ack: assert property (!$initstate && $fell(bus_handshake_req) |-> bus_handshake_ack);
stable_bus_state: assert property (bus_handshake_req |-> $stable(bus_state));
no_bus_contention: assert property (bus_handshake_req && bus_state == 2'b10 |-> !bus_output_enable && !$past(bus_output_enable));
stable_bus_data_out: assert property (bus_handshake_req && bus_state != 2'b10 |-> bus_output_enable && $past(bus_output_enable) && $stable(bus_data_out));
latch_bus_data: assert property (memory_done && memory_read |-> memory_rdata == $past(bus_data_in));
stable_bus_output: assert property ((bus_handshake_req || bus_handshake_ack) && !bus_output_enable |=> !bus_output_enable);
stable_bus_output2: assert property (bus_handshake_req && !bus_output_enable |-> !$past(bus_output_enable));
`ifdef LIVENESS
assume property(bus_handshake_req |-> ##[1:5] bus_handshake_ack);
assume property(!bus_handshake_req |-> ##[1:5] !bus_handshake_ack);
liveness: assert property ((memory_read || memory_write) && !memory_done |-> ##[1:40] memory_done);
`endif
`endif
endmodule
`default_nettype none
module cpu(
input wire clk,
input wire rst_n,
output reg memory_read,
output reg memory_write,
output reg [15:0] memory_addr,
output reg memory_io,
output reg [7:0] memory_wdata,
input wire [7:0] memory_rdata,
input wire memory_done,
input wire debug_req,
input wire int_req,
output wire cpu_fetch,
output wire cpu_halted,
output wire cpu_in_debug,
output wire cpu_int_ack
);
reg [15:0] AL;
reg [15:0] rPC;
reg [15:0] rSP;
reg [7:0] rA, rB, rC, rD, rE, rH, rL;
reg [7:0] rPSR;
reg [7:0] rIR;
reg [5:0] state;
localparam CPU_FETCH = 0;
localparam CPU_DECODE = 1;
localparam CPU_MVI0 = 2;
localparam CPU_MVI1 = 3;
localparam CPU_ALU0 = 4;
localparam CPU_ALU1 = 5;
localparam CPU_MOV = 6;
localparam CPU_JMP0 = 7;
localparam CPU_JMP1 = 8;
localparam CPU_PUSH0 = 9;
localparam CPU_PUSH1 = 10;
localparam CPU_PUSH2 = 11;
localparam CPU_POP0 = 12;
localparam CPU_POP1 = 13;
localparam CPU_HALT = 14;
localparam CPU_LXI0 = 15;
localparam CPU_LXI1 = 16;
localparam CPU_DIRECT0 = 17;
localparam CPU_DIRECT1 = 18;
localparam CPU_DIRECT2 = 19;
localparam CPU_DIRECT3 = 20;
localparam CPU_UNARY = 21;
localparam CPU_CALL0 = 22;
localparam CPU_CALL1 = 23;
localparam CPU_CALL2 = 24;
localparam CPU_CALL3 = 25;
localparam CPU_RET0 = 26;
localparam CPU_RET1 = 27;
localparam CPU_PCHL0 = 28;
localparam CPU_PCHL1 = 29;
localparam CPU_PCHL2 = 30;
localparam CPU_SPHL0 = 31;
localparam CPU_SPHL1 = 32;
localparam CPU_INRDCR0 = 33;
localparam CPU_INRDCR1 = 34;
localparam CPU_INXDCX0 = 35;
localparam CPU_INXDCX1 = 36;
localparam CPU_INXDCX2 = 37;
localparam CPU_INXDCX3 = 38;
localparam CPU_LDAXSTAX0 = 39;
localparam CPU_LDAXSTAX1 = 40;
localparam CPU_LDAXSTAX2 = 41;
localparam CPU_XCHG0 = 42;
localparam CPU_XCHG1 = 43;
localparam CPU_XCHG2 = 44;
localparam CPU_XCHG3 = 45;
localparam CPU_XCHG4 = 46;
localparam CPU_XCHG5 = 47;
localparam CPU_DAD0 = 48;
localparam CPU_DAD1 = 49;
localparam CPU_DAD2 = 50;
localparam CPU_DAD3 = 51;
localparam CPU_DAD4 = 52;
localparam CPU_DAD5 = 53;
localparam CPU_DAD6 = 54;
localparam CPU_DAD7 = 55;
localparam CPU_IO0 = 56;
localparam CPU_IO1 = 57;
localparam CPU_EIDI = 58;
localparam CPU_DEBUG0 = 62;
localparam CPU_DEBUG1 = 63;
wire iMOV = rIR[7:6] == 1 && rIR != 8'b01110110;
wire iALU = rIR[7:6] == 2;
wire iALUI = (rIR & ~8'h38) == 8'b1100_0110;
wire iMVI = rIR[7:6] == 0 && rIR[2:0] == 3'b110;
wire iJMP = rIR == 8'b1100_0011;
wire iPUSH = (rIR & ~8'h30) == 8'b1100_0101;
wire iPOP = (rIR & ~8'h30) == 8'b1100_0001;
wire iHALT = rIR == 8'h76;
wire iLXI = (rIR & ~8'h30) == 8'b0000_0001;
wire iLDA = rIR == 8'h3A;
wire iSTA = rIR == 8'h32;
wire iLHLD = rIR == 8'h2A;
wire iSHLD = rIR == 8'h22;
wire iUNARY = (rIR & ~8'h38) == 8'b0000_0111;
wire iCALL = rIR == 8'hCD;
wire iCALLcc = (rIR & ~8'h38) == 8'b1100_0100;
wire iRST = (rIR & ~8'h38) == 8'b1100_0111;
wire iRET = rIR == 8'hC9;
wire iRETcc = (rIR & ~8'h38) == 8'b1100_0000;
wire iJMPcc = (rIR & ~8'h38) == 8'b1100_0010;
wire iPCHL = rIR == 8'hE9;
wire iSPHL = rIR == 8'hF9;
wire iINR = (rIR & ~8'h38) == 8'b0000_0100;
wire iDCR = (rIR & ~8'h38) == 8'b0000_0101;
wire iINX = (rIR & ~8'h30) == 8'b0000_0011;
wire iDCX = (rIR & ~8'h30) == 8'b0000_1011;
wire iINX_SP = rIR == 8'b0011_0011;
wire iDCX_SP = rIR == 8'b0011_1011;
wire iLDAX = (rIR & ~8'h10) == 8'b0000_1010;
wire iSTAX = (rIR & ~8'h10) == 8'b0000_0010;
wire iXCHG = rIR == 8'b1110_1011;
wire iXTHL = rIR == 8'b1110_0011;
wire iDAD = (rIR & ~8'h30) == 8'b0000_1001;
wire iIN = rIR == 8'b1101_1011;
wire iOUT = rIR == 8'b1101_0011;
wire iNOP = rIR == 8'b0000_0000;
wire iEI = rIR == 8'b1111_1011;
wire iDI = rIR == 8'b1111_0011;
wire undefined =
(rIR & ~8'h38) == 8'b0000_0000 && !iNOP
|| rIR == 8'b1101_1001
|| (rIR & ~8'h30) == 8'b1100_1101 && !iCALL
|| rIR == 8'b1100_1011;
wire memory_operand =
iMOV && (rIR[5:3] == 3'b110 || rIR[2:0] == 3'b110)
|| iALU && rIR[2:0] == 3'b110
|| (iINR || iDCR || iMVI) && rIR[5:3] == 3'b110;
wire dbgEXIT = rIR[6];
wire dbgREAD = !rIR[7] && !dbgEXIT;
wire dbgWRITE = rIR[7];
reg condition;
always @(*) begin
case(rIR[5:3])
3'b000: condition = !rPSR[6];
3'b001: condition = rPSR[6];
3'b010: condition = !rPSR[0];
3'b011: condition = rPSR[0];
3'b100: condition = !rPSR[2];
3'b101: condition = rPSR[2];
3'b110: condition = !rPSR[7];
3'b111: condition = rPSR[7];
endcase
end
reg int_enabled;
reg int_latch;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
int_enabled <= 1'b0;
int_latch <= 1'b0;
end else begin
if(state == CPU_EIDI) begin
if(iEI)
int_enabled <= 1'b1;
if(iDI)
int_enabled <= 1'b0;
end
if(cpu_int_ack)
int_enabled <= 1'b0;
if(cycle_done)
int_latch <= int_req && int_enabled && !(state == CPU_EIDI && iDI || cpu_int_ack);
end
end
assign cpu_int_ack = state == CPU_FETCH && int_latch;
reg [5:0] decode_goto;
reg missing_decoder_case;
always @(*) begin
decode_goto = CPU_FETCH;
missing_decoder_case = 1'b0;
case(1'b1)
iMOV: decode_goto = CPU_MOV;
iALU, iALUI: decode_goto = CPU_ALU0;
iMVI: decode_goto = CPU_MVI0;
iJMP, iJMPcc: decode_goto = CPU_JMP0;
iPUSH: decode_goto = CPU_PUSH0;
iPOP: decode_goto = CPU_POP0;
iHALT: decode_goto = CPU_HALT;
iLXI: decode_goto = CPU_LXI0;
iLDA, iSTA, iLHLD, iSHLD: decode_goto = CPU_DIRECT0;
iUNARY: decode_goto = CPU_UNARY;
iCALL, iCALLcc, iRST: decode_goto = CPU_CALL0;
iRET: decode_goto = CPU_RET0;
iRETcc: decode_goto = condition ? CPU_RET0 : CPU_FETCH;
iPCHL: decode_goto = CPU_PCHL0;
iSPHL: decode_goto = CPU_SPHL0;
iINR, iDCR: decode_goto = CPU_INRDCR0;
iINX, iDCX: decode_goto = CPU_INXDCX0;
iLDAX, iSTAX: decode_goto = CPU_LDAXSTAX0;
iXCHG, iXTHL: decode_goto = CPU_XCHG0;
iDAD: decode_goto = CPU_DAD0;
iIN, iOUT: decode_goto = CPU_IO0;
iNOP, undefined: decode_goto = CPU_FETCH;
iEI, iDI: decode_goto = CPU_EIDI;
default: missing_decoder_case = 1'b1;
endcase
end
always @(posedge clk) begin
if(state == CPU_DECODE && undefined)
$display("undefined opcode %x", rIR);
end
reg [7:0] aluIn;
reg [7:0] aluOut;
reg alu_carry_out, alu_aux_carry_out;
reg [4:0] alu_op;
reg [7:0] set_flags;
localparam ALU_ADD = 0;
localparam ALU_ADC = 1;
localparam ALU_SUB = 2;
localparam ALU_SBB = 3;
localparam ALU_AND = 4;
localparam ALU_XOR = 5;
localparam ALU_OR = 6;
localparam ALU_CMP = 7;
localparam ALU_RLC = 8;
localparam ALU_RRC = 9;
localparam ALU_RAL = 10;
localparam ALU_RAR = 11;
localparam ALU_DAA = 12;
localparam ALU_CMA = 13;
localparam ALU_STC = 14;
localparam ALU_CMC = 15;
localparam ALU_INC = 16;
localparam ALU_DEC = 17;
localparam ALU_NOP = 31;
reg [7:0] daa_operand;
always @(*) begin
daa_operand = 8'h00;
if(rA[3:0] > 9 || rPSR[4])
daa_operand[3:0] = 6;
if(rA >= 8'h9a || rPSR[0])
daa_operand[7:4] = 6;
end
always @(*) begin
alu_carry_out = 1'b0;
alu_aux_carry_out = 1'b0;
aluOut = aluIn;
case(alu_op)
ALU_ADD, ALU_ADC: begin
{alu_carry_out, aluOut} = rA + aluIn + (rPSR[0] & (alu_op == ALU_ADC));
alu_aux_carry_out = (((rA & 15) + (aluIn & 15) + (rPSR[0] & (alu_op == ALU_ADC))) & 16) != 0;
end
ALU_SUB, ALU_SBB, ALU_CMP: begin
{alu_carry_out, aluOut} = rA - aluIn - (rPSR[0] & (alu_op == ALU_SBB));
alu_aux_carry_out = (((rA & 15) - (aluIn & 15) - (rPSR[0] & (alu_op == ALU_SBB))) & 16) == 0;
end
ALU_AND: begin
aluOut = rA & aluIn;
alu_aux_carry_out = rA[3] | aluIn[3];
end
ALU_OR:
aluOut = rA | aluIn;
ALU_XOR:
aluOut = rA ^ aluIn;
ALU_RLC: begin
aluOut = {rA[6:0], rA[7]};
alu_carry_out = rA[7];
end
ALU_RRC: begin
aluOut = {rA[0], rA[7:1]};
alu_carry_out = rA[0];
end
ALU_RAL: begin
{alu_carry_out, aluOut} = {rA, rPSR[0]};
end
ALU_RAR: begin
{aluOut, alu_carry_out} = {rPSR[0], rA};
end
ALU_CMA: aluOut = ~rA;
ALU_CMC: begin
aluOut = rA;
alu_carry_out = ~rPSR[0];
end
ALU_STC: begin
aluOut = rA;
alu_carry_out = 1'b1;
end
ALU_DAA: begin
{alu_carry_out, aluOut} = (rA + daa_operand) | (rPSR[0] ? 9'h100 : 9'h000);
alu_aux_carry_out = (((rA & 15) + (daa_operand & 15)) & 16) != 0;
end
ALU_INC: begin
{alu_carry_out, aluOut} = aluIn + 1;
alu_aux_carry_out = (aluIn & 15) == 15;
end
ALU_DEC: begin
{alu_carry_out, aluOut} = aluIn - 1;
alu_aux_carry_out = (aluIn & 15) != 0;
end
endcase
end
wire alu_zero = aluOut == 0;
wire alu_parity = ~^aluOut;
wire alu_sign = aluOut[7];
wire [7:0] alu_flags = {alu_sign, alu_zero, 1'b0, alu_aux_carry_out, 1'b0, alu_parity, 1'b1, alu_carry_out};
wire cycle_done = !memory_read && !memory_write || memory_done;
wire pc_increment =
state == CPU_FETCH && !debug_req && !cpu_int_ack
|| state == CPU_MVI0 || state == CPU_JMP0 || state == CPU_JMP1 && iJMPcc && !condition
|| state == CPU_ALU0 && iALUI
|| state == CPU_LXI0 || state == CPU_LXI1
|| state == CPU_DIRECT0 || state == CPU_DIRECT1
|| (state == CPU_CALL0 || state == CPU_CALL1) && !iRST
|| state == CPU_IO0;
wire al_increment = state == CPU_DIRECT2;
wire sp_decrement =
state == CPU_PUSH0 || state == CPU_PUSH1
|| state == CPU_CALL1 && (!iCALLcc || condition)
|| state == CPU_CALL2
|| state == CPU_INXDCX0 && iDCX_SP
|| state == CPU_XCHG5 && iXTHL;
wire sp_increment =
state == CPU_POP0 || state == CPU_POP1
|| state == CPU_RET0 || state == CPU_RET1
|| state == CPU_INXDCX0 && iINX_SP
|| state == CPU_XCHG2 && iXTHL;
wire pc_jmp =
state == CPU_JMP1 && (!iJMPcc || condition)
|| state == CPU_RET1;
wire pc_jmp_al = state == CPU_CALL3 && !iRST || state == CPU_PCHL2;
wire pc_rst_jmp = state == CPU_CALL3 && iRST;
wire ir_load = state == CPU_FETCH || state == CPU_DEBUG0;
assign cpu_fetch = state == CPU_FETCH;
assign cpu_halted = state == CPU_HALT;
assign cpu_in_debug = state == CPU_DEBUG0 || state == CPU_DEBUG1;
reg [4:0] db_dst;
reg [4:0] db_src;
localparam DB_ALL = 5'b00010;
localparam DB_ALH = 5'b00011;
localparam DB_SPL = 5'b00100;
localparam DB_SPH = 5'b00101;
localparam DB_PSR = 5'b00110;
localparam DB_ALU = 5'b00111;
localparam DB_B = 5'b01000;
localparam DB_C = 5'b01001;
localparam DB_D = 5'b01010;
localparam DB_E = 5'b01011;
localparam DB_H = 5'b01100;
localparam DB_L = 5'b01101;
localparam DB_MEM = 5'b01110;
localparam DB_A = 5'b01111;
localparam DB_PCL = 5'b10000;
localparam DB_PCH = 5'b10001;
reg [7:0] DB;
always @(*) begin
DB = 8'bx;
case(db_src)
DB_PSR: DB = rPSR;
DB_ALU: DB = aluOut;
DB_B: DB = rB;
DB_C: DB = rC;
DB_D: DB = rD;
DB_E: DB = rE;
DB_H: DB = rH;
DB_L: DB = rL;
DB_MEM: DB = memory_rdata;
DB_A: DB = rA;
DB_SPL: DB = rSP[7:0];
DB_SPH: DB = rSP[15:8];
DB_PCL: DB = rPC[7:0];
DB_PCH: DB = rPC[15:8];
DB_ALL: DB = AL[7:0];
DB_ALH: DB = AL[15:8];
endcase
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
rPC <= 0;
rIR <= 0;
rSP <= 0;
AL <= 0;
end else begin
if(cycle_done) begin
if(pc_increment)
rPC <= rPC + 1;
if(pc_jmp)
rPC <= {memory_rdata, aluIn};
if(pc_jmp_al)
rPC <= AL;
if(pc_rst_jmp)
rPC <= rIR & 8'h38;
if(ir_load)
rIR <= memory_rdata;
if(db_dst == DB_SPH)
rSP[15:8] <= DB;
if(db_dst == DB_SPL)
rSP[7:0] <= DB;
if(sp_increment)
rSP <= rSP + 1;
if(sp_decrement)
rSP <= rSP - 1;
if(db_dst == DB_ALH)
AL[15:8] <= DB;
if(db_dst == DB_ALL)
AL[7:0] <= DB;
if(al_increment)
AL <= AL + 1;
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
rPSR <= 2;
end else begin
if(cycle_done) begin
if(db_dst == DB_PSR)
rPSR <= DB & ~8'h28 | 2;
else
rPSR <= (rPSR & ~set_flags | alu_flags & set_flags) & ~8'h28 | 2;
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
{rA, rB, rC, rD, rE, rH, rL} <= 0;
aluIn <= 0;
end else begin
if(cycle_done) begin
case(db_dst)
DB_ALU: aluIn <= DB;
DB_B: rB <= DB;
DB_C: rC <= DB;
DB_D: rD <= DB;
DB_E: rE <= DB;
DB_H: rH <= DB;
DB_L: rL <= DB;
DB_A: rA <= DB;
endcase
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
state <= CPU_FETCH;
end else begin
if(cycle_done) begin
case(state)
CPU_FETCH:
if(debug_req)
state <= CPU_DEBUG0;
else
state <= CPU_DECODE;
CPU_DECODE:
state <= decode_goto;
CPU_HALT:
if(debug_req)
state <= CPU_DEBUG0;
else if(int_latch)
state <= CPU_FETCH;
CPU_MVI0:
state <= memory_operand ? CPU_MVI1 : CPU_FETCH;
CPU_MVI1:
state <= CPU_FETCH;
CPU_MOV:
state <= CPU_FETCH;
CPU_ALU0:
state <= CPU_ALU1;
CPU_ALU1:
state <= CPU_FETCH;
CPU_JMP0:
state <= CPU_JMP1;
CPU_JMP1:
state <= CPU_FETCH;
CPU_PUSH0:
state <= CPU_PUSH1;
CPU_PUSH1:
state <= CPU_PUSH2;
CPU_PUSH2:
state <= CPU_FETCH;
CPU_POP0:
state <= CPU_POP1;
CPU_POP1:
state <= CPU_FETCH;
CPU_LXI0:
state <= CPU_LXI1;
CPU_LXI1:
state <= CPU_FETCH;
CPU_DIRECT0:
state <= CPU_DIRECT1;
CPU_DIRECT1:
state <= CPU_DIRECT2;
CPU_DIRECT2:
if(iLHLD || iSHLD)
state <= CPU_DIRECT3;
else
state <= CPU_FETCH;
CPU_DIRECT3:
state <= CPU_FETCH;
CPU_UNARY:
state <= CPU_FETCH;
CPU_CALL0:
state <= CPU_CALL1;
CPU_CALL1:
if(!iCALLcc || condition)
state <= CPU_CALL2;
else
state <= CPU_FETCH;
CPU_CALL2:
state <= CPU_CALL3;
CPU_CALL3:
state <= CPU_FETCH;
CPU_RET0:
state <= CPU_RET1;
CPU_RET1:
state <= CPU_FETCH;
CPU_PCHL0:
state <= CPU_PCHL1;
CPU_PCHL1:
state <= CPU_PCHL2;
CPU_PCHL2:
state <= CPU_FETCH;
CPU_SPHL0:
state <= CPU_SPHL1;
CPU_SPHL1:
state <= CPU_FETCH;
CPU_INRDCR0:
state <= CPU_INRDCR1;
CPU_INRDCR1:
state <= CPU_FETCH;
CPU_INXDCX0:
state <= iINX_SP || iDCX_SP ? CPU_FETCH : CPU_INXDCX1;
CPU_INXDCX1:
state <= alu_carry_out ? CPU_INXDCX2 : CPU_FETCH;
CPU_INXDCX2:
state <= CPU_INXDCX3;
CPU_INXDCX3:
state <= CPU_FETCH;
CPU_LDAXSTAX0:
state <= CPU_LDAXSTAX1;
CPU_LDAXSTAX1:
state <= CPU_LDAXSTAX2;
CPU_LDAXSTAX2:
state <= CPU_FETCH;
CPU_DEBUG0:
state <= CPU_DEBUG1;
CPU_DEBUG1:
if(dbgEXIT)
state <= CPU_FETCH;
else
state <= CPU_DEBUG0;
CPU_XCHG0:
state <= CPU_XCHG1;
CPU_XCHG1:
state <= CPU_XCHG2;
CPU_XCHG2:
state <= CPU_XCHG3;
CPU_XCHG3:
state <= CPU_XCHG4;
CPU_XCHG4:
state <= CPU_XCHG5;
CPU_XCHG5:
state <= CPU_FETCH;
CPU_DAD0:
state <= CPU_DAD1;
CPU_DAD1:
state <= CPU_DAD2;
CPU_DAD2:
state <= CPU_DAD3;
CPU_DAD3:
state <= CPU_DAD4;
CPU_DAD4:
state <= CPU_DAD5;
CPU_DAD5:
state <= CPU_DAD6;
CPU_DAD6:
state <= CPU_DAD7;
CPU_DAD7:
state <= CPU_FETCH;
CPU_IO0:
state <= CPU_IO1;
CPU_IO1:
state <= CPU_FETCH;
CPU_EIDI:
state <= CPU_FETCH;
`ifndef SYNTHESIS
default:
assert(0);
`endif
endcase
end
end
end
always @(*) begin
memory_addr = 16'bx;
memory_wdata = 8'bx;
memory_read = 1'b0;
memory_write = 1'b0;
memory_io = 1'b0;
case(state)
CPU_FETCH, CPU_MVI0, CPU_JMP0, CPU_JMP1, CPU_LXI0, CPU_LXI1, CPU_DIRECT0, CPU_DIRECT1, CPU_IO0: begin
memory_addr = rPC;
memory_read = 1'b1;
end
CPU_CALL0, CPU_CALL1: begin
memory_addr = rPC;
memory_read = !iRST;
end
CPU_MVI1: begin
memory_addr = {rH, rL};
memory_wdata = DB;
memory_write = 1'b1;
end
CPU_MOV: begin
memory_addr = {rH, rL};
if(rIR[5:3] == 6) begin
memory_wdata = DB;
memory_write = 1'b1;
end else if(rIR[2:0] == 6)
memory_read = 1'b1;
end
CPU_ALU0: begin
if(iALUI) begin
memory_addr = rPC;
memory_read = 1'b1;
end else if(memory_operand) begin
memory_addr = {rH, rL};
memory_read = 1'b1;
end
end
CPU_PUSH1, CPU_PUSH2: begin
memory_addr = rSP;
memory_wdata = DB;
memory_write = 1'b1;
end
CPU_POP0, CPU_POP1, CPU_RET0, CPU_RET1: begin
memory_addr = rSP;
memory_read = 1'b1;
end
CPU_DIRECT2, CPU_DIRECT3: begin
memory_addr = AL;
memory_read = iLDA || iLHLD;
memory_write = iSTA || iSHLD;
memory_wdata = DB;
end
CPU_CALL2, CPU_CALL3: begin
memory_addr = rSP;
memory_wdata = DB;
memory_write = 1'b1;
end
CPU_INRDCR0, CPU_INRDCR1: begin
if(memory_operand) begin
memory_addr = {rH, rL};
memory_wdata = DB;
memory_read = state == CPU_INRDCR0;
memory_write = state == CPU_INRDCR1;
end
end
CPU_LDAXSTAX2: begin
memory_addr = AL;
memory_read = iLDAX;
memory_write = iSTAX;
memory_wdata = DB;
end
CPU_XCHG1, CPU_XCHG4: begin
if(iXTHL) begin
memory_read = 1'b1;
memory_addr = rSP;
end
end
CPU_XCHG2, CPU_XCHG5: begin
if(iXTHL) begin
memory_write = 1'b1;
memory_wdata = DB;
memory_addr = rSP;
end
end
CPU_IO1: begin
memory_addr = {8'b0, AL[7:0]};
memory_wdata = DB;
memory_read = iIN;
memory_write = iOUT;
memory_io = 1'b1;
end
CPU_DEBUG0: begin
memory_addr = 16'hCAFE;
memory_read = 1'b1;
memory_io = 1'b1;
end
CPU_DEBUG1: begin
memory_io = 1'b1;
if(dbgREAD) begin
memory_addr = 16'hCAFF;
memory_write = 1'b1;
memory_wdata = DB;
end
if(dbgWRITE) begin
memory_addr = 16'hCAFF;
memory_read = 1'b1;
end
end
endcase
end
always @(*) begin
db_src = 4'b0000;
db_dst = 4'b0000;
alu_op = ALU_NOP;
set_flags = 0;
case(state)
CPU_MOV: begin
db_src = {1'b1, rIR[2:0]};
db_dst = {1'b1, rIR[5:3]};
end
CPU_MVI0: begin
db_src = DB_MEM;
db_dst = memory_operand ? DB_ALU : {1'b1, rIR[5:3]};
end
CPU_MVI1: begin
db_src = DB_ALU;
end
CPU_ALU0: begin
db_src = iALUI ? DB_MEM : {1'b1, rIR[2:0]};
db_dst = DB_ALU;
end
CPU_ALU1: begin
db_src = DB_ALU;
if(rIR[5:3] != 3'b111)
db_dst = DB_A;
alu_op = rIR[5:3];
set_flags = 8'hff;
end
CPU_JMP0, CPU_RET0: begin
db_src = DB_MEM;
db_dst = DB_ALU;
end
CPU_PUSH1, CPU_PUSH2: begin
if(rIR[5:4] == 3)
db_src = state == CPU_PUSH1 ? DB_A : DB_PSR;
else
db_src = {1'b1, rIR[5:4], state == CPU_PUSH2};
end
CPU_POP0, CPU_POP1: begin
db_src = DB_MEM;
if(rIR[5:4] == 3)
db_dst = state == CPU_POP1 ? DB_A : DB_PSR;
else
db_dst = {1'b1, rIR[5:4], state == CPU_POP0};
end
CPU_LXI0, CPU_LXI1: begin
db_src = DB_MEM;
if(rIR[5:4] == 3)
db_dst = state == CPU_LXI1 ? DB_SPH : DB_SPL;
else
db_dst = {1'b1, rIR[5:4], state != CPU_LXI1};
end
CPU_DIRECT0, CPU_DIRECT1: begin
db_src = DB_MEM;
db_dst = state == CPU_DIRECT1 ? DB_ALH : DB_ALL;
end
CPU_DIRECT2: begin
case(1'b1)
iSTA:
db_src = DB_A;
iLDA: begin
db_src = DB_MEM;
db_dst = DB_A;
end
iSHLD:
db_src = DB_L;
iLHLD: begin
db_src = DB_MEM;
db_dst = DB_L;
end
endcase
end
CPU_DIRECT3: begin
if(iSHLD)
db_src = DB_H;
else begin
db_src = DB_MEM;
db_dst = DB_H;
end
end
CPU_UNARY: begin
db_src = DB_ALU;
db_dst = DB_A;
alu_op = {1'b1, rIR[5:3]};
case(rIR[5:3])
4: set_flags = 8'hff;
5: set_flags = 0;
default: set_flags = 1;
endcase
end
CPU_CALL0: begin
db_src = DB_MEM;
db_dst = DB_ALL;
end
CPU_CALL1: begin
db_src = DB_MEM;
db_dst = DB_ALH;
end
CPU_CALL2:
db_src = DB_PCH;
CPU_CALL3:
db_src = DB_PCL;
CPU_PCHL0: begin
db_src = DB_L;
db_dst = DB_ALL;
end
CPU_PCHL1: begin
db_src = DB_H;
db_dst = DB_ALH;
end
CPU_SPHL0: begin
db_src = DB_L;
db_dst = DB_SPL;
end
CPU_SPHL1: begin
db_src = DB_H;
db_dst = DB_SPH;
end
CPU_INRDCR0: begin
db_src = {1'b1, rIR[5:3]};
db_dst = DB_ALU;
end
CPU_INRDCR1: begin
db_src = DB_ALU;
db_dst = {1'b1, rIR[5:3]};
alu_op = iDCR ? ALU_DEC : ALU_INC;
set_flags = 8'hfe;
end
CPU_INXDCX0, CPU_INXDCX2: begin
db_src = {1'b1, rIR[5:4], state == CPU_INXDCX0};
db_dst = DB_ALU;
end
CPU_INXDCX1, CPU_INXDCX3: begin
db_src = DB_ALU;
db_dst = {1'b1, rIR[5:4], state == CPU_INXDCX1};
alu_op = iDCX ? ALU_DEC : ALU_INC;
end
CPU_LDAXSTAX0, CPU_LDAXSTAX1: begin
db_src = {1'b1, 1'b0, rIR[4], state == CPU_LDAXSTAX0};
db_dst = state == CPU_LDAXSTAX1 ? DB_ALH : DB_ALL;
end
CPU_LDAXSTAX2: begin
if(iLDAX) begin
db_src = DB_MEM;
db_dst = DB_A;
end else
db_src = DB_A;
end
CPU_DEBUG1: begin
if(dbgREAD) begin
db_src = rIR[4:0];
end
if(dbgWRITE) begin
db_src = DB_MEM;
db_dst = rIR[4:0];
end
end
CPU_XCHG0: begin
db_src = DB_L;
db_dst = DB_ALL;
end
CPU_XCHG1: begin
db_src = iXTHL ? DB_MEM : DB_E;
db_dst = DB_L;
end
CPU_XCHG2: begin
db_src = DB_ALL;
if(iXCHG)
db_dst = DB_E;
end
CPU_XCHG3: begin
db_src = DB_H;
db_dst = DB_ALL;
end
CPU_XCHG4: begin
db_src = iXTHL ? DB_MEM : DB_D;
db_dst = DB_H;
end
CPU_XCHG5: begin
db_src = DB_ALL;
if(iXCHG)
db_dst = DB_D;
end
CPU_DAD0: begin
db_src = DB_A;
db_dst = DB_ALL;
end
CPU_DAD1: begin
db_src = DB_L;
db_dst = DB_A;
end
CPU_DAD2: begin
db_src = rIR[5:4] == 3 ? DB_SPL : {1'b1, rIR[5:4], 1'b1};
db_dst = DB_ALU;
end
CPU_DAD3: begin
alu_op = ALU_ADD;
db_src = DB_ALU;
db_dst = DB_L;
set_flags = 8'h01;
end
CPU_DAD4: begin
db_src = DB_H;
db_dst = DB_A;
end
CPU_DAD5: begin
db_src = rIR[5:4] == 3 ? DB_SPH : {1'b1, rIR[5:4], 1'b0};
db_dst = DB_ALU;
end
CPU_DAD6: begin
alu_op = ALU_ADC;
db_src = DB_ALU;
db_dst = DB_H;
set_flags = 8'h01;
end
CPU_DAD7: begin
db_src = DB_ALL;
db_dst = DB_A;
end
CPU_IO0: begin
db_src = DB_MEM;
db_dst = DB_ALL;
end
CPU_IO1: begin
if(iIN) begin
db_src = DB_MEM;
db_dst = DB_A;
end
if(iOUT)
db_src = DB_A;
end
endcase
end
`ifdef FORMAL
initial state = CPU_FETCH;
default clocking
@(posedge clk);
endclocking
default disable iff(!rst_n);
assume property (memory_done |=> !memory_done);
assume property (debug_req && !cpu_in_debug |=> debug_req);
read_until_done: assert property (memory_read && !memory_done |=> memory_read);
write_until_done: assert property (memory_write && !memory_done |=> memory_write);
not_read_and_write: assert property (!memory_read || !memory_write);
stable_memory_addr: assert property (!$initstate && (memory_read && $past(memory_read) || memory_write && $past(memory_write)) && !$past(memory_done) |-> $stable(memory_addr) && $stable(memory_io));
stable_memory_wdata: assert property (!$initstate && memory_write && $past(memory_write) && !$past(memory_done) && state != CPU_DEBUG1 |-> $stable(memory_wdata));
assert property (state == CPU_ALU0 || state == CPU_ALU1 |-> iALU || iALUI);
assert property (state == CPU_HALT |-> iHALT);
assert property (state == CPU_POP0 || state == CPU_POP1 |-> iPOP);
assert property (state == CPU_PUSH0 || state == CPU_PUSH1 || state == CPU_PUSH2 |-> iPUSH);
assert property (state == CPU_PCHL0 || state == CPU_PCHL1 || state == CPU_PCHL2 |-> iPCHL);
assert property (state == CPU_RET0 || state == CPU_RET1 |-> iRET || iRETcc);
assert property (state == CPU_UNARY |-> iUNARY);
assert property (state == CPU_INRDCR0 || state == CPU_INRDCR1 |-> iINR || iDCR);
assert property (state == CPU_DAD0 || state == CPU_DAD1 || state == CPU_DAD2 || state == CPU_DAD3 || state == CPU_DAD4 || state == CPU_DAD5 || state == CPU_DAD6 || state == CPU_DAD7 |-> iDAD);
assert property (state == CPU_JMP0 || state == CPU_JMP1 |-> iJMP || iJMPcc);
assert property (state == CPU_INXDCX0 || state == CPU_INXDCX1 || state == CPU_INXDCX2 || state == CPU_INXDCX3 |-> iINX || iDCX);
assert property (state == CPU_MOV |-> iMOV);
assert property (state == CPU_DIRECT0 || state == CPU_DIRECT1 || state == CPU_DIRECT2 |-> iLDA || iSTA || iLHLD || iSHLD);
assert property (state == CPU_DIRECT3 |-> iLHLD || iSHLD);
assert property (state == CPU_MVI0 || state == CPU_MVI1 |-> iMVI);
assert property (state == CPU_LXI0 || state == CPU_LXI1 |-> iLXI);
assert property (state == CPU_LDAXSTAX0 || state == CPU_LDAXSTAX1 || state == CPU_LDAXSTAX2 |-> iLDAX || iSTAX);
assert property (state == CPU_SPHL0 || state == CPU_SPHL1 |-> iSPHL);
assert property (state == CPU_IO0 || state == CPU_IO1 |-> iIN || iOUT);
assert property (state == CPU_CALL0 || state == CPU_CALL1 || state == CPU_CALL2 || state == CPU_CALL3 |-> iCALL || iCALLcc || iRST);
assert property (state == CPU_XCHG0 || state == CPU_XCHG1 || state == CPU_XCHG2 || state == CPU_XCHG3 || state == CPU_XCHG4 || state == CPU_XCHG5 |-> iXCHG || iXTHL);
assert property (state == CPU_EIDI |-> iEI || iDI);
exactly_one_decode: assert property ($onehot({
iMOV, iALU, iALUI, iMVI, iJMP, iPUSH, iPOP, iHALT, iLXI, iLDA, iSTA, iLHLD, iSHLD,
iUNARY, iCALL, iCALLcc, iRST, iRET, iRETcc, iJMPcc, iPCHL, iSPHL, iINR, iDCR,
iINX, iDCX, iLDAX, iSTAX, iXCHG, iXTHL, iDAD, iIN, iOUT, iNOP, iEI, iDI,
undefined}));
inx_sp_dcx_sp: assert property ((!iINX_SP || iINX) && (!iDCX_SP || iDCX));
no_missing_cases: assert property (!missing_decoder_case);
`ifdef LIVENESS
assume property (memory_read |-> ##[1:3] memory_done);
assume property (memory_write |-> ##[1:3] memory_done);
assert property (state != CPU_FETCH |-> ##[1:40] state == CPU_FETCH || state == CPU_HALT || state == CPU_DEBUG0 || state == CPU_DEBUG1);
assert property (debug_req && !cpu_in_debug |-> ##[1:40] cpu_in_debug);
`endif
`endif
endmodule
|
module tt_um_aiju_8080 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] bus_data_out; // From bus_if_i of bus_if.v
wire bus_handshake_req; // From bus_if_i of bus_if.v
wire bus_io; // From bus_if_i of bus_if.v
wire bus_output_enable; // From bus_if_i of bus_if.v
wire [1:0] bus_state; // From bus_if_i of bus_if.v
wire cpu_fetch; // From cpu_i of cpu.v
wire cpu_halted; // From cpu_i of cpu.v
wire cpu_in_debug; // From cpu_i of cpu.v
wire cpu_int_ack; // From cpu_i of cpu.v
wire [15:0] memory_addr; // From cpu_i of cpu.v
wire memory_done; // From bus_if_i of bus_if.v
wire memory_io; // From cpu_i of cpu.v
wire [7:0] memory_rdata; // From bus_if_i of bus_if.v
wire memory_read; // From cpu_i of cpu.v
wire [7:0] memory_wdata; // From cpu_i of cpu.v
wire memory_write; // From cpu_i of cpu.v
// End of automatics
assign uo_out[0] = bus_handshake_req;
assign uo_out[1] = bus_state[0];
assign uo_out[2] = bus_state[1];
assign uo_out[3] = bus_io;
assign uo_out[4] = cpu_fetch;
assign uo_out[5] = cpu_in_debug;
assign uo_out[6] = cpu_halted;
assign uo_out[7] = cpu_int_ack;
wire ext_bus_handshake_ack = ui_in[0];
wire ext_debug_req = ui_in[1];
wire ext_int_req = ui_in[2];
wire bus_handshake_ack;
(*keep_hierarchy*) sync bus_handshake_ack_sync(
.clk(clk),
.rst_n(rst_n),
.in(ext_bus_handshake_ack),
.out(bus_handshake_ack)
);
wire debug_req;
(*keep_hierarchy*) sync debug_req_sync(
.clk(clk),
.rst_n(rst_n),
.in(ext_debug_req),
.out(debug_req)
);
wire int_req;
(*keep_hierarchy*) sync int_req_sync(
.clk(clk),
.rst_n(rst_n),
.in(ext_int_req),
.out(int_req)
);
wire [7:0] bus_data_in = uio_in;
assign uio_out = bus_data_out;
assign uio_oe = {8{bus_output_enable}};
bus_if bus_if_i(/*AUTOINST*/
// Outputs
.bus_handshake_req(bus_handshake_req),
.bus_state (bus_state[1:0]),
.bus_data_out (bus_data_out[7:0]),
.bus_output_enable(bus_output_enable),
.bus_io (bus_io),
.memory_rdata (memory_rdata[7:0]),
.memory_done (memory_done),
// Inputs
.clk (clk),
.rst_n (rst_n),
.bus_handshake_ack(bus_handshake_ack),
.bus_data_in (bus_data_in[7:0]),
.memory_read (memory_read),
.memory_write (memory_write),
.memory_addr (memory_addr[15:0]),
.memory_io (memory_io),
.memory_wdata (memory_wdata[7:0]));
cpu cpu_i(/*AUTOINST*/
// Outputs
.memory_read (memory_read),
.memory_write (memory_write),
.memory_addr (memory_addr[15:0]),
.memory_io (memory_io),
.memory_wdata (memory_wdata[7:0]),
.cpu_fetch (cpu_fetch),
.cpu_halted (cpu_halted),
.cpu_in_debug (cpu_in_debug),
.cpu_int_ack (cpu_int_ack),
// Inputs
.clk (clk),
.rst_n (rst_n),
.memory_rdata (memory_rdata[7:0]),
.memory_done (memory_done),
.debug_req (debug_req),
.int_req (int_req));
endmodule
|
tt06-finale_0050
|
tt06-finale
|
andrewtron3000-tt06-verilog-template
|
task_Counter
|
tt_um_andrewtron3000
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 andrewtron3000
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_andrewtron3000 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// Held in reset while ena is not set
wire reset_n;
assign reset_n = rst_n & ena;
assign uio_oe = 8'b00000000; // All bidirectional outputs disabled
assign uio_out = 0;
// Assign output
assign uo_out[0] = 0;
assign uo_out[1] = 0;
assign uo_out[2] = 0;
assign uo_out[3] = 0;
assign uo_out[4] = driver_sout; // uo_out[4] is UART TX
assign uo_out[5] = 0;
assign uo_out[6] = 0;
assign uo_out[7] = 0;
// ports of submodule driver
wire driver_sin, driver_sout;
assign driver_sin = 0;
wire startup_input_ready;
wire startup_input_enable;
wire operation_mode_ready;
wire operation_mode_enable;
// submodule rule_30_driver
mkRule30Driver rule_30_driver(.CLK(clk),
.RST_N(reset_n),
.operation_mode_arg(uio_in),
.EN_operation_mode(operation_mode_enable),
.RDY_operation_mode(operation_mode_ready),
.startup_value_v(ui_in),
.EN_startup_value(startup_input_enable),
.RDY_startup_value(startup_input_ready),
.txrx_SIN(driver_sin),
.txrx_SOUT(driver_sout));
assign startup_input_enable = startup_input_ready;
assign operation_mode_enable = operation_mode_ready;
endmodule
//
// Generated by Bluespec Compiler, version 2024.01-1-g4d953407 (build 4d953407)
//
// On Thu Apr 18 23:03:53 EDT 2024
//
//
// Ports:
// Name I/O size props
// RDY_operation_mode O 1
// RDY_startup_value O 1
// txrx_SOUT O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// operation_mode_arg I 8
// startup_value_v I 8
// txrx_SIN I 1 reg
// EN_operation_mode I 1
// EN_startup_value I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkRule30Driver(CLK,
RST_N,
operation_mode_arg,
EN_operation_mode,
RDY_operation_mode,
startup_value_v,
EN_startup_value,
RDY_startup_value,
txrx_SIN,
txrx_SOUT);
input CLK;
input RST_N;
// action method operation_mode
input [7 : 0] operation_mode_arg;
input EN_operation_mode;
output RDY_operation_mode;
// action method startup_value
input [7 : 0] startup_value_v;
input EN_startup_value;
output RDY_startup_value;
// action method txrx_sin
input txrx_SIN;
// value method txrx_sout
output txrx_SOUT;
// signals for module outputs
wire RDY_operation_mode, RDY_startup_value, txrx_SOUT;
// inlined wires
wire uart_fifoXmit_r_enq$whas,
uart_pwRecvCellCountReset$whas,
uart_pwRecvEnableBitCount$whas,
uart_pwRecvResetBitCount$whas,
uart_pwXmitCellCountReset$whas,
uart_pwXmitEnableBitCount$whas,
uart_pwXmitLoadBuffer$whas,
xmas_fsm_start_wire$whas,
xmas_fsm_state_set_pw$whas;
// register a
reg [7 : 0] a;
wire [7 : 0] a$D_IN;
wire a$EN;
// register op_mode
reg op_mode;
wire op_mode$D_IN, op_mode$EN;
// register transmit_state
reg [1 : 0] transmit_state;
wire [1 : 0] transmit_state$D_IN;
wire transmit_state$EN;
// register uart_rRecvBitCount
reg [3 : 0] uart_rRecvBitCount;
wire [3 : 0] uart_rRecvBitCount$D_IN;
wire uart_rRecvBitCount$EN;
// register uart_rRecvCellCount
reg [3 : 0] uart_rRecvCellCount;
wire [3 : 0] uart_rRecvCellCount$D_IN;
wire uart_rRecvCellCount$EN;
// register uart_rRecvData
reg uart_rRecvData;
wire uart_rRecvData$D_IN, uart_rRecvData$EN;
// register uart_rRecvState
reg [2 : 0] uart_rRecvState;
reg [2 : 0] uart_rRecvState$D_IN;
wire uart_rRecvState$EN;
// register uart_rXmitBitCount
reg [3 : 0] uart_rXmitBitCount;
wire [3 : 0] uart_rXmitBitCount$D_IN;
wire uart_rXmitBitCount$EN;
// register uart_rXmitCellCount
reg [3 : 0] uart_rXmitCellCount;
wire [3 : 0] uart_rXmitCellCount$D_IN;
wire uart_rXmitCellCount$EN;
// register uart_rXmitDataOut
reg uart_rXmitDataOut;
reg uart_rXmitDataOut$D_IN;
wire uart_rXmitDataOut$EN;
// register uart_rXmitState
reg [2 : 0] uart_rXmitState;
reg [2 : 0] uart_rXmitState$D_IN;
wire uart_rXmitState$EN;
// register uart_vrRecvBuffer_0
reg uart_vrRecvBuffer_0;
wire uart_vrRecvBuffer_0$D_IN, uart_vrRecvBuffer_0$EN;
// register uart_vrRecvBuffer_1
reg uart_vrRecvBuffer_1;
wire uart_vrRecvBuffer_1$D_IN, uart_vrRecvBuffer_1$EN;
// register uart_vrRecvBuffer_2
reg uart_vrRecvBuffer_2;
wire uart_vrRecvBuffer_2$D_IN, uart_vrRecvBuffer_2$EN;
// register uart_vrRecvBuffer_3
reg uart_vrRecvBuffer_3;
wire uart_vrRecvBuffer_3$D_IN, uart_vrRecvBuffer_3$EN;
// register uart_vrRecvBuffer_4
reg uart_vrRecvBuffer_4;
wire uart_vrRecvBuffer_4$D_IN, uart_vrRecvBuffer_4$EN;
// register uart_vrRecvBuffer_5
reg uart_vrRecvBuffer_5;
wire uart_vrRecvBuffer_5$D_IN, uart_vrRecvBuffer_5$EN;
// register uart_vrRecvBuffer_6
reg uart_vrRecvBuffer_6;
wire uart_vrRecvBuffer_6$D_IN, uart_vrRecvBuffer_6$EN;
// register uart_vrRecvBuffer_7
reg uart_vrRecvBuffer_7;
wire uart_vrRecvBuffer_7$D_IN, uart_vrRecvBuffer_7$EN;
// register uart_vrXmitBuffer_0
reg uart_vrXmitBuffer_0;
wire uart_vrXmitBuffer_0$D_IN, uart_vrXmitBuffer_0$EN;
// register uart_vrXmitBuffer_1
reg uart_vrXmitBuffer_1;
wire uart_vrXmitBuffer_1$D_IN, uart_vrXmitBuffer_1$EN;
// register uart_vrXmitBuffer_2
reg uart_vrXmitBuffer_2;
wire uart_vrXmitBuffer_2$D_IN, uart_vrXmitBuffer_2$EN;
// register uart_vrXmitBuffer_3
reg uart_vrXmitBuffer_3;
wire uart_vrXmitBuffer_3$D_IN, uart_vrXmitBuffer_3$EN;
// register uart_vrXmitBuffer_4
reg uart_vrXmitBuffer_4;
wire uart_vrXmitBuffer_4$D_IN, uart_vrXmitBuffer_4$EN;
// register uart_vrXmitBuffer_5
reg uart_vrXmitBuffer_5;
wire uart_vrXmitBuffer_5$D_IN, uart_vrXmitBuffer_5$EN;
// register uart_vrXmitBuffer_6
reg uart_vrXmitBuffer_6;
wire uart_vrXmitBuffer_6$D_IN, uart_vrXmitBuffer_6$EN;
// register uart_vrXmitBuffer_7
reg uart_vrXmitBuffer_7;
wire uart_vrXmitBuffer_7$D_IN, uart_vrXmitBuffer_7$EN;
// register xmas_fsm_start_reg
reg xmas_fsm_start_reg;
wire xmas_fsm_start_reg$D_IN, xmas_fsm_start_reg$EN;
// register xmas_fsm_start_reg_1
reg xmas_fsm_start_reg_1;
wire xmas_fsm_start_reg_1$D_IN, xmas_fsm_start_reg_1$EN;
// register xmas_fsm_state_fired
reg xmas_fsm_state_fired;
wire xmas_fsm_state_fired$D_IN, xmas_fsm_state_fired$EN;
// register xmas_fsm_state_mkFSMstate
reg [4 : 0] xmas_fsm_state_mkFSMstate;
reg [4 : 0] xmas_fsm_state_mkFSMstate$D_IN;
wire xmas_fsm_state_mkFSMstate$EN;
// ports of submodule rule30
wire [7 : 0] rule30$getResult, rule30$start_a;
wire rule30$EN_getResult,
rule30$EN_start,
rule30$RDY_getResult,
rule30$RDY_start;
// ports of submodule uart_baudGen_rBaudCounter
wire [15 : 0] uart_baudGen_rBaudCounter$DATA_A,
uart_baudGen_rBaudCounter$DATA_B,
uart_baudGen_rBaudCounter$DATA_C,
uart_baudGen_rBaudCounter$DATA_F,
uart_baudGen_rBaudCounter$Q_OUT;
wire uart_baudGen_rBaudCounter$ADDA,
uart_baudGen_rBaudCounter$ADDB,
uart_baudGen_rBaudCounter$SETC,
uart_baudGen_rBaudCounter$SETF;
// ports of submodule uart_baudGen_rBaudTickCounter
wire [2 : 0] uart_baudGen_rBaudTickCounter$DATA_A,
uart_baudGen_rBaudTickCounter$DATA_B,
uart_baudGen_rBaudTickCounter$DATA_C,
uart_baudGen_rBaudTickCounter$DATA_F,
uart_baudGen_rBaudTickCounter$Q_OUT;
wire uart_baudGen_rBaudTickCounter$ADDA,
uart_baudGen_rBaudTickCounter$ADDB,
uart_baudGen_rBaudTickCounter$SETC,
uart_baudGen_rBaudTickCounter$SETF;
// ports of submodule uart_fifoRecv
wire [7 : 0] uart_fifoRecv$D_IN;
wire uart_fifoRecv$CLR,
uart_fifoRecv$DEQ,
uart_fifoRecv$EMPTY_N,
uart_fifoRecv$ENQ;
// ports of submodule uart_fifoXmit
reg [7 : 0] uart_fifoXmit$D_IN;
wire [7 : 0] uart_fifoXmit$D_OUT;
wire uart_fifoXmit$CLR,
uart_fifoXmit$DEQ,
uart_fifoXmit$EMPTY_N,
uart_fifoXmit$ENQ,
uart_fifoXmit$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_compute,
CAN_FIRE_RL_dump_rx,
CAN_FIRE_RL_get_result,
CAN_FIRE_RL_uart_baudGen_assert_2x_baud_tick,
CAN_FIRE_RL_uart_baudGen_baud_count_wire,
CAN_FIRE_RL_uart_baudGen_baud_tick_count_wire,
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x,
CAN_FIRE_RL_uart_baud_generator_clock_enable,
CAN_FIRE_RL_uart_fifoRecv__updateLevelCounter,
CAN_FIRE_RL_uart_fifoXmit__updateLevelCounter,
CAN_FIRE_RL_uart_receive_bit_cell_time_counter,
CAN_FIRE_RL_uart_receive_bit_counter,
CAN_FIRE_RL_uart_receive_buffer_shift,
CAN_FIRE_RL_uart_receive_find_center_of_bit_cell,
CAN_FIRE_RL_uart_receive_parity_bit,
CAN_FIRE_RL_uart_receive_sample_pin,
CAN_FIRE_RL_uart_receive_stop_first_bit,
CAN_FIRE_RL_uart_receive_stop_last_bit,
CAN_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample,
CAN_FIRE_RL_uart_receive_wait_for_start_bit,
CAN_FIRE_RL_uart_transmit_bit_cell_time_counter,
CAN_FIRE_RL_uart_transmit_bit_counter,
CAN_FIRE_RL_uart_transmit_buffer_load,
CAN_FIRE_RL_uart_transmit_buffer_shift,
CAN_FIRE_RL_uart_transmit_send_parity_bit,
CAN_FIRE_RL_uart_transmit_send_start_bit,
CAN_FIRE_RL_uart_transmit_send_stop_bit,
CAN_FIRE_RL_uart_transmit_send_stop_bit1_5,
CAN_FIRE_RL_uart_transmit_send_stop_bit2,
CAN_FIRE_RL_uart_transmit_shift_next_bit,
CAN_FIRE_RL_uart_transmit_wait_1_bit_cell_time,
CAN_FIRE_RL_uart_transmit_wait_for_start_command,
CAN_FIRE_RL_xmas_fsm_action_l42c32,
CAN_FIRE_RL_xmas_fsm_action_l43c32,
CAN_FIRE_RL_xmas_fsm_action_l44c32,
CAN_FIRE_RL_xmas_fsm_action_l45c32,
CAN_FIRE_RL_xmas_fsm_action_l46c32,
CAN_FIRE_RL_xmas_fsm_action_l47c32,
CAN_FIRE_RL_xmas_fsm_action_l48c32,
CAN_FIRE_RL_xmas_fsm_action_l49c32,
CAN_FIRE_RL_xmas_fsm_action_l50c32,
CAN_FIRE_RL_xmas_fsm_action_l51c32,
CAN_FIRE_RL_xmas_fsm_action_l52c32,
CAN_FIRE_RL_xmas_fsm_action_l53c32,
CAN_FIRE_RL_xmas_fsm_action_l54c32,
CAN_FIRE_RL_xmas_fsm_action_l55c32,
CAN_FIRE_RL_xmas_fsm_action_l56c32,
CAN_FIRE_RL_xmas_fsm_action_l57c32,
CAN_FIRE_RL_xmas_fsm_action_l58c32,
CAN_FIRE_RL_xmas_fsm_action_l59c32,
CAN_FIRE_RL_xmas_fsm_action_l60c32,
CAN_FIRE_RL_xmas_fsm_action_l61c32,
CAN_FIRE_RL_xmas_fsm_action_l62c32,
CAN_FIRE_RL_xmas_fsm_action_l63c32,
CAN_FIRE_RL_xmas_fsm_action_l64c32,
CAN_FIRE_RL_xmas_fsm_action_l65c32,
CAN_FIRE_RL_xmas_fsm_action_l66c32,
CAN_FIRE_RL_xmas_fsm_fsm_start,
CAN_FIRE_RL_xmas_fsm_idle_l40c27,
CAN_FIRE_RL_xmas_fsm_idle_l40c27_1,
CAN_FIRE_RL_xmas_fsm_restart,
CAN_FIRE_RL_xmas_fsm_start_reg__dreg_update,
CAN_FIRE_RL_xmas_fsm_state_every,
CAN_FIRE_RL_xmas_fsm_state_fired__dreg_update,
CAN_FIRE_RL_xmas_fsm_state_handle_abort,
CAN_FIRE___me_check_34,
CAN_FIRE___me_check_35,
CAN_FIRE___me_check_36,
CAN_FIRE___me_check_37,
CAN_FIRE___me_check_38,
CAN_FIRE___me_check_39,
CAN_FIRE___me_check_40,
CAN_FIRE___me_check_41,
CAN_FIRE___me_check_42,
CAN_FIRE___me_check_43,
CAN_FIRE___me_check_44,
CAN_FIRE___me_check_45,
CAN_FIRE___me_check_46,
CAN_FIRE___me_check_47,
CAN_FIRE___me_check_48,
CAN_FIRE___me_check_49,
CAN_FIRE___me_check_50,
CAN_FIRE___me_check_51,
CAN_FIRE___me_check_52,
CAN_FIRE___me_check_53,
CAN_FIRE___me_check_54,
CAN_FIRE___me_check_55,
CAN_FIRE___me_check_56,
CAN_FIRE___me_check_57,
CAN_FIRE_operation_mode,
CAN_FIRE_startup_value,
CAN_FIRE_txrx_sin,
WILL_FIRE_RL_compute,
WILL_FIRE_RL_dump_rx,
WILL_FIRE_RL_get_result,
WILL_FIRE_RL_uart_baudGen_assert_2x_baud_tick,
WILL_FIRE_RL_uart_baudGen_baud_count_wire,
WILL_FIRE_RL_uart_baudGen_baud_tick_count_wire,
WILL_FIRE_RL_uart_baudGen_count_baudtick_16x,
WILL_FIRE_RL_uart_baud_generator_clock_enable,
WILL_FIRE_RL_uart_fifoRecv__updateLevelCounter,
WILL_FIRE_RL_uart_fifoXmit__updateLevelCounter,
WILL_FIRE_RL_uart_receive_bit_cell_time_counter,
WILL_FIRE_RL_uart_receive_bit_counter,
WILL_FIRE_RL_uart_receive_buffer_shift,
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell,
WILL_FIRE_RL_uart_receive_parity_bit,
WILL_FIRE_RL_uart_receive_sample_pin,
WILL_FIRE_RL_uart_receive_stop_first_bit,
WILL_FIRE_RL_uart_receive_stop_last_bit,
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample,
WILL_FIRE_RL_uart_receive_wait_for_start_bit,
WILL_FIRE_RL_uart_transmit_bit_cell_time_counter,
WILL_FIRE_RL_uart_transmit_bit_counter,
WILL_FIRE_RL_uart_transmit_buffer_load,
WILL_FIRE_RL_uart_transmit_buffer_shift,
WILL_FIRE_RL_uart_transmit_send_parity_bit,
WILL_FIRE_RL_uart_transmit_send_start_bit,
WILL_FIRE_RL_uart_transmit_send_stop_bit,
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5,
WILL_FIRE_RL_uart_transmit_send_stop_bit2,
WILL_FIRE_RL_uart_transmit_shift_next_bit,
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time,
WILL_FIRE_RL_uart_transmit_wait_for_start_command,
WILL_FIRE_RL_xmas_fsm_action_l42c32,
WILL_FIRE_RL_xmas_fsm_action_l43c32,
WILL_FIRE_RL_xmas_fsm_action_l44c32,
WILL_FIRE_RL_xmas_fsm_action_l45c32,
WILL_FIRE_RL_xmas_fsm_action_l46c32,
WILL_FIRE_RL_xmas_fsm_action_l47c32,
WILL_FIRE_RL_xmas_fsm_action_l48c32,
WILL_FIRE_RL_xmas_fsm_action_l49c32,
WILL_FIRE_RL_xmas_fsm_action_l50c32,
WILL_FIRE_RL_xmas_fsm_action_l51c32,
WILL_FIRE_RL_xmas_fsm_action_l52c32,
WILL_FIRE_RL_xmas_fsm_action_l53c32,
WILL_FIRE_RL_xmas_fsm_action_l54c32,
WILL_FIRE_RL_xmas_fsm_action_l55c32,
WILL_FIRE_RL_xmas_fsm_action_l56c32,
WILL_FIRE_RL_xmas_fsm_action_l57c32,
WILL_FIRE_RL_xmas_fsm_action_l58c32,
WILL_FIRE_RL_xmas_fsm_action_l59c32,
WILL_FIRE_RL_xmas_fsm_action_l60c32,
WILL_FIRE_RL_xmas_fsm_action_l61c32,
WILL_FIRE_RL_xmas_fsm_action_l62c32,
WILL_FIRE_RL_xmas_fsm_action_l63c32,
WILL_FIRE_RL_xmas_fsm_action_l64c32,
WILL_FIRE_RL_xmas_fsm_action_l65c32,
WILL_FIRE_RL_xmas_fsm_action_l66c32,
WILL_FIRE_RL_xmas_fsm_fsm_start,
WILL_FIRE_RL_xmas_fsm_idle_l40c27,
WILL_FIRE_RL_xmas_fsm_idle_l40c27_1,
WILL_FIRE_RL_xmas_fsm_restart,
WILL_FIRE_RL_xmas_fsm_start_reg__dreg_update,
WILL_FIRE_RL_xmas_fsm_state_every,
WILL_FIRE_RL_xmas_fsm_state_fired__dreg_update,
WILL_FIRE_RL_xmas_fsm_state_handle_abort,
WILL_FIRE___me_check_34,
WILL_FIRE___me_check_35,
WILL_FIRE___me_check_36,
WILL_FIRE___me_check_37,
WILL_FIRE___me_check_38,
WILL_FIRE___me_check_39,
WILL_FIRE___me_check_40,
WILL_FIRE___me_check_41,
WILL_FIRE___me_check_42,
WILL_FIRE___me_check_43,
WILL_FIRE___me_check_44,
WILL_FIRE___me_check_45,
WILL_FIRE___me_check_46,
WILL_FIRE___me_check_47,
WILL_FIRE___me_check_48,
WILL_FIRE___me_check_49,
WILL_FIRE___me_check_50,
WILL_FIRE___me_check_51,
WILL_FIRE___me_check_52,
WILL_FIRE___me_check_53,
WILL_FIRE___me_check_54,
WILL_FIRE___me_check_55,
WILL_FIRE___me_check_56,
WILL_FIRE___me_check_57,
WILL_FIRE_operation_mode,
WILL_FIRE_startup_value,
WILL_FIRE_txrx_sin;
// inputs to muxes for submodule ports
reg [2 : 0] MUX_uart_rRecvState$write_1__VAL_3;
wire [2 : 0] MUX_uart_rRecvState$write_1__VAL_1,
MUX_uart_rRecvState$write_1__VAL_2,
MUX_uart_rRecvState$write_1__VAL_4,
MUX_uart_rXmitState$write_1__VAL_1,
MUX_uart_rXmitState$write_1__VAL_2,
MUX_uart_rXmitState$write_1__VAL_3,
MUX_uart_rXmitState$write_1__VAL_4,
MUX_uart_rXmitState$write_1__VAL_5,
MUX_uart_rXmitState$write_1__VAL_6,
MUX_uart_rXmitState$write_1__VAL_7;
wire MUX_transmit_state$write_1__SEL_1,
MUX_uart_fifoXmit$enq_1__SEL_11,
MUX_uart_fifoXmit$enq_1__SEL_15,
MUX_uart_fifoXmit$enq_1__SEL_16,
MUX_uart_fifoXmit$enq_1__SEL_17,
MUX_uart_fifoXmit$enq_1__SEL_2,
MUX_uart_fifoXmit$enq_1__SEL_3,
MUX_uart_rRecvState$write_1__SEL_6,
MUX_uart_rXmitDataOut$write_1__SEL_1,
MUX_uart_rXmitDataOut$write_1__SEL_2,
MUX_uart_rXmitDataOut$write_1__SEL_3,
MUX_xmas_fsm_start_reg$write_1__SEL_1,
MUX_xmas_fsm_state_mkFSMstate$write_1__SEL_1;
// remaining internal signals
wire [3 : 0] x__h2985, x__h4689, x__h6445, x__h6471;
wire _dor2uart_pwXmitCellCountReset$EN_wset,
uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29,
xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302;
// action method operation_mode
assign RDY_operation_mode =
transmit_state == 2'd0 && !op_mode &&
xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302 &&
!xmas_fsm_start_reg ;
assign CAN_FIRE_operation_mode =
transmit_state == 2'd0 && !op_mode &&
xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302 &&
!xmas_fsm_start_reg ;
assign WILL_FIRE_operation_mode = EN_operation_mode ;
// action method startup_value
assign RDY_startup_value = transmit_state == 2'd0 && !op_mode ;
assign CAN_FIRE_startup_value = transmit_state == 2'd0 && !op_mode ;
assign WILL_FIRE_startup_value = EN_startup_value ;
// action method txrx_sin
assign CAN_FIRE_txrx_sin = 1'd1 ;
assign WILL_FIRE_txrx_sin = 1'd1 ;
// value method txrx_sout
assign txrx_SOUT = uart_rXmitDataOut ;
// submodule rule30
mkRule30 rule30(.CLK(CLK),
.RST_N(RST_N),
.start_a(rule30$start_a),
.EN_start(rule30$EN_start),
.EN_getResult(rule30$EN_getResult),
.RDY_start(rule30$RDY_start),
.getResult(rule30$getResult),
.RDY_getResult(rule30$RDY_getResult));
// submodule uart_baudGen_rBaudCounter
Counter #(.width(32'd16), .init(16'd0)) uart_baudGen_rBaudCounter(.CLK(CLK),
.RST(RST_N),
.DATA_A(uart_baudGen_rBaudCounter$DATA_A),
.DATA_B(uart_baudGen_rBaudCounter$DATA_B),
.DATA_C(uart_baudGen_rBaudCounter$DATA_C),
.DATA_F(uart_baudGen_rBaudCounter$DATA_F),
.ADDA(uart_baudGen_rBaudCounter$ADDA),
.ADDB(uart_baudGen_rBaudCounter$ADDB),
.SETC(uart_baudGen_rBaudCounter$SETC),
.SETF(uart_baudGen_rBaudCounter$SETF),
.Q_OUT(uart_baudGen_rBaudCounter$Q_OUT));
// submodule uart_baudGen_rBaudTickCounter
Counter #(.width(32'd3),
.init(3'd0)) uart_baudGen_rBaudTickCounter(.CLK(CLK),
.RST(RST_N),
.DATA_A(uart_baudGen_rBaudTickCounter$DATA_A),
.DATA_B(uart_baudGen_rBaudTickCounter$DATA_B),
.DATA_C(uart_baudGen_rBaudTickCounter$DATA_C),
.DATA_F(uart_baudGen_rBaudTickCounter$DATA_F),
.ADDA(uart_baudGen_rBaudTickCounter$ADDA),
.ADDB(uart_baudGen_rBaudTickCounter$ADDB),
.SETC(uart_baudGen_rBaudTickCounter$SETC),
.SETF(uart_baudGen_rBaudTickCounter$SETF),
.Q_OUT(uart_baudGen_rBaudTickCounter$Q_OUT));
// submodule uart_fifoRecv
SizedFIFO #(.p1width(32'd8),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(1'd1)) uart_fifoRecv(.RST(RST_N),
.CLK(CLK),
.D_IN(uart_fifoRecv$D_IN),
.ENQ(uart_fifoRecv$ENQ),
.DEQ(uart_fifoRecv$DEQ),
.CLR(uart_fifoRecv$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N(uart_fifoRecv$EMPTY_N));
// submodule uart_fifoXmit
SizedFIFO #(.p1width(32'd8),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(1'd1)) uart_fifoXmit(.RST(RST_N),
.CLK(CLK),
.D_IN(uart_fifoXmit$D_IN),
.ENQ(uart_fifoXmit$ENQ),
.DEQ(uart_fifoXmit$DEQ),
.CLR(uart_fifoXmit$CLR),
.D_OUT(uart_fifoXmit$D_OUT),
.FULL_N(uart_fifoXmit$FULL_N),
.EMPTY_N(uart_fifoXmit$EMPTY_N));
// rule RL_dump_rx
assign CAN_FIRE_RL_dump_rx = uart_fifoRecv$EMPTY_N ;
assign WILL_FIRE_RL_dump_rx = uart_fifoRecv$EMPTY_N ;
// rule RL_compute
assign CAN_FIRE_RL_compute =
rule30$RDY_start && transmit_state == 2'd1 && !op_mode ;
assign WILL_FIRE_RL_compute = CAN_FIRE_RL_compute ;
// rule RL_uart_baudGen_baud_count_wire
assign CAN_FIRE_RL_uart_baudGen_baud_count_wire = 1'd1 ;
assign WILL_FIRE_RL_uart_baudGen_baud_count_wire = 1'd1 ;
// rule RL_uart_baud_generator_clock_enable
assign CAN_FIRE_RL_uart_baud_generator_clock_enable = 1'd1 ;
assign WILL_FIRE_RL_uart_baud_generator_clock_enable = 1'd1 ;
// rule RL_uart_receive_wait_for_start_bit
assign CAN_FIRE_RL_uart_receive_wait_for_start_bit =
uart_rRecvState == 3'd0 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_wait_for_start_bit =
CAN_FIRE_RL_uart_receive_wait_for_start_bit ;
// rule RL_uart_receive_find_center_of_bit_cell
assign CAN_FIRE_RL_uart_receive_find_center_of_bit_cell =
uart_rRecvState == 3'd1 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_find_center_of_bit_cell =
CAN_FIRE_RL_uart_receive_find_center_of_bit_cell ;
// rule RL_uart_receive_wait_bit_cell_time_for_sample
assign CAN_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample =
uart_rRecvState == 3'd2 && uart_rRecvCellCount == 4'hF &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample =
CAN_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample ;
// rule RL_uart_receive_sample_pin
assign CAN_FIRE_RL_uart_receive_sample_pin =
CAN_FIRE_RL_uart_receive_buffer_shift ;
assign WILL_FIRE_RL_uart_receive_sample_pin =
CAN_FIRE_RL_uart_receive_buffer_shift ;
// rule RL_uart_receive_parity_bit
assign CAN_FIRE_RL_uart_receive_parity_bit =
uart_rRecvState == 3'd4 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_parity_bit =
CAN_FIRE_RL_uart_receive_parity_bit ;
// rule RL_uart_receive_stop_first_bit
assign CAN_FIRE_RL_uart_receive_stop_first_bit =
uart_rRecvState == 3'd5 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_stop_first_bit =
CAN_FIRE_RL_uart_receive_stop_first_bit ;
// rule RL_uart_receive_bit_counter
assign CAN_FIRE_RL_uart_receive_bit_counter = 1'd1 ;
assign WILL_FIRE_RL_uart_receive_bit_counter = 1'd1 ;
// rule RL_uart_receive_stop_last_bit
assign CAN_FIRE_RL_uart_receive_stop_last_bit =
uart_rRecvState == 3'd6 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_stop_last_bit =
CAN_FIRE_RL_uart_receive_stop_last_bit ;
// rule RL_uart_receive_bit_cell_time_counter
assign CAN_FIRE_RL_uart_receive_bit_cell_time_counter =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
assign WILL_FIRE_RL_uart_receive_bit_cell_time_counter =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// rule RL_uart_receive_buffer_shift
assign CAN_FIRE_RL_uart_receive_buffer_shift =
uart_rRecvState == 3'd3 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_buffer_shift =
CAN_FIRE_RL_uart_receive_buffer_shift ;
// rule RL_uart_transmit_wait_for_start_command
assign CAN_FIRE_RL_uart_transmit_wait_for_start_command =
uart_rXmitState == 3'd0 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_wait_for_start_command =
CAN_FIRE_RL_uart_transmit_wait_for_start_command ;
// rule RL_get_result
assign CAN_FIRE_RL_get_result =
rule30$RDY_getResult && uart_fifoXmit$FULL_N &&
transmit_state == 2'd2 &&
!op_mode &&
xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302 &&
!xmas_fsm_start_reg ;
assign WILL_FIRE_RL_get_result = CAN_FIRE_RL_get_result ;
// rule RL_uart_transmit_send_start_bit
assign CAN_FIRE_RL_uart_transmit_send_start_bit =
uart_rXmitState == 3'd1 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_start_bit =
CAN_FIRE_RL_uart_transmit_send_start_bit ;
// rule RL_uart_transmit_wait_1_bit_cell_time
assign CAN_FIRE_RL_uart_transmit_wait_1_bit_cell_time =
uart_rXmitState == 3'd2 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time =
CAN_FIRE_RL_uart_transmit_wait_1_bit_cell_time ;
// rule RL_uart_transmit_bit_counter
assign CAN_FIRE_RL_uart_transmit_bit_counter = 1'd1 ;
assign WILL_FIRE_RL_uart_transmit_bit_counter = 1'd1 ;
// rule RL_uart_transmit_shift_next_bit
assign CAN_FIRE_RL_uart_transmit_shift_next_bit =
uart_rXmitState == 3'd3 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_shift_next_bit =
CAN_FIRE_RL_uart_transmit_shift_next_bit ;
// rule RL_uart_transmit_buffer_load
assign CAN_FIRE_RL_uart_transmit_buffer_load =
uart_fifoXmit$EMPTY_N && uart_pwXmitLoadBuffer$whas ;
assign WILL_FIRE_RL_uart_transmit_buffer_load =
CAN_FIRE_RL_uart_transmit_buffer_load ;
// rule RL_uart_transmit_buffer_shift
assign CAN_FIRE_RL_uart_transmit_buffer_shift =
!uart_pwXmitLoadBuffer$whas &&
CAN_FIRE_RL_uart_transmit_shift_next_bit ;
assign WILL_FIRE_RL_uart_transmit_buffer_shift =
CAN_FIRE_RL_uart_transmit_buffer_shift ;
// rule RL_uart_transmit_send_parity_bit
assign CAN_FIRE_RL_uart_transmit_send_parity_bit =
uart_rXmitState == 3'd7 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_parity_bit =
CAN_FIRE_RL_uart_transmit_send_parity_bit ;
// rule RL_uart_transmit_send_stop_bit
assign CAN_FIRE_RL_uart_transmit_send_stop_bit =
uart_rXmitState == 3'd4 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_stop_bit =
CAN_FIRE_RL_uart_transmit_send_stop_bit ;
// rule RL_uart_transmit_send_stop_bit1_5
assign CAN_FIRE_RL_uart_transmit_send_stop_bit1_5 =
uart_rXmitState == 3'd5 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 =
CAN_FIRE_RL_uart_transmit_send_stop_bit1_5 ;
// rule RL_uart_transmit_send_stop_bit2
assign CAN_FIRE_RL_uart_transmit_send_stop_bit2 =
uart_rXmitState == 3'd6 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_stop_bit2 =
CAN_FIRE_RL_uart_transmit_send_stop_bit2 ;
// rule RL_uart_transmit_bit_cell_time_counter
assign CAN_FIRE_RL_uart_transmit_bit_cell_time_counter =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
assign WILL_FIRE_RL_uart_transmit_bit_cell_time_counter =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// rule RL_uart_baudGen_baud_tick_count_wire
assign CAN_FIRE_RL_uart_baudGen_baud_tick_count_wire = 1'd1 ;
assign WILL_FIRE_RL_uart_baudGen_baud_tick_count_wire = 1'd1 ;
// rule RL_uart_baudGen_assert_2x_baud_tick
assign CAN_FIRE_RL_uart_baudGen_assert_2x_baud_tick =
uart_baudGen_rBaudTickCounter$Q_OUT == 3'd0 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_baudGen_assert_2x_baud_tick =
CAN_FIRE_RL_uart_baudGen_assert_2x_baud_tick ;
// rule RL_uart_baudGen_count_baudtick_16x
assign CAN_FIRE_RL_uart_baudGen_count_baudtick_16x =
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_baudGen_count_baudtick_16x =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// rule RL_uart_fifoRecv__updateLevelCounter
assign CAN_FIRE_RL_uart_fifoRecv__updateLevelCounter =
CAN_FIRE_RL_uart_receive_stop_last_bit != uart_fifoRecv$EMPTY_N ;
assign WILL_FIRE_RL_uart_fifoRecv__updateLevelCounter =
CAN_FIRE_RL_uart_fifoRecv__updateLevelCounter ;
// rule RL_xmas_fsm_restart
assign CAN_FIRE_RL_xmas_fsm_restart =
xmas_fsm_start_reg_1 && !xmas_fsm_state_fired ;
assign WILL_FIRE_RL_xmas_fsm_restart = CAN_FIRE_RL_xmas_fsm_restart ;
// rule RL_xmas_fsm_action_l43c32
assign CAN_FIRE_RL_xmas_fsm_action_l43c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd1 ;
assign WILL_FIRE_RL_xmas_fsm_action_l43c32 =
CAN_FIRE_RL_xmas_fsm_action_l43c32 ;
// rule RL_xmas_fsm_action_l44c32
assign CAN_FIRE_RL_xmas_fsm_action_l44c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd2 ;
assign WILL_FIRE_RL_xmas_fsm_action_l44c32 =
CAN_FIRE_RL_xmas_fsm_action_l44c32 ;
// rule RL_xmas_fsm_action_l45c32
assign CAN_FIRE_RL_xmas_fsm_action_l45c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd3 ;
assign WILL_FIRE_RL_xmas_fsm_action_l45c32 =
CAN_FIRE_RL_xmas_fsm_action_l45c32 ;
// rule RL_xmas_fsm_action_l46c32
assign CAN_FIRE_RL_xmas_fsm_action_l46c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd4 ;
assign WILL_FIRE_RL_xmas_fsm_action_l46c32 =
CAN_FIRE_RL_xmas_fsm_action_l46c32 ;
// rule RL_xmas_fsm_action_l47c32
assign CAN_FIRE_RL_xmas_fsm_action_l47c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd5 ;
assign WILL_FIRE_RL_xmas_fsm_action_l47c32 =
CAN_FIRE_RL_xmas_fsm_action_l47c32 ;
// rule RL_xmas_fsm_action_l48c32
assign CAN_FIRE_RL_xmas_fsm_action_l48c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd6 ;
assign WILL_FIRE_RL_xmas_fsm_action_l48c32 =
CAN_FIRE_RL_xmas_fsm_action_l48c32 ;
// rule RL_xmas_fsm_action_l49c32
assign CAN_FIRE_RL_xmas_fsm_action_l49c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd7 ;
assign WILL_FIRE_RL_xmas_fsm_action_l49c32 =
CAN_FIRE_RL_xmas_fsm_action_l49c32 ;
// rule RL_xmas_fsm_action_l50c32
assign CAN_FIRE_RL_xmas_fsm_action_l50c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd8 ;
assign WILL_FIRE_RL_xmas_fsm_action_l50c32 =
CAN_FIRE_RL_xmas_fsm_action_l50c32 ;
// rule RL_xmas_fsm_action_l51c32
assign CAN_FIRE_RL_xmas_fsm_action_l51c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd9 ;
assign WILL_FIRE_RL_xmas_fsm_action_l51c32 =
CAN_FIRE_RL_xmas_fsm_action_l51c32 ;
// rule RL_xmas_fsm_action_l52c32
assign CAN_FIRE_RL_xmas_fsm_action_l52c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd10 ;
assign WILL_FIRE_RL_xmas_fsm_action_l52c32 =
CAN_FIRE_RL_xmas_fsm_action_l52c32 ;
// rule RL_xmas_fsm_action_l53c32
assign CAN_FIRE_RL_xmas_fsm_action_l53c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd11 ;
assign WILL_FIRE_RL_xmas_fsm_action_l53c32 =
CAN_FIRE_RL_xmas_fsm_action_l53c32 ;
// rule RL_xmas_fsm_action_l54c32
assign CAN_FIRE_RL_xmas_fsm_action_l54c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd12 ;
assign WILL_FIRE_RL_xmas_fsm_action_l54c32 =
CAN_FIRE_RL_xmas_fsm_action_l54c32 ;
// rule RL_xmas_fsm_action_l55c32
assign CAN_FIRE_RL_xmas_fsm_action_l55c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd13 ;
assign WILL_FIRE_RL_xmas_fsm_action_l55c32 =
CAN_FIRE_RL_xmas_fsm_action_l55c32 ;
// rule RL_xmas_fsm_action_l56c32
assign CAN_FIRE_RL_xmas_fsm_action_l56c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd14 ;
assign WILL_FIRE_RL_xmas_fsm_action_l56c32 =
CAN_FIRE_RL_xmas_fsm_action_l56c32 ;
// rule RL_xmas_fsm_action_l57c32
assign CAN_FIRE_RL_xmas_fsm_action_l57c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd15 ;
assign WILL_FIRE_RL_xmas_fsm_action_l57c32 =
CAN_FIRE_RL_xmas_fsm_action_l57c32 ;
// rule RL_xmas_fsm_action_l58c32
assign CAN_FIRE_RL_xmas_fsm_action_l58c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd16 ;
assign WILL_FIRE_RL_xmas_fsm_action_l58c32 =
CAN_FIRE_RL_xmas_fsm_action_l58c32 ;
// rule RL_xmas_fsm_action_l59c32
assign CAN_FIRE_RL_xmas_fsm_action_l59c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd17 ;
assign WILL_FIRE_RL_xmas_fsm_action_l59c32 =
CAN_FIRE_RL_xmas_fsm_action_l59c32 ;
// rule RL_xmas_fsm_action_l60c32
assign CAN_FIRE_RL_xmas_fsm_action_l60c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd18 ;
assign WILL_FIRE_RL_xmas_fsm_action_l60c32 =
CAN_FIRE_RL_xmas_fsm_action_l60c32 ;
// rule RL_xmas_fsm_action_l61c32
assign CAN_FIRE_RL_xmas_fsm_action_l61c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd19 ;
assign WILL_FIRE_RL_xmas_fsm_action_l61c32 =
CAN_FIRE_RL_xmas_fsm_action_l61c32 ;
// rule RL_xmas_fsm_action_l62c32
assign CAN_FIRE_RL_xmas_fsm_action_l62c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd20 ;
assign WILL_FIRE_RL_xmas_fsm_action_l62c32 =
CAN_FIRE_RL_xmas_fsm_action_l62c32 ;
// rule RL_xmas_fsm_action_l63c32
assign CAN_FIRE_RL_xmas_fsm_action_l63c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd21 ;
assign WILL_FIRE_RL_xmas_fsm_action_l63c32 =
CAN_FIRE_RL_xmas_fsm_action_l63c32 ;
// rule RL_xmas_fsm_action_l64c32
assign CAN_FIRE_RL_xmas_fsm_action_l64c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd22 ;
assign WILL_FIRE_RL_xmas_fsm_action_l64c32 =
CAN_FIRE_RL_xmas_fsm_action_l64c32 ;
// rule RL_xmas_fsm_action_l65c32
assign CAN_FIRE_RL_xmas_fsm_action_l65c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd23 ;
assign WILL_FIRE_RL_xmas_fsm_action_l65c32 =
CAN_FIRE_RL_xmas_fsm_action_l65c32 ;
// rule RL_xmas_fsm_action_l66c32
assign CAN_FIRE_RL_xmas_fsm_action_l66c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd24 ;
assign WILL_FIRE_RL_xmas_fsm_action_l66c32 =
CAN_FIRE_RL_xmas_fsm_action_l66c32 ;
// rule __me_check_35
assign CAN_FIRE___me_check_35 = 1'b1 ;
assign WILL_FIRE___me_check_35 = 1'b1 ;
// rule __me_check_36
assign CAN_FIRE___me_check_36 = 1'b1 ;
assign WILL_FIRE___me_check_36 = 1'b1 ;
// rule __me_check_37
assign CAN_FIRE___me_check_37 = 1'b1 ;
assign WILL_FIRE___me_check_37 = 1'b1 ;
// rule __me_check_38
assign CAN_FIRE___me_check_38 = 1'b1 ;
assign WILL_FIRE___me_check_38 = 1'b1 ;
// rule __me_check_39
assign CAN_FIRE___me_check_39 = 1'b1 ;
assign WILL_FIRE___me_check_39 = 1'b1 ;
// rule __me_check_40
assign CAN_FIRE___me_check_40 = 1'b1 ;
assign WILL_FIRE___me_check_40 = 1'b1 ;
// rule __me_check_41
assign CAN_FIRE___me_check_41 = 1'b1 ;
assign WILL_FIRE___me_check_41 = 1'b1 ;
// rule __me_check_43
assign CAN_FIRE___me_check_43 = 1'b1 ;
assign WILL_FIRE___me_check_43 = 1'b1 ;
// rule __me_check_42
assign CAN_FIRE___me_check_42 = 1'b1 ;
assign WILL_FIRE___me_check_42 = 1'b1 ;
// rule __me_check_44
assign CAN_FIRE___me_check_44 = 1'b1 ;
assign WILL_FIRE___me_check_44 = 1'b1 ;
// rule __me_check_45
assign CAN_FIRE___me_check_45 = 1'b1 ;
assign WILL_FIRE___me_check_45 = 1'b1 ;
// rule __me_check_46
assign CAN_FIRE___me_check_46 = 1'b1 ;
assign WILL_FIRE___me_check_46 = 1'b1 ;
// rule __me_check_47
assign CAN_FIRE___me_check_47 = 1'b1 ;
assign WILL_FIRE___me_check_47 = 1'b1 ;
// rule __me_check_48
assign CAN_FIRE___me_check_48 = 1'b1 ;
assign WILL_FIRE___me_check_48 = 1'b1 ;
// rule __me_check_49
assign CAN_FIRE___me_check_49 = 1'b1 ;
assign WILL_FIRE___me_check_49 = 1'b1 ;
// rule __me_check_51
assign CAN_FIRE___me_check_51 = 1'b1 ;
assign WILL_FIRE___me_check_51 = 1'b1 ;
// rule __me_check_50
assign CAN_FIRE___me_check_50 = 1'b1 ;
assign WILL_FIRE___me_check_50 = 1'b1 ;
// rule __me_check_52
assign CAN_FIRE___me_check_52 = 1'b1 ;
assign WILL_FIRE___me_check_52 = 1'b1 ;
// rule __me_check_53
assign CAN_FIRE___me_check_53 = 1'b1 ;
assign WILL_FIRE___me_check_53 = 1'b1 ;
// rule __me_check_54
assign CAN_FIRE___me_check_54 = 1'b1 ;
assign WILL_FIRE___me_check_54 = 1'b1 ;
// rule __me_check_55
assign CAN_FIRE___me_check_55 = 1'b1 ;
assign WILL_FIRE___me_check_55 = 1'b1 ;
// rule __me_check_56
assign CAN_FIRE___me_check_56 = 1'b1 ;
assign WILL_FIRE___me_check_56 = 1'b1 ;
// rule __me_check_57
assign CAN_FIRE___me_check_57 = 1'b1 ;
assign WILL_FIRE___me_check_57 = 1'b1 ;
// rule RL_xmas_fsm_idle_l40c27_1
assign CAN_FIRE_RL_xmas_fsm_idle_l40c27_1 =
!op_mode && xmas_fsm_state_mkFSMstate == 5'd25 ;
assign WILL_FIRE_RL_xmas_fsm_idle_l40c27_1 =
CAN_FIRE_RL_xmas_fsm_idle_l40c27_1 ;
// rule RL_xmas_fsm_fsm_start
assign CAN_FIRE_RL_xmas_fsm_fsm_start =
(op_mode && xmas_fsm_state_mkFSMstate == 5'd0 ||
op_mode && xmas_fsm_state_mkFSMstate == 5'd27 ||
!op_mode && xmas_fsm_state_mkFSMstate == 5'd0 ||
!op_mode &&
(xmas_fsm_state_mkFSMstate == 5'd25 ||
xmas_fsm_state_mkFSMstate == 5'd27)) &&
(!xmas_fsm_start_reg_1 || xmas_fsm_state_fired) &&
xmas_fsm_start_reg ;
assign WILL_FIRE_RL_xmas_fsm_fsm_start = CAN_FIRE_RL_xmas_fsm_fsm_start ;
// rule RL_xmas_fsm_action_l42c32
assign CAN_FIRE_RL_xmas_fsm_action_l42c32 =
uart_fifoXmit$FULL_N &&
(op_mode && xmas_fsm_start_wire$whas &&
xmas_fsm_state_mkFSMstate == 5'd0 ||
op_mode && xmas_fsm_state_mkFSMstate == 5'd25) ;
assign WILL_FIRE_RL_xmas_fsm_action_l42c32 =
CAN_FIRE_RL_xmas_fsm_action_l42c32 ;
// rule __me_check_34
assign CAN_FIRE___me_check_34 = 1'b1 ;
assign WILL_FIRE___me_check_34 = 1'b1 ;
// rule RL_uart_fifoXmit__updateLevelCounter
assign CAN_FIRE_RL_uart_fifoXmit__updateLevelCounter =
uart_fifoXmit_r_enq$whas !=
CAN_FIRE_RL_uart_transmit_buffer_load ;
assign WILL_FIRE_RL_uart_fifoXmit__updateLevelCounter =
CAN_FIRE_RL_uart_fifoXmit__updateLevelCounter ;
// rule RL_xmas_fsm_idle_l40c27
assign CAN_FIRE_RL_xmas_fsm_idle_l40c27 =
!op_mode && xmas_fsm_start_wire$whas &&
xmas_fsm_state_mkFSMstate == 5'd0 ;
assign WILL_FIRE_RL_xmas_fsm_idle_l40c27 =
CAN_FIRE_RL_xmas_fsm_idle_l40c27 ;
// rule RL_xmas_fsm_start_reg__dreg_update
assign CAN_FIRE_RL_xmas_fsm_start_reg__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_xmas_fsm_start_reg__dreg_update = 1'd1 ;
// rule RL_xmas_fsm_state_handle_abort
assign CAN_FIRE_RL_xmas_fsm_state_handle_abort = 1'b0 ;
assign WILL_FIRE_RL_xmas_fsm_state_handle_abort = 1'b0 ;
// rule RL_xmas_fsm_state_every
assign CAN_FIRE_RL_xmas_fsm_state_every = 1'd1 ;
assign WILL_FIRE_RL_xmas_fsm_state_every = 1'd1 ;
// rule RL_xmas_fsm_state_fired__dreg_update
assign CAN_FIRE_RL_xmas_fsm_state_fired__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_xmas_fsm_state_fired__dreg_update = 1'd1 ;
// inputs to muxes for submodule ports
assign MUX_transmit_state$write_1__SEL_1 =
WILL_FIRE_RL_get_result || EN_startup_value ;
assign MUX_uart_fifoXmit$enq_1__SEL_2 =
WILL_FIRE_RL_xmas_fsm_action_l66c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_3 =
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_11 =
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_15 =
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_16 =
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_17 =
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ;
assign MUX_uart_rRecvState$write_1__SEL_6 =
WILL_FIRE_RL_uart_receive_parity_bit ||
WILL_FIRE_RL_uart_receive_sample_pin ;
assign MUX_uart_rXmitDataOut$write_1__SEL_1 =
WILL_FIRE_RL_uart_transmit_shift_next_bit ||
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ;
assign MUX_uart_rXmitDataOut$write_1__SEL_2 =
WILL_FIRE_RL_uart_transmit_send_parity_bit ||
WILL_FIRE_RL_uart_transmit_send_start_bit ;
assign MUX_uart_rXmitDataOut$write_1__SEL_3 =
WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit ||
WILL_FIRE_RL_uart_transmit_wait_for_start_command ;
assign MUX_xmas_fsm_start_reg$write_1__SEL_1 =
EN_operation_mode && operation_mode_arg == 8'hA5 ;
assign MUX_xmas_fsm_state_mkFSMstate$write_1__SEL_1 =
WILL_FIRE_RL_xmas_fsm_idle_l40c27_1 ||
WILL_FIRE_RL_xmas_fsm_idle_l40c27 ;
assign MUX_uart_rRecvState$write_1__VAL_1 = uart_rRecvData ? 3'd0 : 3'd1 ;
assign MUX_uart_rRecvState$write_1__VAL_2 =
(uart_rRecvCellCount == 4'h4) ?
(uart_rRecvData ? 3'd0 : 3'd2) :
3'd1 ;
always@(uart_rRecvBitCount)
begin
case (uart_rRecvBitCount)
4'd8, 4'd9, 4'd10: MUX_uart_rRecvState$write_1__VAL_3 = 3'd6;
default: MUX_uart_rRecvState$write_1__VAL_3 = 3'd3;
endcase
end
assign MUX_uart_rRecvState$write_1__VAL_4 = uart_rRecvData ? 3'd2 : 3'd0 ;
assign MUX_uart_rXmitState$write_1__VAL_1 =
uart_fifoXmit$EMPTY_N ? 3'd1 : 3'd0 ;
assign MUX_uart_rXmitState$write_1__VAL_2 =
(uart_rXmitCellCount == 4'hF) ? 3'd2 : 3'd1 ;
assign MUX_uart_rXmitState$write_1__VAL_3 =
(uart_rXmitCellCount == 4'hF) ?
((uart_rXmitBitCount == 4'd7) ? 3'd4 : 3'd3) :
3'd2 ;
assign MUX_uart_rXmitState$write_1__VAL_4 =
(uart_rXmitCellCount == 4'hF) ? 3'd4 : 3'd7 ;
assign MUX_uart_rXmitState$write_1__VAL_5 =
(uart_rXmitCellCount == 4'hF) ? 3'd0 : 3'd4 ;
assign MUX_uart_rXmitState$write_1__VAL_6 =
(uart_rXmitCellCount == 4'h7) ? 3'd0 : 3'd5 ;
assign MUX_uart_rXmitState$write_1__VAL_7 =
(uart_rXmitCellCount == 4'hF) ? 3'd0 : 3'd6 ;
// inlined wires
assign xmas_fsm_start_wire$whas =
WILL_FIRE_RL_xmas_fsm_fsm_start ||
WILL_FIRE_RL_xmas_fsm_restart ;
assign uart_pwRecvCellCountReset$whas =
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell &&
uart_rRecvCellCount == 4'h4 ||
WILL_FIRE_RL_uart_receive_stop_last_bit ||
WILL_FIRE_RL_uart_receive_stop_first_bit ||
WILL_FIRE_RL_uart_receive_parity_bit ||
WILL_FIRE_RL_uart_receive_sample_pin ||
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample ||
WILL_FIRE_RL_uart_receive_wait_for_start_bit ;
assign uart_pwRecvResetBitCount$whas =
WILL_FIRE_RL_uart_receive_wait_for_start_bit && uart_rRecvData ;
assign uart_pwRecvEnableBitCount$whas =
WILL_FIRE_RL_uart_receive_stop_first_bit ||
WILL_FIRE_RL_uart_receive_parity_bit ||
WILL_FIRE_RL_uart_receive_sample_pin ;
assign uart_fifoXmit_r_enq$whas =
WILL_FIRE_RL_get_result || WILL_FIRE_RL_xmas_fsm_action_l66c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ||
WILL_FIRE_RL_xmas_fsm_action_l64c32 ||
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l62c32 ||
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ||
WILL_FIRE_RL_xmas_fsm_action_l57c32 ||
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l55c32 ||
WILL_FIRE_RL_xmas_fsm_action_l54c32 ||
WILL_FIRE_RL_xmas_fsm_action_l53c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ||
WILL_FIRE_RL_xmas_fsm_action_l49c32 ||
WILL_FIRE_RL_xmas_fsm_action_l48c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ||
WILL_FIRE_RL_xmas_fsm_action_l46c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ||
WILL_FIRE_RL_xmas_fsm_action_l43c32 ||
WILL_FIRE_RL_xmas_fsm_action_l42c32 ;
assign uart_pwXmitCellCountReset$whas =
WILL_FIRE_RL_uart_transmit_wait_for_start_command &&
uart_fifoXmit$EMPTY_N ||
_dor2uart_pwXmitCellCountReset$EN_wset &&
uart_rXmitCellCount == 4'hF ||
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 &&
uart_rXmitCellCount == 4'h7 ;
assign uart_pwXmitEnableBitCount$whas =
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time &&
uart_rXmitCellCount == 4'hF &&
uart_rXmitBitCount != 4'd7 ;
assign uart_pwXmitLoadBuffer$whas =
WILL_FIRE_RL_uart_transmit_wait_for_start_command &&
uart_fifoXmit$EMPTY_N ;
assign xmas_fsm_state_set_pw$whas =
WILL_FIRE_RL_xmas_fsm_idle_l40c27_1 ||
WILL_FIRE_RL_xmas_fsm_idle_l40c27 ||
WILL_FIRE_RL_xmas_fsm_action_l66c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ||
WILL_FIRE_RL_xmas_fsm_action_l64c32 ||
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l62c32 ||
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ||
WILL_FIRE_RL_xmas_fsm_action_l57c32 ||
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l55c32 ||
WILL_FIRE_RL_xmas_fsm_action_l54c32 ||
WILL_FIRE_RL_xmas_fsm_action_l53c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ||
WILL_FIRE_RL_xmas_fsm_action_l49c32 ||
WILL_FIRE_RL_xmas_fsm_action_l48c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ||
WILL_FIRE_RL_xmas_fsm_action_l46c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ||
WILL_FIRE_RL_xmas_fsm_action_l43c32 ||
WILL_FIRE_RL_xmas_fsm_action_l42c32 ;
// register a
assign a$D_IN = EN_startup_value ? startup_value_v : rule30$getResult ;
assign a$EN = EN_startup_value || WILL_FIRE_RL_get_result ;
// register op_mode
assign op_mode$D_IN = 1'd1 ;
assign op_mode$EN = MUX_xmas_fsm_start_reg$write_1__SEL_1 ;
// register transmit_state
assign transmit_state$D_IN =
MUX_transmit_state$write_1__SEL_1 ? 2'd1 : 2'd2 ;
assign transmit_state$EN =
WILL_FIRE_RL_get_result || EN_startup_value ||
WILL_FIRE_RL_compute ;
// register uart_rRecvBitCount
assign uart_rRecvBitCount$D_IN =
uart_pwRecvResetBitCount$whas ? 4'd0 : x__h4689 ;
assign uart_rRecvBitCount$EN =
uart_pwRecvResetBitCount$whas || uart_pwRecvEnableBitCount$whas ;
// register uart_rRecvCellCount
assign uart_rRecvCellCount$D_IN =
uart_pwRecvCellCountReset$whas ? 4'd0 : x__h2985 ;
assign uart_rRecvCellCount$EN =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// register uart_rRecvData
assign uart_rRecvData$D_IN = txrx_SIN ;
assign uart_rRecvData$EN = 1'd1 ;
// register uart_rRecvState
always@(WILL_FIRE_RL_uart_receive_wait_for_start_bit or
MUX_uart_rRecvState$write_1__VAL_1 or
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell or
MUX_uart_rRecvState$write_1__VAL_2 or
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample or
MUX_uart_rRecvState$write_1__VAL_3 or
WILL_FIRE_RL_uart_receive_stop_first_bit or
MUX_uart_rRecvState$write_1__VAL_4 or
WILL_FIRE_RL_uart_receive_stop_last_bit or
MUX_uart_rRecvState$write_1__SEL_6)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_uart_receive_wait_for_start_bit:
uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_1;
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell:
uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_2;
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample:
uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_3;
WILL_FIRE_RL_uart_receive_stop_first_bit:
uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_4;
WILL_FIRE_RL_uart_receive_stop_last_bit: uart_rRecvState$D_IN = 3'd0;
MUX_uart_rRecvState$write_1__SEL_6: uart_rRecvState$D_IN = 3'd2;
default: uart_rRecvState$D_IN = 3'b010 /* unspecified value */ ;
endcase
end
assign uart_rRecvState$EN =
WILL_FIRE_RL_uart_receive_wait_for_start_bit ||
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell ||
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample ||
WILL_FIRE_RL_uart_receive_stop_first_bit ||
WILL_FIRE_RL_uart_receive_stop_last_bit ||
WILL_FIRE_RL_uart_receive_parity_bit ||
WILL_FIRE_RL_uart_receive_sample_pin ;
// register uart_rXmitBitCount
assign uart_rXmitBitCount$D_IN =
CAN_FIRE_RL_uart_transmit_wait_for_start_command ?
4'd0 :
x__h6471 ;
assign uart_rXmitBitCount$EN =
CAN_FIRE_RL_uart_transmit_wait_for_start_command ||
uart_pwXmitEnableBitCount$whas ;
// register uart_rXmitCellCount
assign uart_rXmitCellCount$D_IN =
uart_pwXmitCellCountReset$whas ? 4'd0 : x__h6445 ;
assign uart_rXmitCellCount$EN =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// register uart_rXmitDataOut
always@(MUX_uart_rXmitDataOut$write_1__SEL_1 or
uart_vrXmitBuffer_0 or
MUX_uart_rXmitDataOut$write_1__SEL_2 or
MUX_uart_rXmitDataOut$write_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_uart_rXmitDataOut$write_1__SEL_1:
uart_rXmitDataOut$D_IN = uart_vrXmitBuffer_0;
MUX_uart_rXmitDataOut$write_1__SEL_2: uart_rXmitDataOut$D_IN = 1'b0;
MUX_uart_rXmitDataOut$write_1__SEL_3: uart_rXmitDataOut$D_IN = 1'b1;
default: uart_rXmitDataOut$D_IN = 1'b0 /* unspecified value */ ;
endcase
end
assign uart_rXmitDataOut$EN =
WILL_FIRE_RL_uart_transmit_shift_next_bit ||
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ||
WILL_FIRE_RL_uart_transmit_send_parity_bit ||
WILL_FIRE_RL_uart_transmit_send_start_bit ||
WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit ||
WILL_FIRE_RL_uart_transmit_wait_for_start_command ;
// register uart_rXmitState
always@(WILL_FIRE_RL_uart_transmit_wait_for_start_command or
MUX_uart_rXmitState$write_1__VAL_1 or
WILL_FIRE_RL_uart_transmit_send_start_bit or
MUX_uart_rXmitState$write_1__VAL_2 or
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time or
MUX_uart_rXmitState$write_1__VAL_3 or
WILL_FIRE_RL_uart_transmit_send_parity_bit or
MUX_uart_rXmitState$write_1__VAL_4 or
WILL_FIRE_RL_uart_transmit_send_stop_bit or
MUX_uart_rXmitState$write_1__VAL_5 or
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 or
MUX_uart_rXmitState$write_1__VAL_6 or
WILL_FIRE_RL_uart_transmit_send_stop_bit2 or
MUX_uart_rXmitState$write_1__VAL_7 or
WILL_FIRE_RL_uart_transmit_shift_next_bit)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_uart_transmit_wait_for_start_command:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_1;
WILL_FIRE_RL_uart_transmit_send_start_bit:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_2;
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_3;
WILL_FIRE_RL_uart_transmit_send_parity_bit:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_4;
WILL_FIRE_RL_uart_transmit_send_stop_bit:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_5;
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_6;
WILL_FIRE_RL_uart_transmit_send_stop_bit2:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_7;
WILL_FIRE_RL_uart_transmit_shift_next_bit: uart_rXmitState$D_IN = 3'd2;
default: uart_rXmitState$D_IN = 3'b010 /* unspecified value */ ;
endcase
end
assign uart_rXmitState$EN =
WILL_FIRE_RL_uart_transmit_wait_for_start_command ||
WILL_FIRE_RL_uart_transmit_send_start_bit ||
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ||
WILL_FIRE_RL_uart_transmit_send_parity_bit ||
WILL_FIRE_RL_uart_transmit_send_stop_bit ||
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
WILL_FIRE_RL_uart_transmit_shift_next_bit ;
// register uart_vrRecvBuffer_0
assign uart_vrRecvBuffer_0$D_IN = uart_vrRecvBuffer_1 ;
assign uart_vrRecvBuffer_0$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_1
assign uart_vrRecvBuffer_1$D_IN = uart_vrRecvBuffer_2 ;
assign uart_vrRecvBuffer_1$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_2
assign uart_vrRecvBuffer_2$D_IN = uart_vrRecvBuffer_3 ;
assign uart_vrRecvBuffer_2$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_3
assign uart_vrRecvBuffer_3$D_IN = uart_vrRecvBuffer_4 ;
assign uart_vrRecvBuffer_3$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_4
assign uart_vrRecvBuffer_4$D_IN = uart_vrRecvBuffer_5 ;
assign uart_vrRecvBuffer_4$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_5
assign uart_vrRecvBuffer_5$D_IN = uart_vrRecvBuffer_6 ;
assign uart_vrRecvBuffer_5$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_6
assign uart_vrRecvBuffer_6$D_IN = uart_vrRecvBuffer_7 ;
assign uart_vrRecvBuffer_6$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_7
assign uart_vrRecvBuffer_7$D_IN = uart_rRecvData ;
assign uart_vrRecvBuffer_7$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrXmitBuffer_0
assign uart_vrXmitBuffer_0$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[0] :
uart_vrXmitBuffer_1 ;
assign uart_vrXmitBuffer_0$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_1
assign uart_vrXmitBuffer_1$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[1] :
uart_vrXmitBuffer_2 ;
assign uart_vrXmitBuffer_1$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_2
assign uart_vrXmitBuffer_2$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[2] :
uart_vrXmitBuffer_3 ;
assign uart_vrXmitBuffer_2$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_3
assign uart_vrXmitBuffer_3$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[3] :
uart_vrXmitBuffer_4 ;
assign uart_vrXmitBuffer_3$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_4
assign uart_vrXmitBuffer_4$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[4] :
uart_vrXmitBuffer_5 ;
assign uart_vrXmitBuffer_4$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_5
assign uart_vrXmitBuffer_5$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[5] :
uart_vrXmitBuffer_6 ;
assign uart_vrXmitBuffer_5$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_6
assign uart_vrXmitBuffer_6$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[6] :
uart_vrXmitBuffer_7 ;
assign uart_vrXmitBuffer_6$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_7
assign uart_vrXmitBuffer_7$D_IN =
!WILL_FIRE_RL_uart_transmit_buffer_load ||
uart_fifoXmit$D_OUT[7] ;
assign uart_vrXmitBuffer_7$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register xmas_fsm_start_reg
assign xmas_fsm_start_reg$D_IN = MUX_xmas_fsm_start_reg$write_1__SEL_1 ;
assign xmas_fsm_start_reg$EN =
EN_operation_mode && operation_mode_arg == 8'hA5 ||
WILL_FIRE_RL_xmas_fsm_fsm_start ;
// register xmas_fsm_start_reg_1
assign xmas_fsm_start_reg_1$D_IN = xmas_fsm_start_wire$whas ;
assign xmas_fsm_start_reg_1$EN = 1'd1 ;
// register xmas_fsm_state_fired
assign xmas_fsm_state_fired$D_IN = xmas_fsm_state_set_pw$whas ;
assign xmas_fsm_state_fired$EN = 1'd1 ;
// register xmas_fsm_state_mkFSMstate
always@(MUX_xmas_fsm_state_mkFSMstate$write_1__SEL_1 or
WILL_FIRE_RL_xmas_fsm_action_l42c32 or
WILL_FIRE_RL_xmas_fsm_action_l43c32 or
WILL_FIRE_RL_xmas_fsm_action_l44c32 or
WILL_FIRE_RL_xmas_fsm_action_l45c32 or
WILL_FIRE_RL_xmas_fsm_action_l46c32 or
WILL_FIRE_RL_xmas_fsm_action_l47c32 or
WILL_FIRE_RL_xmas_fsm_action_l48c32 or
WILL_FIRE_RL_xmas_fsm_action_l49c32 or
WILL_FIRE_RL_xmas_fsm_action_l50c32 or
WILL_FIRE_RL_xmas_fsm_action_l51c32 or
WILL_FIRE_RL_xmas_fsm_action_l52c32 or
WILL_FIRE_RL_xmas_fsm_action_l53c32 or
WILL_FIRE_RL_xmas_fsm_action_l54c32 or
WILL_FIRE_RL_xmas_fsm_action_l55c32 or
WILL_FIRE_RL_xmas_fsm_action_l56c32 or
WILL_FIRE_RL_xmas_fsm_action_l57c32 or
WILL_FIRE_RL_xmas_fsm_action_l58c32 or
WILL_FIRE_RL_xmas_fsm_action_l59c32 or
WILL_FIRE_RL_xmas_fsm_action_l60c32 or
WILL_FIRE_RL_xmas_fsm_action_l61c32 or
WILL_FIRE_RL_xmas_fsm_action_l62c32 or
WILL_FIRE_RL_xmas_fsm_action_l63c32 or
WILL_FIRE_RL_xmas_fsm_action_l64c32 or
WILL_FIRE_RL_xmas_fsm_action_l65c32 or
WILL_FIRE_RL_xmas_fsm_action_l66c32)
begin
case (1'b1) // synopsys parallel_case
MUX_xmas_fsm_state_mkFSMstate$write_1__SEL_1:
xmas_fsm_state_mkFSMstate$D_IN = 5'd0;
WILL_FIRE_RL_xmas_fsm_action_l42c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd1;
WILL_FIRE_RL_xmas_fsm_action_l43c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd2;
WILL_FIRE_RL_xmas_fsm_action_l44c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd3;
WILL_FIRE_RL_xmas_fsm_action_l45c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd4;
WILL_FIRE_RL_xmas_fsm_action_l46c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd5;
WILL_FIRE_RL_xmas_fsm_action_l47c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd6;
WILL_FIRE_RL_xmas_fsm_action_l48c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd7;
WILL_FIRE_RL_xmas_fsm_action_l49c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd8;
WILL_FIRE_RL_xmas_fsm_action_l50c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd9;
WILL_FIRE_RL_xmas_fsm_action_l51c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd10;
WILL_FIRE_RL_xmas_fsm_action_l52c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd11;
WILL_FIRE_RL_xmas_fsm_action_l53c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd12;
WILL_FIRE_RL_xmas_fsm_action_l54c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd13;
WILL_FIRE_RL_xmas_fsm_action_l55c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd14;
WILL_FIRE_RL_xmas_fsm_action_l56c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd15;
WILL_FIRE_RL_xmas_fsm_action_l57c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd16;
WILL_FIRE_RL_xmas_fsm_action_l58c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd17;
WILL_FIRE_RL_xmas_fsm_action_l59c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd18;
WILL_FIRE_RL_xmas_fsm_action_l60c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd19;
WILL_FIRE_RL_xmas_fsm_action_l61c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd20;
WILL_FIRE_RL_xmas_fsm_action_l62c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd21;
WILL_FIRE_RL_xmas_fsm_action_l63c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd22;
WILL_FIRE_RL_xmas_fsm_action_l64c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd23;
WILL_FIRE_RL_xmas_fsm_action_l65c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd24;
WILL_FIRE_RL_xmas_fsm_action_l66c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd25;
default: xmas_fsm_state_mkFSMstate$D_IN =
5'b01010 /* unspecified value */ ;
endcase
end
assign xmas_fsm_state_mkFSMstate$EN =
WILL_FIRE_RL_xmas_fsm_idle_l40c27_1 ||
WILL_FIRE_RL_xmas_fsm_idle_l40c27 ||
WILL_FIRE_RL_xmas_fsm_action_l42c32 ||
WILL_FIRE_RL_xmas_fsm_action_l43c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l46c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ||
WILL_FIRE_RL_xmas_fsm_action_l48c32 ||
WILL_FIRE_RL_xmas_fsm_action_l49c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l53c32 ||
WILL_FIRE_RL_xmas_fsm_action_l54c32 ||
WILL_FIRE_RL_xmas_fsm_action_l55c32 ||
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l57c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ||
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l62c32 ||
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l64c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ||
WILL_FIRE_RL_xmas_fsm_action_l66c32 ;
// submodule rule30
assign rule30$start_a = a ;
assign rule30$EN_start = CAN_FIRE_RL_compute ;
assign rule30$EN_getResult = CAN_FIRE_RL_get_result ;
// submodule uart_baudGen_rBaudCounter
assign uart_baudGen_rBaudCounter$DATA_A = 16'd1 ;
assign uart_baudGen_rBaudCounter$DATA_B = 16'h0 ;
assign uart_baudGen_rBaudCounter$DATA_C = 16'h0 ;
assign uart_baudGen_rBaudCounter$DATA_F = 16'd0 ;
assign uart_baudGen_rBaudCounter$ADDA =
uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign uart_baudGen_rBaudCounter$ADDB = 1'b0 ;
assign uart_baudGen_rBaudCounter$SETC = 1'b0 ;
assign uart_baudGen_rBaudCounter$SETF =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// submodule uart_baudGen_rBaudTickCounter
assign uart_baudGen_rBaudTickCounter$DATA_A = 3'd1 ;
assign uart_baudGen_rBaudTickCounter$DATA_B = 3'h0 ;
assign uart_baudGen_rBaudTickCounter$DATA_C = 3'h0 ;
assign uart_baudGen_rBaudTickCounter$DATA_F = 3'h0 ;
assign uart_baudGen_rBaudTickCounter$ADDA =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
assign uart_baudGen_rBaudTickCounter$ADDB = 1'b0 ;
assign uart_baudGen_rBaudTickCounter$SETC = 1'b0 ;
assign uart_baudGen_rBaudTickCounter$SETF = 1'b0 ;
// submodule uart_fifoRecv
assign uart_fifoRecv$D_IN =
{ uart_vrRecvBuffer_7,
uart_vrRecvBuffer_6,
uart_vrRecvBuffer_5,
uart_vrRecvBuffer_4,
uart_vrRecvBuffer_3,
uart_vrRecvBuffer_2,
uart_vrRecvBuffer_1,
uart_vrRecvBuffer_0 } ;
assign uart_fifoRecv$ENQ = CAN_FIRE_RL_uart_receive_stop_last_bit ;
assign uart_fifoRecv$DEQ = uart_fifoRecv$EMPTY_N ;
assign uart_fifoRecv$CLR = 1'b0 ;
// submodule uart_fifoXmit
always@(WILL_FIRE_RL_get_result or
rule30$getResult or
MUX_uart_fifoXmit$enq_1__SEL_2 or
MUX_uart_fifoXmit$enq_1__SEL_3 or
WILL_FIRE_RL_xmas_fsm_action_l64c32 or
WILL_FIRE_RL_xmas_fsm_action_l53c32 or
WILL_FIRE_RL_xmas_fsm_action_l54c32 or
WILL_FIRE_RL_xmas_fsm_action_l55c32 or
WILL_FIRE_RL_xmas_fsm_action_l42c32 or
WILL_FIRE_RL_xmas_fsm_action_l57c32 or
WILL_FIRE_RL_xmas_fsm_action_l48c32 or
MUX_uart_fifoXmit$enq_1__SEL_11 or
WILL_FIRE_RL_xmas_fsm_action_l43c32 or
WILL_FIRE_RL_xmas_fsm_action_l49c32 or
WILL_FIRE_RL_xmas_fsm_action_l62c32 or
MUX_uart_fifoXmit$enq_1__SEL_15 or
MUX_uart_fifoXmit$enq_1__SEL_16 or
MUX_uart_fifoXmit$enq_1__SEL_17 or
WILL_FIRE_RL_xmas_fsm_action_l46c32)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_get_result: uart_fifoXmit$D_IN = rule30$getResult;
MUX_uart_fifoXmit$enq_1__SEL_2: uart_fifoXmit$D_IN = 8'h09;
MUX_uart_fifoXmit$enq_1__SEL_3: uart_fifoXmit$D_IN = 8'h20;
WILL_FIRE_RL_xmas_fsm_action_l64c32: uart_fifoXmit$D_IN = 8'h21;
WILL_FIRE_RL_xmas_fsm_action_l53c32: uart_fifoXmit$D_IN = 8'h27;
WILL_FIRE_RL_xmas_fsm_action_l54c32: uart_fifoXmit$D_IN = 8'h32;
WILL_FIRE_RL_xmas_fsm_action_l55c32: uart_fifoXmit$D_IN = 8'h34;
WILL_FIRE_RL_xmas_fsm_action_l42c32: uart_fifoXmit$D_IN = 8'h4D;
WILL_FIRE_RL_xmas_fsm_action_l57c32: uart_fifoXmit$D_IN = 8'h53;
WILL_FIRE_RL_xmas_fsm_action_l48c32: uart_fifoXmit$D_IN = 8'h58;
MUX_uart_fifoXmit$enq_1__SEL_11: uart_fifoXmit$D_IN = 8'h61;
WILL_FIRE_RL_xmas_fsm_action_l43c32: uart_fifoXmit$D_IN = 8'h65;
WILL_FIRE_RL_xmas_fsm_action_l49c32: uart_fifoXmit$D_IN = 8'h6D;
WILL_FIRE_RL_xmas_fsm_action_l62c32: uart_fifoXmit$D_IN = 8'h6F;
MUX_uart_fifoXmit$enq_1__SEL_15: uart_fifoXmit$D_IN = 8'h72;
MUX_uart_fifoXmit$enq_1__SEL_16: uart_fifoXmit$D_IN = 8'h73;
MUX_uart_fifoXmit$enq_1__SEL_17: uart_fifoXmit$D_IN = 8'h74;
WILL_FIRE_RL_xmas_fsm_action_l46c32: uart_fifoXmit$D_IN = 8'h79;
default: uart_fifoXmit$D_IN = 8'b10101010 /* unspecified value */ ;
endcase
end
assign uart_fifoXmit$ENQ =
WILL_FIRE_RL_get_result || WILL_FIRE_RL_xmas_fsm_action_l66c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ||
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ||
WILL_FIRE_RL_xmas_fsm_action_l64c32 ||
WILL_FIRE_RL_xmas_fsm_action_l53c32 ||
WILL_FIRE_RL_xmas_fsm_action_l54c32 ||
WILL_FIRE_RL_xmas_fsm_action_l55c32 ||
WILL_FIRE_RL_xmas_fsm_action_l42c32 ||
WILL_FIRE_RL_xmas_fsm_action_l57c32 ||
WILL_FIRE_RL_xmas_fsm_action_l48c32 ||
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ||
WILL_FIRE_RL_xmas_fsm_action_l43c32 ||
WILL_FIRE_RL_xmas_fsm_action_l49c32 ||
WILL_FIRE_RL_xmas_fsm_action_l62c32 ||
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ||
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ||
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ||
WILL_FIRE_RL_xmas_fsm_action_l46c32 ;
assign uart_fifoXmit$DEQ = CAN_FIRE_RL_uart_transmit_buffer_load ;
assign uart_fifoXmit$CLR = 1'b0 ;
// remaining internal signals
assign _dor2uart_pwXmitCellCountReset$EN_wset =
WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit ||
WILL_FIRE_RL_uart_transmit_send_parity_bit ||
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ||
WILL_FIRE_RL_uart_transmit_send_start_bit ;
assign uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 =
uart_baudGen_rBaudCounter$Q_OUT + 16'd1 < 16'd27 ;
assign x__h2985 = uart_rRecvCellCount + 4'd1 ;
assign x__h4689 = uart_rRecvBitCount + 4'd1 ;
assign x__h6445 = uart_rXmitCellCount + 4'd1 ;
assign x__h6471 = uart_rXmitBitCount + 4'd1 ;
assign xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302 =
(xmas_fsm_state_mkFSMstate == 5'd0 ||
xmas_fsm_state_mkFSMstate == 5'd25 ||
xmas_fsm_state_mkFSMstate == 5'd27) &&
(!xmas_fsm_start_reg_1 || xmas_fsm_state_fired) ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
a <= `BSV_ASSIGNMENT_DELAY 8'b0;
op_mode <= `BSV_ASSIGNMENT_DELAY 1'd0;
transmit_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
uart_rRecvData <= `BSV_ASSIGNMENT_DELAY 1'd1;
xmas_fsm_start_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
xmas_fsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
xmas_fsm_state_fired <= `BSV_ASSIGNMENT_DELAY 1'd0;
xmas_fsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY 5'd0;
end
else
begin
if (a$EN) a <= `BSV_ASSIGNMENT_DELAY a$D_IN;
if (op_mode$EN) op_mode <= `BSV_ASSIGNMENT_DELAY op_mode$D_IN;
if (transmit_state$EN)
transmit_state <= `BSV_ASSIGNMENT_DELAY transmit_state$D_IN;
if (uart_rRecvData$EN)
uart_rRecvData <= `BSV_ASSIGNMENT_DELAY uart_rRecvData$D_IN;
if (xmas_fsm_start_reg$EN)
xmas_fsm_start_reg <= `BSV_ASSIGNMENT_DELAY xmas_fsm_start_reg$D_IN;
if (xmas_fsm_start_reg_1$EN)
xmas_fsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY
xmas_fsm_start_reg_1$D_IN;
if (xmas_fsm_state_fired$EN)
xmas_fsm_state_fired <= `BSV_ASSIGNMENT_DELAY
xmas_fsm_state_fired$D_IN;
if (xmas_fsm_state_mkFSMstate$EN)
xmas_fsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY
xmas_fsm_state_mkFSMstate$D_IN;
end
if (uart_vrRecvBuffer_0$EN)
uart_vrRecvBuffer_0 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_0$D_IN;
if (uart_vrRecvBuffer_1$EN)
uart_vrRecvBuffer_1 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_1$D_IN;
if (uart_vrRecvBuffer_2$EN)
uart_vrRecvBuffer_2 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_2$D_IN;
if (uart_vrRecvBuffer_3$EN)
uart_vrRecvBuffer_3 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_3$D_IN;
if (uart_vrRecvBuffer_4$EN)
uart_vrRecvBuffer_4 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_4$D_IN;
if (uart_vrRecvBuffer_5$EN)
uart_vrRecvBuffer_5 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_5$D_IN;
if (uart_vrRecvBuffer_6$EN)
uart_vrRecvBuffer_6 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_6$D_IN;
if (uart_vrRecvBuffer_7$EN)
uart_vrRecvBuffer_7 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_7$D_IN;
if (uart_vrXmitBuffer_0$EN)
uart_vrXmitBuffer_0 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_0$D_IN;
if (uart_vrXmitBuffer_1$EN)
uart_vrXmitBuffer_1 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_1$D_IN;
if (uart_vrXmitBuffer_2$EN)
uart_vrXmitBuffer_2 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_2$D_IN;
if (uart_vrXmitBuffer_3$EN)
uart_vrXmitBuffer_3 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_3$D_IN;
if (uart_vrXmitBuffer_4$EN)
uart_vrXmitBuffer_4 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_4$D_IN;
if (uart_vrXmitBuffer_5$EN)
uart_vrXmitBuffer_5 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_5$D_IN;
if (uart_vrXmitBuffer_6$EN)
uart_vrXmitBuffer_6 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_6$D_IN;
if (uart_vrXmitBuffer_7$EN)
uart_vrXmitBuffer_7 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_7$D_IN;
end
always@(posedge CLK or `BSV_RESET_EDGE RST_N)
if (RST_N == `BSV_RESET_VALUE)
begin
uart_rRecvBitCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
uart_rRecvCellCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
uart_rRecvState <= `BSV_ASSIGNMENT_DELAY 3'd0;
uart_rXmitBitCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
uart_rXmitCellCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
uart_rXmitDataOut <= `BSV_ASSIGNMENT_DELAY 1'd1;
uart_rXmitState <= `BSV_ASSIGNMENT_DELAY 3'd0;
end
else
begin
if (uart_rRecvBitCount$EN)
uart_rRecvBitCount <= `BSV_ASSIGNMENT_DELAY uart_rRecvBitCount$D_IN;
if (uart_rRecvCellCount$EN)
uart_rRecvCellCount <= `BSV_ASSIGNMENT_DELAY uart_rRecvCellCount$D_IN;
if (uart_rRecvState$EN)
uart_rRecvState <= `BSV_ASSIGNMENT_DELAY uart_rRecvState$D_IN;
if (uart_rXmitBitCount$EN)
uart_rXmitBitCount <= `BSV_ASSIGNMENT_DELAY uart_rXmitBitCount$D_IN;
if (uart_rXmitCellCount$EN)
uart_rXmitCellCount <= `BSV_ASSIGNMENT_DELAY uart_rXmitCellCount$D_IN;
if (uart_rXmitDataOut$EN)
uart_rXmitDataOut <= `BSV_ASSIGNMENT_DELAY uart_rXmitDataOut$D_IN;
if (uart_rXmitState$EN)
uart_rXmitState <= `BSV_ASSIGNMENT_DELAY uart_rXmitState$D_IN;
end
// handling of system tasks
endmodule // mkRule30Driver
//
// Generated by Bluespec Compiler, version 2024.01-1-g4d953407 (build 4d953407)
//
// On Thu Apr 18 23:03:51 EDT 2024
//
//
// Ports:
// Name I/O size props
// RDY_start O 1
// getResult O 8 reg
// RDY_getResult O 1
// CLK I 1 clock
// RST_N I 1 reset
// start_a I 8
// EN_start I 1
// EN_getResult I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkRule30(CLK,
RST_N,
start_a,
EN_start,
RDY_start,
EN_getResult,
getResult,
RDY_getResult);
input CLK;
input RST_N;
// action method start
input [7 : 0] start_a;
input EN_start;
output RDY_start;
// actionvalue method getResult
input EN_getResult;
output [7 : 0] getResult;
output RDY_getResult;
// signals for module outputs
wire [7 : 0] getResult;
wire RDY_getResult, RDY_start;
// register busy_flag
reg busy_flag;
wire busy_flag$D_IN, busy_flag$EN;
// register r30
reg [7 : 0] r30;
wire [7 : 0] r30$D_IN;
wire r30$EN;
// register step_complete
reg step_complete;
wire step_complete$D_IN, step_complete$EN;
// register x
reg [55 : 0] x;
wire [55 : 0] x$D_IN;
wire x$EN;
// rule scheduling signals
wire CAN_FIRE_RL_stepper,
CAN_FIRE_getResult,
CAN_FIRE_start,
WILL_FIRE_RL_stepper,
WILL_FIRE_getResult,
WILL_FIRE_start;
// inputs to muxes for submodule ports
wire [55 : 0] MUX_x$write_1__VAL_1, MUX_x$write_1__VAL_2;
// remaining internal signals
wire [51 : 0] r30_BIT_x_BITS_52_TO_50_6_7_CONCAT_r30_BIT_x_B_ETC___d146;
wire [47 : 0] r30_BIT_x_BITS_48_TO_46_4_5_CONCAT_r30_BIT_x_B_ETC___d144;
wire [43 : 0] r30_BIT_x_BITS_44_TO_42_2_3_CONCAT_r30_BIT_x_B_ETC___d142;
wire [39 : 0] r30_BIT_x_BITS_40_TO_38_0_1_CONCAT_r30_BIT_x_B_ETC___d140;
wire [35 : 0] r30_BIT_x_BITS_36_TO_34_8_9_CONCAT_r30_BIT_x_B_ETC___d138;
wire [31 : 0] r30_BIT_x_BITS_32_TO_30_6_7_CONCAT_r30_BIT_x_B_ETC___d136;
wire [27 : 0] r30_BIT_x_BITS_28_TO_26_4_5_CONCAT_r30_BIT_x_B_ETC___d134;
wire [23 : 0] r30_BIT_x_BITS_24_TO_22_2_3_CONCAT_r30_BIT_x_B_ETC___d132;
wire [19 : 0] r30_BIT_x_BITS_20_TO_18_0_1_CONCAT_r30_BIT_x_B_ETC___d130;
wire [15 : 0] r30_BIT_x_BITS_16_TO_14_8_9_CONCAT_r30_BIT_x_B_ETC___d128;
wire [11 : 0] r30_BIT_x_BITS_12_TO_10_6_7_CONCAT_r30_BIT_x_B_ETC___d126;
wire [7 : 0] r30_BIT_x_BITS_8_TO_6_04_05_CONCAT_r30_BIT_x_B_ETC___d124;
wire [3 : 0] r30_BIT_x_BITS_4_TO_2_12_13_CONCAT_r30_BIT_x_B_ETC___d122;
wire [2 : 0] b0__h167, b55__h222;
// action method start
assign RDY_start = !busy_flag ;
assign CAN_FIRE_start = !busy_flag ;
assign WILL_FIRE_start = EN_start ;
// actionvalue method getResult
assign getResult = x[31:24] ;
assign RDY_getResult = busy_flag && step_complete ;
assign CAN_FIRE_getResult = busy_flag && step_complete ;
assign WILL_FIRE_getResult = EN_getResult ;
// rule RL_stepper
assign CAN_FIRE_RL_stepper = busy_flag && !step_complete ;
assign WILL_FIRE_RL_stepper = CAN_FIRE_RL_stepper ;
// inputs to muxes for submodule ports
assign MUX_x$write_1__VAL_1 =
{ r30[b55__h222],
r30[x[55:53]],
r30[x[54:52]],
r30[x[53:51]],
r30_BIT_x_BITS_52_TO_50_6_7_CONCAT_r30_BIT_x_B_ETC___d146 } ;
assign MUX_x$write_1__VAL_2 = { x[55:32], start_a, x[23:0] } ;
// register busy_flag
assign busy_flag$D_IN = !EN_getResult ;
assign busy_flag$EN = EN_getResult || EN_start ;
// register r30
assign r30$D_IN = 8'h0 ;
assign r30$EN = 1'b0 ;
// register step_complete
assign step_complete$D_IN = !EN_start ;
assign step_complete$EN = EN_start || WILL_FIRE_RL_stepper ;
// register x
assign x$D_IN =
WILL_FIRE_RL_stepper ?
MUX_x$write_1__VAL_1 :
MUX_x$write_1__VAL_2 ;
assign x$EN = WILL_FIRE_RL_stepper || EN_start ;
// remaining internal signals
assign b0__h167 = { x[1:0], 1'b0 } ;
assign b55__h222 = { 1'b0, x[55:54] } ;
assign r30_BIT_x_BITS_12_TO_10_6_7_CONCAT_r30_BIT_x_B_ETC___d126 =
{ r30[x[12:10]],
r30[x[11:9]],
r30[x[10:8]],
r30[x[9:7]],
r30_BIT_x_BITS_8_TO_6_04_05_CONCAT_r30_BIT_x_B_ETC___d124 } ;
assign r30_BIT_x_BITS_16_TO_14_8_9_CONCAT_r30_BIT_x_B_ETC___d128 =
{ r30[x[16:14]],
r30[x[15:13]],
r30[x[14:12]],
r30[x[13:11]],
r30_BIT_x_BITS_12_TO_10_6_7_CONCAT_r30_BIT_x_B_ETC___d126 } ;
assign r30_BIT_x_BITS_20_TO_18_0_1_CONCAT_r30_BIT_x_B_ETC___d130 =
{ r30[x[20:18]],
r30[x[19:17]],
r30[x[18:16]],
r30[x[17:15]],
r30_BIT_x_BITS_16_TO_14_8_9_CONCAT_r30_BIT_x_B_ETC___d128 } ;
assign r30_BIT_x_BITS_24_TO_22_2_3_CONCAT_r30_BIT_x_B_ETC___d132 =
{ r30[x[24:22]],
r30[x[23:21]],
r30[x[22:20]],
r30[x[21:19]],
r30_BIT_x_BITS_20_TO_18_0_1_CONCAT_r30_BIT_x_B_ETC___d130 } ;
assign r30_BIT_x_BITS_28_TO_26_4_5_CONCAT_r30_BIT_x_B_ETC___d134 =
{ r30[x[28:26]],
r30[x[27:25]],
r30[x[26:24]],
r30[x[25:23]],
r30_BIT_x_BITS_24_TO_22_2_3_CONCAT_r30_BIT_x_B_ETC___d132 } ;
assign r30_BIT_x_BITS_32_TO_30_6_7_CONCAT_r30_BIT_x_B_ETC___d136 =
{ r30[x[32:30]],
r30[x[31:29]],
r30[x[30:28]],
r30[x[29:27]],
r30_BIT_x_BITS_28_TO_26_4_5_CONCAT_r30_BIT_x_B_ETC___d134 } ;
assign r30_BIT_x_BITS_36_TO_34_8_9_CONCAT_r30_BIT_x_B_ETC___d138 =
{ r30[x[36:34]],
r30[x[35:33]],
r30[x[34:32]],
r30[x[33:31]],
r30_BIT_x_BITS_32_TO_30_6_7_CONCAT_r30_BIT_x_B_ETC___d136 } ;
assign r30_BIT_x_BITS_40_TO_38_0_1_CONCAT_r30_BIT_x_B_ETC___d140 =
{ r30[x[40:38]],
r30[x[39:37]],
r30[x[38:36]],
r30[x[37:35]],
r30_BIT_x_BITS_36_TO_34_8_9_CONCAT_r30_BIT_x_B_ETC___d138 } ;
assign r30_BIT_x_BITS_44_TO_42_2_3_CONCAT_r30_BIT_x_B_ETC___d142 =
{ r30[x[44:42]],
r30[x[43:41]],
r30[x[42:40]],
r30[x[41:39]],
r30_BIT_x_BITS_40_TO_38_0_1_CONCAT_r30_BIT_x_B_ETC___d140 } ;
assign r30_BIT_x_BITS_48_TO_46_4_5_CONCAT_r30_BIT_x_B_ETC___d144 =
{ r30[x[48:46]],
r30[x[47:45]],
r30[x[46:44]],
r30[x[45:43]],
r30_BIT_x_BITS_44_TO_42_2_3_CONCAT_r30_BIT_x_B_ETC___d142 } ;
assign r30_BIT_x_BITS_4_TO_2_12_13_CONCAT_r30_BIT_x_B_ETC___d122 =
{ r30[x[4:2]], r30[x[3:1]], r30[x[2:0]], r30[b0__h167] } ;
assign r30_BIT_x_BITS_52_TO_50_6_7_CONCAT_r30_BIT_x_B_ETC___d146 =
{ r30[x[52:50]],
r30[x[51:49]],
r30[x[50:48]],
r30[x[49:47]],
r30_BIT_x_BITS_48_TO_46_4_5_CONCAT_r30_BIT_x_B_ETC___d144 } ;
assign r30_BIT_x_BITS_8_TO_6_04_05_CONCAT_r30_BIT_x_B_ETC___d124 =
{ r30[x[8:6]],
r30[x[7:5]],
r30[x[6:4]],
r30[x[5:3]],
r30_BIT_x_BITS_4_TO_2_12_13_CONCAT_r30_BIT_x_B_ETC___d122 } ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
busy_flag <= `BSV_ASSIGNMENT_DELAY 1'd0;
r30 <= `BSV_ASSIGNMENT_DELAY 8'd30;
step_complete <= `BSV_ASSIGNMENT_DELAY 1'd0;
x <= `BSV_ASSIGNMENT_DELAY 56'd0;
end
else
begin
if (busy_flag$EN) busy_flag <= `BSV_ASSIGNMENT_DELAY busy_flag$D_IN;
if (r30$EN) r30 <= `BSV_ASSIGNMENT_DELAY r30$D_IN;
if (step_complete$EN)
step_complete <= `BSV_ASSIGNMENT_DELAY step_complete$D_IN;
if (x$EN) x <= `BSV_ASSIGNMENT_DELAY x$D_IN;
end
end
endmodule // mkRule30
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
// N -bit counter with load, set and 2 increment
module Counter(CLK,
RST,
Q_OUT,
DATA_A, ADDA,
DATA_B, ADDB,
DATA_C, SETC,
DATA_F, SETF);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
`ifdef BSV_RESET_FIFO_HEAD
`define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_HEAD
`endif
`ifdef BSV_RESET_FIFO_ARRAY
`define BSV_ARESET_EDGE_ARRAY `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_ARRAY
`endif
// Sized fifo. Model has output register which improves timing
module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR);
parameter p1width = 1; // data width
parameter p2depth = 3;
parameter p3cntr_width = 1; // log(p2depth-1)
// The -1 is allowed since this model has a fast output register
parameter guarded = 1'b1;
localparam p2depth2 = (p2depth >= 2) ? (p2depth -2) : 0 ;
input CLK;
input RST;
input CLR;
input [p1width - 1 : 0] D_IN;
input ENQ;
input DEQ;
output FULL_N;
output EMPTY_N;
output [p1width - 1 : 0] D_OUT;
reg not_ring_full;
reg ring_empty;
reg [p3cntr_width-1 : 0] head;
wire [p3cntr_width-1 : 0] next_head;
reg [p3cntr_width-1 : 0] tail;
wire [p3cntr_width-1 : 0] next_tail;
// if the depth is too small, don't create an ill-sized array;
// instead, make a 1-sized array and let the initial block report an error
reg [p1width - 1 : 0] arr[0: p2depth2];
reg [p1width - 1 : 0] D_OUT;
reg hasodata;
wire [p3cntr_width-1:0] depthLess2 = p2depth2[p3cntr_width-1:0] ;
wire [p3cntr_width-1 : 0] incr_tail;
wire [p3cntr_width-1 : 0] incr_head;
assign incr_tail = tail + 1'b1 ;
assign incr_head = head + 1'b1 ;
assign next_head = (head == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_head ;
assign next_tail = (tail == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_tail ;
assign EMPTY_N = hasodata;
assign FULL_N = not_ring_full;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin : initial_block
integer i;
D_OUT = {((p1width + 1)/2){2'b10}} ;
ring_empty = 1'b1;
not_ring_full = 1'b1;
hasodata = 1'b0;
head = {p3cntr_width {1'b0}} ;
tail = {p3cntr_width {1'b0}} ;
for (i = 0; i <= p2depth2; i = i + 1)
begin
arr[i] = D_OUT ;
end
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
always @(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (RST == `BSV_RESET_VALUE)
else
begin
casez ({CLR, DEQ, ENQ, hasodata, ring_empty})
// Clear operation
5'b1????: begin
head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
// -----------------------
// DEQ && ENQ case -- change head and tail if added to ring
5'b011?0: begin
tail <= `BSV_ASSIGNMENT_DELAY next_tail;
head <= `BSV_ASSIGNMENT_DELAY next_head;
end
// -----------------------
// DEQ only and NO data is in ring
5'b010?1: begin
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
// DEQ only and data is in ring (move the head pointer)
5'b010?0: begin
head <= `BSV_ASSIGNMENT_DELAY next_head;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
ring_empty <= `BSV_ASSIGNMENT_DELAY next_head == tail ;
end
// -----------------------
// ENQ only when empty
5'b0010?: begin
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b1;
end
// ENQ only when not empty
5'b0011?: begin
if ( not_ring_full ) // Drop this test to save redundant test
// but be warnned that with test fifo overflow causes loss of new data
// while without test fifo drops all but head entry! (pointer overflow)
begin
tail <= `BSV_ASSIGNMENT_DELAY next_tail;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b0;
not_ring_full <= `BSV_ASSIGNMENT_DELAY ! (next_tail == head) ;
end
end
endcase
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// Update the fast data out register
always @(posedge CLK `BSV_ARESET_EDGE_HEAD)
begin
`ifdef BSV_RESET_FIFO_HEAD
if (RST == `BSV_RESET_VALUE)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
end // if (RST == `BSV_RESET_VALUE)
else
`endif
begin
casez ({CLR, DEQ, ENQ, hasodata, ring_empty})
// DEQ && ENQ cases
5'b011?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end
5'b011?1: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end
// DEQ only and data is in ring
5'b010?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end
// ENQ only when empty
5'b0010?: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end
endcase
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// Update the memory array reset is OFF
always @(posedge CLK `BSV_ARESET_EDGE_ARRAY)
begin: array
`ifdef BSV_RESET_FIFO_ARRAY
if (RST == `BSV_RESET_VALUE)
begin: rst_array
integer i;
for (i = 0; i <= p2depth2 && p2depth > 2; i = i + 1)
begin
arr[i] <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
end
end // if (RST == `BSV_RESET_VALUE)
else
`endif
begin
if (!CLR && ENQ && ((DEQ && !ring_empty) || (!DEQ && hasodata && not_ring_full)))
begin
arr[tail] <= `BSV_ASSIGNMENT_DELAY D_IN;
end
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if (RST == ! `BSV_RESET_VALUE)
begin
if ( ! EMPTY_N && DEQ )
begin
deqerror = 1 ;
$display( "Warning: SizedFIFO: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && (!DEQ || guarded) )
begin
enqerror = 1 ;
$display( "Warning: SizedFIFO: %m -- Enqueuing to a full fifo" ) ;
end
end
end // block: error_checks
// synopsys translate_on
// synopsys translate_off
// Some assertions about parameter values
initial
begin : parameter_assertions
integer ok ;
ok = 1 ;
if ( p2depth <= 1)
begin
ok = 0;
$display ( "Warning SizedFIFO: %m -- depth parameter increased from %0d to 2", p2depth);
end
if ( p3cntr_width <= 0 )
begin
ok = 0;
$display ( "ERROR SizedFIFO: %m -- width parameter must be greater than 0" ) ;
end
if ( ok == 0 ) $finish ;
end // initial begin
// synopsys translate_on
endmodule
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
`ifdef BSV_RESET_FIFO_HEAD
`define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_HEAD
`endif
// Depth 1 FIFO
module FIFO1(CLK,
RST,
D_IN,
ENQ,
FULL_N,
D_OUT,
DEQ,
EMPTY_N,
CLR
);
parameter width = 1;
parameter guarded = 1'b1;
input CLK;
input RST;
input [width - 1 : 0] D_IN;
input ENQ;
input DEQ;
input CLR ;
output FULL_N;
output [width - 1 : 0] D_OUT;
output EMPTY_N;
reg [width - 1 : 0] D_OUT;
reg empty_reg ;
assign EMPTY_N = empty_reg ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
D_OUT = {((width + 1)/2) {2'b10}} ;
empty_reg = 1'b0 ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
assign FULL_N = !empty_reg;
always@(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (RST == `BSV_RESET_VALUE)
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (CLR)
else if (ENQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // if (ENQ)
else if (DEQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (DEQ)
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
always@(posedge CLK `BSV_ARESET_EDGE_HEAD)
begin
`ifdef BSV_RESET_FIFO_HEAD
if (RST == `BSV_RESET_VALUE)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
end
else
`endif
begin
if (ENQ)
D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN;
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if (RST == ! `BSV_RESET_VALUE)
begin
if ( ! empty_reg && DEQ )
begin
deqerror = 1 ;
$display( "Warning: FIFO1: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && (!DEQ || guarded) )
begin
enqerror = 1 ;
$display( "Warning: FIFO1: %m -- Enqueuing to a full fifo" ) ;
end
end // if (RST == ! `BSV_RESET_VALUE)
end
// synopsys translate_on
endmodule
|
module Counter(CLK,
RST,
Q_OUT,
DATA_A, ADDA,
DATA_B, ADDB,
DATA_C, SETC,
DATA_F, SETF);
parameter width = 1;
parameter init = 0;
input CLK;
input RST;
input [width - 1 : 0] DATA_A;
input ADDA;
input [width - 1 : 0] DATA_B;
input ADDB;
input [width - 1 : 0] DATA_C;
input SETC;
input [width - 1 : 0] DATA_F;
input SETF;
output [width - 1 : 0] Q_OUT;
reg [width - 1 : 0] q_state ;
assign Q_OUT = q_state ;
always@(posedge CLK `BSV_ARESET_EDGE_META) begin
if (RST == `BSV_RESET_VALUE)
q_state <= `BSV_ASSIGNMENT_DELAY init;
else
begin
if ( SETF )
q_state <= `BSV_ASSIGNMENT_DELAY DATA_F ;
else
q_state <= `BSV_ASSIGNMENT_DELAY (SETC ? DATA_C : q_state ) + (ADDA ? DATA_A : {width {1'b0}}) + (ADDB ? DATA_B : {width {1'b0}} ) ;
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK)
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial begin
q_state = {((width + 1)/2){2'b10}} ;
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule
|
tt06-finale_0051
|
tt06-finale
|
andrewtron3000-tt06-verilog-template
|
task_FIFO1
|
tt_um_andrewtron3000
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 andrewtron3000
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_andrewtron3000 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// Held in reset while ena is not set
wire reset_n;
assign reset_n = rst_n & ena;
assign uio_oe = 8'b00000000; // All bidirectional outputs disabled
assign uio_out = 0;
// Assign output
assign uo_out[0] = 0;
assign uo_out[1] = 0;
assign uo_out[2] = 0;
assign uo_out[3] = 0;
assign uo_out[4] = driver_sout; // uo_out[4] is UART TX
assign uo_out[5] = 0;
assign uo_out[6] = 0;
assign uo_out[7] = 0;
// ports of submodule driver
wire driver_sin, driver_sout;
assign driver_sin = 0;
wire startup_input_ready;
wire startup_input_enable;
wire operation_mode_ready;
wire operation_mode_enable;
// submodule rule_30_driver
mkRule30Driver rule_30_driver(.CLK(clk),
.RST_N(reset_n),
.operation_mode_arg(uio_in),
.EN_operation_mode(operation_mode_enable),
.RDY_operation_mode(operation_mode_ready),
.startup_value_v(ui_in),
.EN_startup_value(startup_input_enable),
.RDY_startup_value(startup_input_ready),
.txrx_SIN(driver_sin),
.txrx_SOUT(driver_sout));
assign startup_input_enable = startup_input_ready;
assign operation_mode_enable = operation_mode_ready;
endmodule
//
// Generated by Bluespec Compiler, version 2024.01-1-g4d953407 (build 4d953407)
//
// On Thu Apr 18 23:03:53 EDT 2024
//
//
// Ports:
// Name I/O size props
// RDY_operation_mode O 1
// RDY_startup_value O 1
// txrx_SOUT O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// operation_mode_arg I 8
// startup_value_v I 8
// txrx_SIN I 1 reg
// EN_operation_mode I 1
// EN_startup_value I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkRule30Driver(CLK,
RST_N,
operation_mode_arg,
EN_operation_mode,
RDY_operation_mode,
startup_value_v,
EN_startup_value,
RDY_startup_value,
txrx_SIN,
txrx_SOUT);
input CLK;
input RST_N;
// action method operation_mode
input [7 : 0] operation_mode_arg;
input EN_operation_mode;
output RDY_operation_mode;
// action method startup_value
input [7 : 0] startup_value_v;
input EN_startup_value;
output RDY_startup_value;
// action method txrx_sin
input txrx_SIN;
// value method txrx_sout
output txrx_SOUT;
// signals for module outputs
wire RDY_operation_mode, RDY_startup_value, txrx_SOUT;
// inlined wires
wire uart_fifoXmit_r_enq$whas,
uart_pwRecvCellCountReset$whas,
uart_pwRecvEnableBitCount$whas,
uart_pwRecvResetBitCount$whas,
uart_pwXmitCellCountReset$whas,
uart_pwXmitEnableBitCount$whas,
uart_pwXmitLoadBuffer$whas,
xmas_fsm_start_wire$whas,
xmas_fsm_state_set_pw$whas;
// register a
reg [7 : 0] a;
wire [7 : 0] a$D_IN;
wire a$EN;
// register op_mode
reg op_mode;
wire op_mode$D_IN, op_mode$EN;
// register transmit_state
reg [1 : 0] transmit_state;
wire [1 : 0] transmit_state$D_IN;
wire transmit_state$EN;
// register uart_rRecvBitCount
reg [3 : 0] uart_rRecvBitCount;
wire [3 : 0] uart_rRecvBitCount$D_IN;
wire uart_rRecvBitCount$EN;
// register uart_rRecvCellCount
reg [3 : 0] uart_rRecvCellCount;
wire [3 : 0] uart_rRecvCellCount$D_IN;
wire uart_rRecvCellCount$EN;
// register uart_rRecvData
reg uart_rRecvData;
wire uart_rRecvData$D_IN, uart_rRecvData$EN;
// register uart_rRecvState
reg [2 : 0] uart_rRecvState;
reg [2 : 0] uart_rRecvState$D_IN;
wire uart_rRecvState$EN;
// register uart_rXmitBitCount
reg [3 : 0] uart_rXmitBitCount;
wire [3 : 0] uart_rXmitBitCount$D_IN;
wire uart_rXmitBitCount$EN;
// register uart_rXmitCellCount
reg [3 : 0] uart_rXmitCellCount;
wire [3 : 0] uart_rXmitCellCount$D_IN;
wire uart_rXmitCellCount$EN;
// register uart_rXmitDataOut
reg uart_rXmitDataOut;
reg uart_rXmitDataOut$D_IN;
wire uart_rXmitDataOut$EN;
// register uart_rXmitState
reg [2 : 0] uart_rXmitState;
reg [2 : 0] uart_rXmitState$D_IN;
wire uart_rXmitState$EN;
// register uart_vrRecvBuffer_0
reg uart_vrRecvBuffer_0;
wire uart_vrRecvBuffer_0$D_IN, uart_vrRecvBuffer_0$EN;
// register uart_vrRecvBuffer_1
reg uart_vrRecvBuffer_1;
wire uart_vrRecvBuffer_1$D_IN, uart_vrRecvBuffer_1$EN;
// register uart_vrRecvBuffer_2
reg uart_vrRecvBuffer_2;
wire uart_vrRecvBuffer_2$D_IN, uart_vrRecvBuffer_2$EN;
// register uart_vrRecvBuffer_3
reg uart_vrRecvBuffer_3;
wire uart_vrRecvBuffer_3$D_IN, uart_vrRecvBuffer_3$EN;
// register uart_vrRecvBuffer_4
reg uart_vrRecvBuffer_4;
wire uart_vrRecvBuffer_4$D_IN, uart_vrRecvBuffer_4$EN;
// register uart_vrRecvBuffer_5
reg uart_vrRecvBuffer_5;
wire uart_vrRecvBuffer_5$D_IN, uart_vrRecvBuffer_5$EN;
// register uart_vrRecvBuffer_6
reg uart_vrRecvBuffer_6;
wire uart_vrRecvBuffer_6$D_IN, uart_vrRecvBuffer_6$EN;
// register uart_vrRecvBuffer_7
reg uart_vrRecvBuffer_7;
wire uart_vrRecvBuffer_7$D_IN, uart_vrRecvBuffer_7$EN;
// register uart_vrXmitBuffer_0
reg uart_vrXmitBuffer_0;
wire uart_vrXmitBuffer_0$D_IN, uart_vrXmitBuffer_0$EN;
// register uart_vrXmitBuffer_1
reg uart_vrXmitBuffer_1;
wire uart_vrXmitBuffer_1$D_IN, uart_vrXmitBuffer_1$EN;
// register uart_vrXmitBuffer_2
reg uart_vrXmitBuffer_2;
wire uart_vrXmitBuffer_2$D_IN, uart_vrXmitBuffer_2$EN;
// register uart_vrXmitBuffer_3
reg uart_vrXmitBuffer_3;
wire uart_vrXmitBuffer_3$D_IN, uart_vrXmitBuffer_3$EN;
// register uart_vrXmitBuffer_4
reg uart_vrXmitBuffer_4;
wire uart_vrXmitBuffer_4$D_IN, uart_vrXmitBuffer_4$EN;
// register uart_vrXmitBuffer_5
reg uart_vrXmitBuffer_5;
wire uart_vrXmitBuffer_5$D_IN, uart_vrXmitBuffer_5$EN;
// register uart_vrXmitBuffer_6
reg uart_vrXmitBuffer_6;
wire uart_vrXmitBuffer_6$D_IN, uart_vrXmitBuffer_6$EN;
// register uart_vrXmitBuffer_7
reg uart_vrXmitBuffer_7;
wire uart_vrXmitBuffer_7$D_IN, uart_vrXmitBuffer_7$EN;
// register xmas_fsm_start_reg
reg xmas_fsm_start_reg;
wire xmas_fsm_start_reg$D_IN, xmas_fsm_start_reg$EN;
// register xmas_fsm_start_reg_1
reg xmas_fsm_start_reg_1;
wire xmas_fsm_start_reg_1$D_IN, xmas_fsm_start_reg_1$EN;
// register xmas_fsm_state_fired
reg xmas_fsm_state_fired;
wire xmas_fsm_state_fired$D_IN, xmas_fsm_state_fired$EN;
// register xmas_fsm_state_mkFSMstate
reg [4 : 0] xmas_fsm_state_mkFSMstate;
reg [4 : 0] xmas_fsm_state_mkFSMstate$D_IN;
wire xmas_fsm_state_mkFSMstate$EN;
// ports of submodule rule30
wire [7 : 0] rule30$getResult, rule30$start_a;
wire rule30$EN_getResult,
rule30$EN_start,
rule30$RDY_getResult,
rule30$RDY_start;
// ports of submodule uart_baudGen_rBaudCounter
wire [15 : 0] uart_baudGen_rBaudCounter$DATA_A,
uart_baudGen_rBaudCounter$DATA_B,
uart_baudGen_rBaudCounter$DATA_C,
uart_baudGen_rBaudCounter$DATA_F,
uart_baudGen_rBaudCounter$Q_OUT;
wire uart_baudGen_rBaudCounter$ADDA,
uart_baudGen_rBaudCounter$ADDB,
uart_baudGen_rBaudCounter$SETC,
uart_baudGen_rBaudCounter$SETF;
// ports of submodule uart_baudGen_rBaudTickCounter
wire [2 : 0] uart_baudGen_rBaudTickCounter$DATA_A,
uart_baudGen_rBaudTickCounter$DATA_B,
uart_baudGen_rBaudTickCounter$DATA_C,
uart_baudGen_rBaudTickCounter$DATA_F,
uart_baudGen_rBaudTickCounter$Q_OUT;
wire uart_baudGen_rBaudTickCounter$ADDA,
uart_baudGen_rBaudTickCounter$ADDB,
uart_baudGen_rBaudTickCounter$SETC,
uart_baudGen_rBaudTickCounter$SETF;
// ports of submodule uart_fifoRecv
wire [7 : 0] uart_fifoRecv$D_IN;
wire uart_fifoRecv$CLR,
uart_fifoRecv$DEQ,
uart_fifoRecv$EMPTY_N,
uart_fifoRecv$ENQ;
// ports of submodule uart_fifoXmit
reg [7 : 0] uart_fifoXmit$D_IN;
wire [7 : 0] uart_fifoXmit$D_OUT;
wire uart_fifoXmit$CLR,
uart_fifoXmit$DEQ,
uart_fifoXmit$EMPTY_N,
uart_fifoXmit$ENQ,
uart_fifoXmit$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_compute,
CAN_FIRE_RL_dump_rx,
CAN_FIRE_RL_get_result,
CAN_FIRE_RL_uart_baudGen_assert_2x_baud_tick,
CAN_FIRE_RL_uart_baudGen_baud_count_wire,
CAN_FIRE_RL_uart_baudGen_baud_tick_count_wire,
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x,
CAN_FIRE_RL_uart_baud_generator_clock_enable,
CAN_FIRE_RL_uart_fifoRecv__updateLevelCounter,
CAN_FIRE_RL_uart_fifoXmit__updateLevelCounter,
CAN_FIRE_RL_uart_receive_bit_cell_time_counter,
CAN_FIRE_RL_uart_receive_bit_counter,
CAN_FIRE_RL_uart_receive_buffer_shift,
CAN_FIRE_RL_uart_receive_find_center_of_bit_cell,
CAN_FIRE_RL_uart_receive_parity_bit,
CAN_FIRE_RL_uart_receive_sample_pin,
CAN_FIRE_RL_uart_receive_stop_first_bit,
CAN_FIRE_RL_uart_receive_stop_last_bit,
CAN_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample,
CAN_FIRE_RL_uart_receive_wait_for_start_bit,
CAN_FIRE_RL_uart_transmit_bit_cell_time_counter,
CAN_FIRE_RL_uart_transmit_bit_counter,
CAN_FIRE_RL_uart_transmit_buffer_load,
CAN_FIRE_RL_uart_transmit_buffer_shift,
CAN_FIRE_RL_uart_transmit_send_parity_bit,
CAN_FIRE_RL_uart_transmit_send_start_bit,
CAN_FIRE_RL_uart_transmit_send_stop_bit,
CAN_FIRE_RL_uart_transmit_send_stop_bit1_5,
CAN_FIRE_RL_uart_transmit_send_stop_bit2,
CAN_FIRE_RL_uart_transmit_shift_next_bit,
CAN_FIRE_RL_uart_transmit_wait_1_bit_cell_time,
CAN_FIRE_RL_uart_transmit_wait_for_start_command,
CAN_FIRE_RL_xmas_fsm_action_l42c32,
CAN_FIRE_RL_xmas_fsm_action_l43c32,
CAN_FIRE_RL_xmas_fsm_action_l44c32,
CAN_FIRE_RL_xmas_fsm_action_l45c32,
CAN_FIRE_RL_xmas_fsm_action_l46c32,
CAN_FIRE_RL_xmas_fsm_action_l47c32,
CAN_FIRE_RL_xmas_fsm_action_l48c32,
CAN_FIRE_RL_xmas_fsm_action_l49c32,
CAN_FIRE_RL_xmas_fsm_action_l50c32,
CAN_FIRE_RL_xmas_fsm_action_l51c32,
CAN_FIRE_RL_xmas_fsm_action_l52c32,
CAN_FIRE_RL_xmas_fsm_action_l53c32,
CAN_FIRE_RL_xmas_fsm_action_l54c32,
CAN_FIRE_RL_xmas_fsm_action_l55c32,
CAN_FIRE_RL_xmas_fsm_action_l56c32,
CAN_FIRE_RL_xmas_fsm_action_l57c32,
CAN_FIRE_RL_xmas_fsm_action_l58c32,
CAN_FIRE_RL_xmas_fsm_action_l59c32,
CAN_FIRE_RL_xmas_fsm_action_l60c32,
CAN_FIRE_RL_xmas_fsm_action_l61c32,
CAN_FIRE_RL_xmas_fsm_action_l62c32,
CAN_FIRE_RL_xmas_fsm_action_l63c32,
CAN_FIRE_RL_xmas_fsm_action_l64c32,
CAN_FIRE_RL_xmas_fsm_action_l65c32,
CAN_FIRE_RL_xmas_fsm_action_l66c32,
CAN_FIRE_RL_xmas_fsm_fsm_start,
CAN_FIRE_RL_xmas_fsm_idle_l40c27,
CAN_FIRE_RL_xmas_fsm_idle_l40c27_1,
CAN_FIRE_RL_xmas_fsm_restart,
CAN_FIRE_RL_xmas_fsm_start_reg__dreg_update,
CAN_FIRE_RL_xmas_fsm_state_every,
CAN_FIRE_RL_xmas_fsm_state_fired__dreg_update,
CAN_FIRE_RL_xmas_fsm_state_handle_abort,
CAN_FIRE___me_check_34,
CAN_FIRE___me_check_35,
CAN_FIRE___me_check_36,
CAN_FIRE___me_check_37,
CAN_FIRE___me_check_38,
CAN_FIRE___me_check_39,
CAN_FIRE___me_check_40,
CAN_FIRE___me_check_41,
CAN_FIRE___me_check_42,
CAN_FIRE___me_check_43,
CAN_FIRE___me_check_44,
CAN_FIRE___me_check_45,
CAN_FIRE___me_check_46,
CAN_FIRE___me_check_47,
CAN_FIRE___me_check_48,
CAN_FIRE___me_check_49,
CAN_FIRE___me_check_50,
CAN_FIRE___me_check_51,
CAN_FIRE___me_check_52,
CAN_FIRE___me_check_53,
CAN_FIRE___me_check_54,
CAN_FIRE___me_check_55,
CAN_FIRE___me_check_56,
CAN_FIRE___me_check_57,
CAN_FIRE_operation_mode,
CAN_FIRE_startup_value,
CAN_FIRE_txrx_sin,
WILL_FIRE_RL_compute,
WILL_FIRE_RL_dump_rx,
WILL_FIRE_RL_get_result,
WILL_FIRE_RL_uart_baudGen_assert_2x_baud_tick,
WILL_FIRE_RL_uart_baudGen_baud_count_wire,
WILL_FIRE_RL_uart_baudGen_baud_tick_count_wire,
WILL_FIRE_RL_uart_baudGen_count_baudtick_16x,
WILL_FIRE_RL_uart_baud_generator_clock_enable,
WILL_FIRE_RL_uart_fifoRecv__updateLevelCounter,
WILL_FIRE_RL_uart_fifoXmit__updateLevelCounter,
WILL_FIRE_RL_uart_receive_bit_cell_time_counter,
WILL_FIRE_RL_uart_receive_bit_counter,
WILL_FIRE_RL_uart_receive_buffer_shift,
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell,
WILL_FIRE_RL_uart_receive_parity_bit,
WILL_FIRE_RL_uart_receive_sample_pin,
WILL_FIRE_RL_uart_receive_stop_first_bit,
WILL_FIRE_RL_uart_receive_stop_last_bit,
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample,
WILL_FIRE_RL_uart_receive_wait_for_start_bit,
WILL_FIRE_RL_uart_transmit_bit_cell_time_counter,
WILL_FIRE_RL_uart_transmit_bit_counter,
WILL_FIRE_RL_uart_transmit_buffer_load,
WILL_FIRE_RL_uart_transmit_buffer_shift,
WILL_FIRE_RL_uart_transmit_send_parity_bit,
WILL_FIRE_RL_uart_transmit_send_start_bit,
WILL_FIRE_RL_uart_transmit_send_stop_bit,
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5,
WILL_FIRE_RL_uart_transmit_send_stop_bit2,
WILL_FIRE_RL_uart_transmit_shift_next_bit,
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time,
WILL_FIRE_RL_uart_transmit_wait_for_start_command,
WILL_FIRE_RL_xmas_fsm_action_l42c32,
WILL_FIRE_RL_xmas_fsm_action_l43c32,
WILL_FIRE_RL_xmas_fsm_action_l44c32,
WILL_FIRE_RL_xmas_fsm_action_l45c32,
WILL_FIRE_RL_xmas_fsm_action_l46c32,
WILL_FIRE_RL_xmas_fsm_action_l47c32,
WILL_FIRE_RL_xmas_fsm_action_l48c32,
WILL_FIRE_RL_xmas_fsm_action_l49c32,
WILL_FIRE_RL_xmas_fsm_action_l50c32,
WILL_FIRE_RL_xmas_fsm_action_l51c32,
WILL_FIRE_RL_xmas_fsm_action_l52c32,
WILL_FIRE_RL_xmas_fsm_action_l53c32,
WILL_FIRE_RL_xmas_fsm_action_l54c32,
WILL_FIRE_RL_xmas_fsm_action_l55c32,
WILL_FIRE_RL_xmas_fsm_action_l56c32,
WILL_FIRE_RL_xmas_fsm_action_l57c32,
WILL_FIRE_RL_xmas_fsm_action_l58c32,
WILL_FIRE_RL_xmas_fsm_action_l59c32,
WILL_FIRE_RL_xmas_fsm_action_l60c32,
WILL_FIRE_RL_xmas_fsm_action_l61c32,
WILL_FIRE_RL_xmas_fsm_action_l62c32,
WILL_FIRE_RL_xmas_fsm_action_l63c32,
WILL_FIRE_RL_xmas_fsm_action_l64c32,
WILL_FIRE_RL_xmas_fsm_action_l65c32,
WILL_FIRE_RL_xmas_fsm_action_l66c32,
WILL_FIRE_RL_xmas_fsm_fsm_start,
WILL_FIRE_RL_xmas_fsm_idle_l40c27,
WILL_FIRE_RL_xmas_fsm_idle_l40c27_1,
WILL_FIRE_RL_xmas_fsm_restart,
WILL_FIRE_RL_xmas_fsm_start_reg__dreg_update,
WILL_FIRE_RL_xmas_fsm_state_every,
WILL_FIRE_RL_xmas_fsm_state_fired__dreg_update,
WILL_FIRE_RL_xmas_fsm_state_handle_abort,
WILL_FIRE___me_check_34,
WILL_FIRE___me_check_35,
WILL_FIRE___me_check_36,
WILL_FIRE___me_check_37,
WILL_FIRE___me_check_38,
WILL_FIRE___me_check_39,
WILL_FIRE___me_check_40,
WILL_FIRE___me_check_41,
WILL_FIRE___me_check_42,
WILL_FIRE___me_check_43,
WILL_FIRE___me_check_44,
WILL_FIRE___me_check_45,
WILL_FIRE___me_check_46,
WILL_FIRE___me_check_47,
WILL_FIRE___me_check_48,
WILL_FIRE___me_check_49,
WILL_FIRE___me_check_50,
WILL_FIRE___me_check_51,
WILL_FIRE___me_check_52,
WILL_FIRE___me_check_53,
WILL_FIRE___me_check_54,
WILL_FIRE___me_check_55,
WILL_FIRE___me_check_56,
WILL_FIRE___me_check_57,
WILL_FIRE_operation_mode,
WILL_FIRE_startup_value,
WILL_FIRE_txrx_sin;
// inputs to muxes for submodule ports
reg [2 : 0] MUX_uart_rRecvState$write_1__VAL_3;
wire [2 : 0] MUX_uart_rRecvState$write_1__VAL_1,
MUX_uart_rRecvState$write_1__VAL_2,
MUX_uart_rRecvState$write_1__VAL_4,
MUX_uart_rXmitState$write_1__VAL_1,
MUX_uart_rXmitState$write_1__VAL_2,
MUX_uart_rXmitState$write_1__VAL_3,
MUX_uart_rXmitState$write_1__VAL_4,
MUX_uart_rXmitState$write_1__VAL_5,
MUX_uart_rXmitState$write_1__VAL_6,
MUX_uart_rXmitState$write_1__VAL_7;
wire MUX_transmit_state$write_1__SEL_1,
MUX_uart_fifoXmit$enq_1__SEL_11,
MUX_uart_fifoXmit$enq_1__SEL_15,
MUX_uart_fifoXmit$enq_1__SEL_16,
MUX_uart_fifoXmit$enq_1__SEL_17,
MUX_uart_fifoXmit$enq_1__SEL_2,
MUX_uart_fifoXmit$enq_1__SEL_3,
MUX_uart_rRecvState$write_1__SEL_6,
MUX_uart_rXmitDataOut$write_1__SEL_1,
MUX_uart_rXmitDataOut$write_1__SEL_2,
MUX_uart_rXmitDataOut$write_1__SEL_3,
MUX_xmas_fsm_start_reg$write_1__SEL_1,
MUX_xmas_fsm_state_mkFSMstate$write_1__SEL_1;
// remaining internal signals
wire [3 : 0] x__h2985, x__h4689, x__h6445, x__h6471;
wire _dor2uart_pwXmitCellCountReset$EN_wset,
uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29,
xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302;
// action method operation_mode
assign RDY_operation_mode =
transmit_state == 2'd0 && !op_mode &&
xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302 &&
!xmas_fsm_start_reg ;
assign CAN_FIRE_operation_mode =
transmit_state == 2'd0 && !op_mode &&
xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302 &&
!xmas_fsm_start_reg ;
assign WILL_FIRE_operation_mode = EN_operation_mode ;
// action method startup_value
assign RDY_startup_value = transmit_state == 2'd0 && !op_mode ;
assign CAN_FIRE_startup_value = transmit_state == 2'd0 && !op_mode ;
assign WILL_FIRE_startup_value = EN_startup_value ;
// action method txrx_sin
assign CAN_FIRE_txrx_sin = 1'd1 ;
assign WILL_FIRE_txrx_sin = 1'd1 ;
// value method txrx_sout
assign txrx_SOUT = uart_rXmitDataOut ;
// submodule rule30
mkRule30 rule30(.CLK(CLK),
.RST_N(RST_N),
.start_a(rule30$start_a),
.EN_start(rule30$EN_start),
.EN_getResult(rule30$EN_getResult),
.RDY_start(rule30$RDY_start),
.getResult(rule30$getResult),
.RDY_getResult(rule30$RDY_getResult));
// submodule uart_baudGen_rBaudCounter
Counter #(.width(32'd16), .init(16'd0)) uart_baudGen_rBaudCounter(.CLK(CLK),
.RST(RST_N),
.DATA_A(uart_baudGen_rBaudCounter$DATA_A),
.DATA_B(uart_baudGen_rBaudCounter$DATA_B),
.DATA_C(uart_baudGen_rBaudCounter$DATA_C),
.DATA_F(uart_baudGen_rBaudCounter$DATA_F),
.ADDA(uart_baudGen_rBaudCounter$ADDA),
.ADDB(uart_baudGen_rBaudCounter$ADDB),
.SETC(uart_baudGen_rBaudCounter$SETC),
.SETF(uart_baudGen_rBaudCounter$SETF),
.Q_OUT(uart_baudGen_rBaudCounter$Q_OUT));
// submodule uart_baudGen_rBaudTickCounter
Counter #(.width(32'd3),
.init(3'd0)) uart_baudGen_rBaudTickCounter(.CLK(CLK),
.RST(RST_N),
.DATA_A(uart_baudGen_rBaudTickCounter$DATA_A),
.DATA_B(uart_baudGen_rBaudTickCounter$DATA_B),
.DATA_C(uart_baudGen_rBaudTickCounter$DATA_C),
.DATA_F(uart_baudGen_rBaudTickCounter$DATA_F),
.ADDA(uart_baudGen_rBaudTickCounter$ADDA),
.ADDB(uart_baudGen_rBaudTickCounter$ADDB),
.SETC(uart_baudGen_rBaudTickCounter$SETC),
.SETF(uart_baudGen_rBaudTickCounter$SETF),
.Q_OUT(uart_baudGen_rBaudTickCounter$Q_OUT));
// submodule uart_fifoRecv
SizedFIFO #(.p1width(32'd8),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(1'd1)) uart_fifoRecv(.RST(RST_N),
.CLK(CLK),
.D_IN(uart_fifoRecv$D_IN),
.ENQ(uart_fifoRecv$ENQ),
.DEQ(uart_fifoRecv$DEQ),
.CLR(uart_fifoRecv$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N(uart_fifoRecv$EMPTY_N));
// submodule uart_fifoXmit
SizedFIFO #(.p1width(32'd8),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(1'd1)) uart_fifoXmit(.RST(RST_N),
.CLK(CLK),
.D_IN(uart_fifoXmit$D_IN),
.ENQ(uart_fifoXmit$ENQ),
.DEQ(uart_fifoXmit$DEQ),
.CLR(uart_fifoXmit$CLR),
.D_OUT(uart_fifoXmit$D_OUT),
.FULL_N(uart_fifoXmit$FULL_N),
.EMPTY_N(uart_fifoXmit$EMPTY_N));
// rule RL_dump_rx
assign CAN_FIRE_RL_dump_rx = uart_fifoRecv$EMPTY_N ;
assign WILL_FIRE_RL_dump_rx = uart_fifoRecv$EMPTY_N ;
// rule RL_compute
assign CAN_FIRE_RL_compute =
rule30$RDY_start && transmit_state == 2'd1 && !op_mode ;
assign WILL_FIRE_RL_compute = CAN_FIRE_RL_compute ;
// rule RL_uart_baudGen_baud_count_wire
assign CAN_FIRE_RL_uart_baudGen_baud_count_wire = 1'd1 ;
assign WILL_FIRE_RL_uart_baudGen_baud_count_wire = 1'd1 ;
// rule RL_uart_baud_generator_clock_enable
assign CAN_FIRE_RL_uart_baud_generator_clock_enable = 1'd1 ;
assign WILL_FIRE_RL_uart_baud_generator_clock_enable = 1'd1 ;
// rule RL_uart_receive_wait_for_start_bit
assign CAN_FIRE_RL_uart_receive_wait_for_start_bit =
uart_rRecvState == 3'd0 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_wait_for_start_bit =
CAN_FIRE_RL_uart_receive_wait_for_start_bit ;
// rule RL_uart_receive_find_center_of_bit_cell
assign CAN_FIRE_RL_uart_receive_find_center_of_bit_cell =
uart_rRecvState == 3'd1 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_find_center_of_bit_cell =
CAN_FIRE_RL_uart_receive_find_center_of_bit_cell ;
// rule RL_uart_receive_wait_bit_cell_time_for_sample
assign CAN_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample =
uart_rRecvState == 3'd2 && uart_rRecvCellCount == 4'hF &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample =
CAN_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample ;
// rule RL_uart_receive_sample_pin
assign CAN_FIRE_RL_uart_receive_sample_pin =
CAN_FIRE_RL_uart_receive_buffer_shift ;
assign WILL_FIRE_RL_uart_receive_sample_pin =
CAN_FIRE_RL_uart_receive_buffer_shift ;
// rule RL_uart_receive_parity_bit
assign CAN_FIRE_RL_uart_receive_parity_bit =
uart_rRecvState == 3'd4 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_parity_bit =
CAN_FIRE_RL_uart_receive_parity_bit ;
// rule RL_uart_receive_stop_first_bit
assign CAN_FIRE_RL_uart_receive_stop_first_bit =
uart_rRecvState == 3'd5 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_stop_first_bit =
CAN_FIRE_RL_uart_receive_stop_first_bit ;
// rule RL_uart_receive_bit_counter
assign CAN_FIRE_RL_uart_receive_bit_counter = 1'd1 ;
assign WILL_FIRE_RL_uart_receive_bit_counter = 1'd1 ;
// rule RL_uart_receive_stop_last_bit
assign CAN_FIRE_RL_uart_receive_stop_last_bit =
uart_rRecvState == 3'd6 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_stop_last_bit =
CAN_FIRE_RL_uart_receive_stop_last_bit ;
// rule RL_uart_receive_bit_cell_time_counter
assign CAN_FIRE_RL_uart_receive_bit_cell_time_counter =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
assign WILL_FIRE_RL_uart_receive_bit_cell_time_counter =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// rule RL_uart_receive_buffer_shift
assign CAN_FIRE_RL_uart_receive_buffer_shift =
uart_rRecvState == 3'd3 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_buffer_shift =
CAN_FIRE_RL_uart_receive_buffer_shift ;
// rule RL_uart_transmit_wait_for_start_command
assign CAN_FIRE_RL_uart_transmit_wait_for_start_command =
uart_rXmitState == 3'd0 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_wait_for_start_command =
CAN_FIRE_RL_uart_transmit_wait_for_start_command ;
// rule RL_get_result
assign CAN_FIRE_RL_get_result =
rule30$RDY_getResult && uart_fifoXmit$FULL_N &&
transmit_state == 2'd2 &&
!op_mode &&
xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302 &&
!xmas_fsm_start_reg ;
assign WILL_FIRE_RL_get_result = CAN_FIRE_RL_get_result ;
// rule RL_uart_transmit_send_start_bit
assign CAN_FIRE_RL_uart_transmit_send_start_bit =
uart_rXmitState == 3'd1 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_start_bit =
CAN_FIRE_RL_uart_transmit_send_start_bit ;
// rule RL_uart_transmit_wait_1_bit_cell_time
assign CAN_FIRE_RL_uart_transmit_wait_1_bit_cell_time =
uart_rXmitState == 3'd2 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time =
CAN_FIRE_RL_uart_transmit_wait_1_bit_cell_time ;
// rule RL_uart_transmit_bit_counter
assign CAN_FIRE_RL_uart_transmit_bit_counter = 1'd1 ;
assign WILL_FIRE_RL_uart_transmit_bit_counter = 1'd1 ;
// rule RL_uart_transmit_shift_next_bit
assign CAN_FIRE_RL_uart_transmit_shift_next_bit =
uart_rXmitState == 3'd3 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_shift_next_bit =
CAN_FIRE_RL_uart_transmit_shift_next_bit ;
// rule RL_uart_transmit_buffer_load
assign CAN_FIRE_RL_uart_transmit_buffer_load =
uart_fifoXmit$EMPTY_N && uart_pwXmitLoadBuffer$whas ;
assign WILL_FIRE_RL_uart_transmit_buffer_load =
CAN_FIRE_RL_uart_transmit_buffer_load ;
// rule RL_uart_transmit_buffer_shift
assign CAN_FIRE_RL_uart_transmit_buffer_shift =
!uart_pwXmitLoadBuffer$whas &&
CAN_FIRE_RL_uart_transmit_shift_next_bit ;
assign WILL_FIRE_RL_uart_transmit_buffer_shift =
CAN_FIRE_RL_uart_transmit_buffer_shift ;
// rule RL_uart_transmit_send_parity_bit
assign CAN_FIRE_RL_uart_transmit_send_parity_bit =
uart_rXmitState == 3'd7 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_parity_bit =
CAN_FIRE_RL_uart_transmit_send_parity_bit ;
// rule RL_uart_transmit_send_stop_bit
assign CAN_FIRE_RL_uart_transmit_send_stop_bit =
uart_rXmitState == 3'd4 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_stop_bit =
CAN_FIRE_RL_uart_transmit_send_stop_bit ;
// rule RL_uart_transmit_send_stop_bit1_5
assign CAN_FIRE_RL_uart_transmit_send_stop_bit1_5 =
uart_rXmitState == 3'd5 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 =
CAN_FIRE_RL_uart_transmit_send_stop_bit1_5 ;
// rule RL_uart_transmit_send_stop_bit2
assign CAN_FIRE_RL_uart_transmit_send_stop_bit2 =
uart_rXmitState == 3'd6 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_stop_bit2 =
CAN_FIRE_RL_uart_transmit_send_stop_bit2 ;
// rule RL_uart_transmit_bit_cell_time_counter
assign CAN_FIRE_RL_uart_transmit_bit_cell_time_counter =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
assign WILL_FIRE_RL_uart_transmit_bit_cell_time_counter =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// rule RL_uart_baudGen_baud_tick_count_wire
assign CAN_FIRE_RL_uart_baudGen_baud_tick_count_wire = 1'd1 ;
assign WILL_FIRE_RL_uart_baudGen_baud_tick_count_wire = 1'd1 ;
// rule RL_uart_baudGen_assert_2x_baud_tick
assign CAN_FIRE_RL_uart_baudGen_assert_2x_baud_tick =
uart_baudGen_rBaudTickCounter$Q_OUT == 3'd0 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_baudGen_assert_2x_baud_tick =
CAN_FIRE_RL_uart_baudGen_assert_2x_baud_tick ;
// rule RL_uart_baudGen_count_baudtick_16x
assign CAN_FIRE_RL_uart_baudGen_count_baudtick_16x =
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_baudGen_count_baudtick_16x =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// rule RL_uart_fifoRecv__updateLevelCounter
assign CAN_FIRE_RL_uart_fifoRecv__updateLevelCounter =
CAN_FIRE_RL_uart_receive_stop_last_bit != uart_fifoRecv$EMPTY_N ;
assign WILL_FIRE_RL_uart_fifoRecv__updateLevelCounter =
CAN_FIRE_RL_uart_fifoRecv__updateLevelCounter ;
// rule RL_xmas_fsm_restart
assign CAN_FIRE_RL_xmas_fsm_restart =
xmas_fsm_start_reg_1 && !xmas_fsm_state_fired ;
assign WILL_FIRE_RL_xmas_fsm_restart = CAN_FIRE_RL_xmas_fsm_restart ;
// rule RL_xmas_fsm_action_l43c32
assign CAN_FIRE_RL_xmas_fsm_action_l43c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd1 ;
assign WILL_FIRE_RL_xmas_fsm_action_l43c32 =
CAN_FIRE_RL_xmas_fsm_action_l43c32 ;
// rule RL_xmas_fsm_action_l44c32
assign CAN_FIRE_RL_xmas_fsm_action_l44c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd2 ;
assign WILL_FIRE_RL_xmas_fsm_action_l44c32 =
CAN_FIRE_RL_xmas_fsm_action_l44c32 ;
// rule RL_xmas_fsm_action_l45c32
assign CAN_FIRE_RL_xmas_fsm_action_l45c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd3 ;
assign WILL_FIRE_RL_xmas_fsm_action_l45c32 =
CAN_FIRE_RL_xmas_fsm_action_l45c32 ;
// rule RL_xmas_fsm_action_l46c32
assign CAN_FIRE_RL_xmas_fsm_action_l46c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd4 ;
assign WILL_FIRE_RL_xmas_fsm_action_l46c32 =
CAN_FIRE_RL_xmas_fsm_action_l46c32 ;
// rule RL_xmas_fsm_action_l47c32
assign CAN_FIRE_RL_xmas_fsm_action_l47c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd5 ;
assign WILL_FIRE_RL_xmas_fsm_action_l47c32 =
CAN_FIRE_RL_xmas_fsm_action_l47c32 ;
// rule RL_xmas_fsm_action_l48c32
assign CAN_FIRE_RL_xmas_fsm_action_l48c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd6 ;
assign WILL_FIRE_RL_xmas_fsm_action_l48c32 =
CAN_FIRE_RL_xmas_fsm_action_l48c32 ;
// rule RL_xmas_fsm_action_l49c32
assign CAN_FIRE_RL_xmas_fsm_action_l49c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd7 ;
assign WILL_FIRE_RL_xmas_fsm_action_l49c32 =
CAN_FIRE_RL_xmas_fsm_action_l49c32 ;
// rule RL_xmas_fsm_action_l50c32
assign CAN_FIRE_RL_xmas_fsm_action_l50c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd8 ;
assign WILL_FIRE_RL_xmas_fsm_action_l50c32 =
CAN_FIRE_RL_xmas_fsm_action_l50c32 ;
// rule RL_xmas_fsm_action_l51c32
assign CAN_FIRE_RL_xmas_fsm_action_l51c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd9 ;
assign WILL_FIRE_RL_xmas_fsm_action_l51c32 =
CAN_FIRE_RL_xmas_fsm_action_l51c32 ;
// rule RL_xmas_fsm_action_l52c32
assign CAN_FIRE_RL_xmas_fsm_action_l52c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd10 ;
assign WILL_FIRE_RL_xmas_fsm_action_l52c32 =
CAN_FIRE_RL_xmas_fsm_action_l52c32 ;
// rule RL_xmas_fsm_action_l53c32
assign CAN_FIRE_RL_xmas_fsm_action_l53c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd11 ;
assign WILL_FIRE_RL_xmas_fsm_action_l53c32 =
CAN_FIRE_RL_xmas_fsm_action_l53c32 ;
// rule RL_xmas_fsm_action_l54c32
assign CAN_FIRE_RL_xmas_fsm_action_l54c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd12 ;
assign WILL_FIRE_RL_xmas_fsm_action_l54c32 =
CAN_FIRE_RL_xmas_fsm_action_l54c32 ;
// rule RL_xmas_fsm_action_l55c32
assign CAN_FIRE_RL_xmas_fsm_action_l55c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd13 ;
assign WILL_FIRE_RL_xmas_fsm_action_l55c32 =
CAN_FIRE_RL_xmas_fsm_action_l55c32 ;
// rule RL_xmas_fsm_action_l56c32
assign CAN_FIRE_RL_xmas_fsm_action_l56c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd14 ;
assign WILL_FIRE_RL_xmas_fsm_action_l56c32 =
CAN_FIRE_RL_xmas_fsm_action_l56c32 ;
// rule RL_xmas_fsm_action_l57c32
assign CAN_FIRE_RL_xmas_fsm_action_l57c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd15 ;
assign WILL_FIRE_RL_xmas_fsm_action_l57c32 =
CAN_FIRE_RL_xmas_fsm_action_l57c32 ;
// rule RL_xmas_fsm_action_l58c32
assign CAN_FIRE_RL_xmas_fsm_action_l58c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd16 ;
assign WILL_FIRE_RL_xmas_fsm_action_l58c32 =
CAN_FIRE_RL_xmas_fsm_action_l58c32 ;
// rule RL_xmas_fsm_action_l59c32
assign CAN_FIRE_RL_xmas_fsm_action_l59c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd17 ;
assign WILL_FIRE_RL_xmas_fsm_action_l59c32 =
CAN_FIRE_RL_xmas_fsm_action_l59c32 ;
// rule RL_xmas_fsm_action_l60c32
assign CAN_FIRE_RL_xmas_fsm_action_l60c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd18 ;
assign WILL_FIRE_RL_xmas_fsm_action_l60c32 =
CAN_FIRE_RL_xmas_fsm_action_l60c32 ;
// rule RL_xmas_fsm_action_l61c32
assign CAN_FIRE_RL_xmas_fsm_action_l61c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd19 ;
assign WILL_FIRE_RL_xmas_fsm_action_l61c32 =
CAN_FIRE_RL_xmas_fsm_action_l61c32 ;
// rule RL_xmas_fsm_action_l62c32
assign CAN_FIRE_RL_xmas_fsm_action_l62c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd20 ;
assign WILL_FIRE_RL_xmas_fsm_action_l62c32 =
CAN_FIRE_RL_xmas_fsm_action_l62c32 ;
// rule RL_xmas_fsm_action_l63c32
assign CAN_FIRE_RL_xmas_fsm_action_l63c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd21 ;
assign WILL_FIRE_RL_xmas_fsm_action_l63c32 =
CAN_FIRE_RL_xmas_fsm_action_l63c32 ;
// rule RL_xmas_fsm_action_l64c32
assign CAN_FIRE_RL_xmas_fsm_action_l64c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd22 ;
assign WILL_FIRE_RL_xmas_fsm_action_l64c32 =
CAN_FIRE_RL_xmas_fsm_action_l64c32 ;
// rule RL_xmas_fsm_action_l65c32
assign CAN_FIRE_RL_xmas_fsm_action_l65c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd23 ;
assign WILL_FIRE_RL_xmas_fsm_action_l65c32 =
CAN_FIRE_RL_xmas_fsm_action_l65c32 ;
// rule RL_xmas_fsm_action_l66c32
assign CAN_FIRE_RL_xmas_fsm_action_l66c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd24 ;
assign WILL_FIRE_RL_xmas_fsm_action_l66c32 =
CAN_FIRE_RL_xmas_fsm_action_l66c32 ;
// rule __me_check_35
assign CAN_FIRE___me_check_35 = 1'b1 ;
assign WILL_FIRE___me_check_35 = 1'b1 ;
// rule __me_check_36
assign CAN_FIRE___me_check_36 = 1'b1 ;
assign WILL_FIRE___me_check_36 = 1'b1 ;
// rule __me_check_37
assign CAN_FIRE___me_check_37 = 1'b1 ;
assign WILL_FIRE___me_check_37 = 1'b1 ;
// rule __me_check_38
assign CAN_FIRE___me_check_38 = 1'b1 ;
assign WILL_FIRE___me_check_38 = 1'b1 ;
// rule __me_check_39
assign CAN_FIRE___me_check_39 = 1'b1 ;
assign WILL_FIRE___me_check_39 = 1'b1 ;
// rule __me_check_40
assign CAN_FIRE___me_check_40 = 1'b1 ;
assign WILL_FIRE___me_check_40 = 1'b1 ;
// rule __me_check_41
assign CAN_FIRE___me_check_41 = 1'b1 ;
assign WILL_FIRE___me_check_41 = 1'b1 ;
// rule __me_check_43
assign CAN_FIRE___me_check_43 = 1'b1 ;
assign WILL_FIRE___me_check_43 = 1'b1 ;
// rule __me_check_42
assign CAN_FIRE___me_check_42 = 1'b1 ;
assign WILL_FIRE___me_check_42 = 1'b1 ;
// rule __me_check_44
assign CAN_FIRE___me_check_44 = 1'b1 ;
assign WILL_FIRE___me_check_44 = 1'b1 ;
// rule __me_check_45
assign CAN_FIRE___me_check_45 = 1'b1 ;
assign WILL_FIRE___me_check_45 = 1'b1 ;
// rule __me_check_46
assign CAN_FIRE___me_check_46 = 1'b1 ;
assign WILL_FIRE___me_check_46 = 1'b1 ;
// rule __me_check_47
assign CAN_FIRE___me_check_47 = 1'b1 ;
assign WILL_FIRE___me_check_47 = 1'b1 ;
// rule __me_check_48
assign CAN_FIRE___me_check_48 = 1'b1 ;
assign WILL_FIRE___me_check_48 = 1'b1 ;
// rule __me_check_49
assign CAN_FIRE___me_check_49 = 1'b1 ;
assign WILL_FIRE___me_check_49 = 1'b1 ;
// rule __me_check_51
assign CAN_FIRE___me_check_51 = 1'b1 ;
assign WILL_FIRE___me_check_51 = 1'b1 ;
// rule __me_check_50
assign CAN_FIRE___me_check_50 = 1'b1 ;
assign WILL_FIRE___me_check_50 = 1'b1 ;
// rule __me_check_52
assign CAN_FIRE___me_check_52 = 1'b1 ;
assign WILL_FIRE___me_check_52 = 1'b1 ;
// rule __me_check_53
assign CAN_FIRE___me_check_53 = 1'b1 ;
assign WILL_FIRE___me_check_53 = 1'b1 ;
// rule __me_check_54
assign CAN_FIRE___me_check_54 = 1'b1 ;
assign WILL_FIRE___me_check_54 = 1'b1 ;
// rule __me_check_55
assign CAN_FIRE___me_check_55 = 1'b1 ;
assign WILL_FIRE___me_check_55 = 1'b1 ;
// rule __me_check_56
assign CAN_FIRE___me_check_56 = 1'b1 ;
assign WILL_FIRE___me_check_56 = 1'b1 ;
// rule __me_check_57
assign CAN_FIRE___me_check_57 = 1'b1 ;
assign WILL_FIRE___me_check_57 = 1'b1 ;
// rule RL_xmas_fsm_idle_l40c27_1
assign CAN_FIRE_RL_xmas_fsm_idle_l40c27_1 =
!op_mode && xmas_fsm_state_mkFSMstate == 5'd25 ;
assign WILL_FIRE_RL_xmas_fsm_idle_l40c27_1 =
CAN_FIRE_RL_xmas_fsm_idle_l40c27_1 ;
// rule RL_xmas_fsm_fsm_start
assign CAN_FIRE_RL_xmas_fsm_fsm_start =
(op_mode && xmas_fsm_state_mkFSMstate == 5'd0 ||
op_mode && xmas_fsm_state_mkFSMstate == 5'd27 ||
!op_mode && xmas_fsm_state_mkFSMstate == 5'd0 ||
!op_mode &&
(xmas_fsm_state_mkFSMstate == 5'd25 ||
xmas_fsm_state_mkFSMstate == 5'd27)) &&
(!xmas_fsm_start_reg_1 || xmas_fsm_state_fired) &&
xmas_fsm_start_reg ;
assign WILL_FIRE_RL_xmas_fsm_fsm_start = CAN_FIRE_RL_xmas_fsm_fsm_start ;
// rule RL_xmas_fsm_action_l42c32
assign CAN_FIRE_RL_xmas_fsm_action_l42c32 =
uart_fifoXmit$FULL_N &&
(op_mode && xmas_fsm_start_wire$whas &&
xmas_fsm_state_mkFSMstate == 5'd0 ||
op_mode && xmas_fsm_state_mkFSMstate == 5'd25) ;
assign WILL_FIRE_RL_xmas_fsm_action_l42c32 =
CAN_FIRE_RL_xmas_fsm_action_l42c32 ;
// rule __me_check_34
assign CAN_FIRE___me_check_34 = 1'b1 ;
assign WILL_FIRE___me_check_34 = 1'b1 ;
// rule RL_uart_fifoXmit__updateLevelCounter
assign CAN_FIRE_RL_uart_fifoXmit__updateLevelCounter =
uart_fifoXmit_r_enq$whas !=
CAN_FIRE_RL_uart_transmit_buffer_load ;
assign WILL_FIRE_RL_uart_fifoXmit__updateLevelCounter =
CAN_FIRE_RL_uart_fifoXmit__updateLevelCounter ;
// rule RL_xmas_fsm_idle_l40c27
assign CAN_FIRE_RL_xmas_fsm_idle_l40c27 =
!op_mode && xmas_fsm_start_wire$whas &&
xmas_fsm_state_mkFSMstate == 5'd0 ;
assign WILL_FIRE_RL_xmas_fsm_idle_l40c27 =
CAN_FIRE_RL_xmas_fsm_idle_l40c27 ;
// rule RL_xmas_fsm_start_reg__dreg_update
assign CAN_FIRE_RL_xmas_fsm_start_reg__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_xmas_fsm_start_reg__dreg_update = 1'd1 ;
// rule RL_xmas_fsm_state_handle_abort
assign CAN_FIRE_RL_xmas_fsm_state_handle_abort = 1'b0 ;
assign WILL_FIRE_RL_xmas_fsm_state_handle_abort = 1'b0 ;
// rule RL_xmas_fsm_state_every
assign CAN_FIRE_RL_xmas_fsm_state_every = 1'd1 ;
assign WILL_FIRE_RL_xmas_fsm_state_every = 1'd1 ;
// rule RL_xmas_fsm_state_fired__dreg_update
assign CAN_FIRE_RL_xmas_fsm_state_fired__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_xmas_fsm_state_fired__dreg_update = 1'd1 ;
// inputs to muxes for submodule ports
assign MUX_transmit_state$write_1__SEL_1 =
WILL_FIRE_RL_get_result || EN_startup_value ;
assign MUX_uart_fifoXmit$enq_1__SEL_2 =
WILL_FIRE_RL_xmas_fsm_action_l66c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_3 =
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_11 =
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_15 =
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_16 =
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_17 =
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ;
assign MUX_uart_rRecvState$write_1__SEL_6 =
WILL_FIRE_RL_uart_receive_parity_bit ||
WILL_FIRE_RL_uart_receive_sample_pin ;
assign MUX_uart_rXmitDataOut$write_1__SEL_1 =
WILL_FIRE_RL_uart_transmit_shift_next_bit ||
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ;
assign MUX_uart_rXmitDataOut$write_1__SEL_2 =
WILL_FIRE_RL_uart_transmit_send_parity_bit ||
WILL_FIRE_RL_uart_transmit_send_start_bit ;
assign MUX_uart_rXmitDataOut$write_1__SEL_3 =
WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit ||
WILL_FIRE_RL_uart_transmit_wait_for_start_command ;
assign MUX_xmas_fsm_start_reg$write_1__SEL_1 =
EN_operation_mode && operation_mode_arg == 8'hA5 ;
assign MUX_xmas_fsm_state_mkFSMstate$write_1__SEL_1 =
WILL_FIRE_RL_xmas_fsm_idle_l40c27_1 ||
WILL_FIRE_RL_xmas_fsm_idle_l40c27 ;
assign MUX_uart_rRecvState$write_1__VAL_1 = uart_rRecvData ? 3'd0 : 3'd1 ;
assign MUX_uart_rRecvState$write_1__VAL_2 =
(uart_rRecvCellCount == 4'h4) ?
(uart_rRecvData ? 3'd0 : 3'd2) :
3'd1 ;
always@(uart_rRecvBitCount)
begin
case (uart_rRecvBitCount)
4'd8, 4'd9, 4'd10: MUX_uart_rRecvState$write_1__VAL_3 = 3'd6;
default: MUX_uart_rRecvState$write_1__VAL_3 = 3'd3;
endcase
end
assign MUX_uart_rRecvState$write_1__VAL_4 = uart_rRecvData ? 3'd2 : 3'd0 ;
assign MUX_uart_rXmitState$write_1__VAL_1 =
uart_fifoXmit$EMPTY_N ? 3'd1 : 3'd0 ;
assign MUX_uart_rXmitState$write_1__VAL_2 =
(uart_rXmitCellCount == 4'hF) ? 3'd2 : 3'd1 ;
assign MUX_uart_rXmitState$write_1__VAL_3 =
(uart_rXmitCellCount == 4'hF) ?
((uart_rXmitBitCount == 4'd7) ? 3'd4 : 3'd3) :
3'd2 ;
assign MUX_uart_rXmitState$write_1__VAL_4 =
(uart_rXmitCellCount == 4'hF) ? 3'd4 : 3'd7 ;
assign MUX_uart_rXmitState$write_1__VAL_5 =
(uart_rXmitCellCount == 4'hF) ? 3'd0 : 3'd4 ;
assign MUX_uart_rXmitState$write_1__VAL_6 =
(uart_rXmitCellCount == 4'h7) ? 3'd0 : 3'd5 ;
assign MUX_uart_rXmitState$write_1__VAL_7 =
(uart_rXmitCellCount == 4'hF) ? 3'd0 : 3'd6 ;
// inlined wires
assign xmas_fsm_start_wire$whas =
WILL_FIRE_RL_xmas_fsm_fsm_start ||
WILL_FIRE_RL_xmas_fsm_restart ;
assign uart_pwRecvCellCountReset$whas =
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell &&
uart_rRecvCellCount == 4'h4 ||
WILL_FIRE_RL_uart_receive_stop_last_bit ||
WILL_FIRE_RL_uart_receive_stop_first_bit ||
WILL_FIRE_RL_uart_receive_parity_bit ||
WILL_FIRE_RL_uart_receive_sample_pin ||
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample ||
WILL_FIRE_RL_uart_receive_wait_for_start_bit ;
assign uart_pwRecvResetBitCount$whas =
WILL_FIRE_RL_uart_receive_wait_for_start_bit && uart_rRecvData ;
assign uart_pwRecvEnableBitCount$whas =
WILL_FIRE_RL_uart_receive_stop_first_bit ||
WILL_FIRE_RL_uart_receive_parity_bit ||
WILL_FIRE_RL_uart_receive_sample_pin ;
assign uart_fifoXmit_r_enq$whas =
WILL_FIRE_RL_get_result || WILL_FIRE_RL_xmas_fsm_action_l66c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ||
WILL_FIRE_RL_xmas_fsm_action_l64c32 ||
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l62c32 ||
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ||
WILL_FIRE_RL_xmas_fsm_action_l57c32 ||
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l55c32 ||
WILL_FIRE_RL_xmas_fsm_action_l54c32 ||
WILL_FIRE_RL_xmas_fsm_action_l53c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ||
WILL_FIRE_RL_xmas_fsm_action_l49c32 ||
WILL_FIRE_RL_xmas_fsm_action_l48c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ||
WILL_FIRE_RL_xmas_fsm_action_l46c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ||
WILL_FIRE_RL_xmas_fsm_action_l43c32 ||
WILL_FIRE_RL_xmas_fsm_action_l42c32 ;
assign uart_pwXmitCellCountReset$whas =
WILL_FIRE_RL_uart_transmit_wait_for_start_command &&
uart_fifoXmit$EMPTY_N ||
_dor2uart_pwXmitCellCountReset$EN_wset &&
uart_rXmitCellCount == 4'hF ||
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 &&
uart_rXmitCellCount == 4'h7 ;
assign uart_pwXmitEnableBitCount$whas =
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time &&
uart_rXmitCellCount == 4'hF &&
uart_rXmitBitCount != 4'd7 ;
assign uart_pwXmitLoadBuffer$whas =
WILL_FIRE_RL_uart_transmit_wait_for_start_command &&
uart_fifoXmit$EMPTY_N ;
assign xmas_fsm_state_set_pw$whas =
WILL_FIRE_RL_xmas_fsm_idle_l40c27_1 ||
WILL_FIRE_RL_xmas_fsm_idle_l40c27 ||
WILL_FIRE_RL_xmas_fsm_action_l66c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ||
WILL_FIRE_RL_xmas_fsm_action_l64c32 ||
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l62c32 ||
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ||
WILL_FIRE_RL_xmas_fsm_action_l57c32 ||
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l55c32 ||
WILL_FIRE_RL_xmas_fsm_action_l54c32 ||
WILL_FIRE_RL_xmas_fsm_action_l53c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ||
WILL_FIRE_RL_xmas_fsm_action_l49c32 ||
WILL_FIRE_RL_xmas_fsm_action_l48c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ||
WILL_FIRE_RL_xmas_fsm_action_l46c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ||
WILL_FIRE_RL_xmas_fsm_action_l43c32 ||
WILL_FIRE_RL_xmas_fsm_action_l42c32 ;
// register a
assign a$D_IN = EN_startup_value ? startup_value_v : rule30$getResult ;
assign a$EN = EN_startup_value || WILL_FIRE_RL_get_result ;
// register op_mode
assign op_mode$D_IN = 1'd1 ;
assign op_mode$EN = MUX_xmas_fsm_start_reg$write_1__SEL_1 ;
// register transmit_state
assign transmit_state$D_IN =
MUX_transmit_state$write_1__SEL_1 ? 2'd1 : 2'd2 ;
assign transmit_state$EN =
WILL_FIRE_RL_get_result || EN_startup_value ||
WILL_FIRE_RL_compute ;
// register uart_rRecvBitCount
assign uart_rRecvBitCount$D_IN =
uart_pwRecvResetBitCount$whas ? 4'd0 : x__h4689 ;
assign uart_rRecvBitCount$EN =
uart_pwRecvResetBitCount$whas || uart_pwRecvEnableBitCount$whas ;
// register uart_rRecvCellCount
assign uart_rRecvCellCount$D_IN =
uart_pwRecvCellCountReset$whas ? 4'd0 : x__h2985 ;
assign uart_rRecvCellCount$EN =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// register uart_rRecvData
assign uart_rRecvData$D_IN = txrx_SIN ;
assign uart_rRecvData$EN = 1'd1 ;
// register uart_rRecvState
always@(WILL_FIRE_RL_uart_receive_wait_for_start_bit or
MUX_uart_rRecvState$write_1__VAL_1 or
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell or
MUX_uart_rRecvState$write_1__VAL_2 or
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample or
MUX_uart_rRecvState$write_1__VAL_3 or
WILL_FIRE_RL_uart_receive_stop_first_bit or
MUX_uart_rRecvState$write_1__VAL_4 or
WILL_FIRE_RL_uart_receive_stop_last_bit or
MUX_uart_rRecvState$write_1__SEL_6)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_uart_receive_wait_for_start_bit:
uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_1;
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell:
uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_2;
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample:
uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_3;
WILL_FIRE_RL_uart_receive_stop_first_bit:
uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_4;
WILL_FIRE_RL_uart_receive_stop_last_bit: uart_rRecvState$D_IN = 3'd0;
MUX_uart_rRecvState$write_1__SEL_6: uart_rRecvState$D_IN = 3'd2;
default: uart_rRecvState$D_IN = 3'b010 /* unspecified value */ ;
endcase
end
assign uart_rRecvState$EN =
WILL_FIRE_RL_uart_receive_wait_for_start_bit ||
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell ||
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample ||
WILL_FIRE_RL_uart_receive_stop_first_bit ||
WILL_FIRE_RL_uart_receive_stop_last_bit ||
WILL_FIRE_RL_uart_receive_parity_bit ||
WILL_FIRE_RL_uart_receive_sample_pin ;
// register uart_rXmitBitCount
assign uart_rXmitBitCount$D_IN =
CAN_FIRE_RL_uart_transmit_wait_for_start_command ?
4'd0 :
x__h6471 ;
assign uart_rXmitBitCount$EN =
CAN_FIRE_RL_uart_transmit_wait_for_start_command ||
uart_pwXmitEnableBitCount$whas ;
// register uart_rXmitCellCount
assign uart_rXmitCellCount$D_IN =
uart_pwXmitCellCountReset$whas ? 4'd0 : x__h6445 ;
assign uart_rXmitCellCount$EN =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// register uart_rXmitDataOut
always@(MUX_uart_rXmitDataOut$write_1__SEL_1 or
uart_vrXmitBuffer_0 or
MUX_uart_rXmitDataOut$write_1__SEL_2 or
MUX_uart_rXmitDataOut$write_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_uart_rXmitDataOut$write_1__SEL_1:
uart_rXmitDataOut$D_IN = uart_vrXmitBuffer_0;
MUX_uart_rXmitDataOut$write_1__SEL_2: uart_rXmitDataOut$D_IN = 1'b0;
MUX_uart_rXmitDataOut$write_1__SEL_3: uart_rXmitDataOut$D_IN = 1'b1;
default: uart_rXmitDataOut$D_IN = 1'b0 /* unspecified value */ ;
endcase
end
assign uart_rXmitDataOut$EN =
WILL_FIRE_RL_uart_transmit_shift_next_bit ||
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ||
WILL_FIRE_RL_uart_transmit_send_parity_bit ||
WILL_FIRE_RL_uart_transmit_send_start_bit ||
WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit ||
WILL_FIRE_RL_uart_transmit_wait_for_start_command ;
// register uart_rXmitState
always@(WILL_FIRE_RL_uart_transmit_wait_for_start_command or
MUX_uart_rXmitState$write_1__VAL_1 or
WILL_FIRE_RL_uart_transmit_send_start_bit or
MUX_uart_rXmitState$write_1__VAL_2 or
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time or
MUX_uart_rXmitState$write_1__VAL_3 or
WILL_FIRE_RL_uart_transmit_send_parity_bit or
MUX_uart_rXmitState$write_1__VAL_4 or
WILL_FIRE_RL_uart_transmit_send_stop_bit or
MUX_uart_rXmitState$write_1__VAL_5 or
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 or
MUX_uart_rXmitState$write_1__VAL_6 or
WILL_FIRE_RL_uart_transmit_send_stop_bit2 or
MUX_uart_rXmitState$write_1__VAL_7 or
WILL_FIRE_RL_uart_transmit_shift_next_bit)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_uart_transmit_wait_for_start_command:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_1;
WILL_FIRE_RL_uart_transmit_send_start_bit:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_2;
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_3;
WILL_FIRE_RL_uart_transmit_send_parity_bit:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_4;
WILL_FIRE_RL_uart_transmit_send_stop_bit:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_5;
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_6;
WILL_FIRE_RL_uart_transmit_send_stop_bit2:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_7;
WILL_FIRE_RL_uart_transmit_shift_next_bit: uart_rXmitState$D_IN = 3'd2;
default: uart_rXmitState$D_IN = 3'b010 /* unspecified value */ ;
endcase
end
assign uart_rXmitState$EN =
WILL_FIRE_RL_uart_transmit_wait_for_start_command ||
WILL_FIRE_RL_uart_transmit_send_start_bit ||
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ||
WILL_FIRE_RL_uart_transmit_send_parity_bit ||
WILL_FIRE_RL_uart_transmit_send_stop_bit ||
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
WILL_FIRE_RL_uart_transmit_shift_next_bit ;
// register uart_vrRecvBuffer_0
assign uart_vrRecvBuffer_0$D_IN = uart_vrRecvBuffer_1 ;
assign uart_vrRecvBuffer_0$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_1
assign uart_vrRecvBuffer_1$D_IN = uart_vrRecvBuffer_2 ;
assign uart_vrRecvBuffer_1$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_2
assign uart_vrRecvBuffer_2$D_IN = uart_vrRecvBuffer_3 ;
assign uart_vrRecvBuffer_2$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_3
assign uart_vrRecvBuffer_3$D_IN = uart_vrRecvBuffer_4 ;
assign uart_vrRecvBuffer_3$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_4
assign uart_vrRecvBuffer_4$D_IN = uart_vrRecvBuffer_5 ;
assign uart_vrRecvBuffer_4$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_5
assign uart_vrRecvBuffer_5$D_IN = uart_vrRecvBuffer_6 ;
assign uart_vrRecvBuffer_5$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_6
assign uart_vrRecvBuffer_6$D_IN = uart_vrRecvBuffer_7 ;
assign uart_vrRecvBuffer_6$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_7
assign uart_vrRecvBuffer_7$D_IN = uart_rRecvData ;
assign uart_vrRecvBuffer_7$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrXmitBuffer_0
assign uart_vrXmitBuffer_0$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[0] :
uart_vrXmitBuffer_1 ;
assign uart_vrXmitBuffer_0$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_1
assign uart_vrXmitBuffer_1$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[1] :
uart_vrXmitBuffer_2 ;
assign uart_vrXmitBuffer_1$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_2
assign uart_vrXmitBuffer_2$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[2] :
uart_vrXmitBuffer_3 ;
assign uart_vrXmitBuffer_2$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_3
assign uart_vrXmitBuffer_3$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[3] :
uart_vrXmitBuffer_4 ;
assign uart_vrXmitBuffer_3$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_4
assign uart_vrXmitBuffer_4$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[4] :
uart_vrXmitBuffer_5 ;
assign uart_vrXmitBuffer_4$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_5
assign uart_vrXmitBuffer_5$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[5] :
uart_vrXmitBuffer_6 ;
assign uart_vrXmitBuffer_5$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_6
assign uart_vrXmitBuffer_6$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[6] :
uart_vrXmitBuffer_7 ;
assign uart_vrXmitBuffer_6$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_7
assign uart_vrXmitBuffer_7$D_IN =
!WILL_FIRE_RL_uart_transmit_buffer_load ||
uart_fifoXmit$D_OUT[7] ;
assign uart_vrXmitBuffer_7$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register xmas_fsm_start_reg
assign xmas_fsm_start_reg$D_IN = MUX_xmas_fsm_start_reg$write_1__SEL_1 ;
assign xmas_fsm_start_reg$EN =
EN_operation_mode && operation_mode_arg == 8'hA5 ||
WILL_FIRE_RL_xmas_fsm_fsm_start ;
// register xmas_fsm_start_reg_1
assign xmas_fsm_start_reg_1$D_IN = xmas_fsm_start_wire$whas ;
assign xmas_fsm_start_reg_1$EN = 1'd1 ;
// register xmas_fsm_state_fired
assign xmas_fsm_state_fired$D_IN = xmas_fsm_state_set_pw$whas ;
assign xmas_fsm_state_fired$EN = 1'd1 ;
// register xmas_fsm_state_mkFSMstate
always@(MUX_xmas_fsm_state_mkFSMstate$write_1__SEL_1 or
WILL_FIRE_RL_xmas_fsm_action_l42c32 or
WILL_FIRE_RL_xmas_fsm_action_l43c32 or
WILL_FIRE_RL_xmas_fsm_action_l44c32 or
WILL_FIRE_RL_xmas_fsm_action_l45c32 or
WILL_FIRE_RL_xmas_fsm_action_l46c32 or
WILL_FIRE_RL_xmas_fsm_action_l47c32 or
WILL_FIRE_RL_xmas_fsm_action_l48c32 or
WILL_FIRE_RL_xmas_fsm_action_l49c32 or
WILL_FIRE_RL_xmas_fsm_action_l50c32 or
WILL_FIRE_RL_xmas_fsm_action_l51c32 or
WILL_FIRE_RL_xmas_fsm_action_l52c32 or
WILL_FIRE_RL_xmas_fsm_action_l53c32 or
WILL_FIRE_RL_xmas_fsm_action_l54c32 or
WILL_FIRE_RL_xmas_fsm_action_l55c32 or
WILL_FIRE_RL_xmas_fsm_action_l56c32 or
WILL_FIRE_RL_xmas_fsm_action_l57c32 or
WILL_FIRE_RL_xmas_fsm_action_l58c32 or
WILL_FIRE_RL_xmas_fsm_action_l59c32 or
WILL_FIRE_RL_xmas_fsm_action_l60c32 or
WILL_FIRE_RL_xmas_fsm_action_l61c32 or
WILL_FIRE_RL_xmas_fsm_action_l62c32 or
WILL_FIRE_RL_xmas_fsm_action_l63c32 or
WILL_FIRE_RL_xmas_fsm_action_l64c32 or
WILL_FIRE_RL_xmas_fsm_action_l65c32 or
WILL_FIRE_RL_xmas_fsm_action_l66c32)
begin
case (1'b1) // synopsys parallel_case
MUX_xmas_fsm_state_mkFSMstate$write_1__SEL_1:
xmas_fsm_state_mkFSMstate$D_IN = 5'd0;
WILL_FIRE_RL_xmas_fsm_action_l42c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd1;
WILL_FIRE_RL_xmas_fsm_action_l43c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd2;
WILL_FIRE_RL_xmas_fsm_action_l44c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd3;
WILL_FIRE_RL_xmas_fsm_action_l45c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd4;
WILL_FIRE_RL_xmas_fsm_action_l46c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd5;
WILL_FIRE_RL_xmas_fsm_action_l47c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd6;
WILL_FIRE_RL_xmas_fsm_action_l48c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd7;
WILL_FIRE_RL_xmas_fsm_action_l49c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd8;
WILL_FIRE_RL_xmas_fsm_action_l50c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd9;
WILL_FIRE_RL_xmas_fsm_action_l51c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd10;
WILL_FIRE_RL_xmas_fsm_action_l52c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd11;
WILL_FIRE_RL_xmas_fsm_action_l53c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd12;
WILL_FIRE_RL_xmas_fsm_action_l54c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd13;
WILL_FIRE_RL_xmas_fsm_action_l55c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd14;
WILL_FIRE_RL_xmas_fsm_action_l56c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd15;
WILL_FIRE_RL_xmas_fsm_action_l57c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd16;
WILL_FIRE_RL_xmas_fsm_action_l58c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd17;
WILL_FIRE_RL_xmas_fsm_action_l59c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd18;
WILL_FIRE_RL_xmas_fsm_action_l60c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd19;
WILL_FIRE_RL_xmas_fsm_action_l61c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd20;
WILL_FIRE_RL_xmas_fsm_action_l62c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd21;
WILL_FIRE_RL_xmas_fsm_action_l63c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd22;
WILL_FIRE_RL_xmas_fsm_action_l64c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd23;
WILL_FIRE_RL_xmas_fsm_action_l65c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd24;
WILL_FIRE_RL_xmas_fsm_action_l66c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd25;
default: xmas_fsm_state_mkFSMstate$D_IN =
5'b01010 /* unspecified value */ ;
endcase
end
assign xmas_fsm_state_mkFSMstate$EN =
WILL_FIRE_RL_xmas_fsm_idle_l40c27_1 ||
WILL_FIRE_RL_xmas_fsm_idle_l40c27 ||
WILL_FIRE_RL_xmas_fsm_action_l42c32 ||
WILL_FIRE_RL_xmas_fsm_action_l43c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l46c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ||
WILL_FIRE_RL_xmas_fsm_action_l48c32 ||
WILL_FIRE_RL_xmas_fsm_action_l49c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l53c32 ||
WILL_FIRE_RL_xmas_fsm_action_l54c32 ||
WILL_FIRE_RL_xmas_fsm_action_l55c32 ||
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l57c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ||
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l62c32 ||
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l64c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ||
WILL_FIRE_RL_xmas_fsm_action_l66c32 ;
// submodule rule30
assign rule30$start_a = a ;
assign rule30$EN_start = CAN_FIRE_RL_compute ;
assign rule30$EN_getResult = CAN_FIRE_RL_get_result ;
// submodule uart_baudGen_rBaudCounter
assign uart_baudGen_rBaudCounter$DATA_A = 16'd1 ;
assign uart_baudGen_rBaudCounter$DATA_B = 16'h0 ;
assign uart_baudGen_rBaudCounter$DATA_C = 16'h0 ;
assign uart_baudGen_rBaudCounter$DATA_F = 16'd0 ;
assign uart_baudGen_rBaudCounter$ADDA =
uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign uart_baudGen_rBaudCounter$ADDB = 1'b0 ;
assign uart_baudGen_rBaudCounter$SETC = 1'b0 ;
assign uart_baudGen_rBaudCounter$SETF =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// submodule uart_baudGen_rBaudTickCounter
assign uart_baudGen_rBaudTickCounter$DATA_A = 3'd1 ;
assign uart_baudGen_rBaudTickCounter$DATA_B = 3'h0 ;
assign uart_baudGen_rBaudTickCounter$DATA_C = 3'h0 ;
assign uart_baudGen_rBaudTickCounter$DATA_F = 3'h0 ;
assign uart_baudGen_rBaudTickCounter$ADDA =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
assign uart_baudGen_rBaudTickCounter$ADDB = 1'b0 ;
assign uart_baudGen_rBaudTickCounter$SETC = 1'b0 ;
assign uart_baudGen_rBaudTickCounter$SETF = 1'b0 ;
// submodule uart_fifoRecv
assign uart_fifoRecv$D_IN =
{ uart_vrRecvBuffer_7,
uart_vrRecvBuffer_6,
uart_vrRecvBuffer_5,
uart_vrRecvBuffer_4,
uart_vrRecvBuffer_3,
uart_vrRecvBuffer_2,
uart_vrRecvBuffer_1,
uart_vrRecvBuffer_0 } ;
assign uart_fifoRecv$ENQ = CAN_FIRE_RL_uart_receive_stop_last_bit ;
assign uart_fifoRecv$DEQ = uart_fifoRecv$EMPTY_N ;
assign uart_fifoRecv$CLR = 1'b0 ;
// submodule uart_fifoXmit
always@(WILL_FIRE_RL_get_result or
rule30$getResult or
MUX_uart_fifoXmit$enq_1__SEL_2 or
MUX_uart_fifoXmit$enq_1__SEL_3 or
WILL_FIRE_RL_xmas_fsm_action_l64c32 or
WILL_FIRE_RL_xmas_fsm_action_l53c32 or
WILL_FIRE_RL_xmas_fsm_action_l54c32 or
WILL_FIRE_RL_xmas_fsm_action_l55c32 or
WILL_FIRE_RL_xmas_fsm_action_l42c32 or
WILL_FIRE_RL_xmas_fsm_action_l57c32 or
WILL_FIRE_RL_xmas_fsm_action_l48c32 or
MUX_uart_fifoXmit$enq_1__SEL_11 or
WILL_FIRE_RL_xmas_fsm_action_l43c32 or
WILL_FIRE_RL_xmas_fsm_action_l49c32 or
WILL_FIRE_RL_xmas_fsm_action_l62c32 or
MUX_uart_fifoXmit$enq_1__SEL_15 or
MUX_uart_fifoXmit$enq_1__SEL_16 or
MUX_uart_fifoXmit$enq_1__SEL_17 or
WILL_FIRE_RL_xmas_fsm_action_l46c32)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_get_result: uart_fifoXmit$D_IN = rule30$getResult;
MUX_uart_fifoXmit$enq_1__SEL_2: uart_fifoXmit$D_IN = 8'h09;
MUX_uart_fifoXmit$enq_1__SEL_3: uart_fifoXmit$D_IN = 8'h20;
WILL_FIRE_RL_xmas_fsm_action_l64c32: uart_fifoXmit$D_IN = 8'h21;
WILL_FIRE_RL_xmas_fsm_action_l53c32: uart_fifoXmit$D_IN = 8'h27;
WILL_FIRE_RL_xmas_fsm_action_l54c32: uart_fifoXmit$D_IN = 8'h32;
WILL_FIRE_RL_xmas_fsm_action_l55c32: uart_fifoXmit$D_IN = 8'h34;
WILL_FIRE_RL_xmas_fsm_action_l42c32: uart_fifoXmit$D_IN = 8'h4D;
WILL_FIRE_RL_xmas_fsm_action_l57c32: uart_fifoXmit$D_IN = 8'h53;
WILL_FIRE_RL_xmas_fsm_action_l48c32: uart_fifoXmit$D_IN = 8'h58;
MUX_uart_fifoXmit$enq_1__SEL_11: uart_fifoXmit$D_IN = 8'h61;
WILL_FIRE_RL_xmas_fsm_action_l43c32: uart_fifoXmit$D_IN = 8'h65;
WILL_FIRE_RL_xmas_fsm_action_l49c32: uart_fifoXmit$D_IN = 8'h6D;
WILL_FIRE_RL_xmas_fsm_action_l62c32: uart_fifoXmit$D_IN = 8'h6F;
MUX_uart_fifoXmit$enq_1__SEL_15: uart_fifoXmit$D_IN = 8'h72;
MUX_uart_fifoXmit$enq_1__SEL_16: uart_fifoXmit$D_IN = 8'h73;
MUX_uart_fifoXmit$enq_1__SEL_17: uart_fifoXmit$D_IN = 8'h74;
WILL_FIRE_RL_xmas_fsm_action_l46c32: uart_fifoXmit$D_IN = 8'h79;
default: uart_fifoXmit$D_IN = 8'b10101010 /* unspecified value */ ;
endcase
end
assign uart_fifoXmit$ENQ =
WILL_FIRE_RL_get_result || WILL_FIRE_RL_xmas_fsm_action_l66c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ||
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ||
WILL_FIRE_RL_xmas_fsm_action_l64c32 ||
WILL_FIRE_RL_xmas_fsm_action_l53c32 ||
WILL_FIRE_RL_xmas_fsm_action_l54c32 ||
WILL_FIRE_RL_xmas_fsm_action_l55c32 ||
WILL_FIRE_RL_xmas_fsm_action_l42c32 ||
WILL_FIRE_RL_xmas_fsm_action_l57c32 ||
WILL_FIRE_RL_xmas_fsm_action_l48c32 ||
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ||
WILL_FIRE_RL_xmas_fsm_action_l43c32 ||
WILL_FIRE_RL_xmas_fsm_action_l49c32 ||
WILL_FIRE_RL_xmas_fsm_action_l62c32 ||
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ||
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ||
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ||
WILL_FIRE_RL_xmas_fsm_action_l46c32 ;
assign uart_fifoXmit$DEQ = CAN_FIRE_RL_uart_transmit_buffer_load ;
assign uart_fifoXmit$CLR = 1'b0 ;
// remaining internal signals
assign _dor2uart_pwXmitCellCountReset$EN_wset =
WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit ||
WILL_FIRE_RL_uart_transmit_send_parity_bit ||
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ||
WILL_FIRE_RL_uart_transmit_send_start_bit ;
assign uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 =
uart_baudGen_rBaudCounter$Q_OUT + 16'd1 < 16'd27 ;
assign x__h2985 = uart_rRecvCellCount + 4'd1 ;
assign x__h4689 = uart_rRecvBitCount + 4'd1 ;
assign x__h6445 = uart_rXmitCellCount + 4'd1 ;
assign x__h6471 = uart_rXmitBitCount + 4'd1 ;
assign xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302 =
(xmas_fsm_state_mkFSMstate == 5'd0 ||
xmas_fsm_state_mkFSMstate == 5'd25 ||
xmas_fsm_state_mkFSMstate == 5'd27) &&
(!xmas_fsm_start_reg_1 || xmas_fsm_state_fired) ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
a <= `BSV_ASSIGNMENT_DELAY 8'b0;
op_mode <= `BSV_ASSIGNMENT_DELAY 1'd0;
transmit_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
uart_rRecvData <= `BSV_ASSIGNMENT_DELAY 1'd1;
xmas_fsm_start_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
xmas_fsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
xmas_fsm_state_fired <= `BSV_ASSIGNMENT_DELAY 1'd0;
xmas_fsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY 5'd0;
end
else
begin
if (a$EN) a <= `BSV_ASSIGNMENT_DELAY a$D_IN;
if (op_mode$EN) op_mode <= `BSV_ASSIGNMENT_DELAY op_mode$D_IN;
if (transmit_state$EN)
transmit_state <= `BSV_ASSIGNMENT_DELAY transmit_state$D_IN;
if (uart_rRecvData$EN)
uart_rRecvData <= `BSV_ASSIGNMENT_DELAY uart_rRecvData$D_IN;
if (xmas_fsm_start_reg$EN)
xmas_fsm_start_reg <= `BSV_ASSIGNMENT_DELAY xmas_fsm_start_reg$D_IN;
if (xmas_fsm_start_reg_1$EN)
xmas_fsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY
xmas_fsm_start_reg_1$D_IN;
if (xmas_fsm_state_fired$EN)
xmas_fsm_state_fired <= `BSV_ASSIGNMENT_DELAY
xmas_fsm_state_fired$D_IN;
if (xmas_fsm_state_mkFSMstate$EN)
xmas_fsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY
xmas_fsm_state_mkFSMstate$D_IN;
end
if (uart_vrRecvBuffer_0$EN)
uart_vrRecvBuffer_0 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_0$D_IN;
if (uart_vrRecvBuffer_1$EN)
uart_vrRecvBuffer_1 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_1$D_IN;
if (uart_vrRecvBuffer_2$EN)
uart_vrRecvBuffer_2 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_2$D_IN;
if (uart_vrRecvBuffer_3$EN)
uart_vrRecvBuffer_3 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_3$D_IN;
if (uart_vrRecvBuffer_4$EN)
uart_vrRecvBuffer_4 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_4$D_IN;
if (uart_vrRecvBuffer_5$EN)
uart_vrRecvBuffer_5 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_5$D_IN;
if (uart_vrRecvBuffer_6$EN)
uart_vrRecvBuffer_6 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_6$D_IN;
if (uart_vrRecvBuffer_7$EN)
uart_vrRecvBuffer_7 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_7$D_IN;
if (uart_vrXmitBuffer_0$EN)
uart_vrXmitBuffer_0 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_0$D_IN;
if (uart_vrXmitBuffer_1$EN)
uart_vrXmitBuffer_1 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_1$D_IN;
if (uart_vrXmitBuffer_2$EN)
uart_vrXmitBuffer_2 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_2$D_IN;
if (uart_vrXmitBuffer_3$EN)
uart_vrXmitBuffer_3 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_3$D_IN;
if (uart_vrXmitBuffer_4$EN)
uart_vrXmitBuffer_4 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_4$D_IN;
if (uart_vrXmitBuffer_5$EN)
uart_vrXmitBuffer_5 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_5$D_IN;
if (uart_vrXmitBuffer_6$EN)
uart_vrXmitBuffer_6 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_6$D_IN;
if (uart_vrXmitBuffer_7$EN)
uart_vrXmitBuffer_7 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_7$D_IN;
end
always@(posedge CLK or `BSV_RESET_EDGE RST_N)
if (RST_N == `BSV_RESET_VALUE)
begin
uart_rRecvBitCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
uart_rRecvCellCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
uart_rRecvState <= `BSV_ASSIGNMENT_DELAY 3'd0;
uart_rXmitBitCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
uart_rXmitCellCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
uart_rXmitDataOut <= `BSV_ASSIGNMENT_DELAY 1'd1;
uart_rXmitState <= `BSV_ASSIGNMENT_DELAY 3'd0;
end
else
begin
if (uart_rRecvBitCount$EN)
uart_rRecvBitCount <= `BSV_ASSIGNMENT_DELAY uart_rRecvBitCount$D_IN;
if (uart_rRecvCellCount$EN)
uart_rRecvCellCount <= `BSV_ASSIGNMENT_DELAY uart_rRecvCellCount$D_IN;
if (uart_rRecvState$EN)
uart_rRecvState <= `BSV_ASSIGNMENT_DELAY uart_rRecvState$D_IN;
if (uart_rXmitBitCount$EN)
uart_rXmitBitCount <= `BSV_ASSIGNMENT_DELAY uart_rXmitBitCount$D_IN;
if (uart_rXmitCellCount$EN)
uart_rXmitCellCount <= `BSV_ASSIGNMENT_DELAY uart_rXmitCellCount$D_IN;
if (uart_rXmitDataOut$EN)
uart_rXmitDataOut <= `BSV_ASSIGNMENT_DELAY uart_rXmitDataOut$D_IN;
if (uart_rXmitState$EN)
uart_rXmitState <= `BSV_ASSIGNMENT_DELAY uart_rXmitState$D_IN;
end
// handling of system tasks
endmodule // mkRule30Driver
//
// Generated by Bluespec Compiler, version 2024.01-1-g4d953407 (build 4d953407)
//
// On Thu Apr 18 23:03:51 EDT 2024
//
//
// Ports:
// Name I/O size props
// RDY_start O 1
// getResult O 8 reg
// RDY_getResult O 1
// CLK I 1 clock
// RST_N I 1 reset
// start_a I 8
// EN_start I 1
// EN_getResult I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkRule30(CLK,
RST_N,
start_a,
EN_start,
RDY_start,
EN_getResult,
getResult,
RDY_getResult);
input CLK;
input RST_N;
// action method start
input [7 : 0] start_a;
input EN_start;
output RDY_start;
// actionvalue method getResult
input EN_getResult;
output [7 : 0] getResult;
output RDY_getResult;
// signals for module outputs
wire [7 : 0] getResult;
wire RDY_getResult, RDY_start;
// register busy_flag
reg busy_flag;
wire busy_flag$D_IN, busy_flag$EN;
// register r30
reg [7 : 0] r30;
wire [7 : 0] r30$D_IN;
wire r30$EN;
// register step_complete
reg step_complete;
wire step_complete$D_IN, step_complete$EN;
// register x
reg [55 : 0] x;
wire [55 : 0] x$D_IN;
wire x$EN;
// rule scheduling signals
wire CAN_FIRE_RL_stepper,
CAN_FIRE_getResult,
CAN_FIRE_start,
WILL_FIRE_RL_stepper,
WILL_FIRE_getResult,
WILL_FIRE_start;
// inputs to muxes for submodule ports
wire [55 : 0] MUX_x$write_1__VAL_1, MUX_x$write_1__VAL_2;
// remaining internal signals
wire [51 : 0] r30_BIT_x_BITS_52_TO_50_6_7_CONCAT_r30_BIT_x_B_ETC___d146;
wire [47 : 0] r30_BIT_x_BITS_48_TO_46_4_5_CONCAT_r30_BIT_x_B_ETC___d144;
wire [43 : 0] r30_BIT_x_BITS_44_TO_42_2_3_CONCAT_r30_BIT_x_B_ETC___d142;
wire [39 : 0] r30_BIT_x_BITS_40_TO_38_0_1_CONCAT_r30_BIT_x_B_ETC___d140;
wire [35 : 0] r30_BIT_x_BITS_36_TO_34_8_9_CONCAT_r30_BIT_x_B_ETC___d138;
wire [31 : 0] r30_BIT_x_BITS_32_TO_30_6_7_CONCAT_r30_BIT_x_B_ETC___d136;
wire [27 : 0] r30_BIT_x_BITS_28_TO_26_4_5_CONCAT_r30_BIT_x_B_ETC___d134;
wire [23 : 0] r30_BIT_x_BITS_24_TO_22_2_3_CONCAT_r30_BIT_x_B_ETC___d132;
wire [19 : 0] r30_BIT_x_BITS_20_TO_18_0_1_CONCAT_r30_BIT_x_B_ETC___d130;
wire [15 : 0] r30_BIT_x_BITS_16_TO_14_8_9_CONCAT_r30_BIT_x_B_ETC___d128;
wire [11 : 0] r30_BIT_x_BITS_12_TO_10_6_7_CONCAT_r30_BIT_x_B_ETC___d126;
wire [7 : 0] r30_BIT_x_BITS_8_TO_6_04_05_CONCAT_r30_BIT_x_B_ETC___d124;
wire [3 : 0] r30_BIT_x_BITS_4_TO_2_12_13_CONCAT_r30_BIT_x_B_ETC___d122;
wire [2 : 0] b0__h167, b55__h222;
// action method start
assign RDY_start = !busy_flag ;
assign CAN_FIRE_start = !busy_flag ;
assign WILL_FIRE_start = EN_start ;
// actionvalue method getResult
assign getResult = x[31:24] ;
assign RDY_getResult = busy_flag && step_complete ;
assign CAN_FIRE_getResult = busy_flag && step_complete ;
assign WILL_FIRE_getResult = EN_getResult ;
// rule RL_stepper
assign CAN_FIRE_RL_stepper = busy_flag && !step_complete ;
assign WILL_FIRE_RL_stepper = CAN_FIRE_RL_stepper ;
// inputs to muxes for submodule ports
assign MUX_x$write_1__VAL_1 =
{ r30[b55__h222],
r30[x[55:53]],
r30[x[54:52]],
r30[x[53:51]],
r30_BIT_x_BITS_52_TO_50_6_7_CONCAT_r30_BIT_x_B_ETC___d146 } ;
assign MUX_x$write_1__VAL_2 = { x[55:32], start_a, x[23:0] } ;
// register busy_flag
assign busy_flag$D_IN = !EN_getResult ;
assign busy_flag$EN = EN_getResult || EN_start ;
// register r30
assign r30$D_IN = 8'h0 ;
assign r30$EN = 1'b0 ;
// register step_complete
assign step_complete$D_IN = !EN_start ;
assign step_complete$EN = EN_start || WILL_FIRE_RL_stepper ;
// register x
assign x$D_IN =
WILL_FIRE_RL_stepper ?
MUX_x$write_1__VAL_1 :
MUX_x$write_1__VAL_2 ;
assign x$EN = WILL_FIRE_RL_stepper || EN_start ;
// remaining internal signals
assign b0__h167 = { x[1:0], 1'b0 } ;
assign b55__h222 = { 1'b0, x[55:54] } ;
assign r30_BIT_x_BITS_12_TO_10_6_7_CONCAT_r30_BIT_x_B_ETC___d126 =
{ r30[x[12:10]],
r30[x[11:9]],
r30[x[10:8]],
r30[x[9:7]],
r30_BIT_x_BITS_8_TO_6_04_05_CONCAT_r30_BIT_x_B_ETC___d124 } ;
assign r30_BIT_x_BITS_16_TO_14_8_9_CONCAT_r30_BIT_x_B_ETC___d128 =
{ r30[x[16:14]],
r30[x[15:13]],
r30[x[14:12]],
r30[x[13:11]],
r30_BIT_x_BITS_12_TO_10_6_7_CONCAT_r30_BIT_x_B_ETC___d126 } ;
assign r30_BIT_x_BITS_20_TO_18_0_1_CONCAT_r30_BIT_x_B_ETC___d130 =
{ r30[x[20:18]],
r30[x[19:17]],
r30[x[18:16]],
r30[x[17:15]],
r30_BIT_x_BITS_16_TO_14_8_9_CONCAT_r30_BIT_x_B_ETC___d128 } ;
assign r30_BIT_x_BITS_24_TO_22_2_3_CONCAT_r30_BIT_x_B_ETC___d132 =
{ r30[x[24:22]],
r30[x[23:21]],
r30[x[22:20]],
r30[x[21:19]],
r30_BIT_x_BITS_20_TO_18_0_1_CONCAT_r30_BIT_x_B_ETC___d130 } ;
assign r30_BIT_x_BITS_28_TO_26_4_5_CONCAT_r30_BIT_x_B_ETC___d134 =
{ r30[x[28:26]],
r30[x[27:25]],
r30[x[26:24]],
r30[x[25:23]],
r30_BIT_x_BITS_24_TO_22_2_3_CONCAT_r30_BIT_x_B_ETC___d132 } ;
assign r30_BIT_x_BITS_32_TO_30_6_7_CONCAT_r30_BIT_x_B_ETC___d136 =
{ r30[x[32:30]],
r30[x[31:29]],
r30[x[30:28]],
r30[x[29:27]],
r30_BIT_x_BITS_28_TO_26_4_5_CONCAT_r30_BIT_x_B_ETC___d134 } ;
assign r30_BIT_x_BITS_36_TO_34_8_9_CONCAT_r30_BIT_x_B_ETC___d138 =
{ r30[x[36:34]],
r30[x[35:33]],
r30[x[34:32]],
r30[x[33:31]],
r30_BIT_x_BITS_32_TO_30_6_7_CONCAT_r30_BIT_x_B_ETC___d136 } ;
assign r30_BIT_x_BITS_40_TO_38_0_1_CONCAT_r30_BIT_x_B_ETC___d140 =
{ r30[x[40:38]],
r30[x[39:37]],
r30[x[38:36]],
r30[x[37:35]],
r30_BIT_x_BITS_36_TO_34_8_9_CONCAT_r30_BIT_x_B_ETC___d138 } ;
assign r30_BIT_x_BITS_44_TO_42_2_3_CONCAT_r30_BIT_x_B_ETC___d142 =
{ r30[x[44:42]],
r30[x[43:41]],
r30[x[42:40]],
r30[x[41:39]],
r30_BIT_x_BITS_40_TO_38_0_1_CONCAT_r30_BIT_x_B_ETC___d140 } ;
assign r30_BIT_x_BITS_48_TO_46_4_5_CONCAT_r30_BIT_x_B_ETC___d144 =
{ r30[x[48:46]],
r30[x[47:45]],
r30[x[46:44]],
r30[x[45:43]],
r30_BIT_x_BITS_44_TO_42_2_3_CONCAT_r30_BIT_x_B_ETC___d142 } ;
assign r30_BIT_x_BITS_4_TO_2_12_13_CONCAT_r30_BIT_x_B_ETC___d122 =
{ r30[x[4:2]], r30[x[3:1]], r30[x[2:0]], r30[b0__h167] } ;
assign r30_BIT_x_BITS_52_TO_50_6_7_CONCAT_r30_BIT_x_B_ETC___d146 =
{ r30[x[52:50]],
r30[x[51:49]],
r30[x[50:48]],
r30[x[49:47]],
r30_BIT_x_BITS_48_TO_46_4_5_CONCAT_r30_BIT_x_B_ETC___d144 } ;
assign r30_BIT_x_BITS_8_TO_6_04_05_CONCAT_r30_BIT_x_B_ETC___d124 =
{ r30[x[8:6]],
r30[x[7:5]],
r30[x[6:4]],
r30[x[5:3]],
r30_BIT_x_BITS_4_TO_2_12_13_CONCAT_r30_BIT_x_B_ETC___d122 } ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
busy_flag <= `BSV_ASSIGNMENT_DELAY 1'd0;
r30 <= `BSV_ASSIGNMENT_DELAY 8'd30;
step_complete <= `BSV_ASSIGNMENT_DELAY 1'd0;
x <= `BSV_ASSIGNMENT_DELAY 56'd0;
end
else
begin
if (busy_flag$EN) busy_flag <= `BSV_ASSIGNMENT_DELAY busy_flag$D_IN;
if (r30$EN) r30 <= `BSV_ASSIGNMENT_DELAY r30$D_IN;
if (step_complete$EN)
step_complete <= `BSV_ASSIGNMENT_DELAY step_complete$D_IN;
if (x$EN) x <= `BSV_ASSIGNMENT_DELAY x$D_IN;
end
end
endmodule // mkRule30
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
// N -bit counter with load, set and 2 increment
module Counter(CLK,
RST,
Q_OUT,
DATA_A, ADDA,
DATA_B, ADDB,
DATA_C, SETC,
DATA_F, SETF);
parameter width = 1;
parameter init = 0;
input CLK;
input RST;
input [width - 1 : 0] DATA_A;
input ADDA;
input [width - 1 : 0] DATA_B;
input ADDB;
input [width - 1 : 0] DATA_C;
input SETC;
input [width - 1 : 0] DATA_F;
input SETF;
output [width - 1 : 0] Q_OUT;
reg [width - 1 : 0] q_state ;
assign Q_OUT = q_state ;
always@(posedge CLK `BSV_ARESET_EDGE_META) begin
if (RST == `BSV_RESET_VALUE)
q_state <= `BSV_ASSIGNMENT_DELAY init;
else
begin
if ( SETF )
q_state <= `BSV_ASSIGNMENT_DELAY DATA_F ;
else
q_state <= `BSV_ASSIGNMENT_DELAY (SETC ? DATA_C : q_state ) + (ADDA ? DATA_A : {width {1'b0}}) + (ADDB ? DATA_B : {width {1'b0}} ) ;
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK)
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial begin
q_state = {((width + 1)/2){2'b10}} ;
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
`ifdef BSV_RESET_FIFO_HEAD
`define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_HEAD
`endif
`ifdef BSV_RESET_FIFO_ARRAY
`define BSV_ARESET_EDGE_ARRAY `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_ARRAY
`endif
// Sized fifo. Model has output register which improves timing
module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR);
parameter p1width = 1; // data width
parameter p2depth = 3;
parameter p3cntr_width = 1; // log(p2depth-1)
// The -1 is allowed since this model has a fast output register
parameter guarded = 1'b1;
localparam p2depth2 = (p2depth >= 2) ? (p2depth -2) : 0 ;
input CLK;
input RST;
input CLR;
input [p1width - 1 : 0] D_IN;
input ENQ;
input DEQ;
output FULL_N;
output EMPTY_N;
output [p1width - 1 : 0] D_OUT;
reg not_ring_full;
reg ring_empty;
reg [p3cntr_width-1 : 0] head;
wire [p3cntr_width-1 : 0] next_head;
reg [p3cntr_width-1 : 0] tail;
wire [p3cntr_width-1 : 0] next_tail;
// if the depth is too small, don't create an ill-sized array;
// instead, make a 1-sized array and let the initial block report an error
reg [p1width - 1 : 0] arr[0: p2depth2];
reg [p1width - 1 : 0] D_OUT;
reg hasodata;
wire [p3cntr_width-1:0] depthLess2 = p2depth2[p3cntr_width-1:0] ;
wire [p3cntr_width-1 : 0] incr_tail;
wire [p3cntr_width-1 : 0] incr_head;
assign incr_tail = tail + 1'b1 ;
assign incr_head = head + 1'b1 ;
assign next_head = (head == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_head ;
assign next_tail = (tail == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_tail ;
assign EMPTY_N = hasodata;
assign FULL_N = not_ring_full;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin : initial_block
integer i;
D_OUT = {((p1width + 1)/2){2'b10}} ;
ring_empty = 1'b1;
not_ring_full = 1'b1;
hasodata = 1'b0;
head = {p3cntr_width {1'b0}} ;
tail = {p3cntr_width {1'b0}} ;
for (i = 0; i <= p2depth2; i = i + 1)
begin
arr[i] = D_OUT ;
end
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
always @(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (RST == `BSV_RESET_VALUE)
else
begin
casez ({CLR, DEQ, ENQ, hasodata, ring_empty})
// Clear operation
5'b1????: begin
head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
// -----------------------
// DEQ && ENQ case -- change head and tail if added to ring
5'b011?0: begin
tail <= `BSV_ASSIGNMENT_DELAY next_tail;
head <= `BSV_ASSIGNMENT_DELAY next_head;
end
// -----------------------
// DEQ only and NO data is in ring
5'b010?1: begin
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
// DEQ only and data is in ring (move the head pointer)
5'b010?0: begin
head <= `BSV_ASSIGNMENT_DELAY next_head;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
ring_empty <= `BSV_ASSIGNMENT_DELAY next_head == tail ;
end
// -----------------------
// ENQ only when empty
5'b0010?: begin
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b1;
end
// ENQ only when not empty
5'b0011?: begin
if ( not_ring_full ) // Drop this test to save redundant test
// but be warnned that with test fifo overflow causes loss of new data
// while without test fifo drops all but head entry! (pointer overflow)
begin
tail <= `BSV_ASSIGNMENT_DELAY next_tail;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b0;
not_ring_full <= `BSV_ASSIGNMENT_DELAY ! (next_tail == head) ;
end
end
endcase
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// Update the fast data out register
always @(posedge CLK `BSV_ARESET_EDGE_HEAD)
begin
`ifdef BSV_RESET_FIFO_HEAD
if (RST == `BSV_RESET_VALUE)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
end // if (RST == `BSV_RESET_VALUE)
else
`endif
begin
casez ({CLR, DEQ, ENQ, hasodata, ring_empty})
// DEQ && ENQ cases
5'b011?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end
5'b011?1: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end
// DEQ only and data is in ring
5'b010?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end
// ENQ only when empty
5'b0010?: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end
endcase
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// Update the memory array reset is OFF
always @(posedge CLK `BSV_ARESET_EDGE_ARRAY)
begin: array
`ifdef BSV_RESET_FIFO_ARRAY
if (RST == `BSV_RESET_VALUE)
begin: rst_array
integer i;
for (i = 0; i <= p2depth2 && p2depth > 2; i = i + 1)
begin
arr[i] <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
end
end // if (RST == `BSV_RESET_VALUE)
else
`endif
begin
if (!CLR && ENQ && ((DEQ && !ring_empty) || (!DEQ && hasodata && not_ring_full)))
begin
arr[tail] <= `BSV_ASSIGNMENT_DELAY D_IN;
end
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if (RST == ! `BSV_RESET_VALUE)
begin
if ( ! EMPTY_N && DEQ )
begin
deqerror = 1 ;
$display( "Warning: SizedFIFO: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && (!DEQ || guarded) )
begin
enqerror = 1 ;
$display( "Warning: SizedFIFO: %m -- Enqueuing to a full fifo" ) ;
end
end
end // block: error_checks
// synopsys translate_on
// synopsys translate_off
// Some assertions about parameter values
initial
begin : parameter_assertions
integer ok ;
ok = 1 ;
if ( p2depth <= 1)
begin
ok = 0;
$display ( "Warning SizedFIFO: %m -- depth parameter increased from %0d to 2", p2depth);
end
if ( p3cntr_width <= 0 )
begin
ok = 0;
$display ( "ERROR SizedFIFO: %m -- width parameter must be greater than 0" ) ;
end
if ( ok == 0 ) $finish ;
end // initial begin
// synopsys translate_on
endmodule
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
`ifdef BSV_RESET_FIFO_HEAD
`define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_HEAD
`endif
// Depth 1 FIFO
module FIFO1(CLK,
RST,
D_IN,
ENQ,
FULL_N,
D_OUT,
DEQ,
EMPTY_N,
CLR
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
|
module FIFO1(CLK,
RST,
D_IN,
ENQ,
FULL_N,
D_OUT,
DEQ,
EMPTY_N,
CLR
);
parameter width = 1;
parameter guarded = 1'b1;
input CLK;
input RST;
input [width - 1 : 0] D_IN;
input ENQ;
input DEQ;
input CLR ;
output FULL_N;
output [width - 1 : 0] D_OUT;
output EMPTY_N;
reg [width - 1 : 0] D_OUT;
reg empty_reg ;
assign EMPTY_N = empty_reg ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
D_OUT = {((width + 1)/2) {2'b10}} ;
empty_reg = 1'b0 ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
assign FULL_N = !empty_reg;
always@(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (RST == `BSV_RESET_VALUE)
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (CLR)
else if (ENQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // if (ENQ)
else if (DEQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (DEQ)
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
always@(posedge CLK `BSV_ARESET_EDGE_HEAD)
begin
`ifdef BSV_RESET_FIFO_HEAD
if (RST == `BSV_RESET_VALUE)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
end
else
`endif
begin
if (ENQ)
D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN;
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if (RST == ! `BSV_RESET_VALUE)
begin
if ( ! empty_reg && DEQ )
begin
deqerror = 1 ;
$display( "Warning: FIFO1: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && (!DEQ || guarded) )
begin
enqerror = 1 ;
$display( "Warning: FIFO1: %m -- Enqueuing to a full fifo" ) ;
end
end // if (RST == ! `BSV_RESET_VALUE)
end
// synopsys translate_on
endmodule
|
tt06-finale_0052
|
tt06-finale
|
andrewtron3000-tt06-verilog-template
|
task_SizedFIFO
|
tt_um_andrewtron3000
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 andrewtron3000
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_andrewtron3000 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// Held in reset while ena is not set
wire reset_n;
assign reset_n = rst_n & ena;
assign uio_oe = 8'b00000000; // All bidirectional outputs disabled
assign uio_out = 0;
// Assign output
assign uo_out[0] = 0;
assign uo_out[1] = 0;
assign uo_out[2] = 0;
assign uo_out[3] = 0;
assign uo_out[4] = driver_sout; // uo_out[4] is UART TX
assign uo_out[5] = 0;
assign uo_out[6] = 0;
assign uo_out[7] = 0;
// ports of submodule driver
wire driver_sin, driver_sout;
assign driver_sin = 0;
wire startup_input_ready;
wire startup_input_enable;
wire operation_mode_ready;
wire operation_mode_enable;
// submodule rule_30_driver
mkRule30Driver rule_30_driver(.CLK(clk),
.RST_N(reset_n),
.operation_mode_arg(uio_in),
.EN_operation_mode(operation_mode_enable),
.RDY_operation_mode(operation_mode_ready),
.startup_value_v(ui_in),
.EN_startup_value(startup_input_enable),
.RDY_startup_value(startup_input_ready),
.txrx_SIN(driver_sin),
.txrx_SOUT(driver_sout));
assign startup_input_enable = startup_input_ready;
assign operation_mode_enable = operation_mode_ready;
endmodule
//
// Generated by Bluespec Compiler, version 2024.01-1-g4d953407 (build 4d953407)
//
// On Thu Apr 18 23:03:53 EDT 2024
//
//
// Ports:
// Name I/O size props
// RDY_operation_mode O 1
// RDY_startup_value O 1
// txrx_SOUT O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// operation_mode_arg I 8
// startup_value_v I 8
// txrx_SIN I 1 reg
// EN_operation_mode I 1
// EN_startup_value I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkRule30Driver(CLK,
RST_N,
operation_mode_arg,
EN_operation_mode,
RDY_operation_mode,
startup_value_v,
EN_startup_value,
RDY_startup_value,
txrx_SIN,
txrx_SOUT);
input CLK;
input RST_N;
// action method operation_mode
input [7 : 0] operation_mode_arg;
input EN_operation_mode;
output RDY_operation_mode;
// action method startup_value
input [7 : 0] startup_value_v;
input EN_startup_value;
output RDY_startup_value;
// action method txrx_sin
input txrx_SIN;
// value method txrx_sout
output txrx_SOUT;
// signals for module outputs
wire RDY_operation_mode, RDY_startup_value, txrx_SOUT;
// inlined wires
wire uart_fifoXmit_r_enq$whas,
uart_pwRecvCellCountReset$whas,
uart_pwRecvEnableBitCount$whas,
uart_pwRecvResetBitCount$whas,
uart_pwXmitCellCountReset$whas,
uart_pwXmitEnableBitCount$whas,
uart_pwXmitLoadBuffer$whas,
xmas_fsm_start_wire$whas,
xmas_fsm_state_set_pw$whas;
// register a
reg [7 : 0] a;
wire [7 : 0] a$D_IN;
wire a$EN;
// register op_mode
reg op_mode;
wire op_mode$D_IN, op_mode$EN;
// register transmit_state
reg [1 : 0] transmit_state;
wire [1 : 0] transmit_state$D_IN;
wire transmit_state$EN;
// register uart_rRecvBitCount
reg [3 : 0] uart_rRecvBitCount;
wire [3 : 0] uart_rRecvBitCount$D_IN;
wire uart_rRecvBitCount$EN;
// register uart_rRecvCellCount
reg [3 : 0] uart_rRecvCellCount;
wire [3 : 0] uart_rRecvCellCount$D_IN;
wire uart_rRecvCellCount$EN;
// register uart_rRecvData
reg uart_rRecvData;
wire uart_rRecvData$D_IN, uart_rRecvData$EN;
// register uart_rRecvState
reg [2 : 0] uart_rRecvState;
reg [2 : 0] uart_rRecvState$D_IN;
wire uart_rRecvState$EN;
// register uart_rXmitBitCount
reg [3 : 0] uart_rXmitBitCount;
wire [3 : 0] uart_rXmitBitCount$D_IN;
wire uart_rXmitBitCount$EN;
// register uart_rXmitCellCount
reg [3 : 0] uart_rXmitCellCount;
wire [3 : 0] uart_rXmitCellCount$D_IN;
wire uart_rXmitCellCount$EN;
// register uart_rXmitDataOut
reg uart_rXmitDataOut;
reg uart_rXmitDataOut$D_IN;
wire uart_rXmitDataOut$EN;
// register uart_rXmitState
reg [2 : 0] uart_rXmitState;
reg [2 : 0] uart_rXmitState$D_IN;
wire uart_rXmitState$EN;
// register uart_vrRecvBuffer_0
reg uart_vrRecvBuffer_0;
wire uart_vrRecvBuffer_0$D_IN, uart_vrRecvBuffer_0$EN;
// register uart_vrRecvBuffer_1
reg uart_vrRecvBuffer_1;
wire uart_vrRecvBuffer_1$D_IN, uart_vrRecvBuffer_1$EN;
// register uart_vrRecvBuffer_2
reg uart_vrRecvBuffer_2;
wire uart_vrRecvBuffer_2$D_IN, uart_vrRecvBuffer_2$EN;
// register uart_vrRecvBuffer_3
reg uart_vrRecvBuffer_3;
wire uart_vrRecvBuffer_3$D_IN, uart_vrRecvBuffer_3$EN;
// register uart_vrRecvBuffer_4
reg uart_vrRecvBuffer_4;
wire uart_vrRecvBuffer_4$D_IN, uart_vrRecvBuffer_4$EN;
// register uart_vrRecvBuffer_5
reg uart_vrRecvBuffer_5;
wire uart_vrRecvBuffer_5$D_IN, uart_vrRecvBuffer_5$EN;
// register uart_vrRecvBuffer_6
reg uart_vrRecvBuffer_6;
wire uart_vrRecvBuffer_6$D_IN, uart_vrRecvBuffer_6$EN;
// register uart_vrRecvBuffer_7
reg uart_vrRecvBuffer_7;
wire uart_vrRecvBuffer_7$D_IN, uart_vrRecvBuffer_7$EN;
// register uart_vrXmitBuffer_0
reg uart_vrXmitBuffer_0;
wire uart_vrXmitBuffer_0$D_IN, uart_vrXmitBuffer_0$EN;
// register uart_vrXmitBuffer_1
reg uart_vrXmitBuffer_1;
wire uart_vrXmitBuffer_1$D_IN, uart_vrXmitBuffer_1$EN;
// register uart_vrXmitBuffer_2
reg uart_vrXmitBuffer_2;
wire uart_vrXmitBuffer_2$D_IN, uart_vrXmitBuffer_2$EN;
// register uart_vrXmitBuffer_3
reg uart_vrXmitBuffer_3;
wire uart_vrXmitBuffer_3$D_IN, uart_vrXmitBuffer_3$EN;
// register uart_vrXmitBuffer_4
reg uart_vrXmitBuffer_4;
wire uart_vrXmitBuffer_4$D_IN, uart_vrXmitBuffer_4$EN;
// register uart_vrXmitBuffer_5
reg uart_vrXmitBuffer_5;
wire uart_vrXmitBuffer_5$D_IN, uart_vrXmitBuffer_5$EN;
// register uart_vrXmitBuffer_6
reg uart_vrXmitBuffer_6;
wire uart_vrXmitBuffer_6$D_IN, uart_vrXmitBuffer_6$EN;
// register uart_vrXmitBuffer_7
reg uart_vrXmitBuffer_7;
wire uart_vrXmitBuffer_7$D_IN, uart_vrXmitBuffer_7$EN;
// register xmas_fsm_start_reg
reg xmas_fsm_start_reg;
wire xmas_fsm_start_reg$D_IN, xmas_fsm_start_reg$EN;
// register xmas_fsm_start_reg_1
reg xmas_fsm_start_reg_1;
wire xmas_fsm_start_reg_1$D_IN, xmas_fsm_start_reg_1$EN;
// register xmas_fsm_state_fired
reg xmas_fsm_state_fired;
wire xmas_fsm_state_fired$D_IN, xmas_fsm_state_fired$EN;
// register xmas_fsm_state_mkFSMstate
reg [4 : 0] xmas_fsm_state_mkFSMstate;
reg [4 : 0] xmas_fsm_state_mkFSMstate$D_IN;
wire xmas_fsm_state_mkFSMstate$EN;
// ports of submodule rule30
wire [7 : 0] rule30$getResult, rule30$start_a;
wire rule30$EN_getResult,
rule30$EN_start,
rule30$RDY_getResult,
rule30$RDY_start;
// ports of submodule uart_baudGen_rBaudCounter
wire [15 : 0] uart_baudGen_rBaudCounter$DATA_A,
uart_baudGen_rBaudCounter$DATA_B,
uart_baudGen_rBaudCounter$DATA_C,
uart_baudGen_rBaudCounter$DATA_F,
uart_baudGen_rBaudCounter$Q_OUT;
wire uart_baudGen_rBaudCounter$ADDA,
uart_baudGen_rBaudCounter$ADDB,
uart_baudGen_rBaudCounter$SETC,
uart_baudGen_rBaudCounter$SETF;
// ports of submodule uart_baudGen_rBaudTickCounter
wire [2 : 0] uart_baudGen_rBaudTickCounter$DATA_A,
uart_baudGen_rBaudTickCounter$DATA_B,
uart_baudGen_rBaudTickCounter$DATA_C,
uart_baudGen_rBaudTickCounter$DATA_F,
uart_baudGen_rBaudTickCounter$Q_OUT;
wire uart_baudGen_rBaudTickCounter$ADDA,
uart_baudGen_rBaudTickCounter$ADDB,
uart_baudGen_rBaudTickCounter$SETC,
uart_baudGen_rBaudTickCounter$SETF;
// ports of submodule uart_fifoRecv
wire [7 : 0] uart_fifoRecv$D_IN;
wire uart_fifoRecv$CLR,
uart_fifoRecv$DEQ,
uart_fifoRecv$EMPTY_N,
uart_fifoRecv$ENQ;
// ports of submodule uart_fifoXmit
reg [7 : 0] uart_fifoXmit$D_IN;
wire [7 : 0] uart_fifoXmit$D_OUT;
wire uart_fifoXmit$CLR,
uart_fifoXmit$DEQ,
uart_fifoXmit$EMPTY_N,
uart_fifoXmit$ENQ,
uart_fifoXmit$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_compute,
CAN_FIRE_RL_dump_rx,
CAN_FIRE_RL_get_result,
CAN_FIRE_RL_uart_baudGen_assert_2x_baud_tick,
CAN_FIRE_RL_uart_baudGen_baud_count_wire,
CAN_FIRE_RL_uart_baudGen_baud_tick_count_wire,
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x,
CAN_FIRE_RL_uart_baud_generator_clock_enable,
CAN_FIRE_RL_uart_fifoRecv__updateLevelCounter,
CAN_FIRE_RL_uart_fifoXmit__updateLevelCounter,
CAN_FIRE_RL_uart_receive_bit_cell_time_counter,
CAN_FIRE_RL_uart_receive_bit_counter,
CAN_FIRE_RL_uart_receive_buffer_shift,
CAN_FIRE_RL_uart_receive_find_center_of_bit_cell,
CAN_FIRE_RL_uart_receive_parity_bit,
CAN_FIRE_RL_uart_receive_sample_pin,
CAN_FIRE_RL_uart_receive_stop_first_bit,
CAN_FIRE_RL_uart_receive_stop_last_bit,
CAN_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample,
CAN_FIRE_RL_uart_receive_wait_for_start_bit,
CAN_FIRE_RL_uart_transmit_bit_cell_time_counter,
CAN_FIRE_RL_uart_transmit_bit_counter,
CAN_FIRE_RL_uart_transmit_buffer_load,
CAN_FIRE_RL_uart_transmit_buffer_shift,
CAN_FIRE_RL_uart_transmit_send_parity_bit,
CAN_FIRE_RL_uart_transmit_send_start_bit,
CAN_FIRE_RL_uart_transmit_send_stop_bit,
CAN_FIRE_RL_uart_transmit_send_stop_bit1_5,
CAN_FIRE_RL_uart_transmit_send_stop_bit2,
CAN_FIRE_RL_uart_transmit_shift_next_bit,
CAN_FIRE_RL_uart_transmit_wait_1_bit_cell_time,
CAN_FIRE_RL_uart_transmit_wait_for_start_command,
CAN_FIRE_RL_xmas_fsm_action_l42c32,
CAN_FIRE_RL_xmas_fsm_action_l43c32,
CAN_FIRE_RL_xmas_fsm_action_l44c32,
CAN_FIRE_RL_xmas_fsm_action_l45c32,
CAN_FIRE_RL_xmas_fsm_action_l46c32,
CAN_FIRE_RL_xmas_fsm_action_l47c32,
CAN_FIRE_RL_xmas_fsm_action_l48c32,
CAN_FIRE_RL_xmas_fsm_action_l49c32,
CAN_FIRE_RL_xmas_fsm_action_l50c32,
CAN_FIRE_RL_xmas_fsm_action_l51c32,
CAN_FIRE_RL_xmas_fsm_action_l52c32,
CAN_FIRE_RL_xmas_fsm_action_l53c32,
CAN_FIRE_RL_xmas_fsm_action_l54c32,
CAN_FIRE_RL_xmas_fsm_action_l55c32,
CAN_FIRE_RL_xmas_fsm_action_l56c32,
CAN_FIRE_RL_xmas_fsm_action_l57c32,
CAN_FIRE_RL_xmas_fsm_action_l58c32,
CAN_FIRE_RL_xmas_fsm_action_l59c32,
CAN_FIRE_RL_xmas_fsm_action_l60c32,
CAN_FIRE_RL_xmas_fsm_action_l61c32,
CAN_FIRE_RL_xmas_fsm_action_l62c32,
CAN_FIRE_RL_xmas_fsm_action_l63c32,
CAN_FIRE_RL_xmas_fsm_action_l64c32,
CAN_FIRE_RL_xmas_fsm_action_l65c32,
CAN_FIRE_RL_xmas_fsm_action_l66c32,
CAN_FIRE_RL_xmas_fsm_fsm_start,
CAN_FIRE_RL_xmas_fsm_idle_l40c27,
CAN_FIRE_RL_xmas_fsm_idle_l40c27_1,
CAN_FIRE_RL_xmas_fsm_restart,
CAN_FIRE_RL_xmas_fsm_start_reg__dreg_update,
CAN_FIRE_RL_xmas_fsm_state_every,
CAN_FIRE_RL_xmas_fsm_state_fired__dreg_update,
CAN_FIRE_RL_xmas_fsm_state_handle_abort,
CAN_FIRE___me_check_34,
CAN_FIRE___me_check_35,
CAN_FIRE___me_check_36,
CAN_FIRE___me_check_37,
CAN_FIRE___me_check_38,
CAN_FIRE___me_check_39,
CAN_FIRE___me_check_40,
CAN_FIRE___me_check_41,
CAN_FIRE___me_check_42,
CAN_FIRE___me_check_43,
CAN_FIRE___me_check_44,
CAN_FIRE___me_check_45,
CAN_FIRE___me_check_46,
CAN_FIRE___me_check_47,
CAN_FIRE___me_check_48,
CAN_FIRE___me_check_49,
CAN_FIRE___me_check_50,
CAN_FIRE___me_check_51,
CAN_FIRE___me_check_52,
CAN_FIRE___me_check_53,
CAN_FIRE___me_check_54,
CAN_FIRE___me_check_55,
CAN_FIRE___me_check_56,
CAN_FIRE___me_check_57,
CAN_FIRE_operation_mode,
CAN_FIRE_startup_value,
CAN_FIRE_txrx_sin,
WILL_FIRE_RL_compute,
WILL_FIRE_RL_dump_rx,
WILL_FIRE_RL_get_result,
WILL_FIRE_RL_uart_baudGen_assert_2x_baud_tick,
WILL_FIRE_RL_uart_baudGen_baud_count_wire,
WILL_FIRE_RL_uart_baudGen_baud_tick_count_wire,
WILL_FIRE_RL_uart_baudGen_count_baudtick_16x,
WILL_FIRE_RL_uart_baud_generator_clock_enable,
WILL_FIRE_RL_uart_fifoRecv__updateLevelCounter,
WILL_FIRE_RL_uart_fifoXmit__updateLevelCounter,
WILL_FIRE_RL_uart_receive_bit_cell_time_counter,
WILL_FIRE_RL_uart_receive_bit_counter,
WILL_FIRE_RL_uart_receive_buffer_shift,
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell,
WILL_FIRE_RL_uart_receive_parity_bit,
WILL_FIRE_RL_uart_receive_sample_pin,
WILL_FIRE_RL_uart_receive_stop_first_bit,
WILL_FIRE_RL_uart_receive_stop_last_bit,
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample,
WILL_FIRE_RL_uart_receive_wait_for_start_bit,
WILL_FIRE_RL_uart_transmit_bit_cell_time_counter,
WILL_FIRE_RL_uart_transmit_bit_counter,
WILL_FIRE_RL_uart_transmit_buffer_load,
WILL_FIRE_RL_uart_transmit_buffer_shift,
WILL_FIRE_RL_uart_transmit_send_parity_bit,
WILL_FIRE_RL_uart_transmit_send_start_bit,
WILL_FIRE_RL_uart_transmit_send_stop_bit,
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5,
WILL_FIRE_RL_uart_transmit_send_stop_bit2,
WILL_FIRE_RL_uart_transmit_shift_next_bit,
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time,
WILL_FIRE_RL_uart_transmit_wait_for_start_command,
WILL_FIRE_RL_xmas_fsm_action_l42c32,
WILL_FIRE_RL_xmas_fsm_action_l43c32,
WILL_FIRE_RL_xmas_fsm_action_l44c32,
WILL_FIRE_RL_xmas_fsm_action_l45c32,
WILL_FIRE_RL_xmas_fsm_action_l46c32,
WILL_FIRE_RL_xmas_fsm_action_l47c32,
WILL_FIRE_RL_xmas_fsm_action_l48c32,
WILL_FIRE_RL_xmas_fsm_action_l49c32,
WILL_FIRE_RL_xmas_fsm_action_l50c32,
WILL_FIRE_RL_xmas_fsm_action_l51c32,
WILL_FIRE_RL_xmas_fsm_action_l52c32,
WILL_FIRE_RL_xmas_fsm_action_l53c32,
WILL_FIRE_RL_xmas_fsm_action_l54c32,
WILL_FIRE_RL_xmas_fsm_action_l55c32,
WILL_FIRE_RL_xmas_fsm_action_l56c32,
WILL_FIRE_RL_xmas_fsm_action_l57c32,
WILL_FIRE_RL_xmas_fsm_action_l58c32,
WILL_FIRE_RL_xmas_fsm_action_l59c32,
WILL_FIRE_RL_xmas_fsm_action_l60c32,
WILL_FIRE_RL_xmas_fsm_action_l61c32,
WILL_FIRE_RL_xmas_fsm_action_l62c32,
WILL_FIRE_RL_xmas_fsm_action_l63c32,
WILL_FIRE_RL_xmas_fsm_action_l64c32,
WILL_FIRE_RL_xmas_fsm_action_l65c32,
WILL_FIRE_RL_xmas_fsm_action_l66c32,
WILL_FIRE_RL_xmas_fsm_fsm_start,
WILL_FIRE_RL_xmas_fsm_idle_l40c27,
WILL_FIRE_RL_xmas_fsm_idle_l40c27_1,
WILL_FIRE_RL_xmas_fsm_restart,
WILL_FIRE_RL_xmas_fsm_start_reg__dreg_update,
WILL_FIRE_RL_xmas_fsm_state_every,
WILL_FIRE_RL_xmas_fsm_state_fired__dreg_update,
WILL_FIRE_RL_xmas_fsm_state_handle_abort,
WILL_FIRE___me_check_34,
WILL_FIRE___me_check_35,
WILL_FIRE___me_check_36,
WILL_FIRE___me_check_37,
WILL_FIRE___me_check_38,
WILL_FIRE___me_check_39,
WILL_FIRE___me_check_40,
WILL_FIRE___me_check_41,
WILL_FIRE___me_check_42,
WILL_FIRE___me_check_43,
WILL_FIRE___me_check_44,
WILL_FIRE___me_check_45,
WILL_FIRE___me_check_46,
WILL_FIRE___me_check_47,
WILL_FIRE___me_check_48,
WILL_FIRE___me_check_49,
WILL_FIRE___me_check_50,
WILL_FIRE___me_check_51,
WILL_FIRE___me_check_52,
WILL_FIRE___me_check_53,
WILL_FIRE___me_check_54,
WILL_FIRE___me_check_55,
WILL_FIRE___me_check_56,
WILL_FIRE___me_check_57,
WILL_FIRE_operation_mode,
WILL_FIRE_startup_value,
WILL_FIRE_txrx_sin;
// inputs to muxes for submodule ports
reg [2 : 0] MUX_uart_rRecvState$write_1__VAL_3;
wire [2 : 0] MUX_uart_rRecvState$write_1__VAL_1,
MUX_uart_rRecvState$write_1__VAL_2,
MUX_uart_rRecvState$write_1__VAL_4,
MUX_uart_rXmitState$write_1__VAL_1,
MUX_uart_rXmitState$write_1__VAL_2,
MUX_uart_rXmitState$write_1__VAL_3,
MUX_uart_rXmitState$write_1__VAL_4,
MUX_uart_rXmitState$write_1__VAL_5,
MUX_uart_rXmitState$write_1__VAL_6,
MUX_uart_rXmitState$write_1__VAL_7;
wire MUX_transmit_state$write_1__SEL_1,
MUX_uart_fifoXmit$enq_1__SEL_11,
MUX_uart_fifoXmit$enq_1__SEL_15,
MUX_uart_fifoXmit$enq_1__SEL_16,
MUX_uart_fifoXmit$enq_1__SEL_17,
MUX_uart_fifoXmit$enq_1__SEL_2,
MUX_uart_fifoXmit$enq_1__SEL_3,
MUX_uart_rRecvState$write_1__SEL_6,
MUX_uart_rXmitDataOut$write_1__SEL_1,
MUX_uart_rXmitDataOut$write_1__SEL_2,
MUX_uart_rXmitDataOut$write_1__SEL_3,
MUX_xmas_fsm_start_reg$write_1__SEL_1,
MUX_xmas_fsm_state_mkFSMstate$write_1__SEL_1;
// remaining internal signals
wire [3 : 0] x__h2985, x__h4689, x__h6445, x__h6471;
wire _dor2uart_pwXmitCellCountReset$EN_wset,
uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29,
xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302;
// action method operation_mode
assign RDY_operation_mode =
transmit_state == 2'd0 && !op_mode &&
xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302 &&
!xmas_fsm_start_reg ;
assign CAN_FIRE_operation_mode =
transmit_state == 2'd0 && !op_mode &&
xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302 &&
!xmas_fsm_start_reg ;
assign WILL_FIRE_operation_mode = EN_operation_mode ;
// action method startup_value
assign RDY_startup_value = transmit_state == 2'd0 && !op_mode ;
assign CAN_FIRE_startup_value = transmit_state == 2'd0 && !op_mode ;
assign WILL_FIRE_startup_value = EN_startup_value ;
// action method txrx_sin
assign CAN_FIRE_txrx_sin = 1'd1 ;
assign WILL_FIRE_txrx_sin = 1'd1 ;
// value method txrx_sout
assign txrx_SOUT = uart_rXmitDataOut ;
// submodule rule30
mkRule30 rule30(.CLK(CLK),
.RST_N(RST_N),
.start_a(rule30$start_a),
.EN_start(rule30$EN_start),
.EN_getResult(rule30$EN_getResult),
.RDY_start(rule30$RDY_start),
.getResult(rule30$getResult),
.RDY_getResult(rule30$RDY_getResult));
// submodule uart_baudGen_rBaudCounter
Counter #(.width(32'd16), .init(16'd0)) uart_baudGen_rBaudCounter(.CLK(CLK),
.RST(RST_N),
.DATA_A(uart_baudGen_rBaudCounter$DATA_A),
.DATA_B(uart_baudGen_rBaudCounter$DATA_B),
.DATA_C(uart_baudGen_rBaudCounter$DATA_C),
.DATA_F(uart_baudGen_rBaudCounter$DATA_F),
.ADDA(uart_baudGen_rBaudCounter$ADDA),
.ADDB(uart_baudGen_rBaudCounter$ADDB),
.SETC(uart_baudGen_rBaudCounter$SETC),
.SETF(uart_baudGen_rBaudCounter$SETF),
.Q_OUT(uart_baudGen_rBaudCounter$Q_OUT));
// submodule uart_baudGen_rBaudTickCounter
Counter #(.width(32'd3),
.init(3'd0)) uart_baudGen_rBaudTickCounter(.CLK(CLK),
.RST(RST_N),
.DATA_A(uart_baudGen_rBaudTickCounter$DATA_A),
.DATA_B(uart_baudGen_rBaudTickCounter$DATA_B),
.DATA_C(uart_baudGen_rBaudTickCounter$DATA_C),
.DATA_F(uart_baudGen_rBaudTickCounter$DATA_F),
.ADDA(uart_baudGen_rBaudTickCounter$ADDA),
.ADDB(uart_baudGen_rBaudTickCounter$ADDB),
.SETC(uart_baudGen_rBaudTickCounter$SETC),
.SETF(uart_baudGen_rBaudTickCounter$SETF),
.Q_OUT(uart_baudGen_rBaudTickCounter$Q_OUT));
// submodule uart_fifoRecv
SizedFIFO #(.p1width(32'd8),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(1'd1)) uart_fifoRecv(.RST(RST_N),
.CLK(CLK),
.D_IN(uart_fifoRecv$D_IN),
.ENQ(uart_fifoRecv$ENQ),
.DEQ(uart_fifoRecv$DEQ),
.CLR(uart_fifoRecv$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N(uart_fifoRecv$EMPTY_N));
// submodule uart_fifoXmit
SizedFIFO #(.p1width(32'd8),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(1'd1)) uart_fifoXmit(.RST(RST_N),
.CLK(CLK),
.D_IN(uart_fifoXmit$D_IN),
.ENQ(uart_fifoXmit$ENQ),
.DEQ(uart_fifoXmit$DEQ),
.CLR(uart_fifoXmit$CLR),
.D_OUT(uart_fifoXmit$D_OUT),
.FULL_N(uart_fifoXmit$FULL_N),
.EMPTY_N(uart_fifoXmit$EMPTY_N));
// rule RL_dump_rx
assign CAN_FIRE_RL_dump_rx = uart_fifoRecv$EMPTY_N ;
assign WILL_FIRE_RL_dump_rx = uart_fifoRecv$EMPTY_N ;
// rule RL_compute
assign CAN_FIRE_RL_compute =
rule30$RDY_start && transmit_state == 2'd1 && !op_mode ;
assign WILL_FIRE_RL_compute = CAN_FIRE_RL_compute ;
// rule RL_uart_baudGen_baud_count_wire
assign CAN_FIRE_RL_uart_baudGen_baud_count_wire = 1'd1 ;
assign WILL_FIRE_RL_uart_baudGen_baud_count_wire = 1'd1 ;
// rule RL_uart_baud_generator_clock_enable
assign CAN_FIRE_RL_uart_baud_generator_clock_enable = 1'd1 ;
assign WILL_FIRE_RL_uart_baud_generator_clock_enable = 1'd1 ;
// rule RL_uart_receive_wait_for_start_bit
assign CAN_FIRE_RL_uart_receive_wait_for_start_bit =
uart_rRecvState == 3'd0 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_wait_for_start_bit =
CAN_FIRE_RL_uart_receive_wait_for_start_bit ;
// rule RL_uart_receive_find_center_of_bit_cell
assign CAN_FIRE_RL_uart_receive_find_center_of_bit_cell =
uart_rRecvState == 3'd1 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_find_center_of_bit_cell =
CAN_FIRE_RL_uart_receive_find_center_of_bit_cell ;
// rule RL_uart_receive_wait_bit_cell_time_for_sample
assign CAN_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample =
uart_rRecvState == 3'd2 && uart_rRecvCellCount == 4'hF &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample =
CAN_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample ;
// rule RL_uart_receive_sample_pin
assign CAN_FIRE_RL_uart_receive_sample_pin =
CAN_FIRE_RL_uart_receive_buffer_shift ;
assign WILL_FIRE_RL_uart_receive_sample_pin =
CAN_FIRE_RL_uart_receive_buffer_shift ;
// rule RL_uart_receive_parity_bit
assign CAN_FIRE_RL_uart_receive_parity_bit =
uart_rRecvState == 3'd4 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_parity_bit =
CAN_FIRE_RL_uart_receive_parity_bit ;
// rule RL_uart_receive_stop_first_bit
assign CAN_FIRE_RL_uart_receive_stop_first_bit =
uart_rRecvState == 3'd5 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_stop_first_bit =
CAN_FIRE_RL_uart_receive_stop_first_bit ;
// rule RL_uart_receive_bit_counter
assign CAN_FIRE_RL_uart_receive_bit_counter = 1'd1 ;
assign WILL_FIRE_RL_uart_receive_bit_counter = 1'd1 ;
// rule RL_uart_receive_stop_last_bit
assign CAN_FIRE_RL_uart_receive_stop_last_bit =
uart_rRecvState == 3'd6 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_stop_last_bit =
CAN_FIRE_RL_uart_receive_stop_last_bit ;
// rule RL_uart_receive_bit_cell_time_counter
assign CAN_FIRE_RL_uart_receive_bit_cell_time_counter =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
assign WILL_FIRE_RL_uart_receive_bit_cell_time_counter =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// rule RL_uart_receive_buffer_shift
assign CAN_FIRE_RL_uart_receive_buffer_shift =
uart_rRecvState == 3'd3 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_buffer_shift =
CAN_FIRE_RL_uart_receive_buffer_shift ;
// rule RL_uart_transmit_wait_for_start_command
assign CAN_FIRE_RL_uart_transmit_wait_for_start_command =
uart_rXmitState == 3'd0 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_wait_for_start_command =
CAN_FIRE_RL_uart_transmit_wait_for_start_command ;
// rule RL_get_result
assign CAN_FIRE_RL_get_result =
rule30$RDY_getResult && uart_fifoXmit$FULL_N &&
transmit_state == 2'd2 &&
!op_mode &&
xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302 &&
!xmas_fsm_start_reg ;
assign WILL_FIRE_RL_get_result = CAN_FIRE_RL_get_result ;
// rule RL_uart_transmit_send_start_bit
assign CAN_FIRE_RL_uart_transmit_send_start_bit =
uart_rXmitState == 3'd1 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_start_bit =
CAN_FIRE_RL_uart_transmit_send_start_bit ;
// rule RL_uart_transmit_wait_1_bit_cell_time
assign CAN_FIRE_RL_uart_transmit_wait_1_bit_cell_time =
uart_rXmitState == 3'd2 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time =
CAN_FIRE_RL_uart_transmit_wait_1_bit_cell_time ;
// rule RL_uart_transmit_bit_counter
assign CAN_FIRE_RL_uart_transmit_bit_counter = 1'd1 ;
assign WILL_FIRE_RL_uart_transmit_bit_counter = 1'd1 ;
// rule RL_uart_transmit_shift_next_bit
assign CAN_FIRE_RL_uart_transmit_shift_next_bit =
uart_rXmitState == 3'd3 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_shift_next_bit =
CAN_FIRE_RL_uart_transmit_shift_next_bit ;
// rule RL_uart_transmit_buffer_load
assign CAN_FIRE_RL_uart_transmit_buffer_load =
uart_fifoXmit$EMPTY_N && uart_pwXmitLoadBuffer$whas ;
assign WILL_FIRE_RL_uart_transmit_buffer_load =
CAN_FIRE_RL_uart_transmit_buffer_load ;
// rule RL_uart_transmit_buffer_shift
assign CAN_FIRE_RL_uart_transmit_buffer_shift =
!uart_pwXmitLoadBuffer$whas &&
CAN_FIRE_RL_uart_transmit_shift_next_bit ;
assign WILL_FIRE_RL_uart_transmit_buffer_shift =
CAN_FIRE_RL_uart_transmit_buffer_shift ;
// rule RL_uart_transmit_send_parity_bit
assign CAN_FIRE_RL_uart_transmit_send_parity_bit =
uart_rXmitState == 3'd7 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_parity_bit =
CAN_FIRE_RL_uart_transmit_send_parity_bit ;
// rule RL_uart_transmit_send_stop_bit
assign CAN_FIRE_RL_uart_transmit_send_stop_bit =
uart_rXmitState == 3'd4 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_stop_bit =
CAN_FIRE_RL_uart_transmit_send_stop_bit ;
// rule RL_uart_transmit_send_stop_bit1_5
assign CAN_FIRE_RL_uart_transmit_send_stop_bit1_5 =
uart_rXmitState == 3'd5 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 =
CAN_FIRE_RL_uart_transmit_send_stop_bit1_5 ;
// rule RL_uart_transmit_send_stop_bit2
assign CAN_FIRE_RL_uart_transmit_send_stop_bit2 =
uart_rXmitState == 3'd6 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_stop_bit2 =
CAN_FIRE_RL_uart_transmit_send_stop_bit2 ;
// rule RL_uart_transmit_bit_cell_time_counter
assign CAN_FIRE_RL_uart_transmit_bit_cell_time_counter =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
assign WILL_FIRE_RL_uart_transmit_bit_cell_time_counter =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// rule RL_uart_baudGen_baud_tick_count_wire
assign CAN_FIRE_RL_uart_baudGen_baud_tick_count_wire = 1'd1 ;
assign WILL_FIRE_RL_uart_baudGen_baud_tick_count_wire = 1'd1 ;
// rule RL_uart_baudGen_assert_2x_baud_tick
assign CAN_FIRE_RL_uart_baudGen_assert_2x_baud_tick =
uart_baudGen_rBaudTickCounter$Q_OUT == 3'd0 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_baudGen_assert_2x_baud_tick =
CAN_FIRE_RL_uart_baudGen_assert_2x_baud_tick ;
// rule RL_uart_baudGen_count_baudtick_16x
assign CAN_FIRE_RL_uart_baudGen_count_baudtick_16x =
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_baudGen_count_baudtick_16x =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// rule RL_uart_fifoRecv__updateLevelCounter
assign CAN_FIRE_RL_uart_fifoRecv__updateLevelCounter =
CAN_FIRE_RL_uart_receive_stop_last_bit != uart_fifoRecv$EMPTY_N ;
assign WILL_FIRE_RL_uart_fifoRecv__updateLevelCounter =
CAN_FIRE_RL_uart_fifoRecv__updateLevelCounter ;
// rule RL_xmas_fsm_restart
assign CAN_FIRE_RL_xmas_fsm_restart =
xmas_fsm_start_reg_1 && !xmas_fsm_state_fired ;
assign WILL_FIRE_RL_xmas_fsm_restart = CAN_FIRE_RL_xmas_fsm_restart ;
// rule RL_xmas_fsm_action_l43c32
assign CAN_FIRE_RL_xmas_fsm_action_l43c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd1 ;
assign WILL_FIRE_RL_xmas_fsm_action_l43c32 =
CAN_FIRE_RL_xmas_fsm_action_l43c32 ;
// rule RL_xmas_fsm_action_l44c32
assign CAN_FIRE_RL_xmas_fsm_action_l44c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd2 ;
assign WILL_FIRE_RL_xmas_fsm_action_l44c32 =
CAN_FIRE_RL_xmas_fsm_action_l44c32 ;
// rule RL_xmas_fsm_action_l45c32
assign CAN_FIRE_RL_xmas_fsm_action_l45c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd3 ;
assign WILL_FIRE_RL_xmas_fsm_action_l45c32 =
CAN_FIRE_RL_xmas_fsm_action_l45c32 ;
// rule RL_xmas_fsm_action_l46c32
assign CAN_FIRE_RL_xmas_fsm_action_l46c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd4 ;
assign WILL_FIRE_RL_xmas_fsm_action_l46c32 =
CAN_FIRE_RL_xmas_fsm_action_l46c32 ;
// rule RL_xmas_fsm_action_l47c32
assign CAN_FIRE_RL_xmas_fsm_action_l47c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd5 ;
assign WILL_FIRE_RL_xmas_fsm_action_l47c32 =
CAN_FIRE_RL_xmas_fsm_action_l47c32 ;
// rule RL_xmas_fsm_action_l48c32
assign CAN_FIRE_RL_xmas_fsm_action_l48c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd6 ;
assign WILL_FIRE_RL_xmas_fsm_action_l48c32 =
CAN_FIRE_RL_xmas_fsm_action_l48c32 ;
// rule RL_xmas_fsm_action_l49c32
assign CAN_FIRE_RL_xmas_fsm_action_l49c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd7 ;
assign WILL_FIRE_RL_xmas_fsm_action_l49c32 =
CAN_FIRE_RL_xmas_fsm_action_l49c32 ;
// rule RL_xmas_fsm_action_l50c32
assign CAN_FIRE_RL_xmas_fsm_action_l50c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd8 ;
assign WILL_FIRE_RL_xmas_fsm_action_l50c32 =
CAN_FIRE_RL_xmas_fsm_action_l50c32 ;
// rule RL_xmas_fsm_action_l51c32
assign CAN_FIRE_RL_xmas_fsm_action_l51c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd9 ;
assign WILL_FIRE_RL_xmas_fsm_action_l51c32 =
CAN_FIRE_RL_xmas_fsm_action_l51c32 ;
// rule RL_xmas_fsm_action_l52c32
assign CAN_FIRE_RL_xmas_fsm_action_l52c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd10 ;
assign WILL_FIRE_RL_xmas_fsm_action_l52c32 =
CAN_FIRE_RL_xmas_fsm_action_l52c32 ;
// rule RL_xmas_fsm_action_l53c32
assign CAN_FIRE_RL_xmas_fsm_action_l53c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd11 ;
assign WILL_FIRE_RL_xmas_fsm_action_l53c32 =
CAN_FIRE_RL_xmas_fsm_action_l53c32 ;
// rule RL_xmas_fsm_action_l54c32
assign CAN_FIRE_RL_xmas_fsm_action_l54c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd12 ;
assign WILL_FIRE_RL_xmas_fsm_action_l54c32 =
CAN_FIRE_RL_xmas_fsm_action_l54c32 ;
// rule RL_xmas_fsm_action_l55c32
assign CAN_FIRE_RL_xmas_fsm_action_l55c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd13 ;
assign WILL_FIRE_RL_xmas_fsm_action_l55c32 =
CAN_FIRE_RL_xmas_fsm_action_l55c32 ;
// rule RL_xmas_fsm_action_l56c32
assign CAN_FIRE_RL_xmas_fsm_action_l56c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd14 ;
assign WILL_FIRE_RL_xmas_fsm_action_l56c32 =
CAN_FIRE_RL_xmas_fsm_action_l56c32 ;
// rule RL_xmas_fsm_action_l57c32
assign CAN_FIRE_RL_xmas_fsm_action_l57c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd15 ;
assign WILL_FIRE_RL_xmas_fsm_action_l57c32 =
CAN_FIRE_RL_xmas_fsm_action_l57c32 ;
// rule RL_xmas_fsm_action_l58c32
assign CAN_FIRE_RL_xmas_fsm_action_l58c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd16 ;
assign WILL_FIRE_RL_xmas_fsm_action_l58c32 =
CAN_FIRE_RL_xmas_fsm_action_l58c32 ;
// rule RL_xmas_fsm_action_l59c32
assign CAN_FIRE_RL_xmas_fsm_action_l59c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd17 ;
assign WILL_FIRE_RL_xmas_fsm_action_l59c32 =
CAN_FIRE_RL_xmas_fsm_action_l59c32 ;
// rule RL_xmas_fsm_action_l60c32
assign CAN_FIRE_RL_xmas_fsm_action_l60c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd18 ;
assign WILL_FIRE_RL_xmas_fsm_action_l60c32 =
CAN_FIRE_RL_xmas_fsm_action_l60c32 ;
// rule RL_xmas_fsm_action_l61c32
assign CAN_FIRE_RL_xmas_fsm_action_l61c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd19 ;
assign WILL_FIRE_RL_xmas_fsm_action_l61c32 =
CAN_FIRE_RL_xmas_fsm_action_l61c32 ;
// rule RL_xmas_fsm_action_l62c32
assign CAN_FIRE_RL_xmas_fsm_action_l62c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd20 ;
assign WILL_FIRE_RL_xmas_fsm_action_l62c32 =
CAN_FIRE_RL_xmas_fsm_action_l62c32 ;
// rule RL_xmas_fsm_action_l63c32
assign CAN_FIRE_RL_xmas_fsm_action_l63c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd21 ;
assign WILL_FIRE_RL_xmas_fsm_action_l63c32 =
CAN_FIRE_RL_xmas_fsm_action_l63c32 ;
// rule RL_xmas_fsm_action_l64c32
assign CAN_FIRE_RL_xmas_fsm_action_l64c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd22 ;
assign WILL_FIRE_RL_xmas_fsm_action_l64c32 =
CAN_FIRE_RL_xmas_fsm_action_l64c32 ;
// rule RL_xmas_fsm_action_l65c32
assign CAN_FIRE_RL_xmas_fsm_action_l65c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd23 ;
assign WILL_FIRE_RL_xmas_fsm_action_l65c32 =
CAN_FIRE_RL_xmas_fsm_action_l65c32 ;
// rule RL_xmas_fsm_action_l66c32
assign CAN_FIRE_RL_xmas_fsm_action_l66c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd24 ;
assign WILL_FIRE_RL_xmas_fsm_action_l66c32 =
CAN_FIRE_RL_xmas_fsm_action_l66c32 ;
// rule __me_check_35
assign CAN_FIRE___me_check_35 = 1'b1 ;
assign WILL_FIRE___me_check_35 = 1'b1 ;
// rule __me_check_36
assign CAN_FIRE___me_check_36 = 1'b1 ;
assign WILL_FIRE___me_check_36 = 1'b1 ;
// rule __me_check_37
assign CAN_FIRE___me_check_37 = 1'b1 ;
assign WILL_FIRE___me_check_37 = 1'b1 ;
// rule __me_check_38
assign CAN_FIRE___me_check_38 = 1'b1 ;
assign WILL_FIRE___me_check_38 = 1'b1 ;
// rule __me_check_39
assign CAN_FIRE___me_check_39 = 1'b1 ;
assign WILL_FIRE___me_check_39 = 1'b1 ;
// rule __me_check_40
assign CAN_FIRE___me_check_40 = 1'b1 ;
assign WILL_FIRE___me_check_40 = 1'b1 ;
// rule __me_check_41
assign CAN_FIRE___me_check_41 = 1'b1 ;
assign WILL_FIRE___me_check_41 = 1'b1 ;
// rule __me_check_43
assign CAN_FIRE___me_check_43 = 1'b1 ;
assign WILL_FIRE___me_check_43 = 1'b1 ;
// rule __me_check_42
assign CAN_FIRE___me_check_42 = 1'b1 ;
assign WILL_FIRE___me_check_42 = 1'b1 ;
// rule __me_check_44
assign CAN_FIRE___me_check_44 = 1'b1 ;
assign WILL_FIRE___me_check_44 = 1'b1 ;
// rule __me_check_45
assign CAN_FIRE___me_check_45 = 1'b1 ;
assign WILL_FIRE___me_check_45 = 1'b1 ;
// rule __me_check_46
assign CAN_FIRE___me_check_46 = 1'b1 ;
assign WILL_FIRE___me_check_46 = 1'b1 ;
// rule __me_check_47
assign CAN_FIRE___me_check_47 = 1'b1 ;
assign WILL_FIRE___me_check_47 = 1'b1 ;
// rule __me_check_48
assign CAN_FIRE___me_check_48 = 1'b1 ;
assign WILL_FIRE___me_check_48 = 1'b1 ;
// rule __me_check_49
assign CAN_FIRE___me_check_49 = 1'b1 ;
assign WILL_FIRE___me_check_49 = 1'b1 ;
// rule __me_check_51
assign CAN_FIRE___me_check_51 = 1'b1 ;
assign WILL_FIRE___me_check_51 = 1'b1 ;
// rule __me_check_50
assign CAN_FIRE___me_check_50 = 1'b1 ;
assign WILL_FIRE___me_check_50 = 1'b1 ;
// rule __me_check_52
assign CAN_FIRE___me_check_52 = 1'b1 ;
assign WILL_FIRE___me_check_52 = 1'b1 ;
// rule __me_check_53
assign CAN_FIRE___me_check_53 = 1'b1 ;
assign WILL_FIRE___me_check_53 = 1'b1 ;
// rule __me_check_54
assign CAN_FIRE___me_check_54 = 1'b1 ;
assign WILL_FIRE___me_check_54 = 1'b1 ;
// rule __me_check_55
assign CAN_FIRE___me_check_55 = 1'b1 ;
assign WILL_FIRE___me_check_55 = 1'b1 ;
// rule __me_check_56
assign CAN_FIRE___me_check_56 = 1'b1 ;
assign WILL_FIRE___me_check_56 = 1'b1 ;
// rule __me_check_57
assign CAN_FIRE___me_check_57 = 1'b1 ;
assign WILL_FIRE___me_check_57 = 1'b1 ;
// rule RL_xmas_fsm_idle_l40c27_1
assign CAN_FIRE_RL_xmas_fsm_idle_l40c27_1 =
!op_mode && xmas_fsm_state_mkFSMstate == 5'd25 ;
assign WILL_FIRE_RL_xmas_fsm_idle_l40c27_1 =
CAN_FIRE_RL_xmas_fsm_idle_l40c27_1 ;
// rule RL_xmas_fsm_fsm_start
assign CAN_FIRE_RL_xmas_fsm_fsm_start =
(op_mode && xmas_fsm_state_mkFSMstate == 5'd0 ||
op_mode && xmas_fsm_state_mkFSMstate == 5'd27 ||
!op_mode && xmas_fsm_state_mkFSMstate == 5'd0 ||
!op_mode &&
(xmas_fsm_state_mkFSMstate == 5'd25 ||
xmas_fsm_state_mkFSMstate == 5'd27)) &&
(!xmas_fsm_start_reg_1 || xmas_fsm_state_fired) &&
xmas_fsm_start_reg ;
assign WILL_FIRE_RL_xmas_fsm_fsm_start = CAN_FIRE_RL_xmas_fsm_fsm_start ;
// rule RL_xmas_fsm_action_l42c32
assign CAN_FIRE_RL_xmas_fsm_action_l42c32 =
uart_fifoXmit$FULL_N &&
(op_mode && xmas_fsm_start_wire$whas &&
xmas_fsm_state_mkFSMstate == 5'd0 ||
op_mode && xmas_fsm_state_mkFSMstate == 5'd25) ;
assign WILL_FIRE_RL_xmas_fsm_action_l42c32 =
CAN_FIRE_RL_xmas_fsm_action_l42c32 ;
// rule __me_check_34
assign CAN_FIRE___me_check_34 = 1'b1 ;
assign WILL_FIRE___me_check_34 = 1'b1 ;
// rule RL_uart_fifoXmit__updateLevelCounter
assign CAN_FIRE_RL_uart_fifoXmit__updateLevelCounter =
uart_fifoXmit_r_enq$whas !=
CAN_FIRE_RL_uart_transmit_buffer_load ;
assign WILL_FIRE_RL_uart_fifoXmit__updateLevelCounter =
CAN_FIRE_RL_uart_fifoXmit__updateLevelCounter ;
// rule RL_xmas_fsm_idle_l40c27
assign CAN_FIRE_RL_xmas_fsm_idle_l40c27 =
!op_mode && xmas_fsm_start_wire$whas &&
xmas_fsm_state_mkFSMstate == 5'd0 ;
assign WILL_FIRE_RL_xmas_fsm_idle_l40c27 =
CAN_FIRE_RL_xmas_fsm_idle_l40c27 ;
// rule RL_xmas_fsm_start_reg__dreg_update
assign CAN_FIRE_RL_xmas_fsm_start_reg__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_xmas_fsm_start_reg__dreg_update = 1'd1 ;
// rule RL_xmas_fsm_state_handle_abort
assign CAN_FIRE_RL_xmas_fsm_state_handle_abort = 1'b0 ;
assign WILL_FIRE_RL_xmas_fsm_state_handle_abort = 1'b0 ;
// rule RL_xmas_fsm_state_every
assign CAN_FIRE_RL_xmas_fsm_state_every = 1'd1 ;
assign WILL_FIRE_RL_xmas_fsm_state_every = 1'd1 ;
// rule RL_xmas_fsm_state_fired__dreg_update
assign CAN_FIRE_RL_xmas_fsm_state_fired__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_xmas_fsm_state_fired__dreg_update = 1'd1 ;
// inputs to muxes for submodule ports
assign MUX_transmit_state$write_1__SEL_1 =
WILL_FIRE_RL_get_result || EN_startup_value ;
assign MUX_uart_fifoXmit$enq_1__SEL_2 =
WILL_FIRE_RL_xmas_fsm_action_l66c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_3 =
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_11 =
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_15 =
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_16 =
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_17 =
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ;
assign MUX_uart_rRecvState$write_1__SEL_6 =
WILL_FIRE_RL_uart_receive_parity_bit ||
WILL_FIRE_RL_uart_receive_sample_pin ;
assign MUX_uart_rXmitDataOut$write_1__SEL_1 =
WILL_FIRE_RL_uart_transmit_shift_next_bit ||
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ;
assign MUX_uart_rXmitDataOut$write_1__SEL_2 =
WILL_FIRE_RL_uart_transmit_send_parity_bit ||
WILL_FIRE_RL_uart_transmit_send_start_bit ;
assign MUX_uart_rXmitDataOut$write_1__SEL_3 =
WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit ||
WILL_FIRE_RL_uart_transmit_wait_for_start_command ;
assign MUX_xmas_fsm_start_reg$write_1__SEL_1 =
EN_operation_mode && operation_mode_arg == 8'hA5 ;
assign MUX_xmas_fsm_state_mkFSMstate$write_1__SEL_1 =
WILL_FIRE_RL_xmas_fsm_idle_l40c27_1 ||
WILL_FIRE_RL_xmas_fsm_idle_l40c27 ;
assign MUX_uart_rRecvState$write_1__VAL_1 = uart_rRecvData ? 3'd0 : 3'd1 ;
assign MUX_uart_rRecvState$write_1__VAL_2 =
(uart_rRecvCellCount == 4'h4) ?
(uart_rRecvData ? 3'd0 : 3'd2) :
3'd1 ;
always@(uart_rRecvBitCount)
begin
case (uart_rRecvBitCount)
4'd8, 4'd9, 4'd10: MUX_uart_rRecvState$write_1__VAL_3 = 3'd6;
default: MUX_uart_rRecvState$write_1__VAL_3 = 3'd3;
endcase
end
assign MUX_uart_rRecvState$write_1__VAL_4 = uart_rRecvData ? 3'd2 : 3'd0 ;
assign MUX_uart_rXmitState$write_1__VAL_1 =
uart_fifoXmit$EMPTY_N ? 3'd1 : 3'd0 ;
assign MUX_uart_rXmitState$write_1__VAL_2 =
(uart_rXmitCellCount == 4'hF) ? 3'd2 : 3'd1 ;
assign MUX_uart_rXmitState$write_1__VAL_3 =
(uart_rXmitCellCount == 4'hF) ?
((uart_rXmitBitCount == 4'd7) ? 3'd4 : 3'd3) :
3'd2 ;
assign MUX_uart_rXmitState$write_1__VAL_4 =
(uart_rXmitCellCount == 4'hF) ? 3'd4 : 3'd7 ;
assign MUX_uart_rXmitState$write_1__VAL_5 =
(uart_rXmitCellCount == 4'hF) ? 3'd0 : 3'd4 ;
assign MUX_uart_rXmitState$write_1__VAL_6 =
(uart_rXmitCellCount == 4'h7) ? 3'd0 : 3'd5 ;
assign MUX_uart_rXmitState$write_1__VAL_7 =
(uart_rXmitCellCount == 4'hF) ? 3'd0 : 3'd6 ;
// inlined wires
assign xmas_fsm_start_wire$whas =
WILL_FIRE_RL_xmas_fsm_fsm_start ||
WILL_FIRE_RL_xmas_fsm_restart ;
assign uart_pwRecvCellCountReset$whas =
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell &&
uart_rRecvCellCount == 4'h4 ||
WILL_FIRE_RL_uart_receive_stop_last_bit ||
WILL_FIRE_RL_uart_receive_stop_first_bit ||
WILL_FIRE_RL_uart_receive_parity_bit ||
WILL_FIRE_RL_uart_receive_sample_pin ||
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample ||
WILL_FIRE_RL_uart_receive_wait_for_start_bit ;
assign uart_pwRecvResetBitCount$whas =
WILL_FIRE_RL_uart_receive_wait_for_start_bit && uart_rRecvData ;
assign uart_pwRecvEnableBitCount$whas =
WILL_FIRE_RL_uart_receive_stop_first_bit ||
WILL_FIRE_RL_uart_receive_parity_bit ||
WILL_FIRE_RL_uart_receive_sample_pin ;
assign uart_fifoXmit_r_enq$whas =
WILL_FIRE_RL_get_result || WILL_FIRE_RL_xmas_fsm_action_l66c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ||
WILL_FIRE_RL_xmas_fsm_action_l64c32 ||
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l62c32 ||
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ||
WILL_FIRE_RL_xmas_fsm_action_l57c32 ||
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l55c32 ||
WILL_FIRE_RL_xmas_fsm_action_l54c32 ||
WILL_FIRE_RL_xmas_fsm_action_l53c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ||
WILL_FIRE_RL_xmas_fsm_action_l49c32 ||
WILL_FIRE_RL_xmas_fsm_action_l48c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ||
WILL_FIRE_RL_xmas_fsm_action_l46c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ||
WILL_FIRE_RL_xmas_fsm_action_l43c32 ||
WILL_FIRE_RL_xmas_fsm_action_l42c32 ;
assign uart_pwXmitCellCountReset$whas =
WILL_FIRE_RL_uart_transmit_wait_for_start_command &&
uart_fifoXmit$EMPTY_N ||
_dor2uart_pwXmitCellCountReset$EN_wset &&
uart_rXmitCellCount == 4'hF ||
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 &&
uart_rXmitCellCount == 4'h7 ;
assign uart_pwXmitEnableBitCount$whas =
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time &&
uart_rXmitCellCount == 4'hF &&
uart_rXmitBitCount != 4'd7 ;
assign uart_pwXmitLoadBuffer$whas =
WILL_FIRE_RL_uart_transmit_wait_for_start_command &&
uart_fifoXmit$EMPTY_N ;
assign xmas_fsm_state_set_pw$whas =
WILL_FIRE_RL_xmas_fsm_idle_l40c27_1 ||
WILL_FIRE_RL_xmas_fsm_idle_l40c27 ||
WILL_FIRE_RL_xmas_fsm_action_l66c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ||
WILL_FIRE_RL_xmas_fsm_action_l64c32 ||
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l62c32 ||
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ||
WILL_FIRE_RL_xmas_fsm_action_l57c32 ||
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l55c32 ||
WILL_FIRE_RL_xmas_fsm_action_l54c32 ||
WILL_FIRE_RL_xmas_fsm_action_l53c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ||
WILL_FIRE_RL_xmas_fsm_action_l49c32 ||
WILL_FIRE_RL_xmas_fsm_action_l48c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ||
WILL_FIRE_RL_xmas_fsm_action_l46c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ||
WILL_FIRE_RL_xmas_fsm_action_l43c32 ||
WILL_FIRE_RL_xmas_fsm_action_l42c32 ;
// register a
assign a$D_IN = EN_startup_value ? startup_value_v : rule30$getResult ;
assign a$EN = EN_startup_value || WILL_FIRE_RL_get_result ;
// register op_mode
assign op_mode$D_IN = 1'd1 ;
assign op_mode$EN = MUX_xmas_fsm_start_reg$write_1__SEL_1 ;
// register transmit_state
assign transmit_state$D_IN =
MUX_transmit_state$write_1__SEL_1 ? 2'd1 : 2'd2 ;
assign transmit_state$EN =
WILL_FIRE_RL_get_result || EN_startup_value ||
WILL_FIRE_RL_compute ;
// register uart_rRecvBitCount
assign uart_rRecvBitCount$D_IN =
uart_pwRecvResetBitCount$whas ? 4'd0 : x__h4689 ;
assign uart_rRecvBitCount$EN =
uart_pwRecvResetBitCount$whas || uart_pwRecvEnableBitCount$whas ;
// register uart_rRecvCellCount
assign uart_rRecvCellCount$D_IN =
uart_pwRecvCellCountReset$whas ? 4'd0 : x__h2985 ;
assign uart_rRecvCellCount$EN =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// register uart_rRecvData
assign uart_rRecvData$D_IN = txrx_SIN ;
assign uart_rRecvData$EN = 1'd1 ;
// register uart_rRecvState
always@(WILL_FIRE_RL_uart_receive_wait_for_start_bit or
MUX_uart_rRecvState$write_1__VAL_1 or
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell or
MUX_uart_rRecvState$write_1__VAL_2 or
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample or
MUX_uart_rRecvState$write_1__VAL_3 or
WILL_FIRE_RL_uart_receive_stop_first_bit or
MUX_uart_rRecvState$write_1__VAL_4 or
WILL_FIRE_RL_uart_receive_stop_last_bit or
MUX_uart_rRecvState$write_1__SEL_6)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_uart_receive_wait_for_start_bit:
uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_1;
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell:
uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_2;
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample:
uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_3;
WILL_FIRE_RL_uart_receive_stop_first_bit:
uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_4;
WILL_FIRE_RL_uart_receive_stop_last_bit: uart_rRecvState$D_IN = 3'd0;
MUX_uart_rRecvState$write_1__SEL_6: uart_rRecvState$D_IN = 3'd2;
default: uart_rRecvState$D_IN = 3'b010 /* unspecified value */ ;
endcase
end
assign uart_rRecvState$EN =
WILL_FIRE_RL_uart_receive_wait_for_start_bit ||
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell ||
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample ||
WILL_FIRE_RL_uart_receive_stop_first_bit ||
WILL_FIRE_RL_uart_receive_stop_last_bit ||
WILL_FIRE_RL_uart_receive_parity_bit ||
WILL_FIRE_RL_uart_receive_sample_pin ;
// register uart_rXmitBitCount
assign uart_rXmitBitCount$D_IN =
CAN_FIRE_RL_uart_transmit_wait_for_start_command ?
4'd0 :
x__h6471 ;
assign uart_rXmitBitCount$EN =
CAN_FIRE_RL_uart_transmit_wait_for_start_command ||
uart_pwXmitEnableBitCount$whas ;
// register uart_rXmitCellCount
assign uart_rXmitCellCount$D_IN =
uart_pwXmitCellCountReset$whas ? 4'd0 : x__h6445 ;
assign uart_rXmitCellCount$EN =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// register uart_rXmitDataOut
always@(MUX_uart_rXmitDataOut$write_1__SEL_1 or
uart_vrXmitBuffer_0 or
MUX_uart_rXmitDataOut$write_1__SEL_2 or
MUX_uart_rXmitDataOut$write_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_uart_rXmitDataOut$write_1__SEL_1:
uart_rXmitDataOut$D_IN = uart_vrXmitBuffer_0;
MUX_uart_rXmitDataOut$write_1__SEL_2: uart_rXmitDataOut$D_IN = 1'b0;
MUX_uart_rXmitDataOut$write_1__SEL_3: uart_rXmitDataOut$D_IN = 1'b1;
default: uart_rXmitDataOut$D_IN = 1'b0 /* unspecified value */ ;
endcase
end
assign uart_rXmitDataOut$EN =
WILL_FIRE_RL_uart_transmit_shift_next_bit ||
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ||
WILL_FIRE_RL_uart_transmit_send_parity_bit ||
WILL_FIRE_RL_uart_transmit_send_start_bit ||
WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit ||
WILL_FIRE_RL_uart_transmit_wait_for_start_command ;
// register uart_rXmitState
always@(WILL_FIRE_RL_uart_transmit_wait_for_start_command or
MUX_uart_rXmitState$write_1__VAL_1 or
WILL_FIRE_RL_uart_transmit_send_start_bit or
MUX_uart_rXmitState$write_1__VAL_2 or
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time or
MUX_uart_rXmitState$write_1__VAL_3 or
WILL_FIRE_RL_uart_transmit_send_parity_bit or
MUX_uart_rXmitState$write_1__VAL_4 or
WILL_FIRE_RL_uart_transmit_send_stop_bit or
MUX_uart_rXmitState$write_1__VAL_5 or
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 or
MUX_uart_rXmitState$write_1__VAL_6 or
WILL_FIRE_RL_uart_transmit_send_stop_bit2 or
MUX_uart_rXmitState$write_1__VAL_7 or
WILL_FIRE_RL_uart_transmit_shift_next_bit)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_uart_transmit_wait_for_start_command:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_1;
WILL_FIRE_RL_uart_transmit_send_start_bit:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_2;
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_3;
WILL_FIRE_RL_uart_transmit_send_parity_bit:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_4;
WILL_FIRE_RL_uart_transmit_send_stop_bit:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_5;
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_6;
WILL_FIRE_RL_uart_transmit_send_stop_bit2:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_7;
WILL_FIRE_RL_uart_transmit_shift_next_bit: uart_rXmitState$D_IN = 3'd2;
default: uart_rXmitState$D_IN = 3'b010 /* unspecified value */ ;
endcase
end
assign uart_rXmitState$EN =
WILL_FIRE_RL_uart_transmit_wait_for_start_command ||
WILL_FIRE_RL_uart_transmit_send_start_bit ||
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ||
WILL_FIRE_RL_uart_transmit_send_parity_bit ||
WILL_FIRE_RL_uart_transmit_send_stop_bit ||
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
WILL_FIRE_RL_uart_transmit_shift_next_bit ;
// register uart_vrRecvBuffer_0
assign uart_vrRecvBuffer_0$D_IN = uart_vrRecvBuffer_1 ;
assign uart_vrRecvBuffer_0$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_1
assign uart_vrRecvBuffer_1$D_IN = uart_vrRecvBuffer_2 ;
assign uart_vrRecvBuffer_1$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_2
assign uart_vrRecvBuffer_2$D_IN = uart_vrRecvBuffer_3 ;
assign uart_vrRecvBuffer_2$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_3
assign uart_vrRecvBuffer_3$D_IN = uart_vrRecvBuffer_4 ;
assign uart_vrRecvBuffer_3$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_4
assign uart_vrRecvBuffer_4$D_IN = uart_vrRecvBuffer_5 ;
assign uart_vrRecvBuffer_4$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_5
assign uart_vrRecvBuffer_5$D_IN = uart_vrRecvBuffer_6 ;
assign uart_vrRecvBuffer_5$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_6
assign uart_vrRecvBuffer_6$D_IN = uart_vrRecvBuffer_7 ;
assign uart_vrRecvBuffer_6$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_7
assign uart_vrRecvBuffer_7$D_IN = uart_rRecvData ;
assign uart_vrRecvBuffer_7$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrXmitBuffer_0
assign uart_vrXmitBuffer_0$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[0] :
uart_vrXmitBuffer_1 ;
assign uart_vrXmitBuffer_0$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_1
assign uart_vrXmitBuffer_1$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[1] :
uart_vrXmitBuffer_2 ;
assign uart_vrXmitBuffer_1$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_2
assign uart_vrXmitBuffer_2$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[2] :
uart_vrXmitBuffer_3 ;
assign uart_vrXmitBuffer_2$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_3
assign uart_vrXmitBuffer_3$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[3] :
uart_vrXmitBuffer_4 ;
assign uart_vrXmitBuffer_3$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_4
assign uart_vrXmitBuffer_4$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[4] :
uart_vrXmitBuffer_5 ;
assign uart_vrXmitBuffer_4$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_5
assign uart_vrXmitBuffer_5$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[5] :
uart_vrXmitBuffer_6 ;
assign uart_vrXmitBuffer_5$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_6
assign uart_vrXmitBuffer_6$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[6] :
uart_vrXmitBuffer_7 ;
assign uart_vrXmitBuffer_6$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_7
assign uart_vrXmitBuffer_7$D_IN =
!WILL_FIRE_RL_uart_transmit_buffer_load ||
uart_fifoXmit$D_OUT[7] ;
assign uart_vrXmitBuffer_7$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register xmas_fsm_start_reg
assign xmas_fsm_start_reg$D_IN = MUX_xmas_fsm_start_reg$write_1__SEL_1 ;
assign xmas_fsm_start_reg$EN =
EN_operation_mode && operation_mode_arg == 8'hA5 ||
WILL_FIRE_RL_xmas_fsm_fsm_start ;
// register xmas_fsm_start_reg_1
assign xmas_fsm_start_reg_1$D_IN = xmas_fsm_start_wire$whas ;
assign xmas_fsm_start_reg_1$EN = 1'd1 ;
// register xmas_fsm_state_fired
assign xmas_fsm_state_fired$D_IN = xmas_fsm_state_set_pw$whas ;
assign xmas_fsm_state_fired$EN = 1'd1 ;
// register xmas_fsm_state_mkFSMstate
always@(MUX_xmas_fsm_state_mkFSMstate$write_1__SEL_1 or
WILL_FIRE_RL_xmas_fsm_action_l42c32 or
WILL_FIRE_RL_xmas_fsm_action_l43c32 or
WILL_FIRE_RL_xmas_fsm_action_l44c32 or
WILL_FIRE_RL_xmas_fsm_action_l45c32 or
WILL_FIRE_RL_xmas_fsm_action_l46c32 or
WILL_FIRE_RL_xmas_fsm_action_l47c32 or
WILL_FIRE_RL_xmas_fsm_action_l48c32 or
WILL_FIRE_RL_xmas_fsm_action_l49c32 or
WILL_FIRE_RL_xmas_fsm_action_l50c32 or
WILL_FIRE_RL_xmas_fsm_action_l51c32 or
WILL_FIRE_RL_xmas_fsm_action_l52c32 or
WILL_FIRE_RL_xmas_fsm_action_l53c32 or
WILL_FIRE_RL_xmas_fsm_action_l54c32 or
WILL_FIRE_RL_xmas_fsm_action_l55c32 or
WILL_FIRE_RL_xmas_fsm_action_l56c32 or
WILL_FIRE_RL_xmas_fsm_action_l57c32 or
WILL_FIRE_RL_xmas_fsm_action_l58c32 or
WILL_FIRE_RL_xmas_fsm_action_l59c32 or
WILL_FIRE_RL_xmas_fsm_action_l60c32 or
WILL_FIRE_RL_xmas_fsm_action_l61c32 or
WILL_FIRE_RL_xmas_fsm_action_l62c32 or
WILL_FIRE_RL_xmas_fsm_action_l63c32 or
WILL_FIRE_RL_xmas_fsm_action_l64c32 or
WILL_FIRE_RL_xmas_fsm_action_l65c32 or
WILL_FIRE_RL_xmas_fsm_action_l66c32)
begin
case (1'b1) // synopsys parallel_case
MUX_xmas_fsm_state_mkFSMstate$write_1__SEL_1:
xmas_fsm_state_mkFSMstate$D_IN = 5'd0;
WILL_FIRE_RL_xmas_fsm_action_l42c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd1;
WILL_FIRE_RL_xmas_fsm_action_l43c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd2;
WILL_FIRE_RL_xmas_fsm_action_l44c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd3;
WILL_FIRE_RL_xmas_fsm_action_l45c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd4;
WILL_FIRE_RL_xmas_fsm_action_l46c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd5;
WILL_FIRE_RL_xmas_fsm_action_l47c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd6;
WILL_FIRE_RL_xmas_fsm_action_l48c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd7;
WILL_FIRE_RL_xmas_fsm_action_l49c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd8;
WILL_FIRE_RL_xmas_fsm_action_l50c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd9;
WILL_FIRE_RL_xmas_fsm_action_l51c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd10;
WILL_FIRE_RL_xmas_fsm_action_l52c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd11;
WILL_FIRE_RL_xmas_fsm_action_l53c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd12;
WILL_FIRE_RL_xmas_fsm_action_l54c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd13;
WILL_FIRE_RL_xmas_fsm_action_l55c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd14;
WILL_FIRE_RL_xmas_fsm_action_l56c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd15;
WILL_FIRE_RL_xmas_fsm_action_l57c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd16;
WILL_FIRE_RL_xmas_fsm_action_l58c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd17;
WILL_FIRE_RL_xmas_fsm_action_l59c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd18;
WILL_FIRE_RL_xmas_fsm_action_l60c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd19;
WILL_FIRE_RL_xmas_fsm_action_l61c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd20;
WILL_FIRE_RL_xmas_fsm_action_l62c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd21;
WILL_FIRE_RL_xmas_fsm_action_l63c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd22;
WILL_FIRE_RL_xmas_fsm_action_l64c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd23;
WILL_FIRE_RL_xmas_fsm_action_l65c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd24;
WILL_FIRE_RL_xmas_fsm_action_l66c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd25;
default: xmas_fsm_state_mkFSMstate$D_IN =
5'b01010 /* unspecified value */ ;
endcase
end
assign xmas_fsm_state_mkFSMstate$EN =
WILL_FIRE_RL_xmas_fsm_idle_l40c27_1 ||
WILL_FIRE_RL_xmas_fsm_idle_l40c27 ||
WILL_FIRE_RL_xmas_fsm_action_l42c32 ||
WILL_FIRE_RL_xmas_fsm_action_l43c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l46c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ||
WILL_FIRE_RL_xmas_fsm_action_l48c32 ||
WILL_FIRE_RL_xmas_fsm_action_l49c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l53c32 ||
WILL_FIRE_RL_xmas_fsm_action_l54c32 ||
WILL_FIRE_RL_xmas_fsm_action_l55c32 ||
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l57c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ||
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l62c32 ||
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l64c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ||
WILL_FIRE_RL_xmas_fsm_action_l66c32 ;
// submodule rule30
assign rule30$start_a = a ;
assign rule30$EN_start = CAN_FIRE_RL_compute ;
assign rule30$EN_getResult = CAN_FIRE_RL_get_result ;
// submodule uart_baudGen_rBaudCounter
assign uart_baudGen_rBaudCounter$DATA_A = 16'd1 ;
assign uart_baudGen_rBaudCounter$DATA_B = 16'h0 ;
assign uart_baudGen_rBaudCounter$DATA_C = 16'h0 ;
assign uart_baudGen_rBaudCounter$DATA_F = 16'd0 ;
assign uart_baudGen_rBaudCounter$ADDA =
uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign uart_baudGen_rBaudCounter$ADDB = 1'b0 ;
assign uart_baudGen_rBaudCounter$SETC = 1'b0 ;
assign uart_baudGen_rBaudCounter$SETF =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// submodule uart_baudGen_rBaudTickCounter
assign uart_baudGen_rBaudTickCounter$DATA_A = 3'd1 ;
assign uart_baudGen_rBaudTickCounter$DATA_B = 3'h0 ;
assign uart_baudGen_rBaudTickCounter$DATA_C = 3'h0 ;
assign uart_baudGen_rBaudTickCounter$DATA_F = 3'h0 ;
assign uart_baudGen_rBaudTickCounter$ADDA =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
assign uart_baudGen_rBaudTickCounter$ADDB = 1'b0 ;
assign uart_baudGen_rBaudTickCounter$SETC = 1'b0 ;
assign uart_baudGen_rBaudTickCounter$SETF = 1'b0 ;
// submodule uart_fifoRecv
assign uart_fifoRecv$D_IN =
{ uart_vrRecvBuffer_7,
uart_vrRecvBuffer_6,
uart_vrRecvBuffer_5,
uart_vrRecvBuffer_4,
uart_vrRecvBuffer_3,
uart_vrRecvBuffer_2,
uart_vrRecvBuffer_1,
uart_vrRecvBuffer_0 } ;
assign uart_fifoRecv$ENQ = CAN_FIRE_RL_uart_receive_stop_last_bit ;
assign uart_fifoRecv$DEQ = uart_fifoRecv$EMPTY_N ;
assign uart_fifoRecv$CLR = 1'b0 ;
// submodule uart_fifoXmit
always@(WILL_FIRE_RL_get_result or
rule30$getResult or
MUX_uart_fifoXmit$enq_1__SEL_2 or
MUX_uart_fifoXmit$enq_1__SEL_3 or
WILL_FIRE_RL_xmas_fsm_action_l64c32 or
WILL_FIRE_RL_xmas_fsm_action_l53c32 or
WILL_FIRE_RL_xmas_fsm_action_l54c32 or
WILL_FIRE_RL_xmas_fsm_action_l55c32 or
WILL_FIRE_RL_xmas_fsm_action_l42c32 or
WILL_FIRE_RL_xmas_fsm_action_l57c32 or
WILL_FIRE_RL_xmas_fsm_action_l48c32 or
MUX_uart_fifoXmit$enq_1__SEL_11 or
WILL_FIRE_RL_xmas_fsm_action_l43c32 or
WILL_FIRE_RL_xmas_fsm_action_l49c32 or
WILL_FIRE_RL_xmas_fsm_action_l62c32 or
MUX_uart_fifoXmit$enq_1__SEL_15 or
MUX_uart_fifoXmit$enq_1__SEL_16 or
MUX_uart_fifoXmit$enq_1__SEL_17 or
WILL_FIRE_RL_xmas_fsm_action_l46c32)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_get_result: uart_fifoXmit$D_IN = rule30$getResult;
MUX_uart_fifoXmit$enq_1__SEL_2: uart_fifoXmit$D_IN = 8'h09;
MUX_uart_fifoXmit$enq_1__SEL_3: uart_fifoXmit$D_IN = 8'h20;
WILL_FIRE_RL_xmas_fsm_action_l64c32: uart_fifoXmit$D_IN = 8'h21;
WILL_FIRE_RL_xmas_fsm_action_l53c32: uart_fifoXmit$D_IN = 8'h27;
WILL_FIRE_RL_xmas_fsm_action_l54c32: uart_fifoXmit$D_IN = 8'h32;
WILL_FIRE_RL_xmas_fsm_action_l55c32: uart_fifoXmit$D_IN = 8'h34;
WILL_FIRE_RL_xmas_fsm_action_l42c32: uart_fifoXmit$D_IN = 8'h4D;
WILL_FIRE_RL_xmas_fsm_action_l57c32: uart_fifoXmit$D_IN = 8'h53;
WILL_FIRE_RL_xmas_fsm_action_l48c32: uart_fifoXmit$D_IN = 8'h58;
MUX_uart_fifoXmit$enq_1__SEL_11: uart_fifoXmit$D_IN = 8'h61;
WILL_FIRE_RL_xmas_fsm_action_l43c32: uart_fifoXmit$D_IN = 8'h65;
WILL_FIRE_RL_xmas_fsm_action_l49c32: uart_fifoXmit$D_IN = 8'h6D;
WILL_FIRE_RL_xmas_fsm_action_l62c32: uart_fifoXmit$D_IN = 8'h6F;
MUX_uart_fifoXmit$enq_1__SEL_15: uart_fifoXmit$D_IN = 8'h72;
MUX_uart_fifoXmit$enq_1__SEL_16: uart_fifoXmit$D_IN = 8'h73;
MUX_uart_fifoXmit$enq_1__SEL_17: uart_fifoXmit$D_IN = 8'h74;
WILL_FIRE_RL_xmas_fsm_action_l46c32: uart_fifoXmit$D_IN = 8'h79;
default: uart_fifoXmit$D_IN = 8'b10101010 /* unspecified value */ ;
endcase
end
assign uart_fifoXmit$ENQ =
WILL_FIRE_RL_get_result || WILL_FIRE_RL_xmas_fsm_action_l66c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ||
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ||
WILL_FIRE_RL_xmas_fsm_action_l64c32 ||
WILL_FIRE_RL_xmas_fsm_action_l53c32 ||
WILL_FIRE_RL_xmas_fsm_action_l54c32 ||
WILL_FIRE_RL_xmas_fsm_action_l55c32 ||
WILL_FIRE_RL_xmas_fsm_action_l42c32 ||
WILL_FIRE_RL_xmas_fsm_action_l57c32 ||
WILL_FIRE_RL_xmas_fsm_action_l48c32 ||
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ||
WILL_FIRE_RL_xmas_fsm_action_l43c32 ||
WILL_FIRE_RL_xmas_fsm_action_l49c32 ||
WILL_FIRE_RL_xmas_fsm_action_l62c32 ||
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ||
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ||
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ||
WILL_FIRE_RL_xmas_fsm_action_l46c32 ;
assign uart_fifoXmit$DEQ = CAN_FIRE_RL_uart_transmit_buffer_load ;
assign uart_fifoXmit$CLR = 1'b0 ;
// remaining internal signals
assign _dor2uart_pwXmitCellCountReset$EN_wset =
WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit ||
WILL_FIRE_RL_uart_transmit_send_parity_bit ||
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ||
WILL_FIRE_RL_uart_transmit_send_start_bit ;
assign uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 =
uart_baudGen_rBaudCounter$Q_OUT + 16'd1 < 16'd27 ;
assign x__h2985 = uart_rRecvCellCount + 4'd1 ;
assign x__h4689 = uart_rRecvBitCount + 4'd1 ;
assign x__h6445 = uart_rXmitCellCount + 4'd1 ;
assign x__h6471 = uart_rXmitBitCount + 4'd1 ;
assign xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302 =
(xmas_fsm_state_mkFSMstate == 5'd0 ||
xmas_fsm_state_mkFSMstate == 5'd25 ||
xmas_fsm_state_mkFSMstate == 5'd27) &&
(!xmas_fsm_start_reg_1 || xmas_fsm_state_fired) ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
a <= `BSV_ASSIGNMENT_DELAY 8'b0;
op_mode <= `BSV_ASSIGNMENT_DELAY 1'd0;
transmit_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
uart_rRecvData <= `BSV_ASSIGNMENT_DELAY 1'd1;
xmas_fsm_start_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
xmas_fsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
xmas_fsm_state_fired <= `BSV_ASSIGNMENT_DELAY 1'd0;
xmas_fsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY 5'd0;
end
else
begin
if (a$EN) a <= `BSV_ASSIGNMENT_DELAY a$D_IN;
if (op_mode$EN) op_mode <= `BSV_ASSIGNMENT_DELAY op_mode$D_IN;
if (transmit_state$EN)
transmit_state <= `BSV_ASSIGNMENT_DELAY transmit_state$D_IN;
if (uart_rRecvData$EN)
uart_rRecvData <= `BSV_ASSIGNMENT_DELAY uart_rRecvData$D_IN;
if (xmas_fsm_start_reg$EN)
xmas_fsm_start_reg <= `BSV_ASSIGNMENT_DELAY xmas_fsm_start_reg$D_IN;
if (xmas_fsm_start_reg_1$EN)
xmas_fsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY
xmas_fsm_start_reg_1$D_IN;
if (xmas_fsm_state_fired$EN)
xmas_fsm_state_fired <= `BSV_ASSIGNMENT_DELAY
xmas_fsm_state_fired$D_IN;
if (xmas_fsm_state_mkFSMstate$EN)
xmas_fsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY
xmas_fsm_state_mkFSMstate$D_IN;
end
if (uart_vrRecvBuffer_0$EN)
uart_vrRecvBuffer_0 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_0$D_IN;
if (uart_vrRecvBuffer_1$EN)
uart_vrRecvBuffer_1 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_1$D_IN;
if (uart_vrRecvBuffer_2$EN)
uart_vrRecvBuffer_2 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_2$D_IN;
if (uart_vrRecvBuffer_3$EN)
uart_vrRecvBuffer_3 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_3$D_IN;
if (uart_vrRecvBuffer_4$EN)
uart_vrRecvBuffer_4 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_4$D_IN;
if (uart_vrRecvBuffer_5$EN)
uart_vrRecvBuffer_5 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_5$D_IN;
if (uart_vrRecvBuffer_6$EN)
uart_vrRecvBuffer_6 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_6$D_IN;
if (uart_vrRecvBuffer_7$EN)
uart_vrRecvBuffer_7 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_7$D_IN;
if (uart_vrXmitBuffer_0$EN)
uart_vrXmitBuffer_0 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_0$D_IN;
if (uart_vrXmitBuffer_1$EN)
uart_vrXmitBuffer_1 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_1$D_IN;
if (uart_vrXmitBuffer_2$EN)
uart_vrXmitBuffer_2 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_2$D_IN;
if (uart_vrXmitBuffer_3$EN)
uart_vrXmitBuffer_3 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_3$D_IN;
if (uart_vrXmitBuffer_4$EN)
uart_vrXmitBuffer_4 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_4$D_IN;
if (uart_vrXmitBuffer_5$EN)
uart_vrXmitBuffer_5 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_5$D_IN;
if (uart_vrXmitBuffer_6$EN)
uart_vrXmitBuffer_6 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_6$D_IN;
if (uart_vrXmitBuffer_7$EN)
uart_vrXmitBuffer_7 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_7$D_IN;
end
always@(posedge CLK or `BSV_RESET_EDGE RST_N)
if (RST_N == `BSV_RESET_VALUE)
begin
uart_rRecvBitCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
uart_rRecvCellCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
uart_rRecvState <= `BSV_ASSIGNMENT_DELAY 3'd0;
uart_rXmitBitCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
uart_rXmitCellCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
uart_rXmitDataOut <= `BSV_ASSIGNMENT_DELAY 1'd1;
uart_rXmitState <= `BSV_ASSIGNMENT_DELAY 3'd0;
end
else
begin
if (uart_rRecvBitCount$EN)
uart_rRecvBitCount <= `BSV_ASSIGNMENT_DELAY uart_rRecvBitCount$D_IN;
if (uart_rRecvCellCount$EN)
uart_rRecvCellCount <= `BSV_ASSIGNMENT_DELAY uart_rRecvCellCount$D_IN;
if (uart_rRecvState$EN)
uart_rRecvState <= `BSV_ASSIGNMENT_DELAY uart_rRecvState$D_IN;
if (uart_rXmitBitCount$EN)
uart_rXmitBitCount <= `BSV_ASSIGNMENT_DELAY uart_rXmitBitCount$D_IN;
if (uart_rXmitCellCount$EN)
uart_rXmitCellCount <= `BSV_ASSIGNMENT_DELAY uart_rXmitCellCount$D_IN;
if (uart_rXmitDataOut$EN)
uart_rXmitDataOut <= `BSV_ASSIGNMENT_DELAY uart_rXmitDataOut$D_IN;
if (uart_rXmitState$EN)
uart_rXmitState <= `BSV_ASSIGNMENT_DELAY uart_rXmitState$D_IN;
end
// handling of system tasks
endmodule // mkRule30Driver
//
// Generated by Bluespec Compiler, version 2024.01-1-g4d953407 (build 4d953407)
//
// On Thu Apr 18 23:03:51 EDT 2024
//
//
// Ports:
// Name I/O size props
// RDY_start O 1
// getResult O 8 reg
// RDY_getResult O 1
// CLK I 1 clock
// RST_N I 1 reset
// start_a I 8
// EN_start I 1
// EN_getResult I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkRule30(CLK,
RST_N,
start_a,
EN_start,
RDY_start,
EN_getResult,
getResult,
RDY_getResult);
input CLK;
input RST_N;
// action method start
input [7 : 0] start_a;
input EN_start;
output RDY_start;
// actionvalue method getResult
input EN_getResult;
output [7 : 0] getResult;
output RDY_getResult;
// signals for module outputs
wire [7 : 0] getResult;
wire RDY_getResult, RDY_start;
// register busy_flag
reg busy_flag;
wire busy_flag$D_IN, busy_flag$EN;
// register r30
reg [7 : 0] r30;
wire [7 : 0] r30$D_IN;
wire r30$EN;
// register step_complete
reg step_complete;
wire step_complete$D_IN, step_complete$EN;
// register x
reg [55 : 0] x;
wire [55 : 0] x$D_IN;
wire x$EN;
// rule scheduling signals
wire CAN_FIRE_RL_stepper,
CAN_FIRE_getResult,
CAN_FIRE_start,
WILL_FIRE_RL_stepper,
WILL_FIRE_getResult,
WILL_FIRE_start;
// inputs to muxes for submodule ports
wire [55 : 0] MUX_x$write_1__VAL_1, MUX_x$write_1__VAL_2;
// remaining internal signals
wire [51 : 0] r30_BIT_x_BITS_52_TO_50_6_7_CONCAT_r30_BIT_x_B_ETC___d146;
wire [47 : 0] r30_BIT_x_BITS_48_TO_46_4_5_CONCAT_r30_BIT_x_B_ETC___d144;
wire [43 : 0] r30_BIT_x_BITS_44_TO_42_2_3_CONCAT_r30_BIT_x_B_ETC___d142;
wire [39 : 0] r30_BIT_x_BITS_40_TO_38_0_1_CONCAT_r30_BIT_x_B_ETC___d140;
wire [35 : 0] r30_BIT_x_BITS_36_TO_34_8_9_CONCAT_r30_BIT_x_B_ETC___d138;
wire [31 : 0] r30_BIT_x_BITS_32_TO_30_6_7_CONCAT_r30_BIT_x_B_ETC___d136;
wire [27 : 0] r30_BIT_x_BITS_28_TO_26_4_5_CONCAT_r30_BIT_x_B_ETC___d134;
wire [23 : 0] r30_BIT_x_BITS_24_TO_22_2_3_CONCAT_r30_BIT_x_B_ETC___d132;
wire [19 : 0] r30_BIT_x_BITS_20_TO_18_0_1_CONCAT_r30_BIT_x_B_ETC___d130;
wire [15 : 0] r30_BIT_x_BITS_16_TO_14_8_9_CONCAT_r30_BIT_x_B_ETC___d128;
wire [11 : 0] r30_BIT_x_BITS_12_TO_10_6_7_CONCAT_r30_BIT_x_B_ETC___d126;
wire [7 : 0] r30_BIT_x_BITS_8_TO_6_04_05_CONCAT_r30_BIT_x_B_ETC___d124;
wire [3 : 0] r30_BIT_x_BITS_4_TO_2_12_13_CONCAT_r30_BIT_x_B_ETC___d122;
wire [2 : 0] b0__h167, b55__h222;
// action method start
assign RDY_start = !busy_flag ;
assign CAN_FIRE_start = !busy_flag ;
assign WILL_FIRE_start = EN_start ;
// actionvalue method getResult
assign getResult = x[31:24] ;
assign RDY_getResult = busy_flag && step_complete ;
assign CAN_FIRE_getResult = busy_flag && step_complete ;
assign WILL_FIRE_getResult = EN_getResult ;
// rule RL_stepper
assign CAN_FIRE_RL_stepper = busy_flag && !step_complete ;
assign WILL_FIRE_RL_stepper = CAN_FIRE_RL_stepper ;
// inputs to muxes for submodule ports
assign MUX_x$write_1__VAL_1 =
{ r30[b55__h222],
r30[x[55:53]],
r30[x[54:52]],
r30[x[53:51]],
r30_BIT_x_BITS_52_TO_50_6_7_CONCAT_r30_BIT_x_B_ETC___d146 } ;
assign MUX_x$write_1__VAL_2 = { x[55:32], start_a, x[23:0] } ;
// register busy_flag
assign busy_flag$D_IN = !EN_getResult ;
assign busy_flag$EN = EN_getResult || EN_start ;
// register r30
assign r30$D_IN = 8'h0 ;
assign r30$EN = 1'b0 ;
// register step_complete
assign step_complete$D_IN = !EN_start ;
assign step_complete$EN = EN_start || WILL_FIRE_RL_stepper ;
// register x
assign x$D_IN =
WILL_FIRE_RL_stepper ?
MUX_x$write_1__VAL_1 :
MUX_x$write_1__VAL_2 ;
assign x$EN = WILL_FIRE_RL_stepper || EN_start ;
// remaining internal signals
assign b0__h167 = { x[1:0], 1'b0 } ;
assign b55__h222 = { 1'b0, x[55:54] } ;
assign r30_BIT_x_BITS_12_TO_10_6_7_CONCAT_r30_BIT_x_B_ETC___d126 =
{ r30[x[12:10]],
r30[x[11:9]],
r30[x[10:8]],
r30[x[9:7]],
r30_BIT_x_BITS_8_TO_6_04_05_CONCAT_r30_BIT_x_B_ETC___d124 } ;
assign r30_BIT_x_BITS_16_TO_14_8_9_CONCAT_r30_BIT_x_B_ETC___d128 =
{ r30[x[16:14]],
r30[x[15:13]],
r30[x[14:12]],
r30[x[13:11]],
r30_BIT_x_BITS_12_TO_10_6_7_CONCAT_r30_BIT_x_B_ETC___d126 } ;
assign r30_BIT_x_BITS_20_TO_18_0_1_CONCAT_r30_BIT_x_B_ETC___d130 =
{ r30[x[20:18]],
r30[x[19:17]],
r30[x[18:16]],
r30[x[17:15]],
r30_BIT_x_BITS_16_TO_14_8_9_CONCAT_r30_BIT_x_B_ETC___d128 } ;
assign r30_BIT_x_BITS_24_TO_22_2_3_CONCAT_r30_BIT_x_B_ETC___d132 =
{ r30[x[24:22]],
r30[x[23:21]],
r30[x[22:20]],
r30[x[21:19]],
r30_BIT_x_BITS_20_TO_18_0_1_CONCAT_r30_BIT_x_B_ETC___d130 } ;
assign r30_BIT_x_BITS_28_TO_26_4_5_CONCAT_r30_BIT_x_B_ETC___d134 =
{ r30[x[28:26]],
r30[x[27:25]],
r30[x[26:24]],
r30[x[25:23]],
r30_BIT_x_BITS_24_TO_22_2_3_CONCAT_r30_BIT_x_B_ETC___d132 } ;
assign r30_BIT_x_BITS_32_TO_30_6_7_CONCAT_r30_BIT_x_B_ETC___d136 =
{ r30[x[32:30]],
r30[x[31:29]],
r30[x[30:28]],
r30[x[29:27]],
r30_BIT_x_BITS_28_TO_26_4_5_CONCAT_r30_BIT_x_B_ETC___d134 } ;
assign r30_BIT_x_BITS_36_TO_34_8_9_CONCAT_r30_BIT_x_B_ETC___d138 =
{ r30[x[36:34]],
r30[x[35:33]],
r30[x[34:32]],
r30[x[33:31]],
r30_BIT_x_BITS_32_TO_30_6_7_CONCAT_r30_BIT_x_B_ETC___d136 } ;
assign r30_BIT_x_BITS_40_TO_38_0_1_CONCAT_r30_BIT_x_B_ETC___d140 =
{ r30[x[40:38]],
r30[x[39:37]],
r30[x[38:36]],
r30[x[37:35]],
r30_BIT_x_BITS_36_TO_34_8_9_CONCAT_r30_BIT_x_B_ETC___d138 } ;
assign r30_BIT_x_BITS_44_TO_42_2_3_CONCAT_r30_BIT_x_B_ETC___d142 =
{ r30[x[44:42]],
r30[x[43:41]],
r30[x[42:40]],
r30[x[41:39]],
r30_BIT_x_BITS_40_TO_38_0_1_CONCAT_r30_BIT_x_B_ETC___d140 } ;
assign r30_BIT_x_BITS_48_TO_46_4_5_CONCAT_r30_BIT_x_B_ETC___d144 =
{ r30[x[48:46]],
r30[x[47:45]],
r30[x[46:44]],
r30[x[45:43]],
r30_BIT_x_BITS_44_TO_42_2_3_CONCAT_r30_BIT_x_B_ETC___d142 } ;
assign r30_BIT_x_BITS_4_TO_2_12_13_CONCAT_r30_BIT_x_B_ETC___d122 =
{ r30[x[4:2]], r30[x[3:1]], r30[x[2:0]], r30[b0__h167] } ;
assign r30_BIT_x_BITS_52_TO_50_6_7_CONCAT_r30_BIT_x_B_ETC___d146 =
{ r30[x[52:50]],
r30[x[51:49]],
r30[x[50:48]],
r30[x[49:47]],
r30_BIT_x_BITS_48_TO_46_4_5_CONCAT_r30_BIT_x_B_ETC___d144 } ;
assign r30_BIT_x_BITS_8_TO_6_04_05_CONCAT_r30_BIT_x_B_ETC___d124 =
{ r30[x[8:6]],
r30[x[7:5]],
r30[x[6:4]],
r30[x[5:3]],
r30_BIT_x_BITS_4_TO_2_12_13_CONCAT_r30_BIT_x_B_ETC___d122 } ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
busy_flag <= `BSV_ASSIGNMENT_DELAY 1'd0;
r30 <= `BSV_ASSIGNMENT_DELAY 8'd30;
step_complete <= `BSV_ASSIGNMENT_DELAY 1'd0;
x <= `BSV_ASSIGNMENT_DELAY 56'd0;
end
else
begin
if (busy_flag$EN) busy_flag <= `BSV_ASSIGNMENT_DELAY busy_flag$D_IN;
if (r30$EN) r30 <= `BSV_ASSIGNMENT_DELAY r30$D_IN;
if (step_complete$EN)
step_complete <= `BSV_ASSIGNMENT_DELAY step_complete$D_IN;
if (x$EN) x <= `BSV_ASSIGNMENT_DELAY x$D_IN;
end
end
endmodule // mkRule30
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
// N -bit counter with load, set and 2 increment
module Counter(CLK,
RST,
Q_OUT,
DATA_A, ADDA,
DATA_B, ADDB,
DATA_C, SETC,
DATA_F, SETF);
parameter width = 1;
parameter init = 0;
input CLK;
input RST;
input [width - 1 : 0] DATA_A;
input ADDA;
input [width - 1 : 0] DATA_B;
input ADDB;
input [width - 1 : 0] DATA_C;
input SETC;
input [width - 1 : 0] DATA_F;
input SETF;
output [width - 1 : 0] Q_OUT;
reg [width - 1 : 0] q_state ;
assign Q_OUT = q_state ;
always@(posedge CLK `BSV_ARESET_EDGE_META) begin
if (RST == `BSV_RESET_VALUE)
q_state <= `BSV_ASSIGNMENT_DELAY init;
else
begin
if ( SETF )
q_state <= `BSV_ASSIGNMENT_DELAY DATA_F ;
else
q_state <= `BSV_ASSIGNMENT_DELAY (SETC ? DATA_C : q_state ) + (ADDA ? DATA_A : {width {1'b0}}) + (ADDB ? DATA_B : {width {1'b0}} ) ;
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK)
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial begin
q_state = {((width + 1)/2){2'b10}} ;
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
`ifdef BSV_RESET_FIFO_HEAD
`define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_HEAD
`endif
`ifdef BSV_RESET_FIFO_ARRAY
`define BSV_ARESET_EDGE_ARRAY `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_ARRAY
`endif
// Sized fifo. Model has output register which improves timing
module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
`ifdef BSV_RESET_FIFO_HEAD
`define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_HEAD
`endif
// Depth 1 FIFO
module FIFO1(CLK,
RST,
D_IN,
ENQ,
FULL_N,
D_OUT,
DEQ,
EMPTY_N,
CLR
);
parameter width = 1;
parameter guarded = 1'b1;
input CLK;
input RST;
input [width - 1 : 0] D_IN;
input ENQ;
input DEQ;
input CLR ;
output FULL_N;
output [width - 1 : 0] D_OUT;
output EMPTY_N;
reg [width - 1 : 0] D_OUT;
reg empty_reg ;
assign EMPTY_N = empty_reg ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
D_OUT = {((width + 1)/2) {2'b10}} ;
empty_reg = 1'b0 ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
assign FULL_N = !empty_reg;
always@(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (RST == `BSV_RESET_VALUE)
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (CLR)
else if (ENQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // if (ENQ)
else if (DEQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (DEQ)
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
always@(posedge CLK `BSV_ARESET_EDGE_HEAD)
begin
`ifdef BSV_RESET_FIFO_HEAD
if (RST == `BSV_RESET_VALUE)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
end
else
`endif
begin
if (ENQ)
D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN;
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if (RST == ! `BSV_RESET_VALUE)
begin
if ( ! empty_reg && DEQ )
begin
deqerror = 1 ;
$display( "Warning: FIFO1: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && (!DEQ || guarded) )
begin
enqerror = 1 ;
$display( "Warning: FIFO1: %m -- Enqueuing to a full fifo" ) ;
end
end // if (RST == ! `BSV_RESET_VALUE)
end
// synopsys translate_on
endmodule
|
module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR);
parameter p1width = 1; // data width
parameter p2depth = 3;
parameter p3cntr_width = 1; // log(p2depth-1)
// The -1 is allowed since this model has a fast output register
parameter guarded = 1'b1;
localparam p2depth2 = (p2depth >= 2) ? (p2depth -2) : 0 ;
input CLK;
input RST;
input CLR;
input [p1width - 1 : 0] D_IN;
input ENQ;
input DEQ;
output FULL_N;
output EMPTY_N;
output [p1width - 1 : 0] D_OUT;
reg not_ring_full;
reg ring_empty;
reg [p3cntr_width-1 : 0] head;
wire [p3cntr_width-1 : 0] next_head;
reg [p3cntr_width-1 : 0] tail;
wire [p3cntr_width-1 : 0] next_tail;
// if the depth is too small, don't create an ill-sized array;
// instead, make a 1-sized array and let the initial block report an error
reg [p1width - 1 : 0] arr[0: p2depth2];
reg [p1width - 1 : 0] D_OUT;
reg hasodata;
wire [p3cntr_width-1:0] depthLess2 = p2depth2[p3cntr_width-1:0] ;
wire [p3cntr_width-1 : 0] incr_tail;
wire [p3cntr_width-1 : 0] incr_head;
assign incr_tail = tail + 1'b1 ;
assign incr_head = head + 1'b1 ;
assign next_head = (head == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_head ;
assign next_tail = (tail == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_tail ;
assign EMPTY_N = hasodata;
assign FULL_N = not_ring_full;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin : initial_block
integer i;
D_OUT = {((p1width + 1)/2){2'b10}} ;
ring_empty = 1'b1;
not_ring_full = 1'b1;
hasodata = 1'b0;
head = {p3cntr_width {1'b0}} ;
tail = {p3cntr_width {1'b0}} ;
for (i = 0; i <= p2depth2; i = i + 1)
begin
arr[i] = D_OUT ;
end
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
always @(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (RST == `BSV_RESET_VALUE)
else
begin
casez ({CLR, DEQ, ENQ, hasodata, ring_empty})
// Clear operation
5'b1????: begin
head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
// -----------------------
// DEQ && ENQ case -- change head and tail if added to ring
5'b011?0: begin
tail <= `BSV_ASSIGNMENT_DELAY next_tail;
head <= `BSV_ASSIGNMENT_DELAY next_head;
end
// -----------------------
// DEQ only and NO data is in ring
5'b010?1: begin
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
// DEQ only and data is in ring (move the head pointer)
5'b010?0: begin
head <= `BSV_ASSIGNMENT_DELAY next_head;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
ring_empty <= `BSV_ASSIGNMENT_DELAY next_head == tail ;
end
// -----------------------
// ENQ only when empty
5'b0010?: begin
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b1;
end
// ENQ only when not empty
5'b0011?: begin
if ( not_ring_full ) // Drop this test to save redundant test
// but be warnned that with test fifo overflow causes loss of new data
// while without test fifo drops all but head entry! (pointer overflow)
begin
tail <= `BSV_ASSIGNMENT_DELAY next_tail;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b0;
not_ring_full <= `BSV_ASSIGNMENT_DELAY ! (next_tail == head) ;
end
end
endcase
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// Update the fast data out register
always @(posedge CLK `BSV_ARESET_EDGE_HEAD)
begin
`ifdef BSV_RESET_FIFO_HEAD
if (RST == `BSV_RESET_VALUE)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
end // if (RST == `BSV_RESET_VALUE)
else
`endif
begin
casez ({CLR, DEQ, ENQ, hasodata, ring_empty})
// DEQ && ENQ cases
5'b011?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end
5'b011?1: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end
// DEQ only and data is in ring
5'b010?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end
// ENQ only when empty
5'b0010?: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end
endcase
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// Update the memory array reset is OFF
always @(posedge CLK `BSV_ARESET_EDGE_ARRAY)
begin: array
`ifdef BSV_RESET_FIFO_ARRAY
if (RST == `BSV_RESET_VALUE)
begin: rst_array
integer i;
for (i = 0; i <= p2depth2 && p2depth > 2; i = i + 1)
begin
arr[i] <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
end
end // if (RST == `BSV_RESET_VALUE)
else
`endif
begin
if (!CLR && ENQ && ((DEQ && !ring_empty) || (!DEQ && hasodata && not_ring_full)))
begin
arr[tail] <= `BSV_ASSIGNMENT_DELAY D_IN;
end
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if (RST == ! `BSV_RESET_VALUE)
begin
if ( ! EMPTY_N && DEQ )
begin
deqerror = 1 ;
$display( "Warning: SizedFIFO: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && (!DEQ || guarded) )
begin
enqerror = 1 ;
$display( "Warning: SizedFIFO: %m -- Enqueuing to a full fifo" ) ;
end
end
end // block: error_checks
// synopsys translate_on
// synopsys translate_off
// Some assertions about parameter values
initial
begin : parameter_assertions
integer ok ;
ok = 1 ;
if ( p2depth <= 1)
begin
ok = 0;
$display ( "Warning SizedFIFO: %m -- depth parameter increased from %0d to 2", p2depth);
end
if ( p3cntr_width <= 0 )
begin
ok = 0;
$display ( "ERROR SizedFIFO: %m -- width parameter must be greater than 0" ) ;
end
if ( ok == 0 ) $finish ;
end // initial begin
// synopsys translate_on
endmodule
|
tt06-finale_0053
|
tt06-finale
|
andrewtron3000-tt06-verilog-template
|
task_mkRule30
|
tt_um_andrewtron3000
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 andrewtron3000
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_andrewtron3000 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// Held in reset while ena is not set
wire reset_n;
assign reset_n = rst_n & ena;
assign uio_oe = 8'b00000000; // All bidirectional outputs disabled
assign uio_out = 0;
// Assign output
assign uo_out[0] = 0;
assign uo_out[1] = 0;
assign uo_out[2] = 0;
assign uo_out[3] = 0;
assign uo_out[4] = driver_sout; // uo_out[4] is UART TX
assign uo_out[5] = 0;
assign uo_out[6] = 0;
assign uo_out[7] = 0;
// ports of submodule driver
wire driver_sin, driver_sout;
assign driver_sin = 0;
wire startup_input_ready;
wire startup_input_enable;
wire operation_mode_ready;
wire operation_mode_enable;
// submodule rule_30_driver
mkRule30Driver rule_30_driver(.CLK(clk),
.RST_N(reset_n),
.operation_mode_arg(uio_in),
.EN_operation_mode(operation_mode_enable),
.RDY_operation_mode(operation_mode_ready),
.startup_value_v(ui_in),
.EN_startup_value(startup_input_enable),
.RDY_startup_value(startup_input_ready),
.txrx_SIN(driver_sin),
.txrx_SOUT(driver_sout));
assign startup_input_enable = startup_input_ready;
assign operation_mode_enable = operation_mode_ready;
endmodule
//
// Generated by Bluespec Compiler, version 2024.01-1-g4d953407 (build 4d953407)
//
// On Thu Apr 18 23:03:53 EDT 2024
//
//
// Ports:
// Name I/O size props
// RDY_operation_mode O 1
// RDY_startup_value O 1
// txrx_SOUT O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// operation_mode_arg I 8
// startup_value_v I 8
// txrx_SIN I 1 reg
// EN_operation_mode I 1
// EN_startup_value I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkRule30Driver(CLK,
RST_N,
operation_mode_arg,
EN_operation_mode,
RDY_operation_mode,
startup_value_v,
EN_startup_value,
RDY_startup_value,
txrx_SIN,
txrx_SOUT);
input CLK;
input RST_N;
// action method operation_mode
input [7 : 0] operation_mode_arg;
input EN_operation_mode;
output RDY_operation_mode;
// action method startup_value
input [7 : 0] startup_value_v;
input EN_startup_value;
output RDY_startup_value;
// action method txrx_sin
input txrx_SIN;
// value method txrx_sout
output txrx_SOUT;
// signals for module outputs
wire RDY_operation_mode, RDY_startup_value, txrx_SOUT;
// inlined wires
wire uart_fifoXmit_r_enq$whas,
uart_pwRecvCellCountReset$whas,
uart_pwRecvEnableBitCount$whas,
uart_pwRecvResetBitCount$whas,
uart_pwXmitCellCountReset$whas,
uart_pwXmitEnableBitCount$whas,
uart_pwXmitLoadBuffer$whas,
xmas_fsm_start_wire$whas,
xmas_fsm_state_set_pw$whas;
// register a
reg [7 : 0] a;
wire [7 : 0] a$D_IN;
wire a$EN;
// register op_mode
reg op_mode;
wire op_mode$D_IN, op_mode$EN;
// register transmit_state
reg [1 : 0] transmit_state;
wire [1 : 0] transmit_state$D_IN;
wire transmit_state$EN;
// register uart_rRecvBitCount
reg [3 : 0] uart_rRecvBitCount;
wire [3 : 0] uart_rRecvBitCount$D_IN;
wire uart_rRecvBitCount$EN;
// register uart_rRecvCellCount
reg [3 : 0] uart_rRecvCellCount;
wire [3 : 0] uart_rRecvCellCount$D_IN;
wire uart_rRecvCellCount$EN;
// register uart_rRecvData
reg uart_rRecvData;
wire uart_rRecvData$D_IN, uart_rRecvData$EN;
// register uart_rRecvState
reg [2 : 0] uart_rRecvState;
reg [2 : 0] uart_rRecvState$D_IN;
wire uart_rRecvState$EN;
// register uart_rXmitBitCount
reg [3 : 0] uart_rXmitBitCount;
wire [3 : 0] uart_rXmitBitCount$D_IN;
wire uart_rXmitBitCount$EN;
// register uart_rXmitCellCount
reg [3 : 0] uart_rXmitCellCount;
wire [3 : 0] uart_rXmitCellCount$D_IN;
wire uart_rXmitCellCount$EN;
// register uart_rXmitDataOut
reg uart_rXmitDataOut;
reg uart_rXmitDataOut$D_IN;
wire uart_rXmitDataOut$EN;
// register uart_rXmitState
reg [2 : 0] uart_rXmitState;
reg [2 : 0] uart_rXmitState$D_IN;
wire uart_rXmitState$EN;
// register uart_vrRecvBuffer_0
reg uart_vrRecvBuffer_0;
wire uart_vrRecvBuffer_0$D_IN, uart_vrRecvBuffer_0$EN;
// register uart_vrRecvBuffer_1
reg uart_vrRecvBuffer_1;
wire uart_vrRecvBuffer_1$D_IN, uart_vrRecvBuffer_1$EN;
// register uart_vrRecvBuffer_2
reg uart_vrRecvBuffer_2;
wire uart_vrRecvBuffer_2$D_IN, uart_vrRecvBuffer_2$EN;
// register uart_vrRecvBuffer_3
reg uart_vrRecvBuffer_3;
wire uart_vrRecvBuffer_3$D_IN, uart_vrRecvBuffer_3$EN;
// register uart_vrRecvBuffer_4
reg uart_vrRecvBuffer_4;
wire uart_vrRecvBuffer_4$D_IN, uart_vrRecvBuffer_4$EN;
// register uart_vrRecvBuffer_5
reg uart_vrRecvBuffer_5;
wire uart_vrRecvBuffer_5$D_IN, uart_vrRecvBuffer_5$EN;
// register uart_vrRecvBuffer_6
reg uart_vrRecvBuffer_6;
wire uart_vrRecvBuffer_6$D_IN, uart_vrRecvBuffer_6$EN;
// register uart_vrRecvBuffer_7
reg uart_vrRecvBuffer_7;
wire uart_vrRecvBuffer_7$D_IN, uart_vrRecvBuffer_7$EN;
// register uart_vrXmitBuffer_0
reg uart_vrXmitBuffer_0;
wire uart_vrXmitBuffer_0$D_IN, uart_vrXmitBuffer_0$EN;
// register uart_vrXmitBuffer_1
reg uart_vrXmitBuffer_1;
wire uart_vrXmitBuffer_1$D_IN, uart_vrXmitBuffer_1$EN;
// register uart_vrXmitBuffer_2
reg uart_vrXmitBuffer_2;
wire uart_vrXmitBuffer_2$D_IN, uart_vrXmitBuffer_2$EN;
// register uart_vrXmitBuffer_3
reg uart_vrXmitBuffer_3;
wire uart_vrXmitBuffer_3$D_IN, uart_vrXmitBuffer_3$EN;
// register uart_vrXmitBuffer_4
reg uart_vrXmitBuffer_4;
wire uart_vrXmitBuffer_4$D_IN, uart_vrXmitBuffer_4$EN;
// register uart_vrXmitBuffer_5
reg uart_vrXmitBuffer_5;
wire uart_vrXmitBuffer_5$D_IN, uart_vrXmitBuffer_5$EN;
// register uart_vrXmitBuffer_6
reg uart_vrXmitBuffer_6;
wire uart_vrXmitBuffer_6$D_IN, uart_vrXmitBuffer_6$EN;
// register uart_vrXmitBuffer_7
reg uart_vrXmitBuffer_7;
wire uart_vrXmitBuffer_7$D_IN, uart_vrXmitBuffer_7$EN;
// register xmas_fsm_start_reg
reg xmas_fsm_start_reg;
wire xmas_fsm_start_reg$D_IN, xmas_fsm_start_reg$EN;
// register xmas_fsm_start_reg_1
reg xmas_fsm_start_reg_1;
wire xmas_fsm_start_reg_1$D_IN, xmas_fsm_start_reg_1$EN;
// register xmas_fsm_state_fired
reg xmas_fsm_state_fired;
wire xmas_fsm_state_fired$D_IN, xmas_fsm_state_fired$EN;
// register xmas_fsm_state_mkFSMstate
reg [4 : 0] xmas_fsm_state_mkFSMstate;
reg [4 : 0] xmas_fsm_state_mkFSMstate$D_IN;
wire xmas_fsm_state_mkFSMstate$EN;
// ports of submodule rule30
wire [7 : 0] rule30$getResult, rule30$start_a;
wire rule30$EN_getResult,
rule30$EN_start,
rule30$RDY_getResult,
rule30$RDY_start;
// ports of submodule uart_baudGen_rBaudCounter
wire [15 : 0] uart_baudGen_rBaudCounter$DATA_A,
uart_baudGen_rBaudCounter$DATA_B,
uart_baudGen_rBaudCounter$DATA_C,
uart_baudGen_rBaudCounter$DATA_F,
uart_baudGen_rBaudCounter$Q_OUT;
wire uart_baudGen_rBaudCounter$ADDA,
uart_baudGen_rBaudCounter$ADDB,
uart_baudGen_rBaudCounter$SETC,
uart_baudGen_rBaudCounter$SETF;
// ports of submodule uart_baudGen_rBaudTickCounter
wire [2 : 0] uart_baudGen_rBaudTickCounter$DATA_A,
uart_baudGen_rBaudTickCounter$DATA_B,
uart_baudGen_rBaudTickCounter$DATA_C,
uart_baudGen_rBaudTickCounter$DATA_F,
uart_baudGen_rBaudTickCounter$Q_OUT;
wire uart_baudGen_rBaudTickCounter$ADDA,
uart_baudGen_rBaudTickCounter$ADDB,
uart_baudGen_rBaudTickCounter$SETC,
uart_baudGen_rBaudTickCounter$SETF;
// ports of submodule uart_fifoRecv
wire [7 : 0] uart_fifoRecv$D_IN;
wire uart_fifoRecv$CLR,
uart_fifoRecv$DEQ,
uart_fifoRecv$EMPTY_N,
uart_fifoRecv$ENQ;
// ports of submodule uart_fifoXmit
reg [7 : 0] uart_fifoXmit$D_IN;
wire [7 : 0] uart_fifoXmit$D_OUT;
wire uart_fifoXmit$CLR,
uart_fifoXmit$DEQ,
uart_fifoXmit$EMPTY_N,
uart_fifoXmit$ENQ,
uart_fifoXmit$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_compute,
CAN_FIRE_RL_dump_rx,
CAN_FIRE_RL_get_result,
CAN_FIRE_RL_uart_baudGen_assert_2x_baud_tick,
CAN_FIRE_RL_uart_baudGen_baud_count_wire,
CAN_FIRE_RL_uart_baudGen_baud_tick_count_wire,
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x,
CAN_FIRE_RL_uart_baud_generator_clock_enable,
CAN_FIRE_RL_uart_fifoRecv__updateLevelCounter,
CAN_FIRE_RL_uart_fifoXmit__updateLevelCounter,
CAN_FIRE_RL_uart_receive_bit_cell_time_counter,
CAN_FIRE_RL_uart_receive_bit_counter,
CAN_FIRE_RL_uart_receive_buffer_shift,
CAN_FIRE_RL_uart_receive_find_center_of_bit_cell,
CAN_FIRE_RL_uart_receive_parity_bit,
CAN_FIRE_RL_uart_receive_sample_pin,
CAN_FIRE_RL_uart_receive_stop_first_bit,
CAN_FIRE_RL_uart_receive_stop_last_bit,
CAN_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample,
CAN_FIRE_RL_uart_receive_wait_for_start_bit,
CAN_FIRE_RL_uart_transmit_bit_cell_time_counter,
CAN_FIRE_RL_uart_transmit_bit_counter,
CAN_FIRE_RL_uart_transmit_buffer_load,
CAN_FIRE_RL_uart_transmit_buffer_shift,
CAN_FIRE_RL_uart_transmit_send_parity_bit,
CAN_FIRE_RL_uart_transmit_send_start_bit,
CAN_FIRE_RL_uart_transmit_send_stop_bit,
CAN_FIRE_RL_uart_transmit_send_stop_bit1_5,
CAN_FIRE_RL_uart_transmit_send_stop_bit2,
CAN_FIRE_RL_uart_transmit_shift_next_bit,
CAN_FIRE_RL_uart_transmit_wait_1_bit_cell_time,
CAN_FIRE_RL_uart_transmit_wait_for_start_command,
CAN_FIRE_RL_xmas_fsm_action_l42c32,
CAN_FIRE_RL_xmas_fsm_action_l43c32,
CAN_FIRE_RL_xmas_fsm_action_l44c32,
CAN_FIRE_RL_xmas_fsm_action_l45c32,
CAN_FIRE_RL_xmas_fsm_action_l46c32,
CAN_FIRE_RL_xmas_fsm_action_l47c32,
CAN_FIRE_RL_xmas_fsm_action_l48c32,
CAN_FIRE_RL_xmas_fsm_action_l49c32,
CAN_FIRE_RL_xmas_fsm_action_l50c32,
CAN_FIRE_RL_xmas_fsm_action_l51c32,
CAN_FIRE_RL_xmas_fsm_action_l52c32,
CAN_FIRE_RL_xmas_fsm_action_l53c32,
CAN_FIRE_RL_xmas_fsm_action_l54c32,
CAN_FIRE_RL_xmas_fsm_action_l55c32,
CAN_FIRE_RL_xmas_fsm_action_l56c32,
CAN_FIRE_RL_xmas_fsm_action_l57c32,
CAN_FIRE_RL_xmas_fsm_action_l58c32,
CAN_FIRE_RL_xmas_fsm_action_l59c32,
CAN_FIRE_RL_xmas_fsm_action_l60c32,
CAN_FIRE_RL_xmas_fsm_action_l61c32,
CAN_FIRE_RL_xmas_fsm_action_l62c32,
CAN_FIRE_RL_xmas_fsm_action_l63c32,
CAN_FIRE_RL_xmas_fsm_action_l64c32,
CAN_FIRE_RL_xmas_fsm_action_l65c32,
CAN_FIRE_RL_xmas_fsm_action_l66c32,
CAN_FIRE_RL_xmas_fsm_fsm_start,
CAN_FIRE_RL_xmas_fsm_idle_l40c27,
CAN_FIRE_RL_xmas_fsm_idle_l40c27_1,
CAN_FIRE_RL_xmas_fsm_restart,
CAN_FIRE_RL_xmas_fsm_start_reg__dreg_update,
CAN_FIRE_RL_xmas_fsm_state_every,
CAN_FIRE_RL_xmas_fsm_state_fired__dreg_update,
CAN_FIRE_RL_xmas_fsm_state_handle_abort,
CAN_FIRE___me_check_34,
CAN_FIRE___me_check_35,
CAN_FIRE___me_check_36,
CAN_FIRE___me_check_37,
CAN_FIRE___me_check_38,
CAN_FIRE___me_check_39,
CAN_FIRE___me_check_40,
CAN_FIRE___me_check_41,
CAN_FIRE___me_check_42,
CAN_FIRE___me_check_43,
CAN_FIRE___me_check_44,
CAN_FIRE___me_check_45,
CAN_FIRE___me_check_46,
CAN_FIRE___me_check_47,
CAN_FIRE___me_check_48,
CAN_FIRE___me_check_49,
CAN_FIRE___me_check_50,
CAN_FIRE___me_check_51,
CAN_FIRE___me_check_52,
CAN_FIRE___me_check_53,
CAN_FIRE___me_check_54,
CAN_FIRE___me_check_55,
CAN_FIRE___me_check_56,
CAN_FIRE___me_check_57,
CAN_FIRE_operation_mode,
CAN_FIRE_startup_value,
CAN_FIRE_txrx_sin,
WILL_FIRE_RL_compute,
WILL_FIRE_RL_dump_rx,
WILL_FIRE_RL_get_result,
WILL_FIRE_RL_uart_baudGen_assert_2x_baud_tick,
WILL_FIRE_RL_uart_baudGen_baud_count_wire,
WILL_FIRE_RL_uart_baudGen_baud_tick_count_wire,
WILL_FIRE_RL_uart_baudGen_count_baudtick_16x,
WILL_FIRE_RL_uart_baud_generator_clock_enable,
WILL_FIRE_RL_uart_fifoRecv__updateLevelCounter,
WILL_FIRE_RL_uart_fifoXmit__updateLevelCounter,
WILL_FIRE_RL_uart_receive_bit_cell_time_counter,
WILL_FIRE_RL_uart_receive_bit_counter,
WILL_FIRE_RL_uart_receive_buffer_shift,
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell,
WILL_FIRE_RL_uart_receive_parity_bit,
WILL_FIRE_RL_uart_receive_sample_pin,
WILL_FIRE_RL_uart_receive_stop_first_bit,
WILL_FIRE_RL_uart_receive_stop_last_bit,
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample,
WILL_FIRE_RL_uart_receive_wait_for_start_bit,
WILL_FIRE_RL_uart_transmit_bit_cell_time_counter,
WILL_FIRE_RL_uart_transmit_bit_counter,
WILL_FIRE_RL_uart_transmit_buffer_load,
WILL_FIRE_RL_uart_transmit_buffer_shift,
WILL_FIRE_RL_uart_transmit_send_parity_bit,
WILL_FIRE_RL_uart_transmit_send_start_bit,
WILL_FIRE_RL_uart_transmit_send_stop_bit,
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5,
WILL_FIRE_RL_uart_transmit_send_stop_bit2,
WILL_FIRE_RL_uart_transmit_shift_next_bit,
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time,
WILL_FIRE_RL_uart_transmit_wait_for_start_command,
WILL_FIRE_RL_xmas_fsm_action_l42c32,
WILL_FIRE_RL_xmas_fsm_action_l43c32,
WILL_FIRE_RL_xmas_fsm_action_l44c32,
WILL_FIRE_RL_xmas_fsm_action_l45c32,
WILL_FIRE_RL_xmas_fsm_action_l46c32,
WILL_FIRE_RL_xmas_fsm_action_l47c32,
WILL_FIRE_RL_xmas_fsm_action_l48c32,
WILL_FIRE_RL_xmas_fsm_action_l49c32,
WILL_FIRE_RL_xmas_fsm_action_l50c32,
WILL_FIRE_RL_xmas_fsm_action_l51c32,
WILL_FIRE_RL_xmas_fsm_action_l52c32,
WILL_FIRE_RL_xmas_fsm_action_l53c32,
WILL_FIRE_RL_xmas_fsm_action_l54c32,
WILL_FIRE_RL_xmas_fsm_action_l55c32,
WILL_FIRE_RL_xmas_fsm_action_l56c32,
WILL_FIRE_RL_xmas_fsm_action_l57c32,
WILL_FIRE_RL_xmas_fsm_action_l58c32,
WILL_FIRE_RL_xmas_fsm_action_l59c32,
WILL_FIRE_RL_xmas_fsm_action_l60c32,
WILL_FIRE_RL_xmas_fsm_action_l61c32,
WILL_FIRE_RL_xmas_fsm_action_l62c32,
WILL_FIRE_RL_xmas_fsm_action_l63c32,
WILL_FIRE_RL_xmas_fsm_action_l64c32,
WILL_FIRE_RL_xmas_fsm_action_l65c32,
WILL_FIRE_RL_xmas_fsm_action_l66c32,
WILL_FIRE_RL_xmas_fsm_fsm_start,
WILL_FIRE_RL_xmas_fsm_idle_l40c27,
WILL_FIRE_RL_xmas_fsm_idle_l40c27_1,
WILL_FIRE_RL_xmas_fsm_restart,
WILL_FIRE_RL_xmas_fsm_start_reg__dreg_update,
WILL_FIRE_RL_xmas_fsm_state_every,
WILL_FIRE_RL_xmas_fsm_state_fired__dreg_update,
WILL_FIRE_RL_xmas_fsm_state_handle_abort,
WILL_FIRE___me_check_34,
WILL_FIRE___me_check_35,
WILL_FIRE___me_check_36,
WILL_FIRE___me_check_37,
WILL_FIRE___me_check_38,
WILL_FIRE___me_check_39,
WILL_FIRE___me_check_40,
WILL_FIRE___me_check_41,
WILL_FIRE___me_check_42,
WILL_FIRE___me_check_43,
WILL_FIRE___me_check_44,
WILL_FIRE___me_check_45,
WILL_FIRE___me_check_46,
WILL_FIRE___me_check_47,
WILL_FIRE___me_check_48,
WILL_FIRE___me_check_49,
WILL_FIRE___me_check_50,
WILL_FIRE___me_check_51,
WILL_FIRE___me_check_52,
WILL_FIRE___me_check_53,
WILL_FIRE___me_check_54,
WILL_FIRE___me_check_55,
WILL_FIRE___me_check_56,
WILL_FIRE___me_check_57,
WILL_FIRE_operation_mode,
WILL_FIRE_startup_value,
WILL_FIRE_txrx_sin;
// inputs to muxes for submodule ports
reg [2 : 0] MUX_uart_rRecvState$write_1__VAL_3;
wire [2 : 0] MUX_uart_rRecvState$write_1__VAL_1,
MUX_uart_rRecvState$write_1__VAL_2,
MUX_uart_rRecvState$write_1__VAL_4,
MUX_uart_rXmitState$write_1__VAL_1,
MUX_uart_rXmitState$write_1__VAL_2,
MUX_uart_rXmitState$write_1__VAL_3,
MUX_uart_rXmitState$write_1__VAL_4,
MUX_uart_rXmitState$write_1__VAL_5,
MUX_uart_rXmitState$write_1__VAL_6,
MUX_uart_rXmitState$write_1__VAL_7;
wire MUX_transmit_state$write_1__SEL_1,
MUX_uart_fifoXmit$enq_1__SEL_11,
MUX_uart_fifoXmit$enq_1__SEL_15,
MUX_uart_fifoXmit$enq_1__SEL_16,
MUX_uart_fifoXmit$enq_1__SEL_17,
MUX_uart_fifoXmit$enq_1__SEL_2,
MUX_uart_fifoXmit$enq_1__SEL_3,
MUX_uart_rRecvState$write_1__SEL_6,
MUX_uart_rXmitDataOut$write_1__SEL_1,
MUX_uart_rXmitDataOut$write_1__SEL_2,
MUX_uart_rXmitDataOut$write_1__SEL_3,
MUX_xmas_fsm_start_reg$write_1__SEL_1,
MUX_xmas_fsm_state_mkFSMstate$write_1__SEL_1;
// remaining internal signals
wire [3 : 0] x__h2985, x__h4689, x__h6445, x__h6471;
wire _dor2uart_pwXmitCellCountReset$EN_wset,
uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29,
xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302;
// action method operation_mode
assign RDY_operation_mode =
transmit_state == 2'd0 && !op_mode &&
xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302 &&
!xmas_fsm_start_reg ;
assign CAN_FIRE_operation_mode =
transmit_state == 2'd0 && !op_mode &&
xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302 &&
!xmas_fsm_start_reg ;
assign WILL_FIRE_operation_mode = EN_operation_mode ;
// action method startup_value
assign RDY_startup_value = transmit_state == 2'd0 && !op_mode ;
assign CAN_FIRE_startup_value = transmit_state == 2'd0 && !op_mode ;
assign WILL_FIRE_startup_value = EN_startup_value ;
// action method txrx_sin
assign CAN_FIRE_txrx_sin = 1'd1 ;
assign WILL_FIRE_txrx_sin = 1'd1 ;
// value method txrx_sout
assign txrx_SOUT = uart_rXmitDataOut ;
// submodule rule30
mkRule30 rule30(.CLK(CLK),
.RST_N(RST_N),
.start_a(rule30$start_a),
.EN_start(rule30$EN_start),
.EN_getResult(rule30$EN_getResult),
.RDY_start(rule30$RDY_start),
.getResult(rule30$getResult),
.RDY_getResult(rule30$RDY_getResult));
// submodule uart_baudGen_rBaudCounter
Counter #(.width(32'd16), .init(16'd0)) uart_baudGen_rBaudCounter(.CLK(CLK),
.RST(RST_N),
.DATA_A(uart_baudGen_rBaudCounter$DATA_A),
.DATA_B(uart_baudGen_rBaudCounter$DATA_B),
.DATA_C(uart_baudGen_rBaudCounter$DATA_C),
.DATA_F(uart_baudGen_rBaudCounter$DATA_F),
.ADDA(uart_baudGen_rBaudCounter$ADDA),
.ADDB(uart_baudGen_rBaudCounter$ADDB),
.SETC(uart_baudGen_rBaudCounter$SETC),
.SETF(uart_baudGen_rBaudCounter$SETF),
.Q_OUT(uart_baudGen_rBaudCounter$Q_OUT));
// submodule uart_baudGen_rBaudTickCounter
Counter #(.width(32'd3),
.init(3'd0)) uart_baudGen_rBaudTickCounter(.CLK(CLK),
.RST(RST_N),
.DATA_A(uart_baudGen_rBaudTickCounter$DATA_A),
.DATA_B(uart_baudGen_rBaudTickCounter$DATA_B),
.DATA_C(uart_baudGen_rBaudTickCounter$DATA_C),
.DATA_F(uart_baudGen_rBaudTickCounter$DATA_F),
.ADDA(uart_baudGen_rBaudTickCounter$ADDA),
.ADDB(uart_baudGen_rBaudTickCounter$ADDB),
.SETC(uart_baudGen_rBaudTickCounter$SETC),
.SETF(uart_baudGen_rBaudTickCounter$SETF),
.Q_OUT(uart_baudGen_rBaudTickCounter$Q_OUT));
// submodule uart_fifoRecv
SizedFIFO #(.p1width(32'd8),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(1'd1)) uart_fifoRecv(.RST(RST_N),
.CLK(CLK),
.D_IN(uart_fifoRecv$D_IN),
.ENQ(uart_fifoRecv$ENQ),
.DEQ(uart_fifoRecv$DEQ),
.CLR(uart_fifoRecv$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N(uart_fifoRecv$EMPTY_N));
// submodule uart_fifoXmit
SizedFIFO #(.p1width(32'd8),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(1'd1)) uart_fifoXmit(.RST(RST_N),
.CLK(CLK),
.D_IN(uart_fifoXmit$D_IN),
.ENQ(uart_fifoXmit$ENQ),
.DEQ(uart_fifoXmit$DEQ),
.CLR(uart_fifoXmit$CLR),
.D_OUT(uart_fifoXmit$D_OUT),
.FULL_N(uart_fifoXmit$FULL_N),
.EMPTY_N(uart_fifoXmit$EMPTY_N));
// rule RL_dump_rx
assign CAN_FIRE_RL_dump_rx = uart_fifoRecv$EMPTY_N ;
assign WILL_FIRE_RL_dump_rx = uart_fifoRecv$EMPTY_N ;
// rule RL_compute
assign CAN_FIRE_RL_compute =
rule30$RDY_start && transmit_state == 2'd1 && !op_mode ;
assign WILL_FIRE_RL_compute = CAN_FIRE_RL_compute ;
// rule RL_uart_baudGen_baud_count_wire
assign CAN_FIRE_RL_uart_baudGen_baud_count_wire = 1'd1 ;
assign WILL_FIRE_RL_uart_baudGen_baud_count_wire = 1'd1 ;
// rule RL_uart_baud_generator_clock_enable
assign CAN_FIRE_RL_uart_baud_generator_clock_enable = 1'd1 ;
assign WILL_FIRE_RL_uart_baud_generator_clock_enable = 1'd1 ;
// rule RL_uart_receive_wait_for_start_bit
assign CAN_FIRE_RL_uart_receive_wait_for_start_bit =
uart_rRecvState == 3'd0 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_wait_for_start_bit =
CAN_FIRE_RL_uart_receive_wait_for_start_bit ;
// rule RL_uart_receive_find_center_of_bit_cell
assign CAN_FIRE_RL_uart_receive_find_center_of_bit_cell =
uart_rRecvState == 3'd1 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_find_center_of_bit_cell =
CAN_FIRE_RL_uart_receive_find_center_of_bit_cell ;
// rule RL_uart_receive_wait_bit_cell_time_for_sample
assign CAN_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample =
uart_rRecvState == 3'd2 && uart_rRecvCellCount == 4'hF &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample =
CAN_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample ;
// rule RL_uart_receive_sample_pin
assign CAN_FIRE_RL_uart_receive_sample_pin =
CAN_FIRE_RL_uart_receive_buffer_shift ;
assign WILL_FIRE_RL_uart_receive_sample_pin =
CAN_FIRE_RL_uart_receive_buffer_shift ;
// rule RL_uart_receive_parity_bit
assign CAN_FIRE_RL_uart_receive_parity_bit =
uart_rRecvState == 3'd4 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_parity_bit =
CAN_FIRE_RL_uart_receive_parity_bit ;
// rule RL_uart_receive_stop_first_bit
assign CAN_FIRE_RL_uart_receive_stop_first_bit =
uart_rRecvState == 3'd5 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_stop_first_bit =
CAN_FIRE_RL_uart_receive_stop_first_bit ;
// rule RL_uart_receive_bit_counter
assign CAN_FIRE_RL_uart_receive_bit_counter = 1'd1 ;
assign WILL_FIRE_RL_uart_receive_bit_counter = 1'd1 ;
// rule RL_uart_receive_stop_last_bit
assign CAN_FIRE_RL_uart_receive_stop_last_bit =
uart_rRecvState == 3'd6 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_stop_last_bit =
CAN_FIRE_RL_uart_receive_stop_last_bit ;
// rule RL_uart_receive_bit_cell_time_counter
assign CAN_FIRE_RL_uart_receive_bit_cell_time_counter =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
assign WILL_FIRE_RL_uart_receive_bit_cell_time_counter =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// rule RL_uart_receive_buffer_shift
assign CAN_FIRE_RL_uart_receive_buffer_shift =
uart_rRecvState == 3'd3 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_buffer_shift =
CAN_FIRE_RL_uart_receive_buffer_shift ;
// rule RL_uart_transmit_wait_for_start_command
assign CAN_FIRE_RL_uart_transmit_wait_for_start_command =
uart_rXmitState == 3'd0 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_wait_for_start_command =
CAN_FIRE_RL_uart_transmit_wait_for_start_command ;
// rule RL_get_result
assign CAN_FIRE_RL_get_result =
rule30$RDY_getResult && uart_fifoXmit$FULL_N &&
transmit_state == 2'd2 &&
!op_mode &&
xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302 &&
!xmas_fsm_start_reg ;
assign WILL_FIRE_RL_get_result = CAN_FIRE_RL_get_result ;
// rule RL_uart_transmit_send_start_bit
assign CAN_FIRE_RL_uart_transmit_send_start_bit =
uart_rXmitState == 3'd1 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_start_bit =
CAN_FIRE_RL_uart_transmit_send_start_bit ;
// rule RL_uart_transmit_wait_1_bit_cell_time
assign CAN_FIRE_RL_uart_transmit_wait_1_bit_cell_time =
uart_rXmitState == 3'd2 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time =
CAN_FIRE_RL_uart_transmit_wait_1_bit_cell_time ;
// rule RL_uart_transmit_bit_counter
assign CAN_FIRE_RL_uart_transmit_bit_counter = 1'd1 ;
assign WILL_FIRE_RL_uart_transmit_bit_counter = 1'd1 ;
// rule RL_uart_transmit_shift_next_bit
assign CAN_FIRE_RL_uart_transmit_shift_next_bit =
uart_rXmitState == 3'd3 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_shift_next_bit =
CAN_FIRE_RL_uart_transmit_shift_next_bit ;
// rule RL_uart_transmit_buffer_load
assign CAN_FIRE_RL_uart_transmit_buffer_load =
uart_fifoXmit$EMPTY_N && uart_pwXmitLoadBuffer$whas ;
assign WILL_FIRE_RL_uart_transmit_buffer_load =
CAN_FIRE_RL_uart_transmit_buffer_load ;
// rule RL_uart_transmit_buffer_shift
assign CAN_FIRE_RL_uart_transmit_buffer_shift =
!uart_pwXmitLoadBuffer$whas &&
CAN_FIRE_RL_uart_transmit_shift_next_bit ;
assign WILL_FIRE_RL_uart_transmit_buffer_shift =
CAN_FIRE_RL_uart_transmit_buffer_shift ;
// rule RL_uart_transmit_send_parity_bit
assign CAN_FIRE_RL_uart_transmit_send_parity_bit =
uart_rXmitState == 3'd7 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_parity_bit =
CAN_FIRE_RL_uart_transmit_send_parity_bit ;
// rule RL_uart_transmit_send_stop_bit
assign CAN_FIRE_RL_uart_transmit_send_stop_bit =
uart_rXmitState == 3'd4 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_stop_bit =
CAN_FIRE_RL_uart_transmit_send_stop_bit ;
// rule RL_uart_transmit_send_stop_bit1_5
assign CAN_FIRE_RL_uart_transmit_send_stop_bit1_5 =
uart_rXmitState == 3'd5 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 =
CAN_FIRE_RL_uart_transmit_send_stop_bit1_5 ;
// rule RL_uart_transmit_send_stop_bit2
assign CAN_FIRE_RL_uart_transmit_send_stop_bit2 =
uart_rXmitState == 3'd6 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_stop_bit2 =
CAN_FIRE_RL_uart_transmit_send_stop_bit2 ;
// rule RL_uart_transmit_bit_cell_time_counter
assign CAN_FIRE_RL_uart_transmit_bit_cell_time_counter =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
assign WILL_FIRE_RL_uart_transmit_bit_cell_time_counter =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// rule RL_uart_baudGen_baud_tick_count_wire
assign CAN_FIRE_RL_uart_baudGen_baud_tick_count_wire = 1'd1 ;
assign WILL_FIRE_RL_uart_baudGen_baud_tick_count_wire = 1'd1 ;
// rule RL_uart_baudGen_assert_2x_baud_tick
assign CAN_FIRE_RL_uart_baudGen_assert_2x_baud_tick =
uart_baudGen_rBaudTickCounter$Q_OUT == 3'd0 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_baudGen_assert_2x_baud_tick =
CAN_FIRE_RL_uart_baudGen_assert_2x_baud_tick ;
// rule RL_uart_baudGen_count_baudtick_16x
assign CAN_FIRE_RL_uart_baudGen_count_baudtick_16x =
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_baudGen_count_baudtick_16x =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// rule RL_uart_fifoRecv__updateLevelCounter
assign CAN_FIRE_RL_uart_fifoRecv__updateLevelCounter =
CAN_FIRE_RL_uart_receive_stop_last_bit != uart_fifoRecv$EMPTY_N ;
assign WILL_FIRE_RL_uart_fifoRecv__updateLevelCounter =
CAN_FIRE_RL_uart_fifoRecv__updateLevelCounter ;
// rule RL_xmas_fsm_restart
assign CAN_FIRE_RL_xmas_fsm_restart =
xmas_fsm_start_reg_1 && !xmas_fsm_state_fired ;
assign WILL_FIRE_RL_xmas_fsm_restart = CAN_FIRE_RL_xmas_fsm_restart ;
// rule RL_xmas_fsm_action_l43c32
assign CAN_FIRE_RL_xmas_fsm_action_l43c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd1 ;
assign WILL_FIRE_RL_xmas_fsm_action_l43c32 =
CAN_FIRE_RL_xmas_fsm_action_l43c32 ;
// rule RL_xmas_fsm_action_l44c32
assign CAN_FIRE_RL_xmas_fsm_action_l44c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd2 ;
assign WILL_FIRE_RL_xmas_fsm_action_l44c32 =
CAN_FIRE_RL_xmas_fsm_action_l44c32 ;
// rule RL_xmas_fsm_action_l45c32
assign CAN_FIRE_RL_xmas_fsm_action_l45c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd3 ;
assign WILL_FIRE_RL_xmas_fsm_action_l45c32 =
CAN_FIRE_RL_xmas_fsm_action_l45c32 ;
// rule RL_xmas_fsm_action_l46c32
assign CAN_FIRE_RL_xmas_fsm_action_l46c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd4 ;
assign WILL_FIRE_RL_xmas_fsm_action_l46c32 =
CAN_FIRE_RL_xmas_fsm_action_l46c32 ;
// rule RL_xmas_fsm_action_l47c32
assign CAN_FIRE_RL_xmas_fsm_action_l47c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd5 ;
assign WILL_FIRE_RL_xmas_fsm_action_l47c32 =
CAN_FIRE_RL_xmas_fsm_action_l47c32 ;
// rule RL_xmas_fsm_action_l48c32
assign CAN_FIRE_RL_xmas_fsm_action_l48c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd6 ;
assign WILL_FIRE_RL_xmas_fsm_action_l48c32 =
CAN_FIRE_RL_xmas_fsm_action_l48c32 ;
// rule RL_xmas_fsm_action_l49c32
assign CAN_FIRE_RL_xmas_fsm_action_l49c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd7 ;
assign WILL_FIRE_RL_xmas_fsm_action_l49c32 =
CAN_FIRE_RL_xmas_fsm_action_l49c32 ;
// rule RL_xmas_fsm_action_l50c32
assign CAN_FIRE_RL_xmas_fsm_action_l50c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd8 ;
assign WILL_FIRE_RL_xmas_fsm_action_l50c32 =
CAN_FIRE_RL_xmas_fsm_action_l50c32 ;
// rule RL_xmas_fsm_action_l51c32
assign CAN_FIRE_RL_xmas_fsm_action_l51c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd9 ;
assign WILL_FIRE_RL_xmas_fsm_action_l51c32 =
CAN_FIRE_RL_xmas_fsm_action_l51c32 ;
// rule RL_xmas_fsm_action_l52c32
assign CAN_FIRE_RL_xmas_fsm_action_l52c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd10 ;
assign WILL_FIRE_RL_xmas_fsm_action_l52c32 =
CAN_FIRE_RL_xmas_fsm_action_l52c32 ;
// rule RL_xmas_fsm_action_l53c32
assign CAN_FIRE_RL_xmas_fsm_action_l53c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd11 ;
assign WILL_FIRE_RL_xmas_fsm_action_l53c32 =
CAN_FIRE_RL_xmas_fsm_action_l53c32 ;
// rule RL_xmas_fsm_action_l54c32
assign CAN_FIRE_RL_xmas_fsm_action_l54c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd12 ;
assign WILL_FIRE_RL_xmas_fsm_action_l54c32 =
CAN_FIRE_RL_xmas_fsm_action_l54c32 ;
// rule RL_xmas_fsm_action_l55c32
assign CAN_FIRE_RL_xmas_fsm_action_l55c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd13 ;
assign WILL_FIRE_RL_xmas_fsm_action_l55c32 =
CAN_FIRE_RL_xmas_fsm_action_l55c32 ;
// rule RL_xmas_fsm_action_l56c32
assign CAN_FIRE_RL_xmas_fsm_action_l56c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd14 ;
assign WILL_FIRE_RL_xmas_fsm_action_l56c32 =
CAN_FIRE_RL_xmas_fsm_action_l56c32 ;
// rule RL_xmas_fsm_action_l57c32
assign CAN_FIRE_RL_xmas_fsm_action_l57c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd15 ;
assign WILL_FIRE_RL_xmas_fsm_action_l57c32 =
CAN_FIRE_RL_xmas_fsm_action_l57c32 ;
// rule RL_xmas_fsm_action_l58c32
assign CAN_FIRE_RL_xmas_fsm_action_l58c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd16 ;
assign WILL_FIRE_RL_xmas_fsm_action_l58c32 =
CAN_FIRE_RL_xmas_fsm_action_l58c32 ;
// rule RL_xmas_fsm_action_l59c32
assign CAN_FIRE_RL_xmas_fsm_action_l59c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd17 ;
assign WILL_FIRE_RL_xmas_fsm_action_l59c32 =
CAN_FIRE_RL_xmas_fsm_action_l59c32 ;
// rule RL_xmas_fsm_action_l60c32
assign CAN_FIRE_RL_xmas_fsm_action_l60c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd18 ;
assign WILL_FIRE_RL_xmas_fsm_action_l60c32 =
CAN_FIRE_RL_xmas_fsm_action_l60c32 ;
// rule RL_xmas_fsm_action_l61c32
assign CAN_FIRE_RL_xmas_fsm_action_l61c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd19 ;
assign WILL_FIRE_RL_xmas_fsm_action_l61c32 =
CAN_FIRE_RL_xmas_fsm_action_l61c32 ;
// rule RL_xmas_fsm_action_l62c32
assign CAN_FIRE_RL_xmas_fsm_action_l62c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd20 ;
assign WILL_FIRE_RL_xmas_fsm_action_l62c32 =
CAN_FIRE_RL_xmas_fsm_action_l62c32 ;
// rule RL_xmas_fsm_action_l63c32
assign CAN_FIRE_RL_xmas_fsm_action_l63c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd21 ;
assign WILL_FIRE_RL_xmas_fsm_action_l63c32 =
CAN_FIRE_RL_xmas_fsm_action_l63c32 ;
// rule RL_xmas_fsm_action_l64c32
assign CAN_FIRE_RL_xmas_fsm_action_l64c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd22 ;
assign WILL_FIRE_RL_xmas_fsm_action_l64c32 =
CAN_FIRE_RL_xmas_fsm_action_l64c32 ;
// rule RL_xmas_fsm_action_l65c32
assign CAN_FIRE_RL_xmas_fsm_action_l65c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd23 ;
assign WILL_FIRE_RL_xmas_fsm_action_l65c32 =
CAN_FIRE_RL_xmas_fsm_action_l65c32 ;
// rule RL_xmas_fsm_action_l66c32
assign CAN_FIRE_RL_xmas_fsm_action_l66c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd24 ;
assign WILL_FIRE_RL_xmas_fsm_action_l66c32 =
CAN_FIRE_RL_xmas_fsm_action_l66c32 ;
// rule __me_check_35
assign CAN_FIRE___me_check_35 = 1'b1 ;
assign WILL_FIRE___me_check_35 = 1'b1 ;
// rule __me_check_36
assign CAN_FIRE___me_check_36 = 1'b1 ;
assign WILL_FIRE___me_check_36 = 1'b1 ;
// rule __me_check_37
assign CAN_FIRE___me_check_37 = 1'b1 ;
assign WILL_FIRE___me_check_37 = 1'b1 ;
// rule __me_check_38
assign CAN_FIRE___me_check_38 = 1'b1 ;
assign WILL_FIRE___me_check_38 = 1'b1 ;
// rule __me_check_39
assign CAN_FIRE___me_check_39 = 1'b1 ;
assign WILL_FIRE___me_check_39 = 1'b1 ;
// rule __me_check_40
assign CAN_FIRE___me_check_40 = 1'b1 ;
assign WILL_FIRE___me_check_40 = 1'b1 ;
// rule __me_check_41
assign CAN_FIRE___me_check_41 = 1'b1 ;
assign WILL_FIRE___me_check_41 = 1'b1 ;
// rule __me_check_43
assign CAN_FIRE___me_check_43 = 1'b1 ;
assign WILL_FIRE___me_check_43 = 1'b1 ;
// rule __me_check_42
assign CAN_FIRE___me_check_42 = 1'b1 ;
assign WILL_FIRE___me_check_42 = 1'b1 ;
// rule __me_check_44
assign CAN_FIRE___me_check_44 = 1'b1 ;
assign WILL_FIRE___me_check_44 = 1'b1 ;
// rule __me_check_45
assign CAN_FIRE___me_check_45 = 1'b1 ;
assign WILL_FIRE___me_check_45 = 1'b1 ;
// rule __me_check_46
assign CAN_FIRE___me_check_46 = 1'b1 ;
assign WILL_FIRE___me_check_46 = 1'b1 ;
// rule __me_check_47
assign CAN_FIRE___me_check_47 = 1'b1 ;
assign WILL_FIRE___me_check_47 = 1'b1 ;
// rule __me_check_48
assign CAN_FIRE___me_check_48 = 1'b1 ;
assign WILL_FIRE___me_check_48 = 1'b1 ;
// rule __me_check_49
assign CAN_FIRE___me_check_49 = 1'b1 ;
assign WILL_FIRE___me_check_49 = 1'b1 ;
// rule __me_check_51
assign CAN_FIRE___me_check_51 = 1'b1 ;
assign WILL_FIRE___me_check_51 = 1'b1 ;
// rule __me_check_50
assign CAN_FIRE___me_check_50 = 1'b1 ;
assign WILL_FIRE___me_check_50 = 1'b1 ;
// rule __me_check_52
assign CAN_FIRE___me_check_52 = 1'b1 ;
assign WILL_FIRE___me_check_52 = 1'b1 ;
// rule __me_check_53
assign CAN_FIRE___me_check_53 = 1'b1 ;
assign WILL_FIRE___me_check_53 = 1'b1 ;
// rule __me_check_54
assign CAN_FIRE___me_check_54 = 1'b1 ;
assign WILL_FIRE___me_check_54 = 1'b1 ;
// rule __me_check_55
assign CAN_FIRE___me_check_55 = 1'b1 ;
assign WILL_FIRE___me_check_55 = 1'b1 ;
// rule __me_check_56
assign CAN_FIRE___me_check_56 = 1'b1 ;
assign WILL_FIRE___me_check_56 = 1'b1 ;
// rule __me_check_57
assign CAN_FIRE___me_check_57 = 1'b1 ;
assign WILL_FIRE___me_check_57 = 1'b1 ;
// rule RL_xmas_fsm_idle_l40c27_1
assign CAN_FIRE_RL_xmas_fsm_idle_l40c27_1 =
!op_mode && xmas_fsm_state_mkFSMstate == 5'd25 ;
assign WILL_FIRE_RL_xmas_fsm_idle_l40c27_1 =
CAN_FIRE_RL_xmas_fsm_idle_l40c27_1 ;
// rule RL_xmas_fsm_fsm_start
assign CAN_FIRE_RL_xmas_fsm_fsm_start =
(op_mode && xmas_fsm_state_mkFSMstate == 5'd0 ||
op_mode && xmas_fsm_state_mkFSMstate == 5'd27 ||
!op_mode && xmas_fsm_state_mkFSMstate == 5'd0 ||
!op_mode &&
(xmas_fsm_state_mkFSMstate == 5'd25 ||
xmas_fsm_state_mkFSMstate == 5'd27)) &&
(!xmas_fsm_start_reg_1 || xmas_fsm_state_fired) &&
xmas_fsm_start_reg ;
assign WILL_FIRE_RL_xmas_fsm_fsm_start = CAN_FIRE_RL_xmas_fsm_fsm_start ;
// rule RL_xmas_fsm_action_l42c32
assign CAN_FIRE_RL_xmas_fsm_action_l42c32 =
uart_fifoXmit$FULL_N &&
(op_mode && xmas_fsm_start_wire$whas &&
xmas_fsm_state_mkFSMstate == 5'd0 ||
op_mode && xmas_fsm_state_mkFSMstate == 5'd25) ;
assign WILL_FIRE_RL_xmas_fsm_action_l42c32 =
CAN_FIRE_RL_xmas_fsm_action_l42c32 ;
// rule __me_check_34
assign CAN_FIRE___me_check_34 = 1'b1 ;
assign WILL_FIRE___me_check_34 = 1'b1 ;
// rule RL_uart_fifoXmit__updateLevelCounter
assign CAN_FIRE_RL_uart_fifoXmit__updateLevelCounter =
uart_fifoXmit_r_enq$whas !=
CAN_FIRE_RL_uart_transmit_buffer_load ;
assign WILL_FIRE_RL_uart_fifoXmit__updateLevelCounter =
CAN_FIRE_RL_uart_fifoXmit__updateLevelCounter ;
// rule RL_xmas_fsm_idle_l40c27
assign CAN_FIRE_RL_xmas_fsm_idle_l40c27 =
!op_mode && xmas_fsm_start_wire$whas &&
xmas_fsm_state_mkFSMstate == 5'd0 ;
assign WILL_FIRE_RL_xmas_fsm_idle_l40c27 =
CAN_FIRE_RL_xmas_fsm_idle_l40c27 ;
// rule RL_xmas_fsm_start_reg__dreg_update
assign CAN_FIRE_RL_xmas_fsm_start_reg__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_xmas_fsm_start_reg__dreg_update = 1'd1 ;
// rule RL_xmas_fsm_state_handle_abort
assign CAN_FIRE_RL_xmas_fsm_state_handle_abort = 1'b0 ;
assign WILL_FIRE_RL_xmas_fsm_state_handle_abort = 1'b0 ;
// rule RL_xmas_fsm_state_every
assign CAN_FIRE_RL_xmas_fsm_state_every = 1'd1 ;
assign WILL_FIRE_RL_xmas_fsm_state_every = 1'd1 ;
// rule RL_xmas_fsm_state_fired__dreg_update
assign CAN_FIRE_RL_xmas_fsm_state_fired__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_xmas_fsm_state_fired__dreg_update = 1'd1 ;
// inputs to muxes for submodule ports
assign MUX_transmit_state$write_1__SEL_1 =
WILL_FIRE_RL_get_result || EN_startup_value ;
assign MUX_uart_fifoXmit$enq_1__SEL_2 =
WILL_FIRE_RL_xmas_fsm_action_l66c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_3 =
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_11 =
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_15 =
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_16 =
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_17 =
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ;
assign MUX_uart_rRecvState$write_1__SEL_6 =
WILL_FIRE_RL_uart_receive_parity_bit ||
WILL_FIRE_RL_uart_receive_sample_pin ;
assign MUX_uart_rXmitDataOut$write_1__SEL_1 =
WILL_FIRE_RL_uart_transmit_shift_next_bit ||
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ;
assign MUX_uart_rXmitDataOut$write_1__SEL_2 =
WILL_FIRE_RL_uart_transmit_send_parity_bit ||
WILL_FIRE_RL_uart_transmit_send_start_bit ;
assign MUX_uart_rXmitDataOut$write_1__SEL_3 =
WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit ||
WILL_FIRE_RL_uart_transmit_wait_for_start_command ;
assign MUX_xmas_fsm_start_reg$write_1__SEL_1 =
EN_operation_mode && operation_mode_arg == 8'hA5 ;
assign MUX_xmas_fsm_state_mkFSMstate$write_1__SEL_1 =
WILL_FIRE_RL_xmas_fsm_idle_l40c27_1 ||
WILL_FIRE_RL_xmas_fsm_idle_l40c27 ;
assign MUX_uart_rRecvState$write_1__VAL_1 = uart_rRecvData ? 3'd0 : 3'd1 ;
assign MUX_uart_rRecvState$write_1__VAL_2 =
(uart_rRecvCellCount == 4'h4) ?
(uart_rRecvData ? 3'd0 : 3'd2) :
3'd1 ;
always@(uart_rRecvBitCount)
begin
case (uart_rRecvBitCount)
4'd8, 4'd9, 4'd10: MUX_uart_rRecvState$write_1__VAL_3 = 3'd6;
default: MUX_uart_rRecvState$write_1__VAL_3 = 3'd3;
endcase
end
assign MUX_uart_rRecvState$write_1__VAL_4 = uart_rRecvData ? 3'd2 : 3'd0 ;
assign MUX_uart_rXmitState$write_1__VAL_1 =
uart_fifoXmit$EMPTY_N ? 3'd1 : 3'd0 ;
assign MUX_uart_rXmitState$write_1__VAL_2 =
(uart_rXmitCellCount == 4'hF) ? 3'd2 : 3'd1 ;
assign MUX_uart_rXmitState$write_1__VAL_3 =
(uart_rXmitCellCount == 4'hF) ?
((uart_rXmitBitCount == 4'd7) ? 3'd4 : 3'd3) :
3'd2 ;
assign MUX_uart_rXmitState$write_1__VAL_4 =
(uart_rXmitCellCount == 4'hF) ? 3'd4 : 3'd7 ;
assign MUX_uart_rXmitState$write_1__VAL_5 =
(uart_rXmitCellCount == 4'hF) ? 3'd0 : 3'd4 ;
assign MUX_uart_rXmitState$write_1__VAL_6 =
(uart_rXmitCellCount == 4'h7) ? 3'd0 : 3'd5 ;
assign MUX_uart_rXmitState$write_1__VAL_7 =
(uart_rXmitCellCount == 4'hF) ? 3'd0 : 3'd6 ;
// inlined wires
assign xmas_fsm_start_wire$whas =
WILL_FIRE_RL_xmas_fsm_fsm_start ||
WILL_FIRE_RL_xmas_fsm_restart ;
assign uart_pwRecvCellCountReset$whas =
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell &&
uart_rRecvCellCount == 4'h4 ||
WILL_FIRE_RL_uart_receive_stop_last_bit ||
WILL_FIRE_RL_uart_receive_stop_first_bit ||
WILL_FIRE_RL_uart_receive_parity_bit ||
WILL_FIRE_RL_uart_receive_sample_pin ||
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample ||
WILL_FIRE_RL_uart_receive_wait_for_start_bit ;
assign uart_pwRecvResetBitCount$whas =
WILL_FIRE_RL_uart_receive_wait_for_start_bit && uart_rRecvData ;
assign uart_pwRecvEnableBitCount$whas =
WILL_FIRE_RL_uart_receive_stop_first_bit ||
WILL_FIRE_RL_uart_receive_parity_bit ||
WILL_FIRE_RL_uart_receive_sample_pin ;
assign uart_fifoXmit_r_enq$whas =
WILL_FIRE_RL_get_result || WILL_FIRE_RL_xmas_fsm_action_l66c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ||
WILL_FIRE_RL_xmas_fsm_action_l64c32 ||
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l62c32 ||
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ||
WILL_FIRE_RL_xmas_fsm_action_l57c32 ||
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l55c32 ||
WILL_FIRE_RL_xmas_fsm_action_l54c32 ||
WILL_FIRE_RL_xmas_fsm_action_l53c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ||
WILL_FIRE_RL_xmas_fsm_action_l49c32 ||
WILL_FIRE_RL_xmas_fsm_action_l48c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ||
WILL_FIRE_RL_xmas_fsm_action_l46c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ||
WILL_FIRE_RL_xmas_fsm_action_l43c32 ||
WILL_FIRE_RL_xmas_fsm_action_l42c32 ;
assign uart_pwXmitCellCountReset$whas =
WILL_FIRE_RL_uart_transmit_wait_for_start_command &&
uart_fifoXmit$EMPTY_N ||
_dor2uart_pwXmitCellCountReset$EN_wset &&
uart_rXmitCellCount == 4'hF ||
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 &&
uart_rXmitCellCount == 4'h7 ;
assign uart_pwXmitEnableBitCount$whas =
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time &&
uart_rXmitCellCount == 4'hF &&
uart_rXmitBitCount != 4'd7 ;
assign uart_pwXmitLoadBuffer$whas =
WILL_FIRE_RL_uart_transmit_wait_for_start_command &&
uart_fifoXmit$EMPTY_N ;
assign xmas_fsm_state_set_pw$whas =
WILL_FIRE_RL_xmas_fsm_idle_l40c27_1 ||
WILL_FIRE_RL_xmas_fsm_idle_l40c27 ||
WILL_FIRE_RL_xmas_fsm_action_l66c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ||
WILL_FIRE_RL_xmas_fsm_action_l64c32 ||
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l62c32 ||
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ||
WILL_FIRE_RL_xmas_fsm_action_l57c32 ||
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l55c32 ||
WILL_FIRE_RL_xmas_fsm_action_l54c32 ||
WILL_FIRE_RL_xmas_fsm_action_l53c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ||
WILL_FIRE_RL_xmas_fsm_action_l49c32 ||
WILL_FIRE_RL_xmas_fsm_action_l48c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ||
WILL_FIRE_RL_xmas_fsm_action_l46c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ||
WILL_FIRE_RL_xmas_fsm_action_l43c32 ||
WILL_FIRE_RL_xmas_fsm_action_l42c32 ;
// register a
assign a$D_IN = EN_startup_value ? startup_value_v : rule30$getResult ;
assign a$EN = EN_startup_value || WILL_FIRE_RL_get_result ;
// register op_mode
assign op_mode$D_IN = 1'd1 ;
assign op_mode$EN = MUX_xmas_fsm_start_reg$write_1__SEL_1 ;
// register transmit_state
assign transmit_state$D_IN =
MUX_transmit_state$write_1__SEL_1 ? 2'd1 : 2'd2 ;
assign transmit_state$EN =
WILL_FIRE_RL_get_result || EN_startup_value ||
WILL_FIRE_RL_compute ;
// register uart_rRecvBitCount
assign uart_rRecvBitCount$D_IN =
uart_pwRecvResetBitCount$whas ? 4'd0 : x__h4689 ;
assign uart_rRecvBitCount$EN =
uart_pwRecvResetBitCount$whas || uart_pwRecvEnableBitCount$whas ;
// register uart_rRecvCellCount
assign uart_rRecvCellCount$D_IN =
uart_pwRecvCellCountReset$whas ? 4'd0 : x__h2985 ;
assign uart_rRecvCellCount$EN =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// register uart_rRecvData
assign uart_rRecvData$D_IN = txrx_SIN ;
assign uart_rRecvData$EN = 1'd1 ;
// register uart_rRecvState
always@(WILL_FIRE_RL_uart_receive_wait_for_start_bit or
MUX_uart_rRecvState$write_1__VAL_1 or
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell or
MUX_uart_rRecvState$write_1__VAL_2 or
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample or
MUX_uart_rRecvState$write_1__VAL_3 or
WILL_FIRE_RL_uart_receive_stop_first_bit or
MUX_uart_rRecvState$write_1__VAL_4 or
WILL_FIRE_RL_uart_receive_stop_last_bit or
MUX_uart_rRecvState$write_1__SEL_6)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_uart_receive_wait_for_start_bit:
uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_1;
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell:
uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_2;
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample:
uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_3;
WILL_FIRE_RL_uart_receive_stop_first_bit:
uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_4;
WILL_FIRE_RL_uart_receive_stop_last_bit: uart_rRecvState$D_IN = 3'd0;
MUX_uart_rRecvState$write_1__SEL_6: uart_rRecvState$D_IN = 3'd2;
default: uart_rRecvState$D_IN = 3'b010 /* unspecified value */ ;
endcase
end
assign uart_rRecvState$EN =
WILL_FIRE_RL_uart_receive_wait_for_start_bit ||
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell ||
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample ||
WILL_FIRE_RL_uart_receive_stop_first_bit ||
WILL_FIRE_RL_uart_receive_stop_last_bit ||
WILL_FIRE_RL_uart_receive_parity_bit ||
WILL_FIRE_RL_uart_receive_sample_pin ;
// register uart_rXmitBitCount
assign uart_rXmitBitCount$D_IN =
CAN_FIRE_RL_uart_transmit_wait_for_start_command ?
4'd0 :
x__h6471 ;
assign uart_rXmitBitCount$EN =
CAN_FIRE_RL_uart_transmit_wait_for_start_command ||
uart_pwXmitEnableBitCount$whas ;
// register uart_rXmitCellCount
assign uart_rXmitCellCount$D_IN =
uart_pwXmitCellCountReset$whas ? 4'd0 : x__h6445 ;
assign uart_rXmitCellCount$EN =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// register uart_rXmitDataOut
always@(MUX_uart_rXmitDataOut$write_1__SEL_1 or
uart_vrXmitBuffer_0 or
MUX_uart_rXmitDataOut$write_1__SEL_2 or
MUX_uart_rXmitDataOut$write_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_uart_rXmitDataOut$write_1__SEL_1:
uart_rXmitDataOut$D_IN = uart_vrXmitBuffer_0;
MUX_uart_rXmitDataOut$write_1__SEL_2: uart_rXmitDataOut$D_IN = 1'b0;
MUX_uart_rXmitDataOut$write_1__SEL_3: uart_rXmitDataOut$D_IN = 1'b1;
default: uart_rXmitDataOut$D_IN = 1'b0 /* unspecified value */ ;
endcase
end
assign uart_rXmitDataOut$EN =
WILL_FIRE_RL_uart_transmit_shift_next_bit ||
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ||
WILL_FIRE_RL_uart_transmit_send_parity_bit ||
WILL_FIRE_RL_uart_transmit_send_start_bit ||
WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit ||
WILL_FIRE_RL_uart_transmit_wait_for_start_command ;
// register uart_rXmitState
always@(WILL_FIRE_RL_uart_transmit_wait_for_start_command or
MUX_uart_rXmitState$write_1__VAL_1 or
WILL_FIRE_RL_uart_transmit_send_start_bit or
MUX_uart_rXmitState$write_1__VAL_2 or
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time or
MUX_uart_rXmitState$write_1__VAL_3 or
WILL_FIRE_RL_uart_transmit_send_parity_bit or
MUX_uart_rXmitState$write_1__VAL_4 or
WILL_FIRE_RL_uart_transmit_send_stop_bit or
MUX_uart_rXmitState$write_1__VAL_5 or
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 or
MUX_uart_rXmitState$write_1__VAL_6 or
WILL_FIRE_RL_uart_transmit_send_stop_bit2 or
MUX_uart_rXmitState$write_1__VAL_7 or
WILL_FIRE_RL_uart_transmit_shift_next_bit)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_uart_transmit_wait_for_start_command:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_1;
WILL_FIRE_RL_uart_transmit_send_start_bit:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_2;
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_3;
WILL_FIRE_RL_uart_transmit_send_parity_bit:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_4;
WILL_FIRE_RL_uart_transmit_send_stop_bit:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_5;
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_6;
WILL_FIRE_RL_uart_transmit_send_stop_bit2:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_7;
WILL_FIRE_RL_uart_transmit_shift_next_bit: uart_rXmitState$D_IN = 3'd2;
default: uart_rXmitState$D_IN = 3'b010 /* unspecified value */ ;
endcase
end
assign uart_rXmitState$EN =
WILL_FIRE_RL_uart_transmit_wait_for_start_command ||
WILL_FIRE_RL_uart_transmit_send_start_bit ||
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ||
WILL_FIRE_RL_uart_transmit_send_parity_bit ||
WILL_FIRE_RL_uart_transmit_send_stop_bit ||
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
WILL_FIRE_RL_uart_transmit_shift_next_bit ;
// register uart_vrRecvBuffer_0
assign uart_vrRecvBuffer_0$D_IN = uart_vrRecvBuffer_1 ;
assign uart_vrRecvBuffer_0$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_1
assign uart_vrRecvBuffer_1$D_IN = uart_vrRecvBuffer_2 ;
assign uart_vrRecvBuffer_1$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_2
assign uart_vrRecvBuffer_2$D_IN = uart_vrRecvBuffer_3 ;
assign uart_vrRecvBuffer_2$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_3
assign uart_vrRecvBuffer_3$D_IN = uart_vrRecvBuffer_4 ;
assign uart_vrRecvBuffer_3$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_4
assign uart_vrRecvBuffer_4$D_IN = uart_vrRecvBuffer_5 ;
assign uart_vrRecvBuffer_4$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_5
assign uart_vrRecvBuffer_5$D_IN = uart_vrRecvBuffer_6 ;
assign uart_vrRecvBuffer_5$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_6
assign uart_vrRecvBuffer_6$D_IN = uart_vrRecvBuffer_7 ;
assign uart_vrRecvBuffer_6$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_7
assign uart_vrRecvBuffer_7$D_IN = uart_rRecvData ;
assign uart_vrRecvBuffer_7$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrXmitBuffer_0
assign uart_vrXmitBuffer_0$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[0] :
uart_vrXmitBuffer_1 ;
assign uart_vrXmitBuffer_0$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_1
assign uart_vrXmitBuffer_1$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[1] :
uart_vrXmitBuffer_2 ;
assign uart_vrXmitBuffer_1$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_2
assign uart_vrXmitBuffer_2$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[2] :
uart_vrXmitBuffer_3 ;
assign uart_vrXmitBuffer_2$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_3
assign uart_vrXmitBuffer_3$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[3] :
uart_vrXmitBuffer_4 ;
assign uart_vrXmitBuffer_3$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_4
assign uart_vrXmitBuffer_4$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[4] :
uart_vrXmitBuffer_5 ;
assign uart_vrXmitBuffer_4$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_5
assign uart_vrXmitBuffer_5$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[5] :
uart_vrXmitBuffer_6 ;
assign uart_vrXmitBuffer_5$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_6
assign uart_vrXmitBuffer_6$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[6] :
uart_vrXmitBuffer_7 ;
assign uart_vrXmitBuffer_6$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_7
assign uart_vrXmitBuffer_7$D_IN =
!WILL_FIRE_RL_uart_transmit_buffer_load ||
uart_fifoXmit$D_OUT[7] ;
assign uart_vrXmitBuffer_7$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register xmas_fsm_start_reg
assign xmas_fsm_start_reg$D_IN = MUX_xmas_fsm_start_reg$write_1__SEL_1 ;
assign xmas_fsm_start_reg$EN =
EN_operation_mode && operation_mode_arg == 8'hA5 ||
WILL_FIRE_RL_xmas_fsm_fsm_start ;
// register xmas_fsm_start_reg_1
assign xmas_fsm_start_reg_1$D_IN = xmas_fsm_start_wire$whas ;
assign xmas_fsm_start_reg_1$EN = 1'd1 ;
// register xmas_fsm_state_fired
assign xmas_fsm_state_fired$D_IN = xmas_fsm_state_set_pw$whas ;
assign xmas_fsm_state_fired$EN = 1'd1 ;
// register xmas_fsm_state_mkFSMstate
always@(MUX_xmas_fsm_state_mkFSMstate$write_1__SEL_1 or
WILL_FIRE_RL_xmas_fsm_action_l42c32 or
WILL_FIRE_RL_xmas_fsm_action_l43c32 or
WILL_FIRE_RL_xmas_fsm_action_l44c32 or
WILL_FIRE_RL_xmas_fsm_action_l45c32 or
WILL_FIRE_RL_xmas_fsm_action_l46c32 or
WILL_FIRE_RL_xmas_fsm_action_l47c32 or
WILL_FIRE_RL_xmas_fsm_action_l48c32 or
WILL_FIRE_RL_xmas_fsm_action_l49c32 or
WILL_FIRE_RL_xmas_fsm_action_l50c32 or
WILL_FIRE_RL_xmas_fsm_action_l51c32 or
WILL_FIRE_RL_xmas_fsm_action_l52c32 or
WILL_FIRE_RL_xmas_fsm_action_l53c32 or
WILL_FIRE_RL_xmas_fsm_action_l54c32 or
WILL_FIRE_RL_xmas_fsm_action_l55c32 or
WILL_FIRE_RL_xmas_fsm_action_l56c32 or
WILL_FIRE_RL_xmas_fsm_action_l57c32 or
WILL_FIRE_RL_xmas_fsm_action_l58c32 or
WILL_FIRE_RL_xmas_fsm_action_l59c32 or
WILL_FIRE_RL_xmas_fsm_action_l60c32 or
WILL_FIRE_RL_xmas_fsm_action_l61c32 or
WILL_FIRE_RL_xmas_fsm_action_l62c32 or
WILL_FIRE_RL_xmas_fsm_action_l63c32 or
WILL_FIRE_RL_xmas_fsm_action_l64c32 or
WILL_FIRE_RL_xmas_fsm_action_l65c32 or
WILL_FIRE_RL_xmas_fsm_action_l66c32)
begin
case (1'b1) // synopsys parallel_case
MUX_xmas_fsm_state_mkFSMstate$write_1__SEL_1:
xmas_fsm_state_mkFSMstate$D_IN = 5'd0;
WILL_FIRE_RL_xmas_fsm_action_l42c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd1;
WILL_FIRE_RL_xmas_fsm_action_l43c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd2;
WILL_FIRE_RL_xmas_fsm_action_l44c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd3;
WILL_FIRE_RL_xmas_fsm_action_l45c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd4;
WILL_FIRE_RL_xmas_fsm_action_l46c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd5;
WILL_FIRE_RL_xmas_fsm_action_l47c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd6;
WILL_FIRE_RL_xmas_fsm_action_l48c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd7;
WILL_FIRE_RL_xmas_fsm_action_l49c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd8;
WILL_FIRE_RL_xmas_fsm_action_l50c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd9;
WILL_FIRE_RL_xmas_fsm_action_l51c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd10;
WILL_FIRE_RL_xmas_fsm_action_l52c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd11;
WILL_FIRE_RL_xmas_fsm_action_l53c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd12;
WILL_FIRE_RL_xmas_fsm_action_l54c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd13;
WILL_FIRE_RL_xmas_fsm_action_l55c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd14;
WILL_FIRE_RL_xmas_fsm_action_l56c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd15;
WILL_FIRE_RL_xmas_fsm_action_l57c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd16;
WILL_FIRE_RL_xmas_fsm_action_l58c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd17;
WILL_FIRE_RL_xmas_fsm_action_l59c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd18;
WILL_FIRE_RL_xmas_fsm_action_l60c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd19;
WILL_FIRE_RL_xmas_fsm_action_l61c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd20;
WILL_FIRE_RL_xmas_fsm_action_l62c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd21;
WILL_FIRE_RL_xmas_fsm_action_l63c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd22;
WILL_FIRE_RL_xmas_fsm_action_l64c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd23;
WILL_FIRE_RL_xmas_fsm_action_l65c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd24;
WILL_FIRE_RL_xmas_fsm_action_l66c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd25;
default: xmas_fsm_state_mkFSMstate$D_IN =
5'b01010 /* unspecified value */ ;
endcase
end
assign xmas_fsm_state_mkFSMstate$EN =
WILL_FIRE_RL_xmas_fsm_idle_l40c27_1 ||
WILL_FIRE_RL_xmas_fsm_idle_l40c27 ||
WILL_FIRE_RL_xmas_fsm_action_l42c32 ||
WILL_FIRE_RL_xmas_fsm_action_l43c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l46c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ||
WILL_FIRE_RL_xmas_fsm_action_l48c32 ||
WILL_FIRE_RL_xmas_fsm_action_l49c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l53c32 ||
WILL_FIRE_RL_xmas_fsm_action_l54c32 ||
WILL_FIRE_RL_xmas_fsm_action_l55c32 ||
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l57c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ||
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l62c32 ||
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l64c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ||
WILL_FIRE_RL_xmas_fsm_action_l66c32 ;
// submodule rule30
assign rule30$start_a = a ;
assign rule30$EN_start = CAN_FIRE_RL_compute ;
assign rule30$EN_getResult = CAN_FIRE_RL_get_result ;
// submodule uart_baudGen_rBaudCounter
assign uart_baudGen_rBaudCounter$DATA_A = 16'd1 ;
assign uart_baudGen_rBaudCounter$DATA_B = 16'h0 ;
assign uart_baudGen_rBaudCounter$DATA_C = 16'h0 ;
assign uart_baudGen_rBaudCounter$DATA_F = 16'd0 ;
assign uart_baudGen_rBaudCounter$ADDA =
uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign uart_baudGen_rBaudCounter$ADDB = 1'b0 ;
assign uart_baudGen_rBaudCounter$SETC = 1'b0 ;
assign uart_baudGen_rBaudCounter$SETF =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// submodule uart_baudGen_rBaudTickCounter
assign uart_baudGen_rBaudTickCounter$DATA_A = 3'd1 ;
assign uart_baudGen_rBaudTickCounter$DATA_B = 3'h0 ;
assign uart_baudGen_rBaudTickCounter$DATA_C = 3'h0 ;
assign uart_baudGen_rBaudTickCounter$DATA_F = 3'h0 ;
assign uart_baudGen_rBaudTickCounter$ADDA =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
assign uart_baudGen_rBaudTickCounter$ADDB = 1'b0 ;
assign uart_baudGen_rBaudTickCounter$SETC = 1'b0 ;
assign uart_baudGen_rBaudTickCounter$SETF = 1'b0 ;
// submodule uart_fifoRecv
assign uart_fifoRecv$D_IN =
{ uart_vrRecvBuffer_7,
uart_vrRecvBuffer_6,
uart_vrRecvBuffer_5,
uart_vrRecvBuffer_4,
uart_vrRecvBuffer_3,
uart_vrRecvBuffer_2,
uart_vrRecvBuffer_1,
uart_vrRecvBuffer_0 } ;
assign uart_fifoRecv$ENQ = CAN_FIRE_RL_uart_receive_stop_last_bit ;
assign uart_fifoRecv$DEQ = uart_fifoRecv$EMPTY_N ;
assign uart_fifoRecv$CLR = 1'b0 ;
// submodule uart_fifoXmit
always@(WILL_FIRE_RL_get_result or
rule30$getResult or
MUX_uart_fifoXmit$enq_1__SEL_2 or
MUX_uart_fifoXmit$enq_1__SEL_3 or
WILL_FIRE_RL_xmas_fsm_action_l64c32 or
WILL_FIRE_RL_xmas_fsm_action_l53c32 or
WILL_FIRE_RL_xmas_fsm_action_l54c32 or
WILL_FIRE_RL_xmas_fsm_action_l55c32 or
WILL_FIRE_RL_xmas_fsm_action_l42c32 or
WILL_FIRE_RL_xmas_fsm_action_l57c32 or
WILL_FIRE_RL_xmas_fsm_action_l48c32 or
MUX_uart_fifoXmit$enq_1__SEL_11 or
WILL_FIRE_RL_xmas_fsm_action_l43c32 or
WILL_FIRE_RL_xmas_fsm_action_l49c32 or
WILL_FIRE_RL_xmas_fsm_action_l62c32 or
MUX_uart_fifoXmit$enq_1__SEL_15 or
MUX_uart_fifoXmit$enq_1__SEL_16 or
MUX_uart_fifoXmit$enq_1__SEL_17 or
WILL_FIRE_RL_xmas_fsm_action_l46c32)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_get_result: uart_fifoXmit$D_IN = rule30$getResult;
MUX_uart_fifoXmit$enq_1__SEL_2: uart_fifoXmit$D_IN = 8'h09;
MUX_uart_fifoXmit$enq_1__SEL_3: uart_fifoXmit$D_IN = 8'h20;
WILL_FIRE_RL_xmas_fsm_action_l64c32: uart_fifoXmit$D_IN = 8'h21;
WILL_FIRE_RL_xmas_fsm_action_l53c32: uart_fifoXmit$D_IN = 8'h27;
WILL_FIRE_RL_xmas_fsm_action_l54c32: uart_fifoXmit$D_IN = 8'h32;
WILL_FIRE_RL_xmas_fsm_action_l55c32: uart_fifoXmit$D_IN = 8'h34;
WILL_FIRE_RL_xmas_fsm_action_l42c32: uart_fifoXmit$D_IN = 8'h4D;
WILL_FIRE_RL_xmas_fsm_action_l57c32: uart_fifoXmit$D_IN = 8'h53;
WILL_FIRE_RL_xmas_fsm_action_l48c32: uart_fifoXmit$D_IN = 8'h58;
MUX_uart_fifoXmit$enq_1__SEL_11: uart_fifoXmit$D_IN = 8'h61;
WILL_FIRE_RL_xmas_fsm_action_l43c32: uart_fifoXmit$D_IN = 8'h65;
WILL_FIRE_RL_xmas_fsm_action_l49c32: uart_fifoXmit$D_IN = 8'h6D;
WILL_FIRE_RL_xmas_fsm_action_l62c32: uart_fifoXmit$D_IN = 8'h6F;
MUX_uart_fifoXmit$enq_1__SEL_15: uart_fifoXmit$D_IN = 8'h72;
MUX_uart_fifoXmit$enq_1__SEL_16: uart_fifoXmit$D_IN = 8'h73;
MUX_uart_fifoXmit$enq_1__SEL_17: uart_fifoXmit$D_IN = 8'h74;
WILL_FIRE_RL_xmas_fsm_action_l46c32: uart_fifoXmit$D_IN = 8'h79;
default: uart_fifoXmit$D_IN = 8'b10101010 /* unspecified value */ ;
endcase
end
assign uart_fifoXmit$ENQ =
WILL_FIRE_RL_get_result || WILL_FIRE_RL_xmas_fsm_action_l66c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ||
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ||
WILL_FIRE_RL_xmas_fsm_action_l64c32 ||
WILL_FIRE_RL_xmas_fsm_action_l53c32 ||
WILL_FIRE_RL_xmas_fsm_action_l54c32 ||
WILL_FIRE_RL_xmas_fsm_action_l55c32 ||
WILL_FIRE_RL_xmas_fsm_action_l42c32 ||
WILL_FIRE_RL_xmas_fsm_action_l57c32 ||
WILL_FIRE_RL_xmas_fsm_action_l48c32 ||
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ||
WILL_FIRE_RL_xmas_fsm_action_l43c32 ||
WILL_FIRE_RL_xmas_fsm_action_l49c32 ||
WILL_FIRE_RL_xmas_fsm_action_l62c32 ||
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ||
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ||
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ||
WILL_FIRE_RL_xmas_fsm_action_l46c32 ;
assign uart_fifoXmit$DEQ = CAN_FIRE_RL_uart_transmit_buffer_load ;
assign uart_fifoXmit$CLR = 1'b0 ;
// remaining internal signals
assign _dor2uart_pwXmitCellCountReset$EN_wset =
WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit ||
WILL_FIRE_RL_uart_transmit_send_parity_bit ||
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ||
WILL_FIRE_RL_uart_transmit_send_start_bit ;
assign uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 =
uart_baudGen_rBaudCounter$Q_OUT + 16'd1 < 16'd27 ;
assign x__h2985 = uart_rRecvCellCount + 4'd1 ;
assign x__h4689 = uart_rRecvBitCount + 4'd1 ;
assign x__h6445 = uart_rXmitCellCount + 4'd1 ;
assign x__h6471 = uart_rXmitBitCount + 4'd1 ;
assign xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302 =
(xmas_fsm_state_mkFSMstate == 5'd0 ||
xmas_fsm_state_mkFSMstate == 5'd25 ||
xmas_fsm_state_mkFSMstate == 5'd27) &&
(!xmas_fsm_start_reg_1 || xmas_fsm_state_fired) ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
a <= `BSV_ASSIGNMENT_DELAY 8'b0;
op_mode <= `BSV_ASSIGNMENT_DELAY 1'd0;
transmit_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
uart_rRecvData <= `BSV_ASSIGNMENT_DELAY 1'd1;
xmas_fsm_start_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
xmas_fsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
xmas_fsm_state_fired <= `BSV_ASSIGNMENT_DELAY 1'd0;
xmas_fsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY 5'd0;
end
else
begin
if (a$EN) a <= `BSV_ASSIGNMENT_DELAY a$D_IN;
if (op_mode$EN) op_mode <= `BSV_ASSIGNMENT_DELAY op_mode$D_IN;
if (transmit_state$EN)
transmit_state <= `BSV_ASSIGNMENT_DELAY transmit_state$D_IN;
if (uart_rRecvData$EN)
uart_rRecvData <= `BSV_ASSIGNMENT_DELAY uart_rRecvData$D_IN;
if (xmas_fsm_start_reg$EN)
xmas_fsm_start_reg <= `BSV_ASSIGNMENT_DELAY xmas_fsm_start_reg$D_IN;
if (xmas_fsm_start_reg_1$EN)
xmas_fsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY
xmas_fsm_start_reg_1$D_IN;
if (xmas_fsm_state_fired$EN)
xmas_fsm_state_fired <= `BSV_ASSIGNMENT_DELAY
xmas_fsm_state_fired$D_IN;
if (xmas_fsm_state_mkFSMstate$EN)
xmas_fsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY
xmas_fsm_state_mkFSMstate$D_IN;
end
if (uart_vrRecvBuffer_0$EN)
uart_vrRecvBuffer_0 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_0$D_IN;
if (uart_vrRecvBuffer_1$EN)
uart_vrRecvBuffer_1 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_1$D_IN;
if (uart_vrRecvBuffer_2$EN)
uart_vrRecvBuffer_2 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_2$D_IN;
if (uart_vrRecvBuffer_3$EN)
uart_vrRecvBuffer_3 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_3$D_IN;
if (uart_vrRecvBuffer_4$EN)
uart_vrRecvBuffer_4 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_4$D_IN;
if (uart_vrRecvBuffer_5$EN)
uart_vrRecvBuffer_5 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_5$D_IN;
if (uart_vrRecvBuffer_6$EN)
uart_vrRecvBuffer_6 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_6$D_IN;
if (uart_vrRecvBuffer_7$EN)
uart_vrRecvBuffer_7 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_7$D_IN;
if (uart_vrXmitBuffer_0$EN)
uart_vrXmitBuffer_0 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_0$D_IN;
if (uart_vrXmitBuffer_1$EN)
uart_vrXmitBuffer_1 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_1$D_IN;
if (uart_vrXmitBuffer_2$EN)
uart_vrXmitBuffer_2 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_2$D_IN;
if (uart_vrXmitBuffer_3$EN)
uart_vrXmitBuffer_3 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_3$D_IN;
if (uart_vrXmitBuffer_4$EN)
uart_vrXmitBuffer_4 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_4$D_IN;
if (uart_vrXmitBuffer_5$EN)
uart_vrXmitBuffer_5 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_5$D_IN;
if (uart_vrXmitBuffer_6$EN)
uart_vrXmitBuffer_6 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_6$D_IN;
if (uart_vrXmitBuffer_7$EN)
uart_vrXmitBuffer_7 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_7$D_IN;
end
always@(posedge CLK or `BSV_RESET_EDGE RST_N)
if (RST_N == `BSV_RESET_VALUE)
begin
uart_rRecvBitCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
uart_rRecvCellCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
uart_rRecvState <= `BSV_ASSIGNMENT_DELAY 3'd0;
uart_rXmitBitCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
uart_rXmitCellCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
uart_rXmitDataOut <= `BSV_ASSIGNMENT_DELAY 1'd1;
uart_rXmitState <= `BSV_ASSIGNMENT_DELAY 3'd0;
end
else
begin
if (uart_rRecvBitCount$EN)
uart_rRecvBitCount <= `BSV_ASSIGNMENT_DELAY uart_rRecvBitCount$D_IN;
if (uart_rRecvCellCount$EN)
uart_rRecvCellCount <= `BSV_ASSIGNMENT_DELAY uart_rRecvCellCount$D_IN;
if (uart_rRecvState$EN)
uart_rRecvState <= `BSV_ASSIGNMENT_DELAY uart_rRecvState$D_IN;
if (uart_rXmitBitCount$EN)
uart_rXmitBitCount <= `BSV_ASSIGNMENT_DELAY uart_rXmitBitCount$D_IN;
if (uart_rXmitCellCount$EN)
uart_rXmitCellCount <= `BSV_ASSIGNMENT_DELAY uart_rXmitCellCount$D_IN;
if (uart_rXmitDataOut$EN)
uart_rXmitDataOut <= `BSV_ASSIGNMENT_DELAY uart_rXmitDataOut$D_IN;
if (uart_rXmitState$EN)
uart_rXmitState <= `BSV_ASSIGNMENT_DELAY uart_rXmitState$D_IN;
end
// handling of system tasks
endmodule // mkRule30Driver
//
// Generated by Bluespec Compiler, version 2024.01-1-g4d953407 (build 4d953407)
//
// On Thu Apr 18 23:03:51 EDT 2024
//
//
// Ports:
// Name I/O size props
// RDY_start O 1
// getResult O 8 reg
// RDY_getResult O 1
// CLK I 1 clock
// RST_N I 1 reset
// start_a I 8
// EN_start I 1
// EN_getResult I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkRule30(CLK,
RST_N,
start_a,
EN_start,
RDY_start,
EN_getResult,
getResult,
RDY_getResult);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
// mkRule30
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
// N -bit counter with load, set and 2 increment
module Counter(CLK,
RST,
Q_OUT,
DATA_A, ADDA,
DATA_B, ADDB,
DATA_C, SETC,
DATA_F, SETF);
parameter width = 1;
parameter init = 0;
input CLK;
input RST;
input [width - 1 : 0] DATA_A;
input ADDA;
input [width - 1 : 0] DATA_B;
input ADDB;
input [width - 1 : 0] DATA_C;
input SETC;
input [width - 1 : 0] DATA_F;
input SETF;
output [width - 1 : 0] Q_OUT;
reg [width - 1 : 0] q_state ;
assign Q_OUT = q_state ;
always@(posedge CLK `BSV_ARESET_EDGE_META) begin
if (RST == `BSV_RESET_VALUE)
q_state <= `BSV_ASSIGNMENT_DELAY init;
else
begin
if ( SETF )
q_state <= `BSV_ASSIGNMENT_DELAY DATA_F ;
else
q_state <= `BSV_ASSIGNMENT_DELAY (SETC ? DATA_C : q_state ) + (ADDA ? DATA_A : {width {1'b0}}) + (ADDB ? DATA_B : {width {1'b0}} ) ;
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK)
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial begin
q_state = {((width + 1)/2){2'b10}} ;
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
`ifdef BSV_RESET_FIFO_HEAD
`define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_HEAD
`endif
`ifdef BSV_RESET_FIFO_ARRAY
`define BSV_ARESET_EDGE_ARRAY `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_ARRAY
`endif
// Sized fifo. Model has output register which improves timing
module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR);
parameter p1width = 1; // data width
parameter p2depth = 3;
parameter p3cntr_width = 1; // log(p2depth-1)
// The -1 is allowed since this model has a fast output register
parameter guarded = 1'b1;
localparam p2depth2 = (p2depth >= 2) ? (p2depth -2) : 0 ;
input CLK;
input RST;
input CLR;
input [p1width - 1 : 0] D_IN;
input ENQ;
input DEQ;
output FULL_N;
output EMPTY_N;
output [p1width - 1 : 0] D_OUT;
reg not_ring_full;
reg ring_empty;
reg [p3cntr_width-1 : 0] head;
wire [p3cntr_width-1 : 0] next_head;
reg [p3cntr_width-1 : 0] tail;
wire [p3cntr_width-1 : 0] next_tail;
// if the depth is too small, don't create an ill-sized array;
// instead, make a 1-sized array and let the initial block report an error
reg [p1width - 1 : 0] arr[0: p2depth2];
reg [p1width - 1 : 0] D_OUT;
reg hasodata;
wire [p3cntr_width-1:0] depthLess2 = p2depth2[p3cntr_width-1:0] ;
wire [p3cntr_width-1 : 0] incr_tail;
wire [p3cntr_width-1 : 0] incr_head;
assign incr_tail = tail + 1'b1 ;
assign incr_head = head + 1'b1 ;
assign next_head = (head == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_head ;
assign next_tail = (tail == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_tail ;
assign EMPTY_N = hasodata;
assign FULL_N = not_ring_full;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin : initial_block
integer i;
D_OUT = {((p1width + 1)/2){2'b10}} ;
ring_empty = 1'b1;
not_ring_full = 1'b1;
hasodata = 1'b0;
head = {p3cntr_width {1'b0}} ;
tail = {p3cntr_width {1'b0}} ;
for (i = 0; i <= p2depth2; i = i + 1)
begin
arr[i] = D_OUT ;
end
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
always @(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (RST == `BSV_RESET_VALUE)
else
begin
casez ({CLR, DEQ, ENQ, hasodata, ring_empty})
// Clear operation
5'b1????: begin
head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
// -----------------------
// DEQ && ENQ case -- change head and tail if added to ring
5'b011?0: begin
tail <= `BSV_ASSIGNMENT_DELAY next_tail;
head <= `BSV_ASSIGNMENT_DELAY next_head;
end
// -----------------------
// DEQ only and NO data is in ring
5'b010?1: begin
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
// DEQ only and data is in ring (move the head pointer)
5'b010?0: begin
head <= `BSV_ASSIGNMENT_DELAY next_head;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
ring_empty <= `BSV_ASSIGNMENT_DELAY next_head == tail ;
end
// -----------------------
// ENQ only when empty
5'b0010?: begin
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b1;
end
// ENQ only when not empty
5'b0011?: begin
if ( not_ring_full ) // Drop this test to save redundant test
// but be warnned that with test fifo overflow causes loss of new data
// while without test fifo drops all but head entry! (pointer overflow)
begin
tail <= `BSV_ASSIGNMENT_DELAY next_tail;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b0;
not_ring_full <= `BSV_ASSIGNMENT_DELAY ! (next_tail == head) ;
end
end
endcase
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// Update the fast data out register
always @(posedge CLK `BSV_ARESET_EDGE_HEAD)
begin
`ifdef BSV_RESET_FIFO_HEAD
if (RST == `BSV_RESET_VALUE)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
end // if (RST == `BSV_RESET_VALUE)
else
`endif
begin
casez ({CLR, DEQ, ENQ, hasodata, ring_empty})
// DEQ && ENQ cases
5'b011?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end
5'b011?1: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end
// DEQ only and data is in ring
5'b010?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end
// ENQ only when empty
5'b0010?: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end
endcase
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// Update the memory array reset is OFF
always @(posedge CLK `BSV_ARESET_EDGE_ARRAY)
begin: array
`ifdef BSV_RESET_FIFO_ARRAY
if (RST == `BSV_RESET_VALUE)
begin: rst_array
integer i;
for (i = 0; i <= p2depth2 && p2depth > 2; i = i + 1)
begin
arr[i] <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
end
end // if (RST == `BSV_RESET_VALUE)
else
`endif
begin
if (!CLR && ENQ && ((DEQ && !ring_empty) || (!DEQ && hasodata && not_ring_full)))
begin
arr[tail] <= `BSV_ASSIGNMENT_DELAY D_IN;
end
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if (RST == ! `BSV_RESET_VALUE)
begin
if ( ! EMPTY_N && DEQ )
begin
deqerror = 1 ;
$display( "Warning: SizedFIFO: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && (!DEQ || guarded) )
begin
enqerror = 1 ;
$display( "Warning: SizedFIFO: %m -- Enqueuing to a full fifo" ) ;
end
end
end // block: error_checks
// synopsys translate_on
// synopsys translate_off
// Some assertions about parameter values
initial
begin : parameter_assertions
integer ok ;
ok = 1 ;
if ( p2depth <= 1)
begin
ok = 0;
$display ( "Warning SizedFIFO: %m -- depth parameter increased from %0d to 2", p2depth);
end
if ( p3cntr_width <= 0 )
begin
ok = 0;
$display ( "ERROR SizedFIFO: %m -- width parameter must be greater than 0" ) ;
end
if ( ok == 0 ) $finish ;
end // initial begin
// synopsys translate_on
endmodule
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
`ifdef BSV_RESET_FIFO_HEAD
`define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_HEAD
`endif
// Depth 1 FIFO
module FIFO1(CLK,
RST,
D_IN,
ENQ,
FULL_N,
D_OUT,
DEQ,
EMPTY_N,
CLR
);
parameter width = 1;
parameter guarded = 1'b1;
input CLK;
input RST;
input [width - 1 : 0] D_IN;
input ENQ;
input DEQ;
input CLR ;
output FULL_N;
output [width - 1 : 0] D_OUT;
output EMPTY_N;
reg [width - 1 : 0] D_OUT;
reg empty_reg ;
assign EMPTY_N = empty_reg ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
D_OUT = {((width + 1)/2) {2'b10}} ;
empty_reg = 1'b0 ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
assign FULL_N = !empty_reg;
always@(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (RST == `BSV_RESET_VALUE)
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (CLR)
else if (ENQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // if (ENQ)
else if (DEQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (DEQ)
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
always@(posedge CLK `BSV_ARESET_EDGE_HEAD)
begin
`ifdef BSV_RESET_FIFO_HEAD
if (RST == `BSV_RESET_VALUE)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
end
else
`endif
begin
if (ENQ)
D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN;
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if (RST == ! `BSV_RESET_VALUE)
begin
if ( ! empty_reg && DEQ )
begin
deqerror = 1 ;
$display( "Warning: FIFO1: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && (!DEQ || guarded) )
begin
enqerror = 1 ;
$display( "Warning: FIFO1: %m -- Enqueuing to a full fifo" ) ;
end
end // if (RST == ! `BSV_RESET_VALUE)
end
// synopsys translate_on
endmodule
|
module mkRule30(CLK,
RST_N,
start_a,
EN_start,
RDY_start,
EN_getResult,
getResult,
RDY_getResult);
input CLK;
input RST_N;
// action method start
input [7 : 0] start_a;
input EN_start;
output RDY_start;
// actionvalue method getResult
input EN_getResult;
output [7 : 0] getResult;
output RDY_getResult;
// signals for module outputs
wire [7 : 0] getResult;
wire RDY_getResult, RDY_start;
// register busy_flag
reg busy_flag;
wire busy_flag$D_IN, busy_flag$EN;
// register r30
reg [7 : 0] r30;
wire [7 : 0] r30$D_IN;
wire r30$EN;
// register step_complete
reg step_complete;
wire step_complete$D_IN, step_complete$EN;
// register x
reg [55 : 0] x;
wire [55 : 0] x$D_IN;
wire x$EN;
// rule scheduling signals
wire CAN_FIRE_RL_stepper,
CAN_FIRE_getResult,
CAN_FIRE_start,
WILL_FIRE_RL_stepper,
WILL_FIRE_getResult,
WILL_FIRE_start;
// inputs to muxes for submodule ports
wire [55 : 0] MUX_x$write_1__VAL_1, MUX_x$write_1__VAL_2;
// remaining internal signals
wire [51 : 0] r30_BIT_x_BITS_52_TO_50_6_7_CONCAT_r30_BIT_x_B_ETC___d146;
wire [47 : 0] r30_BIT_x_BITS_48_TO_46_4_5_CONCAT_r30_BIT_x_B_ETC___d144;
wire [43 : 0] r30_BIT_x_BITS_44_TO_42_2_3_CONCAT_r30_BIT_x_B_ETC___d142;
wire [39 : 0] r30_BIT_x_BITS_40_TO_38_0_1_CONCAT_r30_BIT_x_B_ETC___d140;
wire [35 : 0] r30_BIT_x_BITS_36_TO_34_8_9_CONCAT_r30_BIT_x_B_ETC___d138;
wire [31 : 0] r30_BIT_x_BITS_32_TO_30_6_7_CONCAT_r30_BIT_x_B_ETC___d136;
wire [27 : 0] r30_BIT_x_BITS_28_TO_26_4_5_CONCAT_r30_BIT_x_B_ETC___d134;
wire [23 : 0] r30_BIT_x_BITS_24_TO_22_2_3_CONCAT_r30_BIT_x_B_ETC___d132;
wire [19 : 0] r30_BIT_x_BITS_20_TO_18_0_1_CONCAT_r30_BIT_x_B_ETC___d130;
wire [15 : 0] r30_BIT_x_BITS_16_TO_14_8_9_CONCAT_r30_BIT_x_B_ETC___d128;
wire [11 : 0] r30_BIT_x_BITS_12_TO_10_6_7_CONCAT_r30_BIT_x_B_ETC___d126;
wire [7 : 0] r30_BIT_x_BITS_8_TO_6_04_05_CONCAT_r30_BIT_x_B_ETC___d124;
wire [3 : 0] r30_BIT_x_BITS_4_TO_2_12_13_CONCAT_r30_BIT_x_B_ETC___d122;
wire [2 : 0] b0__h167, b55__h222;
// action method start
assign RDY_start = !busy_flag ;
assign CAN_FIRE_start = !busy_flag ;
assign WILL_FIRE_start = EN_start ;
// actionvalue method getResult
assign getResult = x[31:24] ;
assign RDY_getResult = busy_flag && step_complete ;
assign CAN_FIRE_getResult = busy_flag && step_complete ;
assign WILL_FIRE_getResult = EN_getResult ;
// rule RL_stepper
assign CAN_FIRE_RL_stepper = busy_flag && !step_complete ;
assign WILL_FIRE_RL_stepper = CAN_FIRE_RL_stepper ;
// inputs to muxes for submodule ports
assign MUX_x$write_1__VAL_1 =
{ r30[b55__h222],
r30[x[55:53]],
r30[x[54:52]],
r30[x[53:51]],
r30_BIT_x_BITS_52_TO_50_6_7_CONCAT_r30_BIT_x_B_ETC___d146 } ;
assign MUX_x$write_1__VAL_2 = { x[55:32], start_a, x[23:0] } ;
// register busy_flag
assign busy_flag$D_IN = !EN_getResult ;
assign busy_flag$EN = EN_getResult || EN_start ;
// register r30
assign r30$D_IN = 8'h0 ;
assign r30$EN = 1'b0 ;
// register step_complete
assign step_complete$D_IN = !EN_start ;
assign step_complete$EN = EN_start || WILL_FIRE_RL_stepper ;
// register x
assign x$D_IN =
WILL_FIRE_RL_stepper ?
MUX_x$write_1__VAL_1 :
MUX_x$write_1__VAL_2 ;
assign x$EN = WILL_FIRE_RL_stepper || EN_start ;
// remaining internal signals
assign b0__h167 = { x[1:0], 1'b0 } ;
assign b55__h222 = { 1'b0, x[55:54] } ;
assign r30_BIT_x_BITS_12_TO_10_6_7_CONCAT_r30_BIT_x_B_ETC___d126 =
{ r30[x[12:10]],
r30[x[11:9]],
r30[x[10:8]],
r30[x[9:7]],
r30_BIT_x_BITS_8_TO_6_04_05_CONCAT_r30_BIT_x_B_ETC___d124 } ;
assign r30_BIT_x_BITS_16_TO_14_8_9_CONCAT_r30_BIT_x_B_ETC___d128 =
{ r30[x[16:14]],
r30[x[15:13]],
r30[x[14:12]],
r30[x[13:11]],
r30_BIT_x_BITS_12_TO_10_6_7_CONCAT_r30_BIT_x_B_ETC___d126 } ;
assign r30_BIT_x_BITS_20_TO_18_0_1_CONCAT_r30_BIT_x_B_ETC___d130 =
{ r30[x[20:18]],
r30[x[19:17]],
r30[x[18:16]],
r30[x[17:15]],
r30_BIT_x_BITS_16_TO_14_8_9_CONCAT_r30_BIT_x_B_ETC___d128 } ;
assign r30_BIT_x_BITS_24_TO_22_2_3_CONCAT_r30_BIT_x_B_ETC___d132 =
{ r30[x[24:22]],
r30[x[23:21]],
r30[x[22:20]],
r30[x[21:19]],
r30_BIT_x_BITS_20_TO_18_0_1_CONCAT_r30_BIT_x_B_ETC___d130 } ;
assign r30_BIT_x_BITS_28_TO_26_4_5_CONCAT_r30_BIT_x_B_ETC___d134 =
{ r30[x[28:26]],
r30[x[27:25]],
r30[x[26:24]],
r30[x[25:23]],
r30_BIT_x_BITS_24_TO_22_2_3_CONCAT_r30_BIT_x_B_ETC___d132 } ;
assign r30_BIT_x_BITS_32_TO_30_6_7_CONCAT_r30_BIT_x_B_ETC___d136 =
{ r30[x[32:30]],
r30[x[31:29]],
r30[x[30:28]],
r30[x[29:27]],
r30_BIT_x_BITS_28_TO_26_4_5_CONCAT_r30_BIT_x_B_ETC___d134 } ;
assign r30_BIT_x_BITS_36_TO_34_8_9_CONCAT_r30_BIT_x_B_ETC___d138 =
{ r30[x[36:34]],
r30[x[35:33]],
r30[x[34:32]],
r30[x[33:31]],
r30_BIT_x_BITS_32_TO_30_6_7_CONCAT_r30_BIT_x_B_ETC___d136 } ;
assign r30_BIT_x_BITS_40_TO_38_0_1_CONCAT_r30_BIT_x_B_ETC___d140 =
{ r30[x[40:38]],
r30[x[39:37]],
r30[x[38:36]],
r30[x[37:35]],
r30_BIT_x_BITS_36_TO_34_8_9_CONCAT_r30_BIT_x_B_ETC___d138 } ;
assign r30_BIT_x_BITS_44_TO_42_2_3_CONCAT_r30_BIT_x_B_ETC___d142 =
{ r30[x[44:42]],
r30[x[43:41]],
r30[x[42:40]],
r30[x[41:39]],
r30_BIT_x_BITS_40_TO_38_0_1_CONCAT_r30_BIT_x_B_ETC___d140 } ;
assign r30_BIT_x_BITS_48_TO_46_4_5_CONCAT_r30_BIT_x_B_ETC___d144 =
{ r30[x[48:46]],
r30[x[47:45]],
r30[x[46:44]],
r30[x[45:43]],
r30_BIT_x_BITS_44_TO_42_2_3_CONCAT_r30_BIT_x_B_ETC___d142 } ;
assign r30_BIT_x_BITS_4_TO_2_12_13_CONCAT_r30_BIT_x_B_ETC___d122 =
{ r30[x[4:2]], r30[x[3:1]], r30[x[2:0]], r30[b0__h167] } ;
assign r30_BIT_x_BITS_52_TO_50_6_7_CONCAT_r30_BIT_x_B_ETC___d146 =
{ r30[x[52:50]],
r30[x[51:49]],
r30[x[50:48]],
r30[x[49:47]],
r30_BIT_x_BITS_48_TO_46_4_5_CONCAT_r30_BIT_x_B_ETC___d144 } ;
assign r30_BIT_x_BITS_8_TO_6_04_05_CONCAT_r30_BIT_x_B_ETC___d124 =
{ r30[x[8:6]],
r30[x[7:5]],
r30[x[6:4]],
r30[x[5:3]],
r30_BIT_x_BITS_4_TO_2_12_13_CONCAT_r30_BIT_x_B_ETC___d122 } ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
busy_flag <= `BSV_ASSIGNMENT_DELAY 1'd0;
r30 <= `BSV_ASSIGNMENT_DELAY 8'd30;
step_complete <= `BSV_ASSIGNMENT_DELAY 1'd0;
x <= `BSV_ASSIGNMENT_DELAY 56'd0;
end
else
begin
if (busy_flag$EN) busy_flag <= `BSV_ASSIGNMENT_DELAY busy_flag$D_IN;
if (r30$EN) r30 <= `BSV_ASSIGNMENT_DELAY r30$D_IN;
if (step_complete$EN)
step_complete <= `BSV_ASSIGNMENT_DELAY step_complete$D_IN;
if (x$EN) x <= `BSV_ASSIGNMENT_DELAY x$D_IN;
end
end
endmodule
|
tt06-finale_0054
|
tt06-finale
|
andrewtron3000-tt06-verilog-template
|
task_mkRule30Driver
|
tt_um_andrewtron3000
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 andrewtron3000
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_andrewtron3000 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// Held in reset while ena is not set
wire reset_n;
assign reset_n = rst_n & ena;
assign uio_oe = 8'b00000000; // All bidirectional outputs disabled
assign uio_out = 0;
// Assign output
assign uo_out[0] = 0;
assign uo_out[1] = 0;
assign uo_out[2] = 0;
assign uo_out[3] = 0;
assign uo_out[4] = driver_sout; // uo_out[4] is UART TX
assign uo_out[5] = 0;
assign uo_out[6] = 0;
assign uo_out[7] = 0;
// ports of submodule driver
wire driver_sin, driver_sout;
assign driver_sin = 0;
wire startup_input_ready;
wire startup_input_enable;
wire operation_mode_ready;
wire operation_mode_enable;
// submodule rule_30_driver
mkRule30Driver rule_30_driver(.CLK(clk),
.RST_N(reset_n),
.operation_mode_arg(uio_in),
.EN_operation_mode(operation_mode_enable),
.RDY_operation_mode(operation_mode_ready),
.startup_value_v(ui_in),
.EN_startup_value(startup_input_enable),
.RDY_startup_value(startup_input_ready),
.txrx_SIN(driver_sin),
.txrx_SOUT(driver_sout));
assign startup_input_enable = startup_input_ready;
assign operation_mode_enable = operation_mode_ready;
endmodule
//
// Generated by Bluespec Compiler, version 2024.01-1-g4d953407 (build 4d953407)
//
// On Thu Apr 18 23:03:53 EDT 2024
//
//
// Ports:
// Name I/O size props
// RDY_operation_mode O 1
// RDY_startup_value O 1
// txrx_SOUT O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// operation_mode_arg I 8
// startup_value_v I 8
// txrx_SIN I 1 reg
// EN_operation_mode I 1
// EN_startup_value I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkRule30Driver(CLK,
RST_N,
operation_mode_arg,
EN_operation_mode,
RDY_operation_mode,
startup_value_v,
EN_startup_value,
RDY_startup_value,
txrx_SIN,
txrx_SOUT);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
// mkRule30Driver
//
// Generated by Bluespec Compiler, version 2024.01-1-g4d953407 (build 4d953407)
//
// On Thu Apr 18 23:03:51 EDT 2024
//
//
// Ports:
// Name I/O size props
// RDY_start O 1
// getResult O 8 reg
// RDY_getResult O 1
// CLK I 1 clock
// RST_N I 1 reset
// start_a I 8
// EN_start I 1
// EN_getResult I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkRule30(CLK,
RST_N,
start_a,
EN_start,
RDY_start,
EN_getResult,
getResult,
RDY_getResult);
input CLK;
input RST_N;
// action method start
input [7 : 0] start_a;
input EN_start;
output RDY_start;
// actionvalue method getResult
input EN_getResult;
output [7 : 0] getResult;
output RDY_getResult;
// signals for module outputs
wire [7 : 0] getResult;
wire RDY_getResult, RDY_start;
// register busy_flag
reg busy_flag;
wire busy_flag$D_IN, busy_flag$EN;
// register r30
reg [7 : 0] r30;
wire [7 : 0] r30$D_IN;
wire r30$EN;
// register step_complete
reg step_complete;
wire step_complete$D_IN, step_complete$EN;
// register x
reg [55 : 0] x;
wire [55 : 0] x$D_IN;
wire x$EN;
// rule scheduling signals
wire CAN_FIRE_RL_stepper,
CAN_FIRE_getResult,
CAN_FIRE_start,
WILL_FIRE_RL_stepper,
WILL_FIRE_getResult,
WILL_FIRE_start;
// inputs to muxes for submodule ports
wire [55 : 0] MUX_x$write_1__VAL_1, MUX_x$write_1__VAL_2;
// remaining internal signals
wire [51 : 0] r30_BIT_x_BITS_52_TO_50_6_7_CONCAT_r30_BIT_x_B_ETC___d146;
wire [47 : 0] r30_BIT_x_BITS_48_TO_46_4_5_CONCAT_r30_BIT_x_B_ETC___d144;
wire [43 : 0] r30_BIT_x_BITS_44_TO_42_2_3_CONCAT_r30_BIT_x_B_ETC___d142;
wire [39 : 0] r30_BIT_x_BITS_40_TO_38_0_1_CONCAT_r30_BIT_x_B_ETC___d140;
wire [35 : 0] r30_BIT_x_BITS_36_TO_34_8_9_CONCAT_r30_BIT_x_B_ETC___d138;
wire [31 : 0] r30_BIT_x_BITS_32_TO_30_6_7_CONCAT_r30_BIT_x_B_ETC___d136;
wire [27 : 0] r30_BIT_x_BITS_28_TO_26_4_5_CONCAT_r30_BIT_x_B_ETC___d134;
wire [23 : 0] r30_BIT_x_BITS_24_TO_22_2_3_CONCAT_r30_BIT_x_B_ETC___d132;
wire [19 : 0] r30_BIT_x_BITS_20_TO_18_0_1_CONCAT_r30_BIT_x_B_ETC___d130;
wire [15 : 0] r30_BIT_x_BITS_16_TO_14_8_9_CONCAT_r30_BIT_x_B_ETC___d128;
wire [11 : 0] r30_BIT_x_BITS_12_TO_10_6_7_CONCAT_r30_BIT_x_B_ETC___d126;
wire [7 : 0] r30_BIT_x_BITS_8_TO_6_04_05_CONCAT_r30_BIT_x_B_ETC___d124;
wire [3 : 0] r30_BIT_x_BITS_4_TO_2_12_13_CONCAT_r30_BIT_x_B_ETC___d122;
wire [2 : 0] b0__h167, b55__h222;
// action method start
assign RDY_start = !busy_flag ;
assign CAN_FIRE_start = !busy_flag ;
assign WILL_FIRE_start = EN_start ;
// actionvalue method getResult
assign getResult = x[31:24] ;
assign RDY_getResult = busy_flag && step_complete ;
assign CAN_FIRE_getResult = busy_flag && step_complete ;
assign WILL_FIRE_getResult = EN_getResult ;
// rule RL_stepper
assign CAN_FIRE_RL_stepper = busy_flag && !step_complete ;
assign WILL_FIRE_RL_stepper = CAN_FIRE_RL_stepper ;
// inputs to muxes for submodule ports
assign MUX_x$write_1__VAL_1 =
{ r30[b55__h222],
r30[x[55:53]],
r30[x[54:52]],
r30[x[53:51]],
r30_BIT_x_BITS_52_TO_50_6_7_CONCAT_r30_BIT_x_B_ETC___d146 } ;
assign MUX_x$write_1__VAL_2 = { x[55:32], start_a, x[23:0] } ;
// register busy_flag
assign busy_flag$D_IN = !EN_getResult ;
assign busy_flag$EN = EN_getResult || EN_start ;
// register r30
assign r30$D_IN = 8'h0 ;
assign r30$EN = 1'b0 ;
// register step_complete
assign step_complete$D_IN = !EN_start ;
assign step_complete$EN = EN_start || WILL_FIRE_RL_stepper ;
// register x
assign x$D_IN =
WILL_FIRE_RL_stepper ?
MUX_x$write_1__VAL_1 :
MUX_x$write_1__VAL_2 ;
assign x$EN = WILL_FIRE_RL_stepper || EN_start ;
// remaining internal signals
assign b0__h167 = { x[1:0], 1'b0 } ;
assign b55__h222 = { 1'b0, x[55:54] } ;
assign r30_BIT_x_BITS_12_TO_10_6_7_CONCAT_r30_BIT_x_B_ETC___d126 =
{ r30[x[12:10]],
r30[x[11:9]],
r30[x[10:8]],
r30[x[9:7]],
r30_BIT_x_BITS_8_TO_6_04_05_CONCAT_r30_BIT_x_B_ETC___d124 } ;
assign r30_BIT_x_BITS_16_TO_14_8_9_CONCAT_r30_BIT_x_B_ETC___d128 =
{ r30[x[16:14]],
r30[x[15:13]],
r30[x[14:12]],
r30[x[13:11]],
r30_BIT_x_BITS_12_TO_10_6_7_CONCAT_r30_BIT_x_B_ETC___d126 } ;
assign r30_BIT_x_BITS_20_TO_18_0_1_CONCAT_r30_BIT_x_B_ETC___d130 =
{ r30[x[20:18]],
r30[x[19:17]],
r30[x[18:16]],
r30[x[17:15]],
r30_BIT_x_BITS_16_TO_14_8_9_CONCAT_r30_BIT_x_B_ETC___d128 } ;
assign r30_BIT_x_BITS_24_TO_22_2_3_CONCAT_r30_BIT_x_B_ETC___d132 =
{ r30[x[24:22]],
r30[x[23:21]],
r30[x[22:20]],
r30[x[21:19]],
r30_BIT_x_BITS_20_TO_18_0_1_CONCAT_r30_BIT_x_B_ETC___d130 } ;
assign r30_BIT_x_BITS_28_TO_26_4_5_CONCAT_r30_BIT_x_B_ETC___d134 =
{ r30[x[28:26]],
r30[x[27:25]],
r30[x[26:24]],
r30[x[25:23]],
r30_BIT_x_BITS_24_TO_22_2_3_CONCAT_r30_BIT_x_B_ETC___d132 } ;
assign r30_BIT_x_BITS_32_TO_30_6_7_CONCAT_r30_BIT_x_B_ETC___d136 =
{ r30[x[32:30]],
r30[x[31:29]],
r30[x[30:28]],
r30[x[29:27]],
r30_BIT_x_BITS_28_TO_26_4_5_CONCAT_r30_BIT_x_B_ETC___d134 } ;
assign r30_BIT_x_BITS_36_TO_34_8_9_CONCAT_r30_BIT_x_B_ETC___d138 =
{ r30[x[36:34]],
r30[x[35:33]],
r30[x[34:32]],
r30[x[33:31]],
r30_BIT_x_BITS_32_TO_30_6_7_CONCAT_r30_BIT_x_B_ETC___d136 } ;
assign r30_BIT_x_BITS_40_TO_38_0_1_CONCAT_r30_BIT_x_B_ETC___d140 =
{ r30[x[40:38]],
r30[x[39:37]],
r30[x[38:36]],
r30[x[37:35]],
r30_BIT_x_BITS_36_TO_34_8_9_CONCAT_r30_BIT_x_B_ETC___d138 } ;
assign r30_BIT_x_BITS_44_TO_42_2_3_CONCAT_r30_BIT_x_B_ETC___d142 =
{ r30[x[44:42]],
r30[x[43:41]],
r30[x[42:40]],
r30[x[41:39]],
r30_BIT_x_BITS_40_TO_38_0_1_CONCAT_r30_BIT_x_B_ETC___d140 } ;
assign r30_BIT_x_BITS_48_TO_46_4_5_CONCAT_r30_BIT_x_B_ETC___d144 =
{ r30[x[48:46]],
r30[x[47:45]],
r30[x[46:44]],
r30[x[45:43]],
r30_BIT_x_BITS_44_TO_42_2_3_CONCAT_r30_BIT_x_B_ETC___d142 } ;
assign r30_BIT_x_BITS_4_TO_2_12_13_CONCAT_r30_BIT_x_B_ETC___d122 =
{ r30[x[4:2]], r30[x[3:1]], r30[x[2:0]], r30[b0__h167] } ;
assign r30_BIT_x_BITS_52_TO_50_6_7_CONCAT_r30_BIT_x_B_ETC___d146 =
{ r30[x[52:50]],
r30[x[51:49]],
r30[x[50:48]],
r30[x[49:47]],
r30_BIT_x_BITS_48_TO_46_4_5_CONCAT_r30_BIT_x_B_ETC___d144 } ;
assign r30_BIT_x_BITS_8_TO_6_04_05_CONCAT_r30_BIT_x_B_ETC___d124 =
{ r30[x[8:6]],
r30[x[7:5]],
r30[x[6:4]],
r30[x[5:3]],
r30_BIT_x_BITS_4_TO_2_12_13_CONCAT_r30_BIT_x_B_ETC___d122 } ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
busy_flag <= `BSV_ASSIGNMENT_DELAY 1'd0;
r30 <= `BSV_ASSIGNMENT_DELAY 8'd30;
step_complete <= `BSV_ASSIGNMENT_DELAY 1'd0;
x <= `BSV_ASSIGNMENT_DELAY 56'd0;
end
else
begin
if (busy_flag$EN) busy_flag <= `BSV_ASSIGNMENT_DELAY busy_flag$D_IN;
if (r30$EN) r30 <= `BSV_ASSIGNMENT_DELAY r30$D_IN;
if (step_complete$EN)
step_complete <= `BSV_ASSIGNMENT_DELAY step_complete$D_IN;
if (x$EN) x <= `BSV_ASSIGNMENT_DELAY x$D_IN;
end
end
endmodule // mkRule30
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
// N -bit counter with load, set and 2 increment
module Counter(CLK,
RST,
Q_OUT,
DATA_A, ADDA,
DATA_B, ADDB,
DATA_C, SETC,
DATA_F, SETF);
parameter width = 1;
parameter init = 0;
input CLK;
input RST;
input [width - 1 : 0] DATA_A;
input ADDA;
input [width - 1 : 0] DATA_B;
input ADDB;
input [width - 1 : 0] DATA_C;
input SETC;
input [width - 1 : 0] DATA_F;
input SETF;
output [width - 1 : 0] Q_OUT;
reg [width - 1 : 0] q_state ;
assign Q_OUT = q_state ;
always@(posedge CLK `BSV_ARESET_EDGE_META) begin
if (RST == `BSV_RESET_VALUE)
q_state <= `BSV_ASSIGNMENT_DELAY init;
else
begin
if ( SETF )
q_state <= `BSV_ASSIGNMENT_DELAY DATA_F ;
else
q_state <= `BSV_ASSIGNMENT_DELAY (SETC ? DATA_C : q_state ) + (ADDA ? DATA_A : {width {1'b0}}) + (ADDB ? DATA_B : {width {1'b0}} ) ;
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK)
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial begin
q_state = {((width + 1)/2){2'b10}} ;
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
`ifdef BSV_RESET_FIFO_HEAD
`define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_HEAD
`endif
`ifdef BSV_RESET_FIFO_ARRAY
`define BSV_ARESET_EDGE_ARRAY `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_ARRAY
`endif
// Sized fifo. Model has output register which improves timing
module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR);
parameter p1width = 1; // data width
parameter p2depth = 3;
parameter p3cntr_width = 1; // log(p2depth-1)
// The -1 is allowed since this model has a fast output register
parameter guarded = 1'b1;
localparam p2depth2 = (p2depth >= 2) ? (p2depth -2) : 0 ;
input CLK;
input RST;
input CLR;
input [p1width - 1 : 0] D_IN;
input ENQ;
input DEQ;
output FULL_N;
output EMPTY_N;
output [p1width - 1 : 0] D_OUT;
reg not_ring_full;
reg ring_empty;
reg [p3cntr_width-1 : 0] head;
wire [p3cntr_width-1 : 0] next_head;
reg [p3cntr_width-1 : 0] tail;
wire [p3cntr_width-1 : 0] next_tail;
// if the depth is too small, don't create an ill-sized array;
// instead, make a 1-sized array and let the initial block report an error
reg [p1width - 1 : 0] arr[0: p2depth2];
reg [p1width - 1 : 0] D_OUT;
reg hasodata;
wire [p3cntr_width-1:0] depthLess2 = p2depth2[p3cntr_width-1:0] ;
wire [p3cntr_width-1 : 0] incr_tail;
wire [p3cntr_width-1 : 0] incr_head;
assign incr_tail = tail + 1'b1 ;
assign incr_head = head + 1'b1 ;
assign next_head = (head == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_head ;
assign next_tail = (tail == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_tail ;
assign EMPTY_N = hasodata;
assign FULL_N = not_ring_full;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin : initial_block
integer i;
D_OUT = {((p1width + 1)/2){2'b10}} ;
ring_empty = 1'b1;
not_ring_full = 1'b1;
hasodata = 1'b0;
head = {p3cntr_width {1'b0}} ;
tail = {p3cntr_width {1'b0}} ;
for (i = 0; i <= p2depth2; i = i + 1)
begin
arr[i] = D_OUT ;
end
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
always @(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (RST == `BSV_RESET_VALUE)
else
begin
casez ({CLR, DEQ, ENQ, hasodata, ring_empty})
// Clear operation
5'b1????: begin
head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
// -----------------------
// DEQ && ENQ case -- change head and tail if added to ring
5'b011?0: begin
tail <= `BSV_ASSIGNMENT_DELAY next_tail;
head <= `BSV_ASSIGNMENT_DELAY next_head;
end
// -----------------------
// DEQ only and NO data is in ring
5'b010?1: begin
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
// DEQ only and data is in ring (move the head pointer)
5'b010?0: begin
head <= `BSV_ASSIGNMENT_DELAY next_head;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
ring_empty <= `BSV_ASSIGNMENT_DELAY next_head == tail ;
end
// -----------------------
// ENQ only when empty
5'b0010?: begin
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b1;
end
// ENQ only when not empty
5'b0011?: begin
if ( not_ring_full ) // Drop this test to save redundant test
// but be warnned that with test fifo overflow causes loss of new data
// while without test fifo drops all but head entry! (pointer overflow)
begin
tail <= `BSV_ASSIGNMENT_DELAY next_tail;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b0;
not_ring_full <= `BSV_ASSIGNMENT_DELAY ! (next_tail == head) ;
end
end
endcase
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// Update the fast data out register
always @(posedge CLK `BSV_ARESET_EDGE_HEAD)
begin
`ifdef BSV_RESET_FIFO_HEAD
if (RST == `BSV_RESET_VALUE)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
end // if (RST == `BSV_RESET_VALUE)
else
`endif
begin
casez ({CLR, DEQ, ENQ, hasodata, ring_empty})
// DEQ && ENQ cases
5'b011?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end
5'b011?1: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end
// DEQ only and data is in ring
5'b010?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end
// ENQ only when empty
5'b0010?: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end
endcase
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// Update the memory array reset is OFF
always @(posedge CLK `BSV_ARESET_EDGE_ARRAY)
begin: array
`ifdef BSV_RESET_FIFO_ARRAY
if (RST == `BSV_RESET_VALUE)
begin: rst_array
integer i;
for (i = 0; i <= p2depth2 && p2depth > 2; i = i + 1)
begin
arr[i] <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
end
end // if (RST == `BSV_RESET_VALUE)
else
`endif
begin
if (!CLR && ENQ && ((DEQ && !ring_empty) || (!DEQ && hasodata && not_ring_full)))
begin
arr[tail] <= `BSV_ASSIGNMENT_DELAY D_IN;
end
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if (RST == ! `BSV_RESET_VALUE)
begin
if ( ! EMPTY_N && DEQ )
begin
deqerror = 1 ;
$display( "Warning: SizedFIFO: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && (!DEQ || guarded) )
begin
enqerror = 1 ;
$display( "Warning: SizedFIFO: %m -- Enqueuing to a full fifo" ) ;
end
end
end // block: error_checks
// synopsys translate_on
// synopsys translate_off
// Some assertions about parameter values
initial
begin : parameter_assertions
integer ok ;
ok = 1 ;
if ( p2depth <= 1)
begin
ok = 0;
$display ( "Warning SizedFIFO: %m -- depth parameter increased from %0d to 2", p2depth);
end
if ( p3cntr_width <= 0 )
begin
ok = 0;
$display ( "ERROR SizedFIFO: %m -- width parameter must be greater than 0" ) ;
end
if ( ok == 0 ) $finish ;
end // initial begin
// synopsys translate_on
endmodule
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
`ifdef BSV_RESET_FIFO_HEAD
`define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_HEAD
`endif
// Depth 1 FIFO
module FIFO1(CLK,
RST,
D_IN,
ENQ,
FULL_N,
D_OUT,
DEQ,
EMPTY_N,
CLR
);
parameter width = 1;
parameter guarded = 1'b1;
input CLK;
input RST;
input [width - 1 : 0] D_IN;
input ENQ;
input DEQ;
input CLR ;
output FULL_N;
output [width - 1 : 0] D_OUT;
output EMPTY_N;
reg [width - 1 : 0] D_OUT;
reg empty_reg ;
assign EMPTY_N = empty_reg ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
D_OUT = {((width + 1)/2) {2'b10}} ;
empty_reg = 1'b0 ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
assign FULL_N = !empty_reg;
always@(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (RST == `BSV_RESET_VALUE)
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (CLR)
else if (ENQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // if (ENQ)
else if (DEQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (DEQ)
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
always@(posedge CLK `BSV_ARESET_EDGE_HEAD)
begin
`ifdef BSV_RESET_FIFO_HEAD
if (RST == `BSV_RESET_VALUE)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
end
else
`endif
begin
if (ENQ)
D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN;
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if (RST == ! `BSV_RESET_VALUE)
begin
if ( ! empty_reg && DEQ )
begin
deqerror = 1 ;
$display( "Warning: FIFO1: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && (!DEQ || guarded) )
begin
enqerror = 1 ;
$display( "Warning: FIFO1: %m -- Enqueuing to a full fifo" ) ;
end
end // if (RST == ! `BSV_RESET_VALUE)
end
// synopsys translate_on
endmodule
|
module mkRule30Driver(CLK,
RST_N,
operation_mode_arg,
EN_operation_mode,
RDY_operation_mode,
startup_value_v,
EN_startup_value,
RDY_startup_value,
txrx_SIN,
txrx_SOUT);
input CLK;
input RST_N;
// action method operation_mode
input [7 : 0] operation_mode_arg;
input EN_operation_mode;
output RDY_operation_mode;
// action method startup_value
input [7 : 0] startup_value_v;
input EN_startup_value;
output RDY_startup_value;
// action method txrx_sin
input txrx_SIN;
// value method txrx_sout
output txrx_SOUT;
// signals for module outputs
wire RDY_operation_mode, RDY_startup_value, txrx_SOUT;
// inlined wires
wire uart_fifoXmit_r_enq$whas,
uart_pwRecvCellCountReset$whas,
uart_pwRecvEnableBitCount$whas,
uart_pwRecvResetBitCount$whas,
uart_pwXmitCellCountReset$whas,
uart_pwXmitEnableBitCount$whas,
uart_pwXmitLoadBuffer$whas,
xmas_fsm_start_wire$whas,
xmas_fsm_state_set_pw$whas;
// register a
reg [7 : 0] a;
wire [7 : 0] a$D_IN;
wire a$EN;
// register op_mode
reg op_mode;
wire op_mode$D_IN, op_mode$EN;
// register transmit_state
reg [1 : 0] transmit_state;
wire [1 : 0] transmit_state$D_IN;
wire transmit_state$EN;
// register uart_rRecvBitCount
reg [3 : 0] uart_rRecvBitCount;
wire [3 : 0] uart_rRecvBitCount$D_IN;
wire uart_rRecvBitCount$EN;
// register uart_rRecvCellCount
reg [3 : 0] uart_rRecvCellCount;
wire [3 : 0] uart_rRecvCellCount$D_IN;
wire uart_rRecvCellCount$EN;
// register uart_rRecvData
reg uart_rRecvData;
wire uart_rRecvData$D_IN, uart_rRecvData$EN;
// register uart_rRecvState
reg [2 : 0] uart_rRecvState;
reg [2 : 0] uart_rRecvState$D_IN;
wire uart_rRecvState$EN;
// register uart_rXmitBitCount
reg [3 : 0] uart_rXmitBitCount;
wire [3 : 0] uart_rXmitBitCount$D_IN;
wire uart_rXmitBitCount$EN;
// register uart_rXmitCellCount
reg [3 : 0] uart_rXmitCellCount;
wire [3 : 0] uart_rXmitCellCount$D_IN;
wire uart_rXmitCellCount$EN;
// register uart_rXmitDataOut
reg uart_rXmitDataOut;
reg uart_rXmitDataOut$D_IN;
wire uart_rXmitDataOut$EN;
// register uart_rXmitState
reg [2 : 0] uart_rXmitState;
reg [2 : 0] uart_rXmitState$D_IN;
wire uart_rXmitState$EN;
// register uart_vrRecvBuffer_0
reg uart_vrRecvBuffer_0;
wire uart_vrRecvBuffer_0$D_IN, uart_vrRecvBuffer_0$EN;
// register uart_vrRecvBuffer_1
reg uart_vrRecvBuffer_1;
wire uart_vrRecvBuffer_1$D_IN, uart_vrRecvBuffer_1$EN;
// register uart_vrRecvBuffer_2
reg uart_vrRecvBuffer_2;
wire uart_vrRecvBuffer_2$D_IN, uart_vrRecvBuffer_2$EN;
// register uart_vrRecvBuffer_3
reg uart_vrRecvBuffer_3;
wire uart_vrRecvBuffer_3$D_IN, uart_vrRecvBuffer_3$EN;
// register uart_vrRecvBuffer_4
reg uart_vrRecvBuffer_4;
wire uart_vrRecvBuffer_4$D_IN, uart_vrRecvBuffer_4$EN;
// register uart_vrRecvBuffer_5
reg uart_vrRecvBuffer_5;
wire uart_vrRecvBuffer_5$D_IN, uart_vrRecvBuffer_5$EN;
// register uart_vrRecvBuffer_6
reg uart_vrRecvBuffer_6;
wire uart_vrRecvBuffer_6$D_IN, uart_vrRecvBuffer_6$EN;
// register uart_vrRecvBuffer_7
reg uart_vrRecvBuffer_7;
wire uart_vrRecvBuffer_7$D_IN, uart_vrRecvBuffer_7$EN;
// register uart_vrXmitBuffer_0
reg uart_vrXmitBuffer_0;
wire uart_vrXmitBuffer_0$D_IN, uart_vrXmitBuffer_0$EN;
// register uart_vrXmitBuffer_1
reg uart_vrXmitBuffer_1;
wire uart_vrXmitBuffer_1$D_IN, uart_vrXmitBuffer_1$EN;
// register uart_vrXmitBuffer_2
reg uart_vrXmitBuffer_2;
wire uart_vrXmitBuffer_2$D_IN, uart_vrXmitBuffer_2$EN;
// register uart_vrXmitBuffer_3
reg uart_vrXmitBuffer_3;
wire uart_vrXmitBuffer_3$D_IN, uart_vrXmitBuffer_3$EN;
// register uart_vrXmitBuffer_4
reg uart_vrXmitBuffer_4;
wire uart_vrXmitBuffer_4$D_IN, uart_vrXmitBuffer_4$EN;
// register uart_vrXmitBuffer_5
reg uart_vrXmitBuffer_5;
wire uart_vrXmitBuffer_5$D_IN, uart_vrXmitBuffer_5$EN;
// register uart_vrXmitBuffer_6
reg uart_vrXmitBuffer_6;
wire uart_vrXmitBuffer_6$D_IN, uart_vrXmitBuffer_6$EN;
// register uart_vrXmitBuffer_7
reg uart_vrXmitBuffer_7;
wire uart_vrXmitBuffer_7$D_IN, uart_vrXmitBuffer_7$EN;
// register xmas_fsm_start_reg
reg xmas_fsm_start_reg;
wire xmas_fsm_start_reg$D_IN, xmas_fsm_start_reg$EN;
// register xmas_fsm_start_reg_1
reg xmas_fsm_start_reg_1;
wire xmas_fsm_start_reg_1$D_IN, xmas_fsm_start_reg_1$EN;
// register xmas_fsm_state_fired
reg xmas_fsm_state_fired;
wire xmas_fsm_state_fired$D_IN, xmas_fsm_state_fired$EN;
// register xmas_fsm_state_mkFSMstate
reg [4 : 0] xmas_fsm_state_mkFSMstate;
reg [4 : 0] xmas_fsm_state_mkFSMstate$D_IN;
wire xmas_fsm_state_mkFSMstate$EN;
// ports of submodule rule30
wire [7 : 0] rule30$getResult, rule30$start_a;
wire rule30$EN_getResult,
rule30$EN_start,
rule30$RDY_getResult,
rule30$RDY_start;
// ports of submodule uart_baudGen_rBaudCounter
wire [15 : 0] uart_baudGen_rBaudCounter$DATA_A,
uart_baudGen_rBaudCounter$DATA_B,
uart_baudGen_rBaudCounter$DATA_C,
uart_baudGen_rBaudCounter$DATA_F,
uart_baudGen_rBaudCounter$Q_OUT;
wire uart_baudGen_rBaudCounter$ADDA,
uart_baudGen_rBaudCounter$ADDB,
uart_baudGen_rBaudCounter$SETC,
uart_baudGen_rBaudCounter$SETF;
// ports of submodule uart_baudGen_rBaudTickCounter
wire [2 : 0] uart_baudGen_rBaudTickCounter$DATA_A,
uart_baudGen_rBaudTickCounter$DATA_B,
uart_baudGen_rBaudTickCounter$DATA_C,
uart_baudGen_rBaudTickCounter$DATA_F,
uart_baudGen_rBaudTickCounter$Q_OUT;
wire uart_baudGen_rBaudTickCounter$ADDA,
uart_baudGen_rBaudTickCounter$ADDB,
uart_baudGen_rBaudTickCounter$SETC,
uart_baudGen_rBaudTickCounter$SETF;
// ports of submodule uart_fifoRecv
wire [7 : 0] uart_fifoRecv$D_IN;
wire uart_fifoRecv$CLR,
uart_fifoRecv$DEQ,
uart_fifoRecv$EMPTY_N,
uart_fifoRecv$ENQ;
// ports of submodule uart_fifoXmit
reg [7 : 0] uart_fifoXmit$D_IN;
wire [7 : 0] uart_fifoXmit$D_OUT;
wire uart_fifoXmit$CLR,
uart_fifoXmit$DEQ,
uart_fifoXmit$EMPTY_N,
uart_fifoXmit$ENQ,
uart_fifoXmit$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_compute,
CAN_FIRE_RL_dump_rx,
CAN_FIRE_RL_get_result,
CAN_FIRE_RL_uart_baudGen_assert_2x_baud_tick,
CAN_FIRE_RL_uart_baudGen_baud_count_wire,
CAN_FIRE_RL_uart_baudGen_baud_tick_count_wire,
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x,
CAN_FIRE_RL_uart_baud_generator_clock_enable,
CAN_FIRE_RL_uart_fifoRecv__updateLevelCounter,
CAN_FIRE_RL_uart_fifoXmit__updateLevelCounter,
CAN_FIRE_RL_uart_receive_bit_cell_time_counter,
CAN_FIRE_RL_uart_receive_bit_counter,
CAN_FIRE_RL_uart_receive_buffer_shift,
CAN_FIRE_RL_uart_receive_find_center_of_bit_cell,
CAN_FIRE_RL_uart_receive_parity_bit,
CAN_FIRE_RL_uart_receive_sample_pin,
CAN_FIRE_RL_uart_receive_stop_first_bit,
CAN_FIRE_RL_uart_receive_stop_last_bit,
CAN_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample,
CAN_FIRE_RL_uart_receive_wait_for_start_bit,
CAN_FIRE_RL_uart_transmit_bit_cell_time_counter,
CAN_FIRE_RL_uart_transmit_bit_counter,
CAN_FIRE_RL_uart_transmit_buffer_load,
CAN_FIRE_RL_uart_transmit_buffer_shift,
CAN_FIRE_RL_uart_transmit_send_parity_bit,
CAN_FIRE_RL_uart_transmit_send_start_bit,
CAN_FIRE_RL_uart_transmit_send_stop_bit,
CAN_FIRE_RL_uart_transmit_send_stop_bit1_5,
CAN_FIRE_RL_uart_transmit_send_stop_bit2,
CAN_FIRE_RL_uart_transmit_shift_next_bit,
CAN_FIRE_RL_uart_transmit_wait_1_bit_cell_time,
CAN_FIRE_RL_uart_transmit_wait_for_start_command,
CAN_FIRE_RL_xmas_fsm_action_l42c32,
CAN_FIRE_RL_xmas_fsm_action_l43c32,
CAN_FIRE_RL_xmas_fsm_action_l44c32,
CAN_FIRE_RL_xmas_fsm_action_l45c32,
CAN_FIRE_RL_xmas_fsm_action_l46c32,
CAN_FIRE_RL_xmas_fsm_action_l47c32,
CAN_FIRE_RL_xmas_fsm_action_l48c32,
CAN_FIRE_RL_xmas_fsm_action_l49c32,
CAN_FIRE_RL_xmas_fsm_action_l50c32,
CAN_FIRE_RL_xmas_fsm_action_l51c32,
CAN_FIRE_RL_xmas_fsm_action_l52c32,
CAN_FIRE_RL_xmas_fsm_action_l53c32,
CAN_FIRE_RL_xmas_fsm_action_l54c32,
CAN_FIRE_RL_xmas_fsm_action_l55c32,
CAN_FIRE_RL_xmas_fsm_action_l56c32,
CAN_FIRE_RL_xmas_fsm_action_l57c32,
CAN_FIRE_RL_xmas_fsm_action_l58c32,
CAN_FIRE_RL_xmas_fsm_action_l59c32,
CAN_FIRE_RL_xmas_fsm_action_l60c32,
CAN_FIRE_RL_xmas_fsm_action_l61c32,
CAN_FIRE_RL_xmas_fsm_action_l62c32,
CAN_FIRE_RL_xmas_fsm_action_l63c32,
CAN_FIRE_RL_xmas_fsm_action_l64c32,
CAN_FIRE_RL_xmas_fsm_action_l65c32,
CAN_FIRE_RL_xmas_fsm_action_l66c32,
CAN_FIRE_RL_xmas_fsm_fsm_start,
CAN_FIRE_RL_xmas_fsm_idle_l40c27,
CAN_FIRE_RL_xmas_fsm_idle_l40c27_1,
CAN_FIRE_RL_xmas_fsm_restart,
CAN_FIRE_RL_xmas_fsm_start_reg__dreg_update,
CAN_FIRE_RL_xmas_fsm_state_every,
CAN_FIRE_RL_xmas_fsm_state_fired__dreg_update,
CAN_FIRE_RL_xmas_fsm_state_handle_abort,
CAN_FIRE___me_check_34,
CAN_FIRE___me_check_35,
CAN_FIRE___me_check_36,
CAN_FIRE___me_check_37,
CAN_FIRE___me_check_38,
CAN_FIRE___me_check_39,
CAN_FIRE___me_check_40,
CAN_FIRE___me_check_41,
CAN_FIRE___me_check_42,
CAN_FIRE___me_check_43,
CAN_FIRE___me_check_44,
CAN_FIRE___me_check_45,
CAN_FIRE___me_check_46,
CAN_FIRE___me_check_47,
CAN_FIRE___me_check_48,
CAN_FIRE___me_check_49,
CAN_FIRE___me_check_50,
CAN_FIRE___me_check_51,
CAN_FIRE___me_check_52,
CAN_FIRE___me_check_53,
CAN_FIRE___me_check_54,
CAN_FIRE___me_check_55,
CAN_FIRE___me_check_56,
CAN_FIRE___me_check_57,
CAN_FIRE_operation_mode,
CAN_FIRE_startup_value,
CAN_FIRE_txrx_sin,
WILL_FIRE_RL_compute,
WILL_FIRE_RL_dump_rx,
WILL_FIRE_RL_get_result,
WILL_FIRE_RL_uart_baudGen_assert_2x_baud_tick,
WILL_FIRE_RL_uart_baudGen_baud_count_wire,
WILL_FIRE_RL_uart_baudGen_baud_tick_count_wire,
WILL_FIRE_RL_uart_baudGen_count_baudtick_16x,
WILL_FIRE_RL_uart_baud_generator_clock_enable,
WILL_FIRE_RL_uart_fifoRecv__updateLevelCounter,
WILL_FIRE_RL_uart_fifoXmit__updateLevelCounter,
WILL_FIRE_RL_uart_receive_bit_cell_time_counter,
WILL_FIRE_RL_uart_receive_bit_counter,
WILL_FIRE_RL_uart_receive_buffer_shift,
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell,
WILL_FIRE_RL_uart_receive_parity_bit,
WILL_FIRE_RL_uart_receive_sample_pin,
WILL_FIRE_RL_uart_receive_stop_first_bit,
WILL_FIRE_RL_uart_receive_stop_last_bit,
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample,
WILL_FIRE_RL_uart_receive_wait_for_start_bit,
WILL_FIRE_RL_uart_transmit_bit_cell_time_counter,
WILL_FIRE_RL_uart_transmit_bit_counter,
WILL_FIRE_RL_uart_transmit_buffer_load,
WILL_FIRE_RL_uart_transmit_buffer_shift,
WILL_FIRE_RL_uart_transmit_send_parity_bit,
WILL_FIRE_RL_uart_transmit_send_start_bit,
WILL_FIRE_RL_uart_transmit_send_stop_bit,
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5,
WILL_FIRE_RL_uart_transmit_send_stop_bit2,
WILL_FIRE_RL_uart_transmit_shift_next_bit,
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time,
WILL_FIRE_RL_uart_transmit_wait_for_start_command,
WILL_FIRE_RL_xmas_fsm_action_l42c32,
WILL_FIRE_RL_xmas_fsm_action_l43c32,
WILL_FIRE_RL_xmas_fsm_action_l44c32,
WILL_FIRE_RL_xmas_fsm_action_l45c32,
WILL_FIRE_RL_xmas_fsm_action_l46c32,
WILL_FIRE_RL_xmas_fsm_action_l47c32,
WILL_FIRE_RL_xmas_fsm_action_l48c32,
WILL_FIRE_RL_xmas_fsm_action_l49c32,
WILL_FIRE_RL_xmas_fsm_action_l50c32,
WILL_FIRE_RL_xmas_fsm_action_l51c32,
WILL_FIRE_RL_xmas_fsm_action_l52c32,
WILL_FIRE_RL_xmas_fsm_action_l53c32,
WILL_FIRE_RL_xmas_fsm_action_l54c32,
WILL_FIRE_RL_xmas_fsm_action_l55c32,
WILL_FIRE_RL_xmas_fsm_action_l56c32,
WILL_FIRE_RL_xmas_fsm_action_l57c32,
WILL_FIRE_RL_xmas_fsm_action_l58c32,
WILL_FIRE_RL_xmas_fsm_action_l59c32,
WILL_FIRE_RL_xmas_fsm_action_l60c32,
WILL_FIRE_RL_xmas_fsm_action_l61c32,
WILL_FIRE_RL_xmas_fsm_action_l62c32,
WILL_FIRE_RL_xmas_fsm_action_l63c32,
WILL_FIRE_RL_xmas_fsm_action_l64c32,
WILL_FIRE_RL_xmas_fsm_action_l65c32,
WILL_FIRE_RL_xmas_fsm_action_l66c32,
WILL_FIRE_RL_xmas_fsm_fsm_start,
WILL_FIRE_RL_xmas_fsm_idle_l40c27,
WILL_FIRE_RL_xmas_fsm_idle_l40c27_1,
WILL_FIRE_RL_xmas_fsm_restart,
WILL_FIRE_RL_xmas_fsm_start_reg__dreg_update,
WILL_FIRE_RL_xmas_fsm_state_every,
WILL_FIRE_RL_xmas_fsm_state_fired__dreg_update,
WILL_FIRE_RL_xmas_fsm_state_handle_abort,
WILL_FIRE___me_check_34,
WILL_FIRE___me_check_35,
WILL_FIRE___me_check_36,
WILL_FIRE___me_check_37,
WILL_FIRE___me_check_38,
WILL_FIRE___me_check_39,
WILL_FIRE___me_check_40,
WILL_FIRE___me_check_41,
WILL_FIRE___me_check_42,
WILL_FIRE___me_check_43,
WILL_FIRE___me_check_44,
WILL_FIRE___me_check_45,
WILL_FIRE___me_check_46,
WILL_FIRE___me_check_47,
WILL_FIRE___me_check_48,
WILL_FIRE___me_check_49,
WILL_FIRE___me_check_50,
WILL_FIRE___me_check_51,
WILL_FIRE___me_check_52,
WILL_FIRE___me_check_53,
WILL_FIRE___me_check_54,
WILL_FIRE___me_check_55,
WILL_FIRE___me_check_56,
WILL_FIRE___me_check_57,
WILL_FIRE_operation_mode,
WILL_FIRE_startup_value,
WILL_FIRE_txrx_sin;
// inputs to muxes for submodule ports
reg [2 : 0] MUX_uart_rRecvState$write_1__VAL_3;
wire [2 : 0] MUX_uart_rRecvState$write_1__VAL_1,
MUX_uart_rRecvState$write_1__VAL_2,
MUX_uart_rRecvState$write_1__VAL_4,
MUX_uart_rXmitState$write_1__VAL_1,
MUX_uart_rXmitState$write_1__VAL_2,
MUX_uart_rXmitState$write_1__VAL_3,
MUX_uart_rXmitState$write_1__VAL_4,
MUX_uart_rXmitState$write_1__VAL_5,
MUX_uart_rXmitState$write_1__VAL_6,
MUX_uart_rXmitState$write_1__VAL_7;
wire MUX_transmit_state$write_1__SEL_1,
MUX_uart_fifoXmit$enq_1__SEL_11,
MUX_uart_fifoXmit$enq_1__SEL_15,
MUX_uart_fifoXmit$enq_1__SEL_16,
MUX_uart_fifoXmit$enq_1__SEL_17,
MUX_uart_fifoXmit$enq_1__SEL_2,
MUX_uart_fifoXmit$enq_1__SEL_3,
MUX_uart_rRecvState$write_1__SEL_6,
MUX_uart_rXmitDataOut$write_1__SEL_1,
MUX_uart_rXmitDataOut$write_1__SEL_2,
MUX_uart_rXmitDataOut$write_1__SEL_3,
MUX_xmas_fsm_start_reg$write_1__SEL_1,
MUX_xmas_fsm_state_mkFSMstate$write_1__SEL_1;
// remaining internal signals
wire [3 : 0] x__h2985, x__h4689, x__h6445, x__h6471;
wire _dor2uart_pwXmitCellCountReset$EN_wset,
uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29,
xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302;
// action method operation_mode
assign RDY_operation_mode =
transmit_state == 2'd0 && !op_mode &&
xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302 &&
!xmas_fsm_start_reg ;
assign CAN_FIRE_operation_mode =
transmit_state == 2'd0 && !op_mode &&
xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302 &&
!xmas_fsm_start_reg ;
assign WILL_FIRE_operation_mode = EN_operation_mode ;
// action method startup_value
assign RDY_startup_value = transmit_state == 2'd0 && !op_mode ;
assign CAN_FIRE_startup_value = transmit_state == 2'd0 && !op_mode ;
assign WILL_FIRE_startup_value = EN_startup_value ;
// action method txrx_sin
assign CAN_FIRE_txrx_sin = 1'd1 ;
assign WILL_FIRE_txrx_sin = 1'd1 ;
// value method txrx_sout
assign txrx_SOUT = uart_rXmitDataOut ;
// submodule rule30
mkRule30 rule30(.CLK(CLK),
.RST_N(RST_N),
.start_a(rule30$start_a),
.EN_start(rule30$EN_start),
.EN_getResult(rule30$EN_getResult),
.RDY_start(rule30$RDY_start),
.getResult(rule30$getResult),
.RDY_getResult(rule30$RDY_getResult));
// submodule uart_baudGen_rBaudCounter
Counter #(.width(32'd16), .init(16'd0)) uart_baudGen_rBaudCounter(.CLK(CLK),
.RST(RST_N),
.DATA_A(uart_baudGen_rBaudCounter$DATA_A),
.DATA_B(uart_baudGen_rBaudCounter$DATA_B),
.DATA_C(uart_baudGen_rBaudCounter$DATA_C),
.DATA_F(uart_baudGen_rBaudCounter$DATA_F),
.ADDA(uart_baudGen_rBaudCounter$ADDA),
.ADDB(uart_baudGen_rBaudCounter$ADDB),
.SETC(uart_baudGen_rBaudCounter$SETC),
.SETF(uart_baudGen_rBaudCounter$SETF),
.Q_OUT(uart_baudGen_rBaudCounter$Q_OUT));
// submodule uart_baudGen_rBaudTickCounter
Counter #(.width(32'd3),
.init(3'd0)) uart_baudGen_rBaudTickCounter(.CLK(CLK),
.RST(RST_N),
.DATA_A(uart_baudGen_rBaudTickCounter$DATA_A),
.DATA_B(uart_baudGen_rBaudTickCounter$DATA_B),
.DATA_C(uart_baudGen_rBaudTickCounter$DATA_C),
.DATA_F(uart_baudGen_rBaudTickCounter$DATA_F),
.ADDA(uart_baudGen_rBaudTickCounter$ADDA),
.ADDB(uart_baudGen_rBaudTickCounter$ADDB),
.SETC(uart_baudGen_rBaudTickCounter$SETC),
.SETF(uart_baudGen_rBaudTickCounter$SETF),
.Q_OUT(uart_baudGen_rBaudTickCounter$Q_OUT));
// submodule uart_fifoRecv
SizedFIFO #(.p1width(32'd8),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(1'd1)) uart_fifoRecv(.RST(RST_N),
.CLK(CLK),
.D_IN(uart_fifoRecv$D_IN),
.ENQ(uart_fifoRecv$ENQ),
.DEQ(uart_fifoRecv$DEQ),
.CLR(uart_fifoRecv$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N(uart_fifoRecv$EMPTY_N));
// submodule uart_fifoXmit
SizedFIFO #(.p1width(32'd8),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(1'd1)) uart_fifoXmit(.RST(RST_N),
.CLK(CLK),
.D_IN(uart_fifoXmit$D_IN),
.ENQ(uart_fifoXmit$ENQ),
.DEQ(uart_fifoXmit$DEQ),
.CLR(uart_fifoXmit$CLR),
.D_OUT(uart_fifoXmit$D_OUT),
.FULL_N(uart_fifoXmit$FULL_N),
.EMPTY_N(uart_fifoXmit$EMPTY_N));
// rule RL_dump_rx
assign CAN_FIRE_RL_dump_rx = uart_fifoRecv$EMPTY_N ;
assign WILL_FIRE_RL_dump_rx = uart_fifoRecv$EMPTY_N ;
// rule RL_compute
assign CAN_FIRE_RL_compute =
rule30$RDY_start && transmit_state == 2'd1 && !op_mode ;
assign WILL_FIRE_RL_compute = CAN_FIRE_RL_compute ;
// rule RL_uart_baudGen_baud_count_wire
assign CAN_FIRE_RL_uart_baudGen_baud_count_wire = 1'd1 ;
assign WILL_FIRE_RL_uart_baudGen_baud_count_wire = 1'd1 ;
// rule RL_uart_baud_generator_clock_enable
assign CAN_FIRE_RL_uart_baud_generator_clock_enable = 1'd1 ;
assign WILL_FIRE_RL_uart_baud_generator_clock_enable = 1'd1 ;
// rule RL_uart_receive_wait_for_start_bit
assign CAN_FIRE_RL_uart_receive_wait_for_start_bit =
uart_rRecvState == 3'd0 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_wait_for_start_bit =
CAN_FIRE_RL_uart_receive_wait_for_start_bit ;
// rule RL_uart_receive_find_center_of_bit_cell
assign CAN_FIRE_RL_uart_receive_find_center_of_bit_cell =
uart_rRecvState == 3'd1 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_find_center_of_bit_cell =
CAN_FIRE_RL_uart_receive_find_center_of_bit_cell ;
// rule RL_uart_receive_wait_bit_cell_time_for_sample
assign CAN_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample =
uart_rRecvState == 3'd2 && uart_rRecvCellCount == 4'hF &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample =
CAN_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample ;
// rule RL_uart_receive_sample_pin
assign CAN_FIRE_RL_uart_receive_sample_pin =
CAN_FIRE_RL_uart_receive_buffer_shift ;
assign WILL_FIRE_RL_uart_receive_sample_pin =
CAN_FIRE_RL_uart_receive_buffer_shift ;
// rule RL_uart_receive_parity_bit
assign CAN_FIRE_RL_uart_receive_parity_bit =
uart_rRecvState == 3'd4 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_parity_bit =
CAN_FIRE_RL_uart_receive_parity_bit ;
// rule RL_uart_receive_stop_first_bit
assign CAN_FIRE_RL_uart_receive_stop_first_bit =
uart_rRecvState == 3'd5 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_stop_first_bit =
CAN_FIRE_RL_uart_receive_stop_first_bit ;
// rule RL_uart_receive_bit_counter
assign CAN_FIRE_RL_uart_receive_bit_counter = 1'd1 ;
assign WILL_FIRE_RL_uart_receive_bit_counter = 1'd1 ;
// rule RL_uart_receive_stop_last_bit
assign CAN_FIRE_RL_uart_receive_stop_last_bit =
uart_rRecvState == 3'd6 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_stop_last_bit =
CAN_FIRE_RL_uart_receive_stop_last_bit ;
// rule RL_uart_receive_bit_cell_time_counter
assign CAN_FIRE_RL_uart_receive_bit_cell_time_counter =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
assign WILL_FIRE_RL_uart_receive_bit_cell_time_counter =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// rule RL_uart_receive_buffer_shift
assign CAN_FIRE_RL_uart_receive_buffer_shift =
uart_rRecvState == 3'd3 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_buffer_shift =
CAN_FIRE_RL_uart_receive_buffer_shift ;
// rule RL_uart_transmit_wait_for_start_command
assign CAN_FIRE_RL_uart_transmit_wait_for_start_command =
uart_rXmitState == 3'd0 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_wait_for_start_command =
CAN_FIRE_RL_uart_transmit_wait_for_start_command ;
// rule RL_get_result
assign CAN_FIRE_RL_get_result =
rule30$RDY_getResult && uart_fifoXmit$FULL_N &&
transmit_state == 2'd2 &&
!op_mode &&
xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302 &&
!xmas_fsm_start_reg ;
assign WILL_FIRE_RL_get_result = CAN_FIRE_RL_get_result ;
// rule RL_uart_transmit_send_start_bit
assign CAN_FIRE_RL_uart_transmit_send_start_bit =
uart_rXmitState == 3'd1 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_start_bit =
CAN_FIRE_RL_uart_transmit_send_start_bit ;
// rule RL_uart_transmit_wait_1_bit_cell_time
assign CAN_FIRE_RL_uart_transmit_wait_1_bit_cell_time =
uart_rXmitState == 3'd2 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time =
CAN_FIRE_RL_uart_transmit_wait_1_bit_cell_time ;
// rule RL_uart_transmit_bit_counter
assign CAN_FIRE_RL_uart_transmit_bit_counter = 1'd1 ;
assign WILL_FIRE_RL_uart_transmit_bit_counter = 1'd1 ;
// rule RL_uart_transmit_shift_next_bit
assign CAN_FIRE_RL_uart_transmit_shift_next_bit =
uart_rXmitState == 3'd3 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_shift_next_bit =
CAN_FIRE_RL_uart_transmit_shift_next_bit ;
// rule RL_uart_transmit_buffer_load
assign CAN_FIRE_RL_uart_transmit_buffer_load =
uart_fifoXmit$EMPTY_N && uart_pwXmitLoadBuffer$whas ;
assign WILL_FIRE_RL_uart_transmit_buffer_load =
CAN_FIRE_RL_uart_transmit_buffer_load ;
// rule RL_uart_transmit_buffer_shift
assign CAN_FIRE_RL_uart_transmit_buffer_shift =
!uart_pwXmitLoadBuffer$whas &&
CAN_FIRE_RL_uart_transmit_shift_next_bit ;
assign WILL_FIRE_RL_uart_transmit_buffer_shift =
CAN_FIRE_RL_uart_transmit_buffer_shift ;
// rule RL_uart_transmit_send_parity_bit
assign CAN_FIRE_RL_uart_transmit_send_parity_bit =
uart_rXmitState == 3'd7 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_parity_bit =
CAN_FIRE_RL_uart_transmit_send_parity_bit ;
// rule RL_uart_transmit_send_stop_bit
assign CAN_FIRE_RL_uart_transmit_send_stop_bit =
uart_rXmitState == 3'd4 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_stop_bit =
CAN_FIRE_RL_uart_transmit_send_stop_bit ;
// rule RL_uart_transmit_send_stop_bit1_5
assign CAN_FIRE_RL_uart_transmit_send_stop_bit1_5 =
uart_rXmitState == 3'd5 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 =
CAN_FIRE_RL_uart_transmit_send_stop_bit1_5 ;
// rule RL_uart_transmit_send_stop_bit2
assign CAN_FIRE_RL_uart_transmit_send_stop_bit2 =
uart_rXmitState == 3'd6 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_stop_bit2 =
CAN_FIRE_RL_uart_transmit_send_stop_bit2 ;
// rule RL_uart_transmit_bit_cell_time_counter
assign CAN_FIRE_RL_uart_transmit_bit_cell_time_counter =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
assign WILL_FIRE_RL_uart_transmit_bit_cell_time_counter =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// rule RL_uart_baudGen_baud_tick_count_wire
assign CAN_FIRE_RL_uart_baudGen_baud_tick_count_wire = 1'd1 ;
assign WILL_FIRE_RL_uart_baudGen_baud_tick_count_wire = 1'd1 ;
// rule RL_uart_baudGen_assert_2x_baud_tick
assign CAN_FIRE_RL_uart_baudGen_assert_2x_baud_tick =
uart_baudGen_rBaudTickCounter$Q_OUT == 3'd0 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_baudGen_assert_2x_baud_tick =
CAN_FIRE_RL_uart_baudGen_assert_2x_baud_tick ;
// rule RL_uart_baudGen_count_baudtick_16x
assign CAN_FIRE_RL_uart_baudGen_count_baudtick_16x =
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_baudGen_count_baudtick_16x =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// rule RL_uart_fifoRecv__updateLevelCounter
assign CAN_FIRE_RL_uart_fifoRecv__updateLevelCounter =
CAN_FIRE_RL_uart_receive_stop_last_bit != uart_fifoRecv$EMPTY_N ;
assign WILL_FIRE_RL_uart_fifoRecv__updateLevelCounter =
CAN_FIRE_RL_uart_fifoRecv__updateLevelCounter ;
// rule RL_xmas_fsm_restart
assign CAN_FIRE_RL_xmas_fsm_restart =
xmas_fsm_start_reg_1 && !xmas_fsm_state_fired ;
assign WILL_FIRE_RL_xmas_fsm_restart = CAN_FIRE_RL_xmas_fsm_restart ;
// rule RL_xmas_fsm_action_l43c32
assign CAN_FIRE_RL_xmas_fsm_action_l43c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd1 ;
assign WILL_FIRE_RL_xmas_fsm_action_l43c32 =
CAN_FIRE_RL_xmas_fsm_action_l43c32 ;
// rule RL_xmas_fsm_action_l44c32
assign CAN_FIRE_RL_xmas_fsm_action_l44c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd2 ;
assign WILL_FIRE_RL_xmas_fsm_action_l44c32 =
CAN_FIRE_RL_xmas_fsm_action_l44c32 ;
// rule RL_xmas_fsm_action_l45c32
assign CAN_FIRE_RL_xmas_fsm_action_l45c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd3 ;
assign WILL_FIRE_RL_xmas_fsm_action_l45c32 =
CAN_FIRE_RL_xmas_fsm_action_l45c32 ;
// rule RL_xmas_fsm_action_l46c32
assign CAN_FIRE_RL_xmas_fsm_action_l46c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd4 ;
assign WILL_FIRE_RL_xmas_fsm_action_l46c32 =
CAN_FIRE_RL_xmas_fsm_action_l46c32 ;
// rule RL_xmas_fsm_action_l47c32
assign CAN_FIRE_RL_xmas_fsm_action_l47c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd5 ;
assign WILL_FIRE_RL_xmas_fsm_action_l47c32 =
CAN_FIRE_RL_xmas_fsm_action_l47c32 ;
// rule RL_xmas_fsm_action_l48c32
assign CAN_FIRE_RL_xmas_fsm_action_l48c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd6 ;
assign WILL_FIRE_RL_xmas_fsm_action_l48c32 =
CAN_FIRE_RL_xmas_fsm_action_l48c32 ;
// rule RL_xmas_fsm_action_l49c32
assign CAN_FIRE_RL_xmas_fsm_action_l49c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd7 ;
assign WILL_FIRE_RL_xmas_fsm_action_l49c32 =
CAN_FIRE_RL_xmas_fsm_action_l49c32 ;
// rule RL_xmas_fsm_action_l50c32
assign CAN_FIRE_RL_xmas_fsm_action_l50c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd8 ;
assign WILL_FIRE_RL_xmas_fsm_action_l50c32 =
CAN_FIRE_RL_xmas_fsm_action_l50c32 ;
// rule RL_xmas_fsm_action_l51c32
assign CAN_FIRE_RL_xmas_fsm_action_l51c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd9 ;
assign WILL_FIRE_RL_xmas_fsm_action_l51c32 =
CAN_FIRE_RL_xmas_fsm_action_l51c32 ;
// rule RL_xmas_fsm_action_l52c32
assign CAN_FIRE_RL_xmas_fsm_action_l52c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd10 ;
assign WILL_FIRE_RL_xmas_fsm_action_l52c32 =
CAN_FIRE_RL_xmas_fsm_action_l52c32 ;
// rule RL_xmas_fsm_action_l53c32
assign CAN_FIRE_RL_xmas_fsm_action_l53c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd11 ;
assign WILL_FIRE_RL_xmas_fsm_action_l53c32 =
CAN_FIRE_RL_xmas_fsm_action_l53c32 ;
// rule RL_xmas_fsm_action_l54c32
assign CAN_FIRE_RL_xmas_fsm_action_l54c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd12 ;
assign WILL_FIRE_RL_xmas_fsm_action_l54c32 =
CAN_FIRE_RL_xmas_fsm_action_l54c32 ;
// rule RL_xmas_fsm_action_l55c32
assign CAN_FIRE_RL_xmas_fsm_action_l55c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd13 ;
assign WILL_FIRE_RL_xmas_fsm_action_l55c32 =
CAN_FIRE_RL_xmas_fsm_action_l55c32 ;
// rule RL_xmas_fsm_action_l56c32
assign CAN_FIRE_RL_xmas_fsm_action_l56c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd14 ;
assign WILL_FIRE_RL_xmas_fsm_action_l56c32 =
CAN_FIRE_RL_xmas_fsm_action_l56c32 ;
// rule RL_xmas_fsm_action_l57c32
assign CAN_FIRE_RL_xmas_fsm_action_l57c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd15 ;
assign WILL_FIRE_RL_xmas_fsm_action_l57c32 =
CAN_FIRE_RL_xmas_fsm_action_l57c32 ;
// rule RL_xmas_fsm_action_l58c32
assign CAN_FIRE_RL_xmas_fsm_action_l58c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd16 ;
assign WILL_FIRE_RL_xmas_fsm_action_l58c32 =
CAN_FIRE_RL_xmas_fsm_action_l58c32 ;
// rule RL_xmas_fsm_action_l59c32
assign CAN_FIRE_RL_xmas_fsm_action_l59c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd17 ;
assign WILL_FIRE_RL_xmas_fsm_action_l59c32 =
CAN_FIRE_RL_xmas_fsm_action_l59c32 ;
// rule RL_xmas_fsm_action_l60c32
assign CAN_FIRE_RL_xmas_fsm_action_l60c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd18 ;
assign WILL_FIRE_RL_xmas_fsm_action_l60c32 =
CAN_FIRE_RL_xmas_fsm_action_l60c32 ;
// rule RL_xmas_fsm_action_l61c32
assign CAN_FIRE_RL_xmas_fsm_action_l61c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd19 ;
assign WILL_FIRE_RL_xmas_fsm_action_l61c32 =
CAN_FIRE_RL_xmas_fsm_action_l61c32 ;
// rule RL_xmas_fsm_action_l62c32
assign CAN_FIRE_RL_xmas_fsm_action_l62c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd20 ;
assign WILL_FIRE_RL_xmas_fsm_action_l62c32 =
CAN_FIRE_RL_xmas_fsm_action_l62c32 ;
// rule RL_xmas_fsm_action_l63c32
assign CAN_FIRE_RL_xmas_fsm_action_l63c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd21 ;
assign WILL_FIRE_RL_xmas_fsm_action_l63c32 =
CAN_FIRE_RL_xmas_fsm_action_l63c32 ;
// rule RL_xmas_fsm_action_l64c32
assign CAN_FIRE_RL_xmas_fsm_action_l64c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd22 ;
assign WILL_FIRE_RL_xmas_fsm_action_l64c32 =
CAN_FIRE_RL_xmas_fsm_action_l64c32 ;
// rule RL_xmas_fsm_action_l65c32
assign CAN_FIRE_RL_xmas_fsm_action_l65c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd23 ;
assign WILL_FIRE_RL_xmas_fsm_action_l65c32 =
CAN_FIRE_RL_xmas_fsm_action_l65c32 ;
// rule RL_xmas_fsm_action_l66c32
assign CAN_FIRE_RL_xmas_fsm_action_l66c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd24 ;
assign WILL_FIRE_RL_xmas_fsm_action_l66c32 =
CAN_FIRE_RL_xmas_fsm_action_l66c32 ;
// rule __me_check_35
assign CAN_FIRE___me_check_35 = 1'b1 ;
assign WILL_FIRE___me_check_35 = 1'b1 ;
// rule __me_check_36
assign CAN_FIRE___me_check_36 = 1'b1 ;
assign WILL_FIRE___me_check_36 = 1'b1 ;
// rule __me_check_37
assign CAN_FIRE___me_check_37 = 1'b1 ;
assign WILL_FIRE___me_check_37 = 1'b1 ;
// rule __me_check_38
assign CAN_FIRE___me_check_38 = 1'b1 ;
assign WILL_FIRE___me_check_38 = 1'b1 ;
// rule __me_check_39
assign CAN_FIRE___me_check_39 = 1'b1 ;
assign WILL_FIRE___me_check_39 = 1'b1 ;
// rule __me_check_40
assign CAN_FIRE___me_check_40 = 1'b1 ;
assign WILL_FIRE___me_check_40 = 1'b1 ;
// rule __me_check_41
assign CAN_FIRE___me_check_41 = 1'b1 ;
assign WILL_FIRE___me_check_41 = 1'b1 ;
// rule __me_check_43
assign CAN_FIRE___me_check_43 = 1'b1 ;
assign WILL_FIRE___me_check_43 = 1'b1 ;
// rule __me_check_42
assign CAN_FIRE___me_check_42 = 1'b1 ;
assign WILL_FIRE___me_check_42 = 1'b1 ;
// rule __me_check_44
assign CAN_FIRE___me_check_44 = 1'b1 ;
assign WILL_FIRE___me_check_44 = 1'b1 ;
// rule __me_check_45
assign CAN_FIRE___me_check_45 = 1'b1 ;
assign WILL_FIRE___me_check_45 = 1'b1 ;
// rule __me_check_46
assign CAN_FIRE___me_check_46 = 1'b1 ;
assign WILL_FIRE___me_check_46 = 1'b1 ;
// rule __me_check_47
assign CAN_FIRE___me_check_47 = 1'b1 ;
assign WILL_FIRE___me_check_47 = 1'b1 ;
// rule __me_check_48
assign CAN_FIRE___me_check_48 = 1'b1 ;
assign WILL_FIRE___me_check_48 = 1'b1 ;
// rule __me_check_49
assign CAN_FIRE___me_check_49 = 1'b1 ;
assign WILL_FIRE___me_check_49 = 1'b1 ;
// rule __me_check_51
assign CAN_FIRE___me_check_51 = 1'b1 ;
assign WILL_FIRE___me_check_51 = 1'b1 ;
// rule __me_check_50
assign CAN_FIRE___me_check_50 = 1'b1 ;
assign WILL_FIRE___me_check_50 = 1'b1 ;
// rule __me_check_52
assign CAN_FIRE___me_check_52 = 1'b1 ;
assign WILL_FIRE___me_check_52 = 1'b1 ;
// rule __me_check_53
assign CAN_FIRE___me_check_53 = 1'b1 ;
assign WILL_FIRE___me_check_53 = 1'b1 ;
// rule __me_check_54
assign CAN_FIRE___me_check_54 = 1'b1 ;
assign WILL_FIRE___me_check_54 = 1'b1 ;
// rule __me_check_55
assign CAN_FIRE___me_check_55 = 1'b1 ;
assign WILL_FIRE___me_check_55 = 1'b1 ;
// rule __me_check_56
assign CAN_FIRE___me_check_56 = 1'b1 ;
assign WILL_FIRE___me_check_56 = 1'b1 ;
// rule __me_check_57
assign CAN_FIRE___me_check_57 = 1'b1 ;
assign WILL_FIRE___me_check_57 = 1'b1 ;
// rule RL_xmas_fsm_idle_l40c27_1
assign CAN_FIRE_RL_xmas_fsm_idle_l40c27_1 =
!op_mode && xmas_fsm_state_mkFSMstate == 5'd25 ;
assign WILL_FIRE_RL_xmas_fsm_idle_l40c27_1 =
CAN_FIRE_RL_xmas_fsm_idle_l40c27_1 ;
// rule RL_xmas_fsm_fsm_start
assign CAN_FIRE_RL_xmas_fsm_fsm_start =
(op_mode && xmas_fsm_state_mkFSMstate == 5'd0 ||
op_mode && xmas_fsm_state_mkFSMstate == 5'd27 ||
!op_mode && xmas_fsm_state_mkFSMstate == 5'd0 ||
!op_mode &&
(xmas_fsm_state_mkFSMstate == 5'd25 ||
xmas_fsm_state_mkFSMstate == 5'd27)) &&
(!xmas_fsm_start_reg_1 || xmas_fsm_state_fired) &&
xmas_fsm_start_reg ;
assign WILL_FIRE_RL_xmas_fsm_fsm_start = CAN_FIRE_RL_xmas_fsm_fsm_start ;
// rule RL_xmas_fsm_action_l42c32
assign CAN_FIRE_RL_xmas_fsm_action_l42c32 =
uart_fifoXmit$FULL_N &&
(op_mode && xmas_fsm_start_wire$whas &&
xmas_fsm_state_mkFSMstate == 5'd0 ||
op_mode && xmas_fsm_state_mkFSMstate == 5'd25) ;
assign WILL_FIRE_RL_xmas_fsm_action_l42c32 =
CAN_FIRE_RL_xmas_fsm_action_l42c32 ;
// rule __me_check_34
assign CAN_FIRE___me_check_34 = 1'b1 ;
assign WILL_FIRE___me_check_34 = 1'b1 ;
// rule RL_uart_fifoXmit__updateLevelCounter
assign CAN_FIRE_RL_uart_fifoXmit__updateLevelCounter =
uart_fifoXmit_r_enq$whas !=
CAN_FIRE_RL_uart_transmit_buffer_load ;
assign WILL_FIRE_RL_uart_fifoXmit__updateLevelCounter =
CAN_FIRE_RL_uart_fifoXmit__updateLevelCounter ;
// rule RL_xmas_fsm_idle_l40c27
assign CAN_FIRE_RL_xmas_fsm_idle_l40c27 =
!op_mode && xmas_fsm_start_wire$whas &&
xmas_fsm_state_mkFSMstate == 5'd0 ;
assign WILL_FIRE_RL_xmas_fsm_idle_l40c27 =
CAN_FIRE_RL_xmas_fsm_idle_l40c27 ;
// rule RL_xmas_fsm_start_reg__dreg_update
assign CAN_FIRE_RL_xmas_fsm_start_reg__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_xmas_fsm_start_reg__dreg_update = 1'd1 ;
// rule RL_xmas_fsm_state_handle_abort
assign CAN_FIRE_RL_xmas_fsm_state_handle_abort = 1'b0 ;
assign WILL_FIRE_RL_xmas_fsm_state_handle_abort = 1'b0 ;
// rule RL_xmas_fsm_state_every
assign CAN_FIRE_RL_xmas_fsm_state_every = 1'd1 ;
assign WILL_FIRE_RL_xmas_fsm_state_every = 1'd1 ;
// rule RL_xmas_fsm_state_fired__dreg_update
assign CAN_FIRE_RL_xmas_fsm_state_fired__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_xmas_fsm_state_fired__dreg_update = 1'd1 ;
// inputs to muxes for submodule ports
assign MUX_transmit_state$write_1__SEL_1 =
WILL_FIRE_RL_get_result || EN_startup_value ;
assign MUX_uart_fifoXmit$enq_1__SEL_2 =
WILL_FIRE_RL_xmas_fsm_action_l66c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_3 =
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_11 =
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_15 =
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_16 =
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_17 =
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ;
assign MUX_uart_rRecvState$write_1__SEL_6 =
WILL_FIRE_RL_uart_receive_parity_bit ||
WILL_FIRE_RL_uart_receive_sample_pin ;
assign MUX_uart_rXmitDataOut$write_1__SEL_1 =
WILL_FIRE_RL_uart_transmit_shift_next_bit ||
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ;
assign MUX_uart_rXmitDataOut$write_1__SEL_2 =
WILL_FIRE_RL_uart_transmit_send_parity_bit ||
WILL_FIRE_RL_uart_transmit_send_start_bit ;
assign MUX_uart_rXmitDataOut$write_1__SEL_3 =
WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit ||
WILL_FIRE_RL_uart_transmit_wait_for_start_command ;
assign MUX_xmas_fsm_start_reg$write_1__SEL_1 =
EN_operation_mode && operation_mode_arg == 8'hA5 ;
assign MUX_xmas_fsm_state_mkFSMstate$write_1__SEL_1 =
WILL_FIRE_RL_xmas_fsm_idle_l40c27_1 ||
WILL_FIRE_RL_xmas_fsm_idle_l40c27 ;
assign MUX_uart_rRecvState$write_1__VAL_1 = uart_rRecvData ? 3'd0 : 3'd1 ;
assign MUX_uart_rRecvState$write_1__VAL_2 =
(uart_rRecvCellCount == 4'h4) ?
(uart_rRecvData ? 3'd0 : 3'd2) :
3'd1 ;
always@(uart_rRecvBitCount)
begin
case (uart_rRecvBitCount)
4'd8, 4'd9, 4'd10: MUX_uart_rRecvState$write_1__VAL_3 = 3'd6;
default: MUX_uart_rRecvState$write_1__VAL_3 = 3'd3;
endcase
end
assign MUX_uart_rRecvState$write_1__VAL_4 = uart_rRecvData ? 3'd2 : 3'd0 ;
assign MUX_uart_rXmitState$write_1__VAL_1 =
uart_fifoXmit$EMPTY_N ? 3'd1 : 3'd0 ;
assign MUX_uart_rXmitState$write_1__VAL_2 =
(uart_rXmitCellCount == 4'hF) ? 3'd2 : 3'd1 ;
assign MUX_uart_rXmitState$write_1__VAL_3 =
(uart_rXmitCellCount == 4'hF) ?
((uart_rXmitBitCount == 4'd7) ? 3'd4 : 3'd3) :
3'd2 ;
assign MUX_uart_rXmitState$write_1__VAL_4 =
(uart_rXmitCellCount == 4'hF) ? 3'd4 : 3'd7 ;
assign MUX_uart_rXmitState$write_1__VAL_5 =
(uart_rXmitCellCount == 4'hF) ? 3'd0 : 3'd4 ;
assign MUX_uart_rXmitState$write_1__VAL_6 =
(uart_rXmitCellCount == 4'h7) ? 3'd0 : 3'd5 ;
assign MUX_uart_rXmitState$write_1__VAL_7 =
(uart_rXmitCellCount == 4'hF) ? 3'd0 : 3'd6 ;
// inlined wires
assign xmas_fsm_start_wire$whas =
WILL_FIRE_RL_xmas_fsm_fsm_start ||
WILL_FIRE_RL_xmas_fsm_restart ;
assign uart_pwRecvCellCountReset$whas =
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell &&
uart_rRecvCellCount == 4'h4 ||
WILL_FIRE_RL_uart_receive_stop_last_bit ||
WILL_FIRE_RL_uart_receive_stop_first_bit ||
WILL_FIRE_RL_uart_receive_parity_bit ||
WILL_FIRE_RL_uart_receive_sample_pin ||
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample ||
WILL_FIRE_RL_uart_receive_wait_for_start_bit ;
assign uart_pwRecvResetBitCount$whas =
WILL_FIRE_RL_uart_receive_wait_for_start_bit && uart_rRecvData ;
assign uart_pwRecvEnableBitCount$whas =
WILL_FIRE_RL_uart_receive_stop_first_bit ||
WILL_FIRE_RL_uart_receive_parity_bit ||
WILL_FIRE_RL_uart_receive_sample_pin ;
assign uart_fifoXmit_r_enq$whas =
WILL_FIRE_RL_get_result || WILL_FIRE_RL_xmas_fsm_action_l66c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ||
WILL_FIRE_RL_xmas_fsm_action_l64c32 ||
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l62c32 ||
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ||
WILL_FIRE_RL_xmas_fsm_action_l57c32 ||
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l55c32 ||
WILL_FIRE_RL_xmas_fsm_action_l54c32 ||
WILL_FIRE_RL_xmas_fsm_action_l53c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ||
WILL_FIRE_RL_xmas_fsm_action_l49c32 ||
WILL_FIRE_RL_xmas_fsm_action_l48c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ||
WILL_FIRE_RL_xmas_fsm_action_l46c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ||
WILL_FIRE_RL_xmas_fsm_action_l43c32 ||
WILL_FIRE_RL_xmas_fsm_action_l42c32 ;
assign uart_pwXmitCellCountReset$whas =
WILL_FIRE_RL_uart_transmit_wait_for_start_command &&
uart_fifoXmit$EMPTY_N ||
_dor2uart_pwXmitCellCountReset$EN_wset &&
uart_rXmitCellCount == 4'hF ||
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 &&
uart_rXmitCellCount == 4'h7 ;
assign uart_pwXmitEnableBitCount$whas =
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time &&
uart_rXmitCellCount == 4'hF &&
uart_rXmitBitCount != 4'd7 ;
assign uart_pwXmitLoadBuffer$whas =
WILL_FIRE_RL_uart_transmit_wait_for_start_command &&
uart_fifoXmit$EMPTY_N ;
assign xmas_fsm_state_set_pw$whas =
WILL_FIRE_RL_xmas_fsm_idle_l40c27_1 ||
WILL_FIRE_RL_xmas_fsm_idle_l40c27 ||
WILL_FIRE_RL_xmas_fsm_action_l66c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ||
WILL_FIRE_RL_xmas_fsm_action_l64c32 ||
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l62c32 ||
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ||
WILL_FIRE_RL_xmas_fsm_action_l57c32 ||
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l55c32 ||
WILL_FIRE_RL_xmas_fsm_action_l54c32 ||
WILL_FIRE_RL_xmas_fsm_action_l53c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ||
WILL_FIRE_RL_xmas_fsm_action_l49c32 ||
WILL_FIRE_RL_xmas_fsm_action_l48c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ||
WILL_FIRE_RL_xmas_fsm_action_l46c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ||
WILL_FIRE_RL_xmas_fsm_action_l43c32 ||
WILL_FIRE_RL_xmas_fsm_action_l42c32 ;
// register a
assign a$D_IN = EN_startup_value ? startup_value_v : rule30$getResult ;
assign a$EN = EN_startup_value || WILL_FIRE_RL_get_result ;
// register op_mode
assign op_mode$D_IN = 1'd1 ;
assign op_mode$EN = MUX_xmas_fsm_start_reg$write_1__SEL_1 ;
// register transmit_state
assign transmit_state$D_IN =
MUX_transmit_state$write_1__SEL_1 ? 2'd1 : 2'd2 ;
assign transmit_state$EN =
WILL_FIRE_RL_get_result || EN_startup_value ||
WILL_FIRE_RL_compute ;
// register uart_rRecvBitCount
assign uart_rRecvBitCount$D_IN =
uart_pwRecvResetBitCount$whas ? 4'd0 : x__h4689 ;
assign uart_rRecvBitCount$EN =
uart_pwRecvResetBitCount$whas || uart_pwRecvEnableBitCount$whas ;
// register uart_rRecvCellCount
assign uart_rRecvCellCount$D_IN =
uart_pwRecvCellCountReset$whas ? 4'd0 : x__h2985 ;
assign uart_rRecvCellCount$EN =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// register uart_rRecvData
assign uart_rRecvData$D_IN = txrx_SIN ;
assign uart_rRecvData$EN = 1'd1 ;
// register uart_rRecvState
always@(WILL_FIRE_RL_uart_receive_wait_for_start_bit or
MUX_uart_rRecvState$write_1__VAL_1 or
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell or
MUX_uart_rRecvState$write_1__VAL_2 or
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample or
MUX_uart_rRecvState$write_1__VAL_3 or
WILL_FIRE_RL_uart_receive_stop_first_bit or
MUX_uart_rRecvState$write_1__VAL_4 or
WILL_FIRE_RL_uart_receive_stop_last_bit or
MUX_uart_rRecvState$write_1__SEL_6)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_uart_receive_wait_for_start_bit:
uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_1;
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell:
uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_2;
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample:
uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_3;
WILL_FIRE_RL_uart_receive_stop_first_bit:
uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_4;
WILL_FIRE_RL_uart_receive_stop_last_bit: uart_rRecvState$D_IN = 3'd0;
MUX_uart_rRecvState$write_1__SEL_6: uart_rRecvState$D_IN = 3'd2;
default: uart_rRecvState$D_IN = 3'b010 /* unspecified value */ ;
endcase
end
assign uart_rRecvState$EN =
WILL_FIRE_RL_uart_receive_wait_for_start_bit ||
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell ||
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample ||
WILL_FIRE_RL_uart_receive_stop_first_bit ||
WILL_FIRE_RL_uart_receive_stop_last_bit ||
WILL_FIRE_RL_uart_receive_parity_bit ||
WILL_FIRE_RL_uart_receive_sample_pin ;
// register uart_rXmitBitCount
assign uart_rXmitBitCount$D_IN =
CAN_FIRE_RL_uart_transmit_wait_for_start_command ?
4'd0 :
x__h6471 ;
assign uart_rXmitBitCount$EN =
CAN_FIRE_RL_uart_transmit_wait_for_start_command ||
uart_pwXmitEnableBitCount$whas ;
// register uart_rXmitCellCount
assign uart_rXmitCellCount$D_IN =
uart_pwXmitCellCountReset$whas ? 4'd0 : x__h6445 ;
assign uart_rXmitCellCount$EN =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// register uart_rXmitDataOut
always@(MUX_uart_rXmitDataOut$write_1__SEL_1 or
uart_vrXmitBuffer_0 or
MUX_uart_rXmitDataOut$write_1__SEL_2 or
MUX_uart_rXmitDataOut$write_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_uart_rXmitDataOut$write_1__SEL_1:
uart_rXmitDataOut$D_IN = uart_vrXmitBuffer_0;
MUX_uart_rXmitDataOut$write_1__SEL_2: uart_rXmitDataOut$D_IN = 1'b0;
MUX_uart_rXmitDataOut$write_1__SEL_3: uart_rXmitDataOut$D_IN = 1'b1;
default: uart_rXmitDataOut$D_IN = 1'b0 /* unspecified value */ ;
endcase
end
assign uart_rXmitDataOut$EN =
WILL_FIRE_RL_uart_transmit_shift_next_bit ||
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ||
WILL_FIRE_RL_uart_transmit_send_parity_bit ||
WILL_FIRE_RL_uart_transmit_send_start_bit ||
WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit ||
WILL_FIRE_RL_uart_transmit_wait_for_start_command ;
// register uart_rXmitState
always@(WILL_FIRE_RL_uart_transmit_wait_for_start_command or
MUX_uart_rXmitState$write_1__VAL_1 or
WILL_FIRE_RL_uart_transmit_send_start_bit or
MUX_uart_rXmitState$write_1__VAL_2 or
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time or
MUX_uart_rXmitState$write_1__VAL_3 or
WILL_FIRE_RL_uart_transmit_send_parity_bit or
MUX_uart_rXmitState$write_1__VAL_4 or
WILL_FIRE_RL_uart_transmit_send_stop_bit or
MUX_uart_rXmitState$write_1__VAL_5 or
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 or
MUX_uart_rXmitState$write_1__VAL_6 or
WILL_FIRE_RL_uart_transmit_send_stop_bit2 or
MUX_uart_rXmitState$write_1__VAL_7 or
WILL_FIRE_RL_uart_transmit_shift_next_bit)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_uart_transmit_wait_for_start_command:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_1;
WILL_FIRE_RL_uart_transmit_send_start_bit:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_2;
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_3;
WILL_FIRE_RL_uart_transmit_send_parity_bit:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_4;
WILL_FIRE_RL_uart_transmit_send_stop_bit:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_5;
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_6;
WILL_FIRE_RL_uart_transmit_send_stop_bit2:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_7;
WILL_FIRE_RL_uart_transmit_shift_next_bit: uart_rXmitState$D_IN = 3'd2;
default: uart_rXmitState$D_IN = 3'b010 /* unspecified value */ ;
endcase
end
assign uart_rXmitState$EN =
WILL_FIRE_RL_uart_transmit_wait_for_start_command ||
WILL_FIRE_RL_uart_transmit_send_start_bit ||
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ||
WILL_FIRE_RL_uart_transmit_send_parity_bit ||
WILL_FIRE_RL_uart_transmit_send_stop_bit ||
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
WILL_FIRE_RL_uart_transmit_shift_next_bit ;
// register uart_vrRecvBuffer_0
assign uart_vrRecvBuffer_0$D_IN = uart_vrRecvBuffer_1 ;
assign uart_vrRecvBuffer_0$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_1
assign uart_vrRecvBuffer_1$D_IN = uart_vrRecvBuffer_2 ;
assign uart_vrRecvBuffer_1$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_2
assign uart_vrRecvBuffer_2$D_IN = uart_vrRecvBuffer_3 ;
assign uart_vrRecvBuffer_2$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_3
assign uart_vrRecvBuffer_3$D_IN = uart_vrRecvBuffer_4 ;
assign uart_vrRecvBuffer_3$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_4
assign uart_vrRecvBuffer_4$D_IN = uart_vrRecvBuffer_5 ;
assign uart_vrRecvBuffer_4$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_5
assign uart_vrRecvBuffer_5$D_IN = uart_vrRecvBuffer_6 ;
assign uart_vrRecvBuffer_5$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_6
assign uart_vrRecvBuffer_6$D_IN = uart_vrRecvBuffer_7 ;
assign uart_vrRecvBuffer_6$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_7
assign uart_vrRecvBuffer_7$D_IN = uart_rRecvData ;
assign uart_vrRecvBuffer_7$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrXmitBuffer_0
assign uart_vrXmitBuffer_0$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[0] :
uart_vrXmitBuffer_1 ;
assign uart_vrXmitBuffer_0$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_1
assign uart_vrXmitBuffer_1$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[1] :
uart_vrXmitBuffer_2 ;
assign uart_vrXmitBuffer_1$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_2
assign uart_vrXmitBuffer_2$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[2] :
uart_vrXmitBuffer_3 ;
assign uart_vrXmitBuffer_2$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_3
assign uart_vrXmitBuffer_3$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[3] :
uart_vrXmitBuffer_4 ;
assign uart_vrXmitBuffer_3$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_4
assign uart_vrXmitBuffer_4$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[4] :
uart_vrXmitBuffer_5 ;
assign uart_vrXmitBuffer_4$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_5
assign uart_vrXmitBuffer_5$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[5] :
uart_vrXmitBuffer_6 ;
assign uart_vrXmitBuffer_5$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_6
assign uart_vrXmitBuffer_6$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[6] :
uart_vrXmitBuffer_7 ;
assign uart_vrXmitBuffer_6$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_7
assign uart_vrXmitBuffer_7$D_IN =
!WILL_FIRE_RL_uart_transmit_buffer_load ||
uart_fifoXmit$D_OUT[7] ;
assign uart_vrXmitBuffer_7$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register xmas_fsm_start_reg
assign xmas_fsm_start_reg$D_IN = MUX_xmas_fsm_start_reg$write_1__SEL_1 ;
assign xmas_fsm_start_reg$EN =
EN_operation_mode && operation_mode_arg == 8'hA5 ||
WILL_FIRE_RL_xmas_fsm_fsm_start ;
// register xmas_fsm_start_reg_1
assign xmas_fsm_start_reg_1$D_IN = xmas_fsm_start_wire$whas ;
assign xmas_fsm_start_reg_1$EN = 1'd1 ;
// register xmas_fsm_state_fired
assign xmas_fsm_state_fired$D_IN = xmas_fsm_state_set_pw$whas ;
assign xmas_fsm_state_fired$EN = 1'd1 ;
// register xmas_fsm_state_mkFSMstate
always@(MUX_xmas_fsm_state_mkFSMstate$write_1__SEL_1 or
WILL_FIRE_RL_xmas_fsm_action_l42c32 or
WILL_FIRE_RL_xmas_fsm_action_l43c32 or
WILL_FIRE_RL_xmas_fsm_action_l44c32 or
WILL_FIRE_RL_xmas_fsm_action_l45c32 or
WILL_FIRE_RL_xmas_fsm_action_l46c32 or
WILL_FIRE_RL_xmas_fsm_action_l47c32 or
WILL_FIRE_RL_xmas_fsm_action_l48c32 or
WILL_FIRE_RL_xmas_fsm_action_l49c32 or
WILL_FIRE_RL_xmas_fsm_action_l50c32 or
WILL_FIRE_RL_xmas_fsm_action_l51c32 or
WILL_FIRE_RL_xmas_fsm_action_l52c32 or
WILL_FIRE_RL_xmas_fsm_action_l53c32 or
WILL_FIRE_RL_xmas_fsm_action_l54c32 or
WILL_FIRE_RL_xmas_fsm_action_l55c32 or
WILL_FIRE_RL_xmas_fsm_action_l56c32 or
WILL_FIRE_RL_xmas_fsm_action_l57c32 or
WILL_FIRE_RL_xmas_fsm_action_l58c32 or
WILL_FIRE_RL_xmas_fsm_action_l59c32 or
WILL_FIRE_RL_xmas_fsm_action_l60c32 or
WILL_FIRE_RL_xmas_fsm_action_l61c32 or
WILL_FIRE_RL_xmas_fsm_action_l62c32 or
WILL_FIRE_RL_xmas_fsm_action_l63c32 or
WILL_FIRE_RL_xmas_fsm_action_l64c32 or
WILL_FIRE_RL_xmas_fsm_action_l65c32 or
WILL_FIRE_RL_xmas_fsm_action_l66c32)
begin
case (1'b1) // synopsys parallel_case
MUX_xmas_fsm_state_mkFSMstate$write_1__SEL_1:
xmas_fsm_state_mkFSMstate$D_IN = 5'd0;
WILL_FIRE_RL_xmas_fsm_action_l42c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd1;
WILL_FIRE_RL_xmas_fsm_action_l43c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd2;
WILL_FIRE_RL_xmas_fsm_action_l44c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd3;
WILL_FIRE_RL_xmas_fsm_action_l45c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd4;
WILL_FIRE_RL_xmas_fsm_action_l46c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd5;
WILL_FIRE_RL_xmas_fsm_action_l47c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd6;
WILL_FIRE_RL_xmas_fsm_action_l48c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd7;
WILL_FIRE_RL_xmas_fsm_action_l49c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd8;
WILL_FIRE_RL_xmas_fsm_action_l50c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd9;
WILL_FIRE_RL_xmas_fsm_action_l51c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd10;
WILL_FIRE_RL_xmas_fsm_action_l52c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd11;
WILL_FIRE_RL_xmas_fsm_action_l53c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd12;
WILL_FIRE_RL_xmas_fsm_action_l54c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd13;
WILL_FIRE_RL_xmas_fsm_action_l55c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd14;
WILL_FIRE_RL_xmas_fsm_action_l56c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd15;
WILL_FIRE_RL_xmas_fsm_action_l57c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd16;
WILL_FIRE_RL_xmas_fsm_action_l58c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd17;
WILL_FIRE_RL_xmas_fsm_action_l59c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd18;
WILL_FIRE_RL_xmas_fsm_action_l60c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd19;
WILL_FIRE_RL_xmas_fsm_action_l61c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd20;
WILL_FIRE_RL_xmas_fsm_action_l62c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd21;
WILL_FIRE_RL_xmas_fsm_action_l63c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd22;
WILL_FIRE_RL_xmas_fsm_action_l64c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd23;
WILL_FIRE_RL_xmas_fsm_action_l65c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd24;
WILL_FIRE_RL_xmas_fsm_action_l66c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd25;
default: xmas_fsm_state_mkFSMstate$D_IN =
5'b01010 /* unspecified value */ ;
endcase
end
assign xmas_fsm_state_mkFSMstate$EN =
WILL_FIRE_RL_xmas_fsm_idle_l40c27_1 ||
WILL_FIRE_RL_xmas_fsm_idle_l40c27 ||
WILL_FIRE_RL_xmas_fsm_action_l42c32 ||
WILL_FIRE_RL_xmas_fsm_action_l43c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l46c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ||
WILL_FIRE_RL_xmas_fsm_action_l48c32 ||
WILL_FIRE_RL_xmas_fsm_action_l49c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l53c32 ||
WILL_FIRE_RL_xmas_fsm_action_l54c32 ||
WILL_FIRE_RL_xmas_fsm_action_l55c32 ||
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l57c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ||
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l62c32 ||
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l64c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ||
WILL_FIRE_RL_xmas_fsm_action_l66c32 ;
// submodule rule30
assign rule30$start_a = a ;
assign rule30$EN_start = CAN_FIRE_RL_compute ;
assign rule30$EN_getResult = CAN_FIRE_RL_get_result ;
// submodule uart_baudGen_rBaudCounter
assign uart_baudGen_rBaudCounter$DATA_A = 16'd1 ;
assign uart_baudGen_rBaudCounter$DATA_B = 16'h0 ;
assign uart_baudGen_rBaudCounter$DATA_C = 16'h0 ;
assign uart_baudGen_rBaudCounter$DATA_F = 16'd0 ;
assign uart_baudGen_rBaudCounter$ADDA =
uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign uart_baudGen_rBaudCounter$ADDB = 1'b0 ;
assign uart_baudGen_rBaudCounter$SETC = 1'b0 ;
assign uart_baudGen_rBaudCounter$SETF =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// submodule uart_baudGen_rBaudTickCounter
assign uart_baudGen_rBaudTickCounter$DATA_A = 3'd1 ;
assign uart_baudGen_rBaudTickCounter$DATA_B = 3'h0 ;
assign uart_baudGen_rBaudTickCounter$DATA_C = 3'h0 ;
assign uart_baudGen_rBaudTickCounter$DATA_F = 3'h0 ;
assign uart_baudGen_rBaudTickCounter$ADDA =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
assign uart_baudGen_rBaudTickCounter$ADDB = 1'b0 ;
assign uart_baudGen_rBaudTickCounter$SETC = 1'b0 ;
assign uart_baudGen_rBaudTickCounter$SETF = 1'b0 ;
// submodule uart_fifoRecv
assign uart_fifoRecv$D_IN =
{ uart_vrRecvBuffer_7,
uart_vrRecvBuffer_6,
uart_vrRecvBuffer_5,
uart_vrRecvBuffer_4,
uart_vrRecvBuffer_3,
uart_vrRecvBuffer_2,
uart_vrRecvBuffer_1,
uart_vrRecvBuffer_0 } ;
assign uart_fifoRecv$ENQ = CAN_FIRE_RL_uart_receive_stop_last_bit ;
assign uart_fifoRecv$DEQ = uart_fifoRecv$EMPTY_N ;
assign uart_fifoRecv$CLR = 1'b0 ;
// submodule uart_fifoXmit
always@(WILL_FIRE_RL_get_result or
rule30$getResult or
MUX_uart_fifoXmit$enq_1__SEL_2 or
MUX_uart_fifoXmit$enq_1__SEL_3 or
WILL_FIRE_RL_xmas_fsm_action_l64c32 or
WILL_FIRE_RL_xmas_fsm_action_l53c32 or
WILL_FIRE_RL_xmas_fsm_action_l54c32 or
WILL_FIRE_RL_xmas_fsm_action_l55c32 or
WILL_FIRE_RL_xmas_fsm_action_l42c32 or
WILL_FIRE_RL_xmas_fsm_action_l57c32 or
WILL_FIRE_RL_xmas_fsm_action_l48c32 or
MUX_uart_fifoXmit$enq_1__SEL_11 or
WILL_FIRE_RL_xmas_fsm_action_l43c32 or
WILL_FIRE_RL_xmas_fsm_action_l49c32 or
WILL_FIRE_RL_xmas_fsm_action_l62c32 or
MUX_uart_fifoXmit$enq_1__SEL_15 or
MUX_uart_fifoXmit$enq_1__SEL_16 or
MUX_uart_fifoXmit$enq_1__SEL_17 or
WILL_FIRE_RL_xmas_fsm_action_l46c32)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_get_result: uart_fifoXmit$D_IN = rule30$getResult;
MUX_uart_fifoXmit$enq_1__SEL_2: uart_fifoXmit$D_IN = 8'h09;
MUX_uart_fifoXmit$enq_1__SEL_3: uart_fifoXmit$D_IN = 8'h20;
WILL_FIRE_RL_xmas_fsm_action_l64c32: uart_fifoXmit$D_IN = 8'h21;
WILL_FIRE_RL_xmas_fsm_action_l53c32: uart_fifoXmit$D_IN = 8'h27;
WILL_FIRE_RL_xmas_fsm_action_l54c32: uart_fifoXmit$D_IN = 8'h32;
WILL_FIRE_RL_xmas_fsm_action_l55c32: uart_fifoXmit$D_IN = 8'h34;
WILL_FIRE_RL_xmas_fsm_action_l42c32: uart_fifoXmit$D_IN = 8'h4D;
WILL_FIRE_RL_xmas_fsm_action_l57c32: uart_fifoXmit$D_IN = 8'h53;
WILL_FIRE_RL_xmas_fsm_action_l48c32: uart_fifoXmit$D_IN = 8'h58;
MUX_uart_fifoXmit$enq_1__SEL_11: uart_fifoXmit$D_IN = 8'h61;
WILL_FIRE_RL_xmas_fsm_action_l43c32: uart_fifoXmit$D_IN = 8'h65;
WILL_FIRE_RL_xmas_fsm_action_l49c32: uart_fifoXmit$D_IN = 8'h6D;
WILL_FIRE_RL_xmas_fsm_action_l62c32: uart_fifoXmit$D_IN = 8'h6F;
MUX_uart_fifoXmit$enq_1__SEL_15: uart_fifoXmit$D_IN = 8'h72;
MUX_uart_fifoXmit$enq_1__SEL_16: uart_fifoXmit$D_IN = 8'h73;
MUX_uart_fifoXmit$enq_1__SEL_17: uart_fifoXmit$D_IN = 8'h74;
WILL_FIRE_RL_xmas_fsm_action_l46c32: uart_fifoXmit$D_IN = 8'h79;
default: uart_fifoXmit$D_IN = 8'b10101010 /* unspecified value */ ;
endcase
end
assign uart_fifoXmit$ENQ =
WILL_FIRE_RL_get_result || WILL_FIRE_RL_xmas_fsm_action_l66c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ||
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ||
WILL_FIRE_RL_xmas_fsm_action_l64c32 ||
WILL_FIRE_RL_xmas_fsm_action_l53c32 ||
WILL_FIRE_RL_xmas_fsm_action_l54c32 ||
WILL_FIRE_RL_xmas_fsm_action_l55c32 ||
WILL_FIRE_RL_xmas_fsm_action_l42c32 ||
WILL_FIRE_RL_xmas_fsm_action_l57c32 ||
WILL_FIRE_RL_xmas_fsm_action_l48c32 ||
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ||
WILL_FIRE_RL_xmas_fsm_action_l43c32 ||
WILL_FIRE_RL_xmas_fsm_action_l49c32 ||
WILL_FIRE_RL_xmas_fsm_action_l62c32 ||
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ||
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ||
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ||
WILL_FIRE_RL_xmas_fsm_action_l46c32 ;
assign uart_fifoXmit$DEQ = CAN_FIRE_RL_uart_transmit_buffer_load ;
assign uart_fifoXmit$CLR = 1'b0 ;
// remaining internal signals
assign _dor2uart_pwXmitCellCountReset$EN_wset =
WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit ||
WILL_FIRE_RL_uart_transmit_send_parity_bit ||
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ||
WILL_FIRE_RL_uart_transmit_send_start_bit ;
assign uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 =
uart_baudGen_rBaudCounter$Q_OUT + 16'd1 < 16'd27 ;
assign x__h2985 = uart_rRecvCellCount + 4'd1 ;
assign x__h4689 = uart_rRecvBitCount + 4'd1 ;
assign x__h6445 = uart_rXmitCellCount + 4'd1 ;
assign x__h6471 = uart_rXmitBitCount + 4'd1 ;
assign xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302 =
(xmas_fsm_state_mkFSMstate == 5'd0 ||
xmas_fsm_state_mkFSMstate == 5'd25 ||
xmas_fsm_state_mkFSMstate == 5'd27) &&
(!xmas_fsm_start_reg_1 || xmas_fsm_state_fired) ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
a <= `BSV_ASSIGNMENT_DELAY 8'b0;
op_mode <= `BSV_ASSIGNMENT_DELAY 1'd0;
transmit_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
uart_rRecvData <= `BSV_ASSIGNMENT_DELAY 1'd1;
xmas_fsm_start_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
xmas_fsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
xmas_fsm_state_fired <= `BSV_ASSIGNMENT_DELAY 1'd0;
xmas_fsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY 5'd0;
end
else
begin
if (a$EN) a <= `BSV_ASSIGNMENT_DELAY a$D_IN;
if (op_mode$EN) op_mode <= `BSV_ASSIGNMENT_DELAY op_mode$D_IN;
if (transmit_state$EN)
transmit_state <= `BSV_ASSIGNMENT_DELAY transmit_state$D_IN;
if (uart_rRecvData$EN)
uart_rRecvData <= `BSV_ASSIGNMENT_DELAY uart_rRecvData$D_IN;
if (xmas_fsm_start_reg$EN)
xmas_fsm_start_reg <= `BSV_ASSIGNMENT_DELAY xmas_fsm_start_reg$D_IN;
if (xmas_fsm_start_reg_1$EN)
xmas_fsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY
xmas_fsm_start_reg_1$D_IN;
if (xmas_fsm_state_fired$EN)
xmas_fsm_state_fired <= `BSV_ASSIGNMENT_DELAY
xmas_fsm_state_fired$D_IN;
if (xmas_fsm_state_mkFSMstate$EN)
xmas_fsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY
xmas_fsm_state_mkFSMstate$D_IN;
end
if (uart_vrRecvBuffer_0$EN)
uart_vrRecvBuffer_0 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_0$D_IN;
if (uart_vrRecvBuffer_1$EN)
uart_vrRecvBuffer_1 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_1$D_IN;
if (uart_vrRecvBuffer_2$EN)
uart_vrRecvBuffer_2 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_2$D_IN;
if (uart_vrRecvBuffer_3$EN)
uart_vrRecvBuffer_3 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_3$D_IN;
if (uart_vrRecvBuffer_4$EN)
uart_vrRecvBuffer_4 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_4$D_IN;
if (uart_vrRecvBuffer_5$EN)
uart_vrRecvBuffer_5 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_5$D_IN;
if (uart_vrRecvBuffer_6$EN)
uart_vrRecvBuffer_6 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_6$D_IN;
if (uart_vrRecvBuffer_7$EN)
uart_vrRecvBuffer_7 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_7$D_IN;
if (uart_vrXmitBuffer_0$EN)
uart_vrXmitBuffer_0 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_0$D_IN;
if (uart_vrXmitBuffer_1$EN)
uart_vrXmitBuffer_1 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_1$D_IN;
if (uart_vrXmitBuffer_2$EN)
uart_vrXmitBuffer_2 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_2$D_IN;
if (uart_vrXmitBuffer_3$EN)
uart_vrXmitBuffer_3 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_3$D_IN;
if (uart_vrXmitBuffer_4$EN)
uart_vrXmitBuffer_4 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_4$D_IN;
if (uart_vrXmitBuffer_5$EN)
uart_vrXmitBuffer_5 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_5$D_IN;
if (uart_vrXmitBuffer_6$EN)
uart_vrXmitBuffer_6 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_6$D_IN;
if (uart_vrXmitBuffer_7$EN)
uart_vrXmitBuffer_7 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_7$D_IN;
end
always@(posedge CLK or `BSV_RESET_EDGE RST_N)
if (RST_N == `BSV_RESET_VALUE)
begin
uart_rRecvBitCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
uart_rRecvCellCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
uart_rRecvState <= `BSV_ASSIGNMENT_DELAY 3'd0;
uart_rXmitBitCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
uart_rXmitCellCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
uart_rXmitDataOut <= `BSV_ASSIGNMENT_DELAY 1'd1;
uart_rXmitState <= `BSV_ASSIGNMENT_DELAY 3'd0;
end
else
begin
if (uart_rRecvBitCount$EN)
uart_rRecvBitCount <= `BSV_ASSIGNMENT_DELAY uart_rRecvBitCount$D_IN;
if (uart_rRecvCellCount$EN)
uart_rRecvCellCount <= `BSV_ASSIGNMENT_DELAY uart_rRecvCellCount$D_IN;
if (uart_rRecvState$EN)
uart_rRecvState <= `BSV_ASSIGNMENT_DELAY uart_rRecvState$D_IN;
if (uart_rXmitBitCount$EN)
uart_rXmitBitCount <= `BSV_ASSIGNMENT_DELAY uart_rXmitBitCount$D_IN;
if (uart_rXmitCellCount$EN)
uart_rXmitCellCount <= `BSV_ASSIGNMENT_DELAY uart_rXmitCellCount$D_IN;
if (uart_rXmitDataOut$EN)
uart_rXmitDataOut <= `BSV_ASSIGNMENT_DELAY uart_rXmitDataOut$D_IN;
if (uart_rXmitState$EN)
uart_rXmitState <= `BSV_ASSIGNMENT_DELAY uart_rXmitState$D_IN;
end
// handling of system tasks
endmodule
|
tt06-finale_0055
|
tt06-finale
|
andrewtron3000-tt06-verilog-template
|
task_tt_um_andrewtron3000
|
tt_um_andrewtron3000
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 andrewtron3000
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_andrewtron3000 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
//
// Generated by Bluespec Compiler, version 2024.01-1-g4d953407 (build 4d953407)
//
// On Thu Apr 18 23:03:53 EDT 2024
//
//
// Ports:
// Name I/O size props
// RDY_operation_mode O 1
// RDY_startup_value O 1
// txrx_SOUT O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// operation_mode_arg I 8
// startup_value_v I 8
// txrx_SIN I 1 reg
// EN_operation_mode I 1
// EN_startup_value I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkRule30Driver(CLK,
RST_N,
operation_mode_arg,
EN_operation_mode,
RDY_operation_mode,
startup_value_v,
EN_startup_value,
RDY_startup_value,
txrx_SIN,
txrx_SOUT);
input CLK;
input RST_N;
// action method operation_mode
input [7 : 0] operation_mode_arg;
input EN_operation_mode;
output RDY_operation_mode;
// action method startup_value
input [7 : 0] startup_value_v;
input EN_startup_value;
output RDY_startup_value;
// action method txrx_sin
input txrx_SIN;
// value method txrx_sout
output txrx_SOUT;
// signals for module outputs
wire RDY_operation_mode, RDY_startup_value, txrx_SOUT;
// inlined wires
wire uart_fifoXmit_r_enq$whas,
uart_pwRecvCellCountReset$whas,
uart_pwRecvEnableBitCount$whas,
uart_pwRecvResetBitCount$whas,
uart_pwXmitCellCountReset$whas,
uart_pwXmitEnableBitCount$whas,
uart_pwXmitLoadBuffer$whas,
xmas_fsm_start_wire$whas,
xmas_fsm_state_set_pw$whas;
// register a
reg [7 : 0] a;
wire [7 : 0] a$D_IN;
wire a$EN;
// register op_mode
reg op_mode;
wire op_mode$D_IN, op_mode$EN;
// register transmit_state
reg [1 : 0] transmit_state;
wire [1 : 0] transmit_state$D_IN;
wire transmit_state$EN;
// register uart_rRecvBitCount
reg [3 : 0] uart_rRecvBitCount;
wire [3 : 0] uart_rRecvBitCount$D_IN;
wire uart_rRecvBitCount$EN;
// register uart_rRecvCellCount
reg [3 : 0] uart_rRecvCellCount;
wire [3 : 0] uart_rRecvCellCount$D_IN;
wire uart_rRecvCellCount$EN;
// register uart_rRecvData
reg uart_rRecvData;
wire uart_rRecvData$D_IN, uart_rRecvData$EN;
// register uart_rRecvState
reg [2 : 0] uart_rRecvState;
reg [2 : 0] uart_rRecvState$D_IN;
wire uart_rRecvState$EN;
// register uart_rXmitBitCount
reg [3 : 0] uart_rXmitBitCount;
wire [3 : 0] uart_rXmitBitCount$D_IN;
wire uart_rXmitBitCount$EN;
// register uart_rXmitCellCount
reg [3 : 0] uart_rXmitCellCount;
wire [3 : 0] uart_rXmitCellCount$D_IN;
wire uart_rXmitCellCount$EN;
// register uart_rXmitDataOut
reg uart_rXmitDataOut;
reg uart_rXmitDataOut$D_IN;
wire uart_rXmitDataOut$EN;
// register uart_rXmitState
reg [2 : 0] uart_rXmitState;
reg [2 : 0] uart_rXmitState$D_IN;
wire uart_rXmitState$EN;
// register uart_vrRecvBuffer_0
reg uart_vrRecvBuffer_0;
wire uart_vrRecvBuffer_0$D_IN, uart_vrRecvBuffer_0$EN;
// register uart_vrRecvBuffer_1
reg uart_vrRecvBuffer_1;
wire uart_vrRecvBuffer_1$D_IN, uart_vrRecvBuffer_1$EN;
// register uart_vrRecvBuffer_2
reg uart_vrRecvBuffer_2;
wire uart_vrRecvBuffer_2$D_IN, uart_vrRecvBuffer_2$EN;
// register uart_vrRecvBuffer_3
reg uart_vrRecvBuffer_3;
wire uart_vrRecvBuffer_3$D_IN, uart_vrRecvBuffer_3$EN;
// register uart_vrRecvBuffer_4
reg uart_vrRecvBuffer_4;
wire uart_vrRecvBuffer_4$D_IN, uart_vrRecvBuffer_4$EN;
// register uart_vrRecvBuffer_5
reg uart_vrRecvBuffer_5;
wire uart_vrRecvBuffer_5$D_IN, uart_vrRecvBuffer_5$EN;
// register uart_vrRecvBuffer_6
reg uart_vrRecvBuffer_6;
wire uart_vrRecvBuffer_6$D_IN, uart_vrRecvBuffer_6$EN;
// register uart_vrRecvBuffer_7
reg uart_vrRecvBuffer_7;
wire uart_vrRecvBuffer_7$D_IN, uart_vrRecvBuffer_7$EN;
// register uart_vrXmitBuffer_0
reg uart_vrXmitBuffer_0;
wire uart_vrXmitBuffer_0$D_IN, uart_vrXmitBuffer_0$EN;
// register uart_vrXmitBuffer_1
reg uart_vrXmitBuffer_1;
wire uart_vrXmitBuffer_1$D_IN, uart_vrXmitBuffer_1$EN;
// register uart_vrXmitBuffer_2
reg uart_vrXmitBuffer_2;
wire uart_vrXmitBuffer_2$D_IN, uart_vrXmitBuffer_2$EN;
// register uart_vrXmitBuffer_3
reg uart_vrXmitBuffer_3;
wire uart_vrXmitBuffer_3$D_IN, uart_vrXmitBuffer_3$EN;
// register uart_vrXmitBuffer_4
reg uart_vrXmitBuffer_4;
wire uart_vrXmitBuffer_4$D_IN, uart_vrXmitBuffer_4$EN;
// register uart_vrXmitBuffer_5
reg uart_vrXmitBuffer_5;
wire uart_vrXmitBuffer_5$D_IN, uart_vrXmitBuffer_5$EN;
// register uart_vrXmitBuffer_6
reg uart_vrXmitBuffer_6;
wire uart_vrXmitBuffer_6$D_IN, uart_vrXmitBuffer_6$EN;
// register uart_vrXmitBuffer_7
reg uart_vrXmitBuffer_7;
wire uart_vrXmitBuffer_7$D_IN, uart_vrXmitBuffer_7$EN;
// register xmas_fsm_start_reg
reg xmas_fsm_start_reg;
wire xmas_fsm_start_reg$D_IN, xmas_fsm_start_reg$EN;
// register xmas_fsm_start_reg_1
reg xmas_fsm_start_reg_1;
wire xmas_fsm_start_reg_1$D_IN, xmas_fsm_start_reg_1$EN;
// register xmas_fsm_state_fired
reg xmas_fsm_state_fired;
wire xmas_fsm_state_fired$D_IN, xmas_fsm_state_fired$EN;
// register xmas_fsm_state_mkFSMstate
reg [4 : 0] xmas_fsm_state_mkFSMstate;
reg [4 : 0] xmas_fsm_state_mkFSMstate$D_IN;
wire xmas_fsm_state_mkFSMstate$EN;
// ports of submodule rule30
wire [7 : 0] rule30$getResult, rule30$start_a;
wire rule30$EN_getResult,
rule30$EN_start,
rule30$RDY_getResult,
rule30$RDY_start;
// ports of submodule uart_baudGen_rBaudCounter
wire [15 : 0] uart_baudGen_rBaudCounter$DATA_A,
uart_baudGen_rBaudCounter$DATA_B,
uart_baudGen_rBaudCounter$DATA_C,
uart_baudGen_rBaudCounter$DATA_F,
uart_baudGen_rBaudCounter$Q_OUT;
wire uart_baudGen_rBaudCounter$ADDA,
uart_baudGen_rBaudCounter$ADDB,
uart_baudGen_rBaudCounter$SETC,
uart_baudGen_rBaudCounter$SETF;
// ports of submodule uart_baudGen_rBaudTickCounter
wire [2 : 0] uart_baudGen_rBaudTickCounter$DATA_A,
uart_baudGen_rBaudTickCounter$DATA_B,
uart_baudGen_rBaudTickCounter$DATA_C,
uart_baudGen_rBaudTickCounter$DATA_F,
uart_baudGen_rBaudTickCounter$Q_OUT;
wire uart_baudGen_rBaudTickCounter$ADDA,
uart_baudGen_rBaudTickCounter$ADDB,
uart_baudGen_rBaudTickCounter$SETC,
uart_baudGen_rBaudTickCounter$SETF;
// ports of submodule uart_fifoRecv
wire [7 : 0] uart_fifoRecv$D_IN;
wire uart_fifoRecv$CLR,
uart_fifoRecv$DEQ,
uart_fifoRecv$EMPTY_N,
uart_fifoRecv$ENQ;
// ports of submodule uart_fifoXmit
reg [7 : 0] uart_fifoXmit$D_IN;
wire [7 : 0] uart_fifoXmit$D_OUT;
wire uart_fifoXmit$CLR,
uart_fifoXmit$DEQ,
uart_fifoXmit$EMPTY_N,
uart_fifoXmit$ENQ,
uart_fifoXmit$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_compute,
CAN_FIRE_RL_dump_rx,
CAN_FIRE_RL_get_result,
CAN_FIRE_RL_uart_baudGen_assert_2x_baud_tick,
CAN_FIRE_RL_uart_baudGen_baud_count_wire,
CAN_FIRE_RL_uart_baudGen_baud_tick_count_wire,
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x,
CAN_FIRE_RL_uart_baud_generator_clock_enable,
CAN_FIRE_RL_uart_fifoRecv__updateLevelCounter,
CAN_FIRE_RL_uart_fifoXmit__updateLevelCounter,
CAN_FIRE_RL_uart_receive_bit_cell_time_counter,
CAN_FIRE_RL_uart_receive_bit_counter,
CAN_FIRE_RL_uart_receive_buffer_shift,
CAN_FIRE_RL_uart_receive_find_center_of_bit_cell,
CAN_FIRE_RL_uart_receive_parity_bit,
CAN_FIRE_RL_uart_receive_sample_pin,
CAN_FIRE_RL_uart_receive_stop_first_bit,
CAN_FIRE_RL_uart_receive_stop_last_bit,
CAN_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample,
CAN_FIRE_RL_uart_receive_wait_for_start_bit,
CAN_FIRE_RL_uart_transmit_bit_cell_time_counter,
CAN_FIRE_RL_uart_transmit_bit_counter,
CAN_FIRE_RL_uart_transmit_buffer_load,
CAN_FIRE_RL_uart_transmit_buffer_shift,
CAN_FIRE_RL_uart_transmit_send_parity_bit,
CAN_FIRE_RL_uart_transmit_send_start_bit,
CAN_FIRE_RL_uart_transmit_send_stop_bit,
CAN_FIRE_RL_uart_transmit_send_stop_bit1_5,
CAN_FIRE_RL_uart_transmit_send_stop_bit2,
CAN_FIRE_RL_uart_transmit_shift_next_bit,
CAN_FIRE_RL_uart_transmit_wait_1_bit_cell_time,
CAN_FIRE_RL_uart_transmit_wait_for_start_command,
CAN_FIRE_RL_xmas_fsm_action_l42c32,
CAN_FIRE_RL_xmas_fsm_action_l43c32,
CAN_FIRE_RL_xmas_fsm_action_l44c32,
CAN_FIRE_RL_xmas_fsm_action_l45c32,
CAN_FIRE_RL_xmas_fsm_action_l46c32,
CAN_FIRE_RL_xmas_fsm_action_l47c32,
CAN_FIRE_RL_xmas_fsm_action_l48c32,
CAN_FIRE_RL_xmas_fsm_action_l49c32,
CAN_FIRE_RL_xmas_fsm_action_l50c32,
CAN_FIRE_RL_xmas_fsm_action_l51c32,
CAN_FIRE_RL_xmas_fsm_action_l52c32,
CAN_FIRE_RL_xmas_fsm_action_l53c32,
CAN_FIRE_RL_xmas_fsm_action_l54c32,
CAN_FIRE_RL_xmas_fsm_action_l55c32,
CAN_FIRE_RL_xmas_fsm_action_l56c32,
CAN_FIRE_RL_xmas_fsm_action_l57c32,
CAN_FIRE_RL_xmas_fsm_action_l58c32,
CAN_FIRE_RL_xmas_fsm_action_l59c32,
CAN_FIRE_RL_xmas_fsm_action_l60c32,
CAN_FIRE_RL_xmas_fsm_action_l61c32,
CAN_FIRE_RL_xmas_fsm_action_l62c32,
CAN_FIRE_RL_xmas_fsm_action_l63c32,
CAN_FIRE_RL_xmas_fsm_action_l64c32,
CAN_FIRE_RL_xmas_fsm_action_l65c32,
CAN_FIRE_RL_xmas_fsm_action_l66c32,
CAN_FIRE_RL_xmas_fsm_fsm_start,
CAN_FIRE_RL_xmas_fsm_idle_l40c27,
CAN_FIRE_RL_xmas_fsm_idle_l40c27_1,
CAN_FIRE_RL_xmas_fsm_restart,
CAN_FIRE_RL_xmas_fsm_start_reg__dreg_update,
CAN_FIRE_RL_xmas_fsm_state_every,
CAN_FIRE_RL_xmas_fsm_state_fired__dreg_update,
CAN_FIRE_RL_xmas_fsm_state_handle_abort,
CAN_FIRE___me_check_34,
CAN_FIRE___me_check_35,
CAN_FIRE___me_check_36,
CAN_FIRE___me_check_37,
CAN_FIRE___me_check_38,
CAN_FIRE___me_check_39,
CAN_FIRE___me_check_40,
CAN_FIRE___me_check_41,
CAN_FIRE___me_check_42,
CAN_FIRE___me_check_43,
CAN_FIRE___me_check_44,
CAN_FIRE___me_check_45,
CAN_FIRE___me_check_46,
CAN_FIRE___me_check_47,
CAN_FIRE___me_check_48,
CAN_FIRE___me_check_49,
CAN_FIRE___me_check_50,
CAN_FIRE___me_check_51,
CAN_FIRE___me_check_52,
CAN_FIRE___me_check_53,
CAN_FIRE___me_check_54,
CAN_FIRE___me_check_55,
CAN_FIRE___me_check_56,
CAN_FIRE___me_check_57,
CAN_FIRE_operation_mode,
CAN_FIRE_startup_value,
CAN_FIRE_txrx_sin,
WILL_FIRE_RL_compute,
WILL_FIRE_RL_dump_rx,
WILL_FIRE_RL_get_result,
WILL_FIRE_RL_uart_baudGen_assert_2x_baud_tick,
WILL_FIRE_RL_uart_baudGen_baud_count_wire,
WILL_FIRE_RL_uart_baudGen_baud_tick_count_wire,
WILL_FIRE_RL_uart_baudGen_count_baudtick_16x,
WILL_FIRE_RL_uart_baud_generator_clock_enable,
WILL_FIRE_RL_uart_fifoRecv__updateLevelCounter,
WILL_FIRE_RL_uart_fifoXmit__updateLevelCounter,
WILL_FIRE_RL_uart_receive_bit_cell_time_counter,
WILL_FIRE_RL_uart_receive_bit_counter,
WILL_FIRE_RL_uart_receive_buffer_shift,
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell,
WILL_FIRE_RL_uart_receive_parity_bit,
WILL_FIRE_RL_uart_receive_sample_pin,
WILL_FIRE_RL_uart_receive_stop_first_bit,
WILL_FIRE_RL_uart_receive_stop_last_bit,
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample,
WILL_FIRE_RL_uart_receive_wait_for_start_bit,
WILL_FIRE_RL_uart_transmit_bit_cell_time_counter,
WILL_FIRE_RL_uart_transmit_bit_counter,
WILL_FIRE_RL_uart_transmit_buffer_load,
WILL_FIRE_RL_uart_transmit_buffer_shift,
WILL_FIRE_RL_uart_transmit_send_parity_bit,
WILL_FIRE_RL_uart_transmit_send_start_bit,
WILL_FIRE_RL_uart_transmit_send_stop_bit,
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5,
WILL_FIRE_RL_uart_transmit_send_stop_bit2,
WILL_FIRE_RL_uart_transmit_shift_next_bit,
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time,
WILL_FIRE_RL_uart_transmit_wait_for_start_command,
WILL_FIRE_RL_xmas_fsm_action_l42c32,
WILL_FIRE_RL_xmas_fsm_action_l43c32,
WILL_FIRE_RL_xmas_fsm_action_l44c32,
WILL_FIRE_RL_xmas_fsm_action_l45c32,
WILL_FIRE_RL_xmas_fsm_action_l46c32,
WILL_FIRE_RL_xmas_fsm_action_l47c32,
WILL_FIRE_RL_xmas_fsm_action_l48c32,
WILL_FIRE_RL_xmas_fsm_action_l49c32,
WILL_FIRE_RL_xmas_fsm_action_l50c32,
WILL_FIRE_RL_xmas_fsm_action_l51c32,
WILL_FIRE_RL_xmas_fsm_action_l52c32,
WILL_FIRE_RL_xmas_fsm_action_l53c32,
WILL_FIRE_RL_xmas_fsm_action_l54c32,
WILL_FIRE_RL_xmas_fsm_action_l55c32,
WILL_FIRE_RL_xmas_fsm_action_l56c32,
WILL_FIRE_RL_xmas_fsm_action_l57c32,
WILL_FIRE_RL_xmas_fsm_action_l58c32,
WILL_FIRE_RL_xmas_fsm_action_l59c32,
WILL_FIRE_RL_xmas_fsm_action_l60c32,
WILL_FIRE_RL_xmas_fsm_action_l61c32,
WILL_FIRE_RL_xmas_fsm_action_l62c32,
WILL_FIRE_RL_xmas_fsm_action_l63c32,
WILL_FIRE_RL_xmas_fsm_action_l64c32,
WILL_FIRE_RL_xmas_fsm_action_l65c32,
WILL_FIRE_RL_xmas_fsm_action_l66c32,
WILL_FIRE_RL_xmas_fsm_fsm_start,
WILL_FIRE_RL_xmas_fsm_idle_l40c27,
WILL_FIRE_RL_xmas_fsm_idle_l40c27_1,
WILL_FIRE_RL_xmas_fsm_restart,
WILL_FIRE_RL_xmas_fsm_start_reg__dreg_update,
WILL_FIRE_RL_xmas_fsm_state_every,
WILL_FIRE_RL_xmas_fsm_state_fired__dreg_update,
WILL_FIRE_RL_xmas_fsm_state_handle_abort,
WILL_FIRE___me_check_34,
WILL_FIRE___me_check_35,
WILL_FIRE___me_check_36,
WILL_FIRE___me_check_37,
WILL_FIRE___me_check_38,
WILL_FIRE___me_check_39,
WILL_FIRE___me_check_40,
WILL_FIRE___me_check_41,
WILL_FIRE___me_check_42,
WILL_FIRE___me_check_43,
WILL_FIRE___me_check_44,
WILL_FIRE___me_check_45,
WILL_FIRE___me_check_46,
WILL_FIRE___me_check_47,
WILL_FIRE___me_check_48,
WILL_FIRE___me_check_49,
WILL_FIRE___me_check_50,
WILL_FIRE___me_check_51,
WILL_FIRE___me_check_52,
WILL_FIRE___me_check_53,
WILL_FIRE___me_check_54,
WILL_FIRE___me_check_55,
WILL_FIRE___me_check_56,
WILL_FIRE___me_check_57,
WILL_FIRE_operation_mode,
WILL_FIRE_startup_value,
WILL_FIRE_txrx_sin;
// inputs to muxes for submodule ports
reg [2 : 0] MUX_uart_rRecvState$write_1__VAL_3;
wire [2 : 0] MUX_uart_rRecvState$write_1__VAL_1,
MUX_uart_rRecvState$write_1__VAL_2,
MUX_uart_rRecvState$write_1__VAL_4,
MUX_uart_rXmitState$write_1__VAL_1,
MUX_uart_rXmitState$write_1__VAL_2,
MUX_uart_rXmitState$write_1__VAL_3,
MUX_uart_rXmitState$write_1__VAL_4,
MUX_uart_rXmitState$write_1__VAL_5,
MUX_uart_rXmitState$write_1__VAL_6,
MUX_uart_rXmitState$write_1__VAL_7;
wire MUX_transmit_state$write_1__SEL_1,
MUX_uart_fifoXmit$enq_1__SEL_11,
MUX_uart_fifoXmit$enq_1__SEL_15,
MUX_uart_fifoXmit$enq_1__SEL_16,
MUX_uart_fifoXmit$enq_1__SEL_17,
MUX_uart_fifoXmit$enq_1__SEL_2,
MUX_uart_fifoXmit$enq_1__SEL_3,
MUX_uart_rRecvState$write_1__SEL_6,
MUX_uart_rXmitDataOut$write_1__SEL_1,
MUX_uart_rXmitDataOut$write_1__SEL_2,
MUX_uart_rXmitDataOut$write_1__SEL_3,
MUX_xmas_fsm_start_reg$write_1__SEL_1,
MUX_xmas_fsm_state_mkFSMstate$write_1__SEL_1;
// remaining internal signals
wire [3 : 0] x__h2985, x__h4689, x__h6445, x__h6471;
wire _dor2uart_pwXmitCellCountReset$EN_wset,
uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29,
xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302;
// action method operation_mode
assign RDY_operation_mode =
transmit_state == 2'd0 && !op_mode &&
xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302 &&
!xmas_fsm_start_reg ;
assign CAN_FIRE_operation_mode =
transmit_state == 2'd0 && !op_mode &&
xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302 &&
!xmas_fsm_start_reg ;
assign WILL_FIRE_operation_mode = EN_operation_mode ;
// action method startup_value
assign RDY_startup_value = transmit_state == 2'd0 && !op_mode ;
assign CAN_FIRE_startup_value = transmit_state == 2'd0 && !op_mode ;
assign WILL_FIRE_startup_value = EN_startup_value ;
// action method txrx_sin
assign CAN_FIRE_txrx_sin = 1'd1 ;
assign WILL_FIRE_txrx_sin = 1'd1 ;
// value method txrx_sout
assign txrx_SOUT = uart_rXmitDataOut ;
// submodule rule30
mkRule30 rule30(.CLK(CLK),
.RST_N(RST_N),
.start_a(rule30$start_a),
.EN_start(rule30$EN_start),
.EN_getResult(rule30$EN_getResult),
.RDY_start(rule30$RDY_start),
.getResult(rule30$getResult),
.RDY_getResult(rule30$RDY_getResult));
// submodule uart_baudGen_rBaudCounter
Counter #(.width(32'd16), .init(16'd0)) uart_baudGen_rBaudCounter(.CLK(CLK),
.RST(RST_N),
.DATA_A(uart_baudGen_rBaudCounter$DATA_A),
.DATA_B(uart_baudGen_rBaudCounter$DATA_B),
.DATA_C(uart_baudGen_rBaudCounter$DATA_C),
.DATA_F(uart_baudGen_rBaudCounter$DATA_F),
.ADDA(uart_baudGen_rBaudCounter$ADDA),
.ADDB(uart_baudGen_rBaudCounter$ADDB),
.SETC(uart_baudGen_rBaudCounter$SETC),
.SETF(uart_baudGen_rBaudCounter$SETF),
.Q_OUT(uart_baudGen_rBaudCounter$Q_OUT));
// submodule uart_baudGen_rBaudTickCounter
Counter #(.width(32'd3),
.init(3'd0)) uart_baudGen_rBaudTickCounter(.CLK(CLK),
.RST(RST_N),
.DATA_A(uart_baudGen_rBaudTickCounter$DATA_A),
.DATA_B(uart_baudGen_rBaudTickCounter$DATA_B),
.DATA_C(uart_baudGen_rBaudTickCounter$DATA_C),
.DATA_F(uart_baudGen_rBaudTickCounter$DATA_F),
.ADDA(uart_baudGen_rBaudTickCounter$ADDA),
.ADDB(uart_baudGen_rBaudTickCounter$ADDB),
.SETC(uart_baudGen_rBaudTickCounter$SETC),
.SETF(uart_baudGen_rBaudTickCounter$SETF),
.Q_OUT(uart_baudGen_rBaudTickCounter$Q_OUT));
// submodule uart_fifoRecv
SizedFIFO #(.p1width(32'd8),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(1'd1)) uart_fifoRecv(.RST(RST_N),
.CLK(CLK),
.D_IN(uart_fifoRecv$D_IN),
.ENQ(uart_fifoRecv$ENQ),
.DEQ(uart_fifoRecv$DEQ),
.CLR(uart_fifoRecv$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N(uart_fifoRecv$EMPTY_N));
// submodule uart_fifoXmit
SizedFIFO #(.p1width(32'd8),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(1'd1)) uart_fifoXmit(.RST(RST_N),
.CLK(CLK),
.D_IN(uart_fifoXmit$D_IN),
.ENQ(uart_fifoXmit$ENQ),
.DEQ(uart_fifoXmit$DEQ),
.CLR(uart_fifoXmit$CLR),
.D_OUT(uart_fifoXmit$D_OUT),
.FULL_N(uart_fifoXmit$FULL_N),
.EMPTY_N(uart_fifoXmit$EMPTY_N));
// rule RL_dump_rx
assign CAN_FIRE_RL_dump_rx = uart_fifoRecv$EMPTY_N ;
assign WILL_FIRE_RL_dump_rx = uart_fifoRecv$EMPTY_N ;
// rule RL_compute
assign CAN_FIRE_RL_compute =
rule30$RDY_start && transmit_state == 2'd1 && !op_mode ;
assign WILL_FIRE_RL_compute = CAN_FIRE_RL_compute ;
// rule RL_uart_baudGen_baud_count_wire
assign CAN_FIRE_RL_uart_baudGen_baud_count_wire = 1'd1 ;
assign WILL_FIRE_RL_uart_baudGen_baud_count_wire = 1'd1 ;
// rule RL_uart_baud_generator_clock_enable
assign CAN_FIRE_RL_uart_baud_generator_clock_enable = 1'd1 ;
assign WILL_FIRE_RL_uart_baud_generator_clock_enable = 1'd1 ;
// rule RL_uart_receive_wait_for_start_bit
assign CAN_FIRE_RL_uart_receive_wait_for_start_bit =
uart_rRecvState == 3'd0 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_wait_for_start_bit =
CAN_FIRE_RL_uart_receive_wait_for_start_bit ;
// rule RL_uart_receive_find_center_of_bit_cell
assign CAN_FIRE_RL_uart_receive_find_center_of_bit_cell =
uart_rRecvState == 3'd1 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_find_center_of_bit_cell =
CAN_FIRE_RL_uart_receive_find_center_of_bit_cell ;
// rule RL_uart_receive_wait_bit_cell_time_for_sample
assign CAN_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample =
uart_rRecvState == 3'd2 && uart_rRecvCellCount == 4'hF &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample =
CAN_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample ;
// rule RL_uart_receive_sample_pin
assign CAN_FIRE_RL_uart_receive_sample_pin =
CAN_FIRE_RL_uart_receive_buffer_shift ;
assign WILL_FIRE_RL_uart_receive_sample_pin =
CAN_FIRE_RL_uart_receive_buffer_shift ;
// rule RL_uart_receive_parity_bit
assign CAN_FIRE_RL_uart_receive_parity_bit =
uart_rRecvState == 3'd4 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_parity_bit =
CAN_FIRE_RL_uart_receive_parity_bit ;
// rule RL_uart_receive_stop_first_bit
assign CAN_FIRE_RL_uart_receive_stop_first_bit =
uart_rRecvState == 3'd5 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_stop_first_bit =
CAN_FIRE_RL_uart_receive_stop_first_bit ;
// rule RL_uart_receive_bit_counter
assign CAN_FIRE_RL_uart_receive_bit_counter = 1'd1 ;
assign WILL_FIRE_RL_uart_receive_bit_counter = 1'd1 ;
// rule RL_uart_receive_stop_last_bit
assign CAN_FIRE_RL_uart_receive_stop_last_bit =
uart_rRecvState == 3'd6 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_stop_last_bit =
CAN_FIRE_RL_uart_receive_stop_last_bit ;
// rule RL_uart_receive_bit_cell_time_counter
assign CAN_FIRE_RL_uart_receive_bit_cell_time_counter =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
assign WILL_FIRE_RL_uart_receive_bit_cell_time_counter =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// rule RL_uart_receive_buffer_shift
assign CAN_FIRE_RL_uart_receive_buffer_shift =
uart_rRecvState == 3'd3 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_receive_buffer_shift =
CAN_FIRE_RL_uart_receive_buffer_shift ;
// rule RL_uart_transmit_wait_for_start_command
assign CAN_FIRE_RL_uart_transmit_wait_for_start_command =
uart_rXmitState == 3'd0 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_wait_for_start_command =
CAN_FIRE_RL_uart_transmit_wait_for_start_command ;
// rule RL_get_result
assign CAN_FIRE_RL_get_result =
rule30$RDY_getResult && uart_fifoXmit$FULL_N &&
transmit_state == 2'd2 &&
!op_mode &&
xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302 &&
!xmas_fsm_start_reg ;
assign WILL_FIRE_RL_get_result = CAN_FIRE_RL_get_result ;
// rule RL_uart_transmit_send_start_bit
assign CAN_FIRE_RL_uart_transmit_send_start_bit =
uart_rXmitState == 3'd1 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_start_bit =
CAN_FIRE_RL_uart_transmit_send_start_bit ;
// rule RL_uart_transmit_wait_1_bit_cell_time
assign CAN_FIRE_RL_uart_transmit_wait_1_bit_cell_time =
uart_rXmitState == 3'd2 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time =
CAN_FIRE_RL_uart_transmit_wait_1_bit_cell_time ;
// rule RL_uart_transmit_bit_counter
assign CAN_FIRE_RL_uart_transmit_bit_counter = 1'd1 ;
assign WILL_FIRE_RL_uart_transmit_bit_counter = 1'd1 ;
// rule RL_uart_transmit_shift_next_bit
assign CAN_FIRE_RL_uart_transmit_shift_next_bit =
uart_rXmitState == 3'd3 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_shift_next_bit =
CAN_FIRE_RL_uart_transmit_shift_next_bit ;
// rule RL_uart_transmit_buffer_load
assign CAN_FIRE_RL_uart_transmit_buffer_load =
uart_fifoXmit$EMPTY_N && uart_pwXmitLoadBuffer$whas ;
assign WILL_FIRE_RL_uart_transmit_buffer_load =
CAN_FIRE_RL_uart_transmit_buffer_load ;
// rule RL_uart_transmit_buffer_shift
assign CAN_FIRE_RL_uart_transmit_buffer_shift =
!uart_pwXmitLoadBuffer$whas &&
CAN_FIRE_RL_uart_transmit_shift_next_bit ;
assign WILL_FIRE_RL_uart_transmit_buffer_shift =
CAN_FIRE_RL_uart_transmit_buffer_shift ;
// rule RL_uart_transmit_send_parity_bit
assign CAN_FIRE_RL_uart_transmit_send_parity_bit =
uart_rXmitState == 3'd7 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_parity_bit =
CAN_FIRE_RL_uart_transmit_send_parity_bit ;
// rule RL_uart_transmit_send_stop_bit
assign CAN_FIRE_RL_uart_transmit_send_stop_bit =
uart_rXmitState == 3'd4 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_stop_bit =
CAN_FIRE_RL_uart_transmit_send_stop_bit ;
// rule RL_uart_transmit_send_stop_bit1_5
assign CAN_FIRE_RL_uart_transmit_send_stop_bit1_5 =
uart_rXmitState == 3'd5 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 =
CAN_FIRE_RL_uart_transmit_send_stop_bit1_5 ;
// rule RL_uart_transmit_send_stop_bit2
assign CAN_FIRE_RL_uart_transmit_send_stop_bit2 =
uart_rXmitState == 3'd6 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_transmit_send_stop_bit2 =
CAN_FIRE_RL_uart_transmit_send_stop_bit2 ;
// rule RL_uart_transmit_bit_cell_time_counter
assign CAN_FIRE_RL_uart_transmit_bit_cell_time_counter =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
assign WILL_FIRE_RL_uart_transmit_bit_cell_time_counter =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// rule RL_uart_baudGen_baud_tick_count_wire
assign CAN_FIRE_RL_uart_baudGen_baud_tick_count_wire = 1'd1 ;
assign WILL_FIRE_RL_uart_baudGen_baud_tick_count_wire = 1'd1 ;
// rule RL_uart_baudGen_assert_2x_baud_tick
assign CAN_FIRE_RL_uart_baudGen_assert_2x_baud_tick =
uart_baudGen_rBaudTickCounter$Q_OUT == 3'd0 &&
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_baudGen_assert_2x_baud_tick =
CAN_FIRE_RL_uart_baudGen_assert_2x_baud_tick ;
// rule RL_uart_baudGen_count_baudtick_16x
assign CAN_FIRE_RL_uart_baudGen_count_baudtick_16x =
!uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign WILL_FIRE_RL_uart_baudGen_count_baudtick_16x =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// rule RL_uart_fifoRecv__updateLevelCounter
assign CAN_FIRE_RL_uart_fifoRecv__updateLevelCounter =
CAN_FIRE_RL_uart_receive_stop_last_bit != uart_fifoRecv$EMPTY_N ;
assign WILL_FIRE_RL_uart_fifoRecv__updateLevelCounter =
CAN_FIRE_RL_uart_fifoRecv__updateLevelCounter ;
// rule RL_xmas_fsm_restart
assign CAN_FIRE_RL_xmas_fsm_restart =
xmas_fsm_start_reg_1 && !xmas_fsm_state_fired ;
assign WILL_FIRE_RL_xmas_fsm_restart = CAN_FIRE_RL_xmas_fsm_restart ;
// rule RL_xmas_fsm_action_l43c32
assign CAN_FIRE_RL_xmas_fsm_action_l43c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd1 ;
assign WILL_FIRE_RL_xmas_fsm_action_l43c32 =
CAN_FIRE_RL_xmas_fsm_action_l43c32 ;
// rule RL_xmas_fsm_action_l44c32
assign CAN_FIRE_RL_xmas_fsm_action_l44c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd2 ;
assign WILL_FIRE_RL_xmas_fsm_action_l44c32 =
CAN_FIRE_RL_xmas_fsm_action_l44c32 ;
// rule RL_xmas_fsm_action_l45c32
assign CAN_FIRE_RL_xmas_fsm_action_l45c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd3 ;
assign WILL_FIRE_RL_xmas_fsm_action_l45c32 =
CAN_FIRE_RL_xmas_fsm_action_l45c32 ;
// rule RL_xmas_fsm_action_l46c32
assign CAN_FIRE_RL_xmas_fsm_action_l46c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd4 ;
assign WILL_FIRE_RL_xmas_fsm_action_l46c32 =
CAN_FIRE_RL_xmas_fsm_action_l46c32 ;
// rule RL_xmas_fsm_action_l47c32
assign CAN_FIRE_RL_xmas_fsm_action_l47c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd5 ;
assign WILL_FIRE_RL_xmas_fsm_action_l47c32 =
CAN_FIRE_RL_xmas_fsm_action_l47c32 ;
// rule RL_xmas_fsm_action_l48c32
assign CAN_FIRE_RL_xmas_fsm_action_l48c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd6 ;
assign WILL_FIRE_RL_xmas_fsm_action_l48c32 =
CAN_FIRE_RL_xmas_fsm_action_l48c32 ;
// rule RL_xmas_fsm_action_l49c32
assign CAN_FIRE_RL_xmas_fsm_action_l49c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd7 ;
assign WILL_FIRE_RL_xmas_fsm_action_l49c32 =
CAN_FIRE_RL_xmas_fsm_action_l49c32 ;
// rule RL_xmas_fsm_action_l50c32
assign CAN_FIRE_RL_xmas_fsm_action_l50c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd8 ;
assign WILL_FIRE_RL_xmas_fsm_action_l50c32 =
CAN_FIRE_RL_xmas_fsm_action_l50c32 ;
// rule RL_xmas_fsm_action_l51c32
assign CAN_FIRE_RL_xmas_fsm_action_l51c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd9 ;
assign WILL_FIRE_RL_xmas_fsm_action_l51c32 =
CAN_FIRE_RL_xmas_fsm_action_l51c32 ;
// rule RL_xmas_fsm_action_l52c32
assign CAN_FIRE_RL_xmas_fsm_action_l52c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd10 ;
assign WILL_FIRE_RL_xmas_fsm_action_l52c32 =
CAN_FIRE_RL_xmas_fsm_action_l52c32 ;
// rule RL_xmas_fsm_action_l53c32
assign CAN_FIRE_RL_xmas_fsm_action_l53c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd11 ;
assign WILL_FIRE_RL_xmas_fsm_action_l53c32 =
CAN_FIRE_RL_xmas_fsm_action_l53c32 ;
// rule RL_xmas_fsm_action_l54c32
assign CAN_FIRE_RL_xmas_fsm_action_l54c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd12 ;
assign WILL_FIRE_RL_xmas_fsm_action_l54c32 =
CAN_FIRE_RL_xmas_fsm_action_l54c32 ;
// rule RL_xmas_fsm_action_l55c32
assign CAN_FIRE_RL_xmas_fsm_action_l55c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd13 ;
assign WILL_FIRE_RL_xmas_fsm_action_l55c32 =
CAN_FIRE_RL_xmas_fsm_action_l55c32 ;
// rule RL_xmas_fsm_action_l56c32
assign CAN_FIRE_RL_xmas_fsm_action_l56c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd14 ;
assign WILL_FIRE_RL_xmas_fsm_action_l56c32 =
CAN_FIRE_RL_xmas_fsm_action_l56c32 ;
// rule RL_xmas_fsm_action_l57c32
assign CAN_FIRE_RL_xmas_fsm_action_l57c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd15 ;
assign WILL_FIRE_RL_xmas_fsm_action_l57c32 =
CAN_FIRE_RL_xmas_fsm_action_l57c32 ;
// rule RL_xmas_fsm_action_l58c32
assign CAN_FIRE_RL_xmas_fsm_action_l58c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd16 ;
assign WILL_FIRE_RL_xmas_fsm_action_l58c32 =
CAN_FIRE_RL_xmas_fsm_action_l58c32 ;
// rule RL_xmas_fsm_action_l59c32
assign CAN_FIRE_RL_xmas_fsm_action_l59c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd17 ;
assign WILL_FIRE_RL_xmas_fsm_action_l59c32 =
CAN_FIRE_RL_xmas_fsm_action_l59c32 ;
// rule RL_xmas_fsm_action_l60c32
assign CAN_FIRE_RL_xmas_fsm_action_l60c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd18 ;
assign WILL_FIRE_RL_xmas_fsm_action_l60c32 =
CAN_FIRE_RL_xmas_fsm_action_l60c32 ;
// rule RL_xmas_fsm_action_l61c32
assign CAN_FIRE_RL_xmas_fsm_action_l61c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd19 ;
assign WILL_FIRE_RL_xmas_fsm_action_l61c32 =
CAN_FIRE_RL_xmas_fsm_action_l61c32 ;
// rule RL_xmas_fsm_action_l62c32
assign CAN_FIRE_RL_xmas_fsm_action_l62c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd20 ;
assign WILL_FIRE_RL_xmas_fsm_action_l62c32 =
CAN_FIRE_RL_xmas_fsm_action_l62c32 ;
// rule RL_xmas_fsm_action_l63c32
assign CAN_FIRE_RL_xmas_fsm_action_l63c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd21 ;
assign WILL_FIRE_RL_xmas_fsm_action_l63c32 =
CAN_FIRE_RL_xmas_fsm_action_l63c32 ;
// rule RL_xmas_fsm_action_l64c32
assign CAN_FIRE_RL_xmas_fsm_action_l64c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd22 ;
assign WILL_FIRE_RL_xmas_fsm_action_l64c32 =
CAN_FIRE_RL_xmas_fsm_action_l64c32 ;
// rule RL_xmas_fsm_action_l65c32
assign CAN_FIRE_RL_xmas_fsm_action_l65c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd23 ;
assign WILL_FIRE_RL_xmas_fsm_action_l65c32 =
CAN_FIRE_RL_xmas_fsm_action_l65c32 ;
// rule RL_xmas_fsm_action_l66c32
assign CAN_FIRE_RL_xmas_fsm_action_l66c32 =
uart_fifoXmit$FULL_N && xmas_fsm_state_mkFSMstate == 5'd24 ;
assign WILL_FIRE_RL_xmas_fsm_action_l66c32 =
CAN_FIRE_RL_xmas_fsm_action_l66c32 ;
// rule __me_check_35
assign CAN_FIRE___me_check_35 = 1'b1 ;
assign WILL_FIRE___me_check_35 = 1'b1 ;
// rule __me_check_36
assign CAN_FIRE___me_check_36 = 1'b1 ;
assign WILL_FIRE___me_check_36 = 1'b1 ;
// rule __me_check_37
assign CAN_FIRE___me_check_37 = 1'b1 ;
assign WILL_FIRE___me_check_37 = 1'b1 ;
// rule __me_check_38
assign CAN_FIRE___me_check_38 = 1'b1 ;
assign WILL_FIRE___me_check_38 = 1'b1 ;
// rule __me_check_39
assign CAN_FIRE___me_check_39 = 1'b1 ;
assign WILL_FIRE___me_check_39 = 1'b1 ;
// rule __me_check_40
assign CAN_FIRE___me_check_40 = 1'b1 ;
assign WILL_FIRE___me_check_40 = 1'b1 ;
// rule __me_check_41
assign CAN_FIRE___me_check_41 = 1'b1 ;
assign WILL_FIRE___me_check_41 = 1'b1 ;
// rule __me_check_43
assign CAN_FIRE___me_check_43 = 1'b1 ;
assign WILL_FIRE___me_check_43 = 1'b1 ;
// rule __me_check_42
assign CAN_FIRE___me_check_42 = 1'b1 ;
assign WILL_FIRE___me_check_42 = 1'b1 ;
// rule __me_check_44
assign CAN_FIRE___me_check_44 = 1'b1 ;
assign WILL_FIRE___me_check_44 = 1'b1 ;
// rule __me_check_45
assign CAN_FIRE___me_check_45 = 1'b1 ;
assign WILL_FIRE___me_check_45 = 1'b1 ;
// rule __me_check_46
assign CAN_FIRE___me_check_46 = 1'b1 ;
assign WILL_FIRE___me_check_46 = 1'b1 ;
// rule __me_check_47
assign CAN_FIRE___me_check_47 = 1'b1 ;
assign WILL_FIRE___me_check_47 = 1'b1 ;
// rule __me_check_48
assign CAN_FIRE___me_check_48 = 1'b1 ;
assign WILL_FIRE___me_check_48 = 1'b1 ;
// rule __me_check_49
assign CAN_FIRE___me_check_49 = 1'b1 ;
assign WILL_FIRE___me_check_49 = 1'b1 ;
// rule __me_check_51
assign CAN_FIRE___me_check_51 = 1'b1 ;
assign WILL_FIRE___me_check_51 = 1'b1 ;
// rule __me_check_50
assign CAN_FIRE___me_check_50 = 1'b1 ;
assign WILL_FIRE___me_check_50 = 1'b1 ;
// rule __me_check_52
assign CAN_FIRE___me_check_52 = 1'b1 ;
assign WILL_FIRE___me_check_52 = 1'b1 ;
// rule __me_check_53
assign CAN_FIRE___me_check_53 = 1'b1 ;
assign WILL_FIRE___me_check_53 = 1'b1 ;
// rule __me_check_54
assign CAN_FIRE___me_check_54 = 1'b1 ;
assign WILL_FIRE___me_check_54 = 1'b1 ;
// rule __me_check_55
assign CAN_FIRE___me_check_55 = 1'b1 ;
assign WILL_FIRE___me_check_55 = 1'b1 ;
// rule __me_check_56
assign CAN_FIRE___me_check_56 = 1'b1 ;
assign WILL_FIRE___me_check_56 = 1'b1 ;
// rule __me_check_57
assign CAN_FIRE___me_check_57 = 1'b1 ;
assign WILL_FIRE___me_check_57 = 1'b1 ;
// rule RL_xmas_fsm_idle_l40c27_1
assign CAN_FIRE_RL_xmas_fsm_idle_l40c27_1 =
!op_mode && xmas_fsm_state_mkFSMstate == 5'd25 ;
assign WILL_FIRE_RL_xmas_fsm_idle_l40c27_1 =
CAN_FIRE_RL_xmas_fsm_idle_l40c27_1 ;
// rule RL_xmas_fsm_fsm_start
assign CAN_FIRE_RL_xmas_fsm_fsm_start =
(op_mode && xmas_fsm_state_mkFSMstate == 5'd0 ||
op_mode && xmas_fsm_state_mkFSMstate == 5'd27 ||
!op_mode && xmas_fsm_state_mkFSMstate == 5'd0 ||
!op_mode &&
(xmas_fsm_state_mkFSMstate == 5'd25 ||
xmas_fsm_state_mkFSMstate == 5'd27)) &&
(!xmas_fsm_start_reg_1 || xmas_fsm_state_fired) &&
xmas_fsm_start_reg ;
assign WILL_FIRE_RL_xmas_fsm_fsm_start = CAN_FIRE_RL_xmas_fsm_fsm_start ;
// rule RL_xmas_fsm_action_l42c32
assign CAN_FIRE_RL_xmas_fsm_action_l42c32 =
uart_fifoXmit$FULL_N &&
(op_mode && xmas_fsm_start_wire$whas &&
xmas_fsm_state_mkFSMstate == 5'd0 ||
op_mode && xmas_fsm_state_mkFSMstate == 5'd25) ;
assign WILL_FIRE_RL_xmas_fsm_action_l42c32 =
CAN_FIRE_RL_xmas_fsm_action_l42c32 ;
// rule __me_check_34
assign CAN_FIRE___me_check_34 = 1'b1 ;
assign WILL_FIRE___me_check_34 = 1'b1 ;
// rule RL_uart_fifoXmit__updateLevelCounter
assign CAN_FIRE_RL_uart_fifoXmit__updateLevelCounter =
uart_fifoXmit_r_enq$whas !=
CAN_FIRE_RL_uart_transmit_buffer_load ;
assign WILL_FIRE_RL_uart_fifoXmit__updateLevelCounter =
CAN_FIRE_RL_uart_fifoXmit__updateLevelCounter ;
// rule RL_xmas_fsm_idle_l40c27
assign CAN_FIRE_RL_xmas_fsm_idle_l40c27 =
!op_mode && xmas_fsm_start_wire$whas &&
xmas_fsm_state_mkFSMstate == 5'd0 ;
assign WILL_FIRE_RL_xmas_fsm_idle_l40c27 =
CAN_FIRE_RL_xmas_fsm_idle_l40c27 ;
// rule RL_xmas_fsm_start_reg__dreg_update
assign CAN_FIRE_RL_xmas_fsm_start_reg__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_xmas_fsm_start_reg__dreg_update = 1'd1 ;
// rule RL_xmas_fsm_state_handle_abort
assign CAN_FIRE_RL_xmas_fsm_state_handle_abort = 1'b0 ;
assign WILL_FIRE_RL_xmas_fsm_state_handle_abort = 1'b0 ;
// rule RL_xmas_fsm_state_every
assign CAN_FIRE_RL_xmas_fsm_state_every = 1'd1 ;
assign WILL_FIRE_RL_xmas_fsm_state_every = 1'd1 ;
// rule RL_xmas_fsm_state_fired__dreg_update
assign CAN_FIRE_RL_xmas_fsm_state_fired__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_xmas_fsm_state_fired__dreg_update = 1'd1 ;
// inputs to muxes for submodule ports
assign MUX_transmit_state$write_1__SEL_1 =
WILL_FIRE_RL_get_result || EN_startup_value ;
assign MUX_uart_fifoXmit$enq_1__SEL_2 =
WILL_FIRE_RL_xmas_fsm_action_l66c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_3 =
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_11 =
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_15 =
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_16 =
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ;
assign MUX_uart_fifoXmit$enq_1__SEL_17 =
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ;
assign MUX_uart_rRecvState$write_1__SEL_6 =
WILL_FIRE_RL_uart_receive_parity_bit ||
WILL_FIRE_RL_uart_receive_sample_pin ;
assign MUX_uart_rXmitDataOut$write_1__SEL_1 =
WILL_FIRE_RL_uart_transmit_shift_next_bit ||
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ;
assign MUX_uart_rXmitDataOut$write_1__SEL_2 =
WILL_FIRE_RL_uart_transmit_send_parity_bit ||
WILL_FIRE_RL_uart_transmit_send_start_bit ;
assign MUX_uart_rXmitDataOut$write_1__SEL_3 =
WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit ||
WILL_FIRE_RL_uart_transmit_wait_for_start_command ;
assign MUX_xmas_fsm_start_reg$write_1__SEL_1 =
EN_operation_mode && operation_mode_arg == 8'hA5 ;
assign MUX_xmas_fsm_state_mkFSMstate$write_1__SEL_1 =
WILL_FIRE_RL_xmas_fsm_idle_l40c27_1 ||
WILL_FIRE_RL_xmas_fsm_idle_l40c27 ;
assign MUX_uart_rRecvState$write_1__VAL_1 = uart_rRecvData ? 3'd0 : 3'd1 ;
assign MUX_uart_rRecvState$write_1__VAL_2 =
(uart_rRecvCellCount == 4'h4) ?
(uart_rRecvData ? 3'd0 : 3'd2) :
3'd1 ;
always@(uart_rRecvBitCount)
begin
case (uart_rRecvBitCount)
4'd8, 4'd9, 4'd10: MUX_uart_rRecvState$write_1__VAL_3 = 3'd6;
default: MUX_uart_rRecvState$write_1__VAL_3 = 3'd3;
endcase
end
assign MUX_uart_rRecvState$write_1__VAL_4 = uart_rRecvData ? 3'd2 : 3'd0 ;
assign MUX_uart_rXmitState$write_1__VAL_1 =
uart_fifoXmit$EMPTY_N ? 3'd1 : 3'd0 ;
assign MUX_uart_rXmitState$write_1__VAL_2 =
(uart_rXmitCellCount == 4'hF) ? 3'd2 : 3'd1 ;
assign MUX_uart_rXmitState$write_1__VAL_3 =
(uart_rXmitCellCount == 4'hF) ?
((uart_rXmitBitCount == 4'd7) ? 3'd4 : 3'd3) :
3'd2 ;
assign MUX_uart_rXmitState$write_1__VAL_4 =
(uart_rXmitCellCount == 4'hF) ? 3'd4 : 3'd7 ;
assign MUX_uart_rXmitState$write_1__VAL_5 =
(uart_rXmitCellCount == 4'hF) ? 3'd0 : 3'd4 ;
assign MUX_uart_rXmitState$write_1__VAL_6 =
(uart_rXmitCellCount == 4'h7) ? 3'd0 : 3'd5 ;
assign MUX_uart_rXmitState$write_1__VAL_7 =
(uart_rXmitCellCount == 4'hF) ? 3'd0 : 3'd6 ;
// inlined wires
assign xmas_fsm_start_wire$whas =
WILL_FIRE_RL_xmas_fsm_fsm_start ||
WILL_FIRE_RL_xmas_fsm_restart ;
assign uart_pwRecvCellCountReset$whas =
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell &&
uart_rRecvCellCount == 4'h4 ||
WILL_FIRE_RL_uart_receive_stop_last_bit ||
WILL_FIRE_RL_uart_receive_stop_first_bit ||
WILL_FIRE_RL_uart_receive_parity_bit ||
WILL_FIRE_RL_uart_receive_sample_pin ||
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample ||
WILL_FIRE_RL_uart_receive_wait_for_start_bit ;
assign uart_pwRecvResetBitCount$whas =
WILL_FIRE_RL_uart_receive_wait_for_start_bit && uart_rRecvData ;
assign uart_pwRecvEnableBitCount$whas =
WILL_FIRE_RL_uart_receive_stop_first_bit ||
WILL_FIRE_RL_uart_receive_parity_bit ||
WILL_FIRE_RL_uart_receive_sample_pin ;
assign uart_fifoXmit_r_enq$whas =
WILL_FIRE_RL_get_result || WILL_FIRE_RL_xmas_fsm_action_l66c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ||
WILL_FIRE_RL_xmas_fsm_action_l64c32 ||
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l62c32 ||
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ||
WILL_FIRE_RL_xmas_fsm_action_l57c32 ||
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l55c32 ||
WILL_FIRE_RL_xmas_fsm_action_l54c32 ||
WILL_FIRE_RL_xmas_fsm_action_l53c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ||
WILL_FIRE_RL_xmas_fsm_action_l49c32 ||
WILL_FIRE_RL_xmas_fsm_action_l48c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ||
WILL_FIRE_RL_xmas_fsm_action_l46c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ||
WILL_FIRE_RL_xmas_fsm_action_l43c32 ||
WILL_FIRE_RL_xmas_fsm_action_l42c32 ;
assign uart_pwXmitCellCountReset$whas =
WILL_FIRE_RL_uart_transmit_wait_for_start_command &&
uart_fifoXmit$EMPTY_N ||
_dor2uart_pwXmitCellCountReset$EN_wset &&
uart_rXmitCellCount == 4'hF ||
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 &&
uart_rXmitCellCount == 4'h7 ;
assign uart_pwXmitEnableBitCount$whas =
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time &&
uart_rXmitCellCount == 4'hF &&
uart_rXmitBitCount != 4'd7 ;
assign uart_pwXmitLoadBuffer$whas =
WILL_FIRE_RL_uart_transmit_wait_for_start_command &&
uart_fifoXmit$EMPTY_N ;
assign xmas_fsm_state_set_pw$whas =
WILL_FIRE_RL_xmas_fsm_idle_l40c27_1 ||
WILL_FIRE_RL_xmas_fsm_idle_l40c27 ||
WILL_FIRE_RL_xmas_fsm_action_l66c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ||
WILL_FIRE_RL_xmas_fsm_action_l64c32 ||
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l62c32 ||
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ||
WILL_FIRE_RL_xmas_fsm_action_l57c32 ||
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l55c32 ||
WILL_FIRE_RL_xmas_fsm_action_l54c32 ||
WILL_FIRE_RL_xmas_fsm_action_l53c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ||
WILL_FIRE_RL_xmas_fsm_action_l49c32 ||
WILL_FIRE_RL_xmas_fsm_action_l48c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ||
WILL_FIRE_RL_xmas_fsm_action_l46c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ||
WILL_FIRE_RL_xmas_fsm_action_l43c32 ||
WILL_FIRE_RL_xmas_fsm_action_l42c32 ;
// register a
assign a$D_IN = EN_startup_value ? startup_value_v : rule30$getResult ;
assign a$EN = EN_startup_value || WILL_FIRE_RL_get_result ;
// register op_mode
assign op_mode$D_IN = 1'd1 ;
assign op_mode$EN = MUX_xmas_fsm_start_reg$write_1__SEL_1 ;
// register transmit_state
assign transmit_state$D_IN =
MUX_transmit_state$write_1__SEL_1 ? 2'd1 : 2'd2 ;
assign transmit_state$EN =
WILL_FIRE_RL_get_result || EN_startup_value ||
WILL_FIRE_RL_compute ;
// register uart_rRecvBitCount
assign uart_rRecvBitCount$D_IN =
uart_pwRecvResetBitCount$whas ? 4'd0 : x__h4689 ;
assign uart_rRecvBitCount$EN =
uart_pwRecvResetBitCount$whas || uart_pwRecvEnableBitCount$whas ;
// register uart_rRecvCellCount
assign uart_rRecvCellCount$D_IN =
uart_pwRecvCellCountReset$whas ? 4'd0 : x__h2985 ;
assign uart_rRecvCellCount$EN =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// register uart_rRecvData
assign uart_rRecvData$D_IN = txrx_SIN ;
assign uart_rRecvData$EN = 1'd1 ;
// register uart_rRecvState
always@(WILL_FIRE_RL_uart_receive_wait_for_start_bit or
MUX_uart_rRecvState$write_1__VAL_1 or
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell or
MUX_uart_rRecvState$write_1__VAL_2 or
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample or
MUX_uart_rRecvState$write_1__VAL_3 or
WILL_FIRE_RL_uart_receive_stop_first_bit or
MUX_uart_rRecvState$write_1__VAL_4 or
WILL_FIRE_RL_uart_receive_stop_last_bit or
MUX_uart_rRecvState$write_1__SEL_6)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_uart_receive_wait_for_start_bit:
uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_1;
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell:
uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_2;
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample:
uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_3;
WILL_FIRE_RL_uart_receive_stop_first_bit:
uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_4;
WILL_FIRE_RL_uart_receive_stop_last_bit: uart_rRecvState$D_IN = 3'd0;
MUX_uart_rRecvState$write_1__SEL_6: uart_rRecvState$D_IN = 3'd2;
default: uart_rRecvState$D_IN = 3'b010 /* unspecified value */ ;
endcase
end
assign uart_rRecvState$EN =
WILL_FIRE_RL_uart_receive_wait_for_start_bit ||
WILL_FIRE_RL_uart_receive_find_center_of_bit_cell ||
WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample ||
WILL_FIRE_RL_uart_receive_stop_first_bit ||
WILL_FIRE_RL_uart_receive_stop_last_bit ||
WILL_FIRE_RL_uart_receive_parity_bit ||
WILL_FIRE_RL_uart_receive_sample_pin ;
// register uart_rXmitBitCount
assign uart_rXmitBitCount$D_IN =
CAN_FIRE_RL_uart_transmit_wait_for_start_command ?
4'd0 :
x__h6471 ;
assign uart_rXmitBitCount$EN =
CAN_FIRE_RL_uart_transmit_wait_for_start_command ||
uart_pwXmitEnableBitCount$whas ;
// register uart_rXmitCellCount
assign uart_rXmitCellCount$D_IN =
uart_pwXmitCellCountReset$whas ? 4'd0 : x__h6445 ;
assign uart_rXmitCellCount$EN =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// register uart_rXmitDataOut
always@(MUX_uart_rXmitDataOut$write_1__SEL_1 or
uart_vrXmitBuffer_0 or
MUX_uart_rXmitDataOut$write_1__SEL_2 or
MUX_uart_rXmitDataOut$write_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_uart_rXmitDataOut$write_1__SEL_1:
uart_rXmitDataOut$D_IN = uart_vrXmitBuffer_0;
MUX_uart_rXmitDataOut$write_1__SEL_2: uart_rXmitDataOut$D_IN = 1'b0;
MUX_uart_rXmitDataOut$write_1__SEL_3: uart_rXmitDataOut$D_IN = 1'b1;
default: uart_rXmitDataOut$D_IN = 1'b0 /* unspecified value */ ;
endcase
end
assign uart_rXmitDataOut$EN =
WILL_FIRE_RL_uart_transmit_shift_next_bit ||
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ||
WILL_FIRE_RL_uart_transmit_send_parity_bit ||
WILL_FIRE_RL_uart_transmit_send_start_bit ||
WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit ||
WILL_FIRE_RL_uart_transmit_wait_for_start_command ;
// register uart_rXmitState
always@(WILL_FIRE_RL_uart_transmit_wait_for_start_command or
MUX_uart_rXmitState$write_1__VAL_1 or
WILL_FIRE_RL_uart_transmit_send_start_bit or
MUX_uart_rXmitState$write_1__VAL_2 or
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time or
MUX_uart_rXmitState$write_1__VAL_3 or
WILL_FIRE_RL_uart_transmit_send_parity_bit or
MUX_uart_rXmitState$write_1__VAL_4 or
WILL_FIRE_RL_uart_transmit_send_stop_bit or
MUX_uart_rXmitState$write_1__VAL_5 or
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 or
MUX_uart_rXmitState$write_1__VAL_6 or
WILL_FIRE_RL_uart_transmit_send_stop_bit2 or
MUX_uart_rXmitState$write_1__VAL_7 or
WILL_FIRE_RL_uart_transmit_shift_next_bit)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_uart_transmit_wait_for_start_command:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_1;
WILL_FIRE_RL_uart_transmit_send_start_bit:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_2;
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_3;
WILL_FIRE_RL_uart_transmit_send_parity_bit:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_4;
WILL_FIRE_RL_uart_transmit_send_stop_bit:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_5;
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_6;
WILL_FIRE_RL_uart_transmit_send_stop_bit2:
uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_7;
WILL_FIRE_RL_uart_transmit_shift_next_bit: uart_rXmitState$D_IN = 3'd2;
default: uart_rXmitState$D_IN = 3'b010 /* unspecified value */ ;
endcase
end
assign uart_rXmitState$EN =
WILL_FIRE_RL_uart_transmit_wait_for_start_command ||
WILL_FIRE_RL_uart_transmit_send_start_bit ||
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ||
WILL_FIRE_RL_uart_transmit_send_parity_bit ||
WILL_FIRE_RL_uart_transmit_send_stop_bit ||
WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
WILL_FIRE_RL_uart_transmit_shift_next_bit ;
// register uart_vrRecvBuffer_0
assign uart_vrRecvBuffer_0$D_IN = uart_vrRecvBuffer_1 ;
assign uart_vrRecvBuffer_0$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_1
assign uart_vrRecvBuffer_1$D_IN = uart_vrRecvBuffer_2 ;
assign uart_vrRecvBuffer_1$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_2
assign uart_vrRecvBuffer_2$D_IN = uart_vrRecvBuffer_3 ;
assign uart_vrRecvBuffer_2$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_3
assign uart_vrRecvBuffer_3$D_IN = uart_vrRecvBuffer_4 ;
assign uart_vrRecvBuffer_3$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_4
assign uart_vrRecvBuffer_4$D_IN = uart_vrRecvBuffer_5 ;
assign uart_vrRecvBuffer_4$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_5
assign uart_vrRecvBuffer_5$D_IN = uart_vrRecvBuffer_6 ;
assign uart_vrRecvBuffer_5$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_6
assign uart_vrRecvBuffer_6$D_IN = uart_vrRecvBuffer_7 ;
assign uart_vrRecvBuffer_6$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrRecvBuffer_7
assign uart_vrRecvBuffer_7$D_IN = uart_rRecvData ;
assign uart_vrRecvBuffer_7$EN = CAN_FIRE_RL_uart_receive_buffer_shift ;
// register uart_vrXmitBuffer_0
assign uart_vrXmitBuffer_0$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[0] :
uart_vrXmitBuffer_1 ;
assign uart_vrXmitBuffer_0$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_1
assign uart_vrXmitBuffer_1$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[1] :
uart_vrXmitBuffer_2 ;
assign uart_vrXmitBuffer_1$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_2
assign uart_vrXmitBuffer_2$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[2] :
uart_vrXmitBuffer_3 ;
assign uart_vrXmitBuffer_2$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_3
assign uart_vrXmitBuffer_3$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[3] :
uart_vrXmitBuffer_4 ;
assign uart_vrXmitBuffer_3$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_4
assign uart_vrXmitBuffer_4$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[4] :
uart_vrXmitBuffer_5 ;
assign uart_vrXmitBuffer_4$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_5
assign uart_vrXmitBuffer_5$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[5] :
uart_vrXmitBuffer_6 ;
assign uart_vrXmitBuffer_5$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_6
assign uart_vrXmitBuffer_6$D_IN =
WILL_FIRE_RL_uart_transmit_buffer_load ?
uart_fifoXmit$D_OUT[6] :
uart_vrXmitBuffer_7 ;
assign uart_vrXmitBuffer_6$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register uart_vrXmitBuffer_7
assign uart_vrXmitBuffer_7$D_IN =
!WILL_FIRE_RL_uart_transmit_buffer_load ||
uart_fifoXmit$D_OUT[7] ;
assign uart_vrXmitBuffer_7$EN =
WILL_FIRE_RL_uart_transmit_buffer_load ||
WILL_FIRE_RL_uart_transmit_buffer_shift ;
// register xmas_fsm_start_reg
assign xmas_fsm_start_reg$D_IN = MUX_xmas_fsm_start_reg$write_1__SEL_1 ;
assign xmas_fsm_start_reg$EN =
EN_operation_mode && operation_mode_arg == 8'hA5 ||
WILL_FIRE_RL_xmas_fsm_fsm_start ;
// register xmas_fsm_start_reg_1
assign xmas_fsm_start_reg_1$D_IN = xmas_fsm_start_wire$whas ;
assign xmas_fsm_start_reg_1$EN = 1'd1 ;
// register xmas_fsm_state_fired
assign xmas_fsm_state_fired$D_IN = xmas_fsm_state_set_pw$whas ;
assign xmas_fsm_state_fired$EN = 1'd1 ;
// register xmas_fsm_state_mkFSMstate
always@(MUX_xmas_fsm_state_mkFSMstate$write_1__SEL_1 or
WILL_FIRE_RL_xmas_fsm_action_l42c32 or
WILL_FIRE_RL_xmas_fsm_action_l43c32 or
WILL_FIRE_RL_xmas_fsm_action_l44c32 or
WILL_FIRE_RL_xmas_fsm_action_l45c32 or
WILL_FIRE_RL_xmas_fsm_action_l46c32 or
WILL_FIRE_RL_xmas_fsm_action_l47c32 or
WILL_FIRE_RL_xmas_fsm_action_l48c32 or
WILL_FIRE_RL_xmas_fsm_action_l49c32 or
WILL_FIRE_RL_xmas_fsm_action_l50c32 or
WILL_FIRE_RL_xmas_fsm_action_l51c32 or
WILL_FIRE_RL_xmas_fsm_action_l52c32 or
WILL_FIRE_RL_xmas_fsm_action_l53c32 or
WILL_FIRE_RL_xmas_fsm_action_l54c32 or
WILL_FIRE_RL_xmas_fsm_action_l55c32 or
WILL_FIRE_RL_xmas_fsm_action_l56c32 or
WILL_FIRE_RL_xmas_fsm_action_l57c32 or
WILL_FIRE_RL_xmas_fsm_action_l58c32 or
WILL_FIRE_RL_xmas_fsm_action_l59c32 or
WILL_FIRE_RL_xmas_fsm_action_l60c32 or
WILL_FIRE_RL_xmas_fsm_action_l61c32 or
WILL_FIRE_RL_xmas_fsm_action_l62c32 or
WILL_FIRE_RL_xmas_fsm_action_l63c32 or
WILL_FIRE_RL_xmas_fsm_action_l64c32 or
WILL_FIRE_RL_xmas_fsm_action_l65c32 or
WILL_FIRE_RL_xmas_fsm_action_l66c32)
begin
case (1'b1) // synopsys parallel_case
MUX_xmas_fsm_state_mkFSMstate$write_1__SEL_1:
xmas_fsm_state_mkFSMstate$D_IN = 5'd0;
WILL_FIRE_RL_xmas_fsm_action_l42c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd1;
WILL_FIRE_RL_xmas_fsm_action_l43c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd2;
WILL_FIRE_RL_xmas_fsm_action_l44c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd3;
WILL_FIRE_RL_xmas_fsm_action_l45c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd4;
WILL_FIRE_RL_xmas_fsm_action_l46c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd5;
WILL_FIRE_RL_xmas_fsm_action_l47c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd6;
WILL_FIRE_RL_xmas_fsm_action_l48c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd7;
WILL_FIRE_RL_xmas_fsm_action_l49c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd8;
WILL_FIRE_RL_xmas_fsm_action_l50c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd9;
WILL_FIRE_RL_xmas_fsm_action_l51c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd10;
WILL_FIRE_RL_xmas_fsm_action_l52c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd11;
WILL_FIRE_RL_xmas_fsm_action_l53c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd12;
WILL_FIRE_RL_xmas_fsm_action_l54c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd13;
WILL_FIRE_RL_xmas_fsm_action_l55c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd14;
WILL_FIRE_RL_xmas_fsm_action_l56c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd15;
WILL_FIRE_RL_xmas_fsm_action_l57c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd16;
WILL_FIRE_RL_xmas_fsm_action_l58c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd17;
WILL_FIRE_RL_xmas_fsm_action_l59c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd18;
WILL_FIRE_RL_xmas_fsm_action_l60c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd19;
WILL_FIRE_RL_xmas_fsm_action_l61c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd20;
WILL_FIRE_RL_xmas_fsm_action_l62c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd21;
WILL_FIRE_RL_xmas_fsm_action_l63c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd22;
WILL_FIRE_RL_xmas_fsm_action_l64c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd23;
WILL_FIRE_RL_xmas_fsm_action_l65c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd24;
WILL_FIRE_RL_xmas_fsm_action_l66c32:
xmas_fsm_state_mkFSMstate$D_IN = 5'd25;
default: xmas_fsm_state_mkFSMstate$D_IN =
5'b01010 /* unspecified value */ ;
endcase
end
assign xmas_fsm_state_mkFSMstate$EN =
WILL_FIRE_RL_xmas_fsm_idle_l40c27_1 ||
WILL_FIRE_RL_xmas_fsm_idle_l40c27 ||
WILL_FIRE_RL_xmas_fsm_action_l42c32 ||
WILL_FIRE_RL_xmas_fsm_action_l43c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l46c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ||
WILL_FIRE_RL_xmas_fsm_action_l48c32 ||
WILL_FIRE_RL_xmas_fsm_action_l49c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l53c32 ||
WILL_FIRE_RL_xmas_fsm_action_l54c32 ||
WILL_FIRE_RL_xmas_fsm_action_l55c32 ||
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l57c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ||
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l62c32 ||
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l64c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ||
WILL_FIRE_RL_xmas_fsm_action_l66c32 ;
// submodule rule30
assign rule30$start_a = a ;
assign rule30$EN_start = CAN_FIRE_RL_compute ;
assign rule30$EN_getResult = CAN_FIRE_RL_get_result ;
// submodule uart_baudGen_rBaudCounter
assign uart_baudGen_rBaudCounter$DATA_A = 16'd1 ;
assign uart_baudGen_rBaudCounter$DATA_B = 16'h0 ;
assign uart_baudGen_rBaudCounter$DATA_C = 16'h0 ;
assign uart_baudGen_rBaudCounter$DATA_F = 16'd0 ;
assign uart_baudGen_rBaudCounter$ADDA =
uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 ;
assign uart_baudGen_rBaudCounter$ADDB = 1'b0 ;
assign uart_baudGen_rBaudCounter$SETC = 1'b0 ;
assign uart_baudGen_rBaudCounter$SETF =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
// submodule uart_baudGen_rBaudTickCounter
assign uart_baudGen_rBaudTickCounter$DATA_A = 3'd1 ;
assign uart_baudGen_rBaudTickCounter$DATA_B = 3'h0 ;
assign uart_baudGen_rBaudTickCounter$DATA_C = 3'h0 ;
assign uart_baudGen_rBaudTickCounter$DATA_F = 3'h0 ;
assign uart_baudGen_rBaudTickCounter$ADDA =
CAN_FIRE_RL_uart_baudGen_count_baudtick_16x ;
assign uart_baudGen_rBaudTickCounter$ADDB = 1'b0 ;
assign uart_baudGen_rBaudTickCounter$SETC = 1'b0 ;
assign uart_baudGen_rBaudTickCounter$SETF = 1'b0 ;
// submodule uart_fifoRecv
assign uart_fifoRecv$D_IN =
{ uart_vrRecvBuffer_7,
uart_vrRecvBuffer_6,
uart_vrRecvBuffer_5,
uart_vrRecvBuffer_4,
uart_vrRecvBuffer_3,
uart_vrRecvBuffer_2,
uart_vrRecvBuffer_1,
uart_vrRecvBuffer_0 } ;
assign uart_fifoRecv$ENQ = CAN_FIRE_RL_uart_receive_stop_last_bit ;
assign uart_fifoRecv$DEQ = uart_fifoRecv$EMPTY_N ;
assign uart_fifoRecv$CLR = 1'b0 ;
// submodule uart_fifoXmit
always@(WILL_FIRE_RL_get_result or
rule30$getResult or
MUX_uart_fifoXmit$enq_1__SEL_2 or
MUX_uart_fifoXmit$enq_1__SEL_3 or
WILL_FIRE_RL_xmas_fsm_action_l64c32 or
WILL_FIRE_RL_xmas_fsm_action_l53c32 or
WILL_FIRE_RL_xmas_fsm_action_l54c32 or
WILL_FIRE_RL_xmas_fsm_action_l55c32 or
WILL_FIRE_RL_xmas_fsm_action_l42c32 or
WILL_FIRE_RL_xmas_fsm_action_l57c32 or
WILL_FIRE_RL_xmas_fsm_action_l48c32 or
MUX_uart_fifoXmit$enq_1__SEL_11 or
WILL_FIRE_RL_xmas_fsm_action_l43c32 or
WILL_FIRE_RL_xmas_fsm_action_l49c32 or
WILL_FIRE_RL_xmas_fsm_action_l62c32 or
MUX_uart_fifoXmit$enq_1__SEL_15 or
MUX_uart_fifoXmit$enq_1__SEL_16 or
MUX_uart_fifoXmit$enq_1__SEL_17 or
WILL_FIRE_RL_xmas_fsm_action_l46c32)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_get_result: uart_fifoXmit$D_IN = rule30$getResult;
MUX_uart_fifoXmit$enq_1__SEL_2: uart_fifoXmit$D_IN = 8'h09;
MUX_uart_fifoXmit$enq_1__SEL_3: uart_fifoXmit$D_IN = 8'h20;
WILL_FIRE_RL_xmas_fsm_action_l64c32: uart_fifoXmit$D_IN = 8'h21;
WILL_FIRE_RL_xmas_fsm_action_l53c32: uart_fifoXmit$D_IN = 8'h27;
WILL_FIRE_RL_xmas_fsm_action_l54c32: uart_fifoXmit$D_IN = 8'h32;
WILL_FIRE_RL_xmas_fsm_action_l55c32: uart_fifoXmit$D_IN = 8'h34;
WILL_FIRE_RL_xmas_fsm_action_l42c32: uart_fifoXmit$D_IN = 8'h4D;
WILL_FIRE_RL_xmas_fsm_action_l57c32: uart_fifoXmit$D_IN = 8'h53;
WILL_FIRE_RL_xmas_fsm_action_l48c32: uart_fifoXmit$D_IN = 8'h58;
MUX_uart_fifoXmit$enq_1__SEL_11: uart_fifoXmit$D_IN = 8'h61;
WILL_FIRE_RL_xmas_fsm_action_l43c32: uart_fifoXmit$D_IN = 8'h65;
WILL_FIRE_RL_xmas_fsm_action_l49c32: uart_fifoXmit$D_IN = 8'h6D;
WILL_FIRE_RL_xmas_fsm_action_l62c32: uart_fifoXmit$D_IN = 8'h6F;
MUX_uart_fifoXmit$enq_1__SEL_15: uart_fifoXmit$D_IN = 8'h72;
MUX_uart_fifoXmit$enq_1__SEL_16: uart_fifoXmit$D_IN = 8'h73;
MUX_uart_fifoXmit$enq_1__SEL_17: uart_fifoXmit$D_IN = 8'h74;
WILL_FIRE_RL_xmas_fsm_action_l46c32: uart_fifoXmit$D_IN = 8'h79;
default: uart_fifoXmit$D_IN = 8'b10101010 /* unspecified value */ ;
endcase
end
assign uart_fifoXmit$ENQ =
WILL_FIRE_RL_get_result || WILL_FIRE_RL_xmas_fsm_action_l66c32 ||
WILL_FIRE_RL_xmas_fsm_action_l65c32 ||
WILL_FIRE_RL_xmas_fsm_action_l56c32 ||
WILL_FIRE_RL_xmas_fsm_action_l52c32 ||
WILL_FIRE_RL_xmas_fsm_action_l47c32 ||
WILL_FIRE_RL_xmas_fsm_action_l64c32 ||
WILL_FIRE_RL_xmas_fsm_action_l53c32 ||
WILL_FIRE_RL_xmas_fsm_action_l54c32 ||
WILL_FIRE_RL_xmas_fsm_action_l55c32 ||
WILL_FIRE_RL_xmas_fsm_action_l42c32 ||
WILL_FIRE_RL_xmas_fsm_action_l57c32 ||
WILL_FIRE_RL_xmas_fsm_action_l48c32 ||
WILL_FIRE_RL_xmas_fsm_action_l60c32 ||
WILL_FIRE_RL_xmas_fsm_action_l50c32 ||
WILL_FIRE_RL_xmas_fsm_action_l43c32 ||
WILL_FIRE_RL_xmas_fsm_action_l49c32 ||
WILL_FIRE_RL_xmas_fsm_action_l62c32 ||
WILL_FIRE_RL_xmas_fsm_action_l59c32 ||
WILL_FIRE_RL_xmas_fsm_action_l45c32 ||
WILL_FIRE_RL_xmas_fsm_action_l44c32 ||
WILL_FIRE_RL_xmas_fsm_action_l63c32 ||
WILL_FIRE_RL_xmas_fsm_action_l51c32 ||
WILL_FIRE_RL_xmas_fsm_action_l61c32 ||
WILL_FIRE_RL_xmas_fsm_action_l58c32 ||
WILL_FIRE_RL_xmas_fsm_action_l46c32 ;
assign uart_fifoXmit$DEQ = CAN_FIRE_RL_uart_transmit_buffer_load ;
assign uart_fifoXmit$CLR = 1'b0 ;
// remaining internal signals
assign _dor2uart_pwXmitCellCountReset$EN_wset =
WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
WILL_FIRE_RL_uart_transmit_send_stop_bit ||
WILL_FIRE_RL_uart_transmit_send_parity_bit ||
WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ||
WILL_FIRE_RL_uart_transmit_send_start_bit ;
assign uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_27___d29 =
uart_baudGen_rBaudCounter$Q_OUT + 16'd1 < 16'd27 ;
assign x__h2985 = uart_rRecvCellCount + 4'd1 ;
assign x__h4689 = uart_rRecvBitCount + 4'd1 ;
assign x__h6445 = uart_rXmitCellCount + 4'd1 ;
assign x__h6471 = uart_rXmitBitCount + 4'd1 ;
assign xmas_fsm_abort_whas__57_AND_xmas_fsm_abort_wge_ETC___d302 =
(xmas_fsm_state_mkFSMstate == 5'd0 ||
xmas_fsm_state_mkFSMstate == 5'd25 ||
xmas_fsm_state_mkFSMstate == 5'd27) &&
(!xmas_fsm_start_reg_1 || xmas_fsm_state_fired) ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
a <= `BSV_ASSIGNMENT_DELAY 8'b0;
op_mode <= `BSV_ASSIGNMENT_DELAY 1'd0;
transmit_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
uart_rRecvData <= `BSV_ASSIGNMENT_DELAY 1'd1;
xmas_fsm_start_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
xmas_fsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
xmas_fsm_state_fired <= `BSV_ASSIGNMENT_DELAY 1'd0;
xmas_fsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY 5'd0;
end
else
begin
if (a$EN) a <= `BSV_ASSIGNMENT_DELAY a$D_IN;
if (op_mode$EN) op_mode <= `BSV_ASSIGNMENT_DELAY op_mode$D_IN;
if (transmit_state$EN)
transmit_state <= `BSV_ASSIGNMENT_DELAY transmit_state$D_IN;
if (uart_rRecvData$EN)
uart_rRecvData <= `BSV_ASSIGNMENT_DELAY uart_rRecvData$D_IN;
if (xmas_fsm_start_reg$EN)
xmas_fsm_start_reg <= `BSV_ASSIGNMENT_DELAY xmas_fsm_start_reg$D_IN;
if (xmas_fsm_start_reg_1$EN)
xmas_fsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY
xmas_fsm_start_reg_1$D_IN;
if (xmas_fsm_state_fired$EN)
xmas_fsm_state_fired <= `BSV_ASSIGNMENT_DELAY
xmas_fsm_state_fired$D_IN;
if (xmas_fsm_state_mkFSMstate$EN)
xmas_fsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY
xmas_fsm_state_mkFSMstate$D_IN;
end
if (uart_vrRecvBuffer_0$EN)
uart_vrRecvBuffer_0 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_0$D_IN;
if (uart_vrRecvBuffer_1$EN)
uart_vrRecvBuffer_1 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_1$D_IN;
if (uart_vrRecvBuffer_2$EN)
uart_vrRecvBuffer_2 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_2$D_IN;
if (uart_vrRecvBuffer_3$EN)
uart_vrRecvBuffer_3 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_3$D_IN;
if (uart_vrRecvBuffer_4$EN)
uart_vrRecvBuffer_4 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_4$D_IN;
if (uart_vrRecvBuffer_5$EN)
uart_vrRecvBuffer_5 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_5$D_IN;
if (uart_vrRecvBuffer_6$EN)
uart_vrRecvBuffer_6 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_6$D_IN;
if (uart_vrRecvBuffer_7$EN)
uart_vrRecvBuffer_7 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_7$D_IN;
if (uart_vrXmitBuffer_0$EN)
uart_vrXmitBuffer_0 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_0$D_IN;
if (uart_vrXmitBuffer_1$EN)
uart_vrXmitBuffer_1 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_1$D_IN;
if (uart_vrXmitBuffer_2$EN)
uart_vrXmitBuffer_2 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_2$D_IN;
if (uart_vrXmitBuffer_3$EN)
uart_vrXmitBuffer_3 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_3$D_IN;
if (uart_vrXmitBuffer_4$EN)
uart_vrXmitBuffer_4 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_4$D_IN;
if (uart_vrXmitBuffer_5$EN)
uart_vrXmitBuffer_5 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_5$D_IN;
if (uart_vrXmitBuffer_6$EN)
uart_vrXmitBuffer_6 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_6$D_IN;
if (uart_vrXmitBuffer_7$EN)
uart_vrXmitBuffer_7 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_7$D_IN;
end
always@(posedge CLK or `BSV_RESET_EDGE RST_N)
if (RST_N == `BSV_RESET_VALUE)
begin
uart_rRecvBitCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
uart_rRecvCellCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
uart_rRecvState <= `BSV_ASSIGNMENT_DELAY 3'd0;
uart_rXmitBitCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
uart_rXmitCellCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
uart_rXmitDataOut <= `BSV_ASSIGNMENT_DELAY 1'd1;
uart_rXmitState <= `BSV_ASSIGNMENT_DELAY 3'd0;
end
else
begin
if (uart_rRecvBitCount$EN)
uart_rRecvBitCount <= `BSV_ASSIGNMENT_DELAY uart_rRecvBitCount$D_IN;
if (uart_rRecvCellCount$EN)
uart_rRecvCellCount <= `BSV_ASSIGNMENT_DELAY uart_rRecvCellCount$D_IN;
if (uart_rRecvState$EN)
uart_rRecvState <= `BSV_ASSIGNMENT_DELAY uart_rRecvState$D_IN;
if (uart_rXmitBitCount$EN)
uart_rXmitBitCount <= `BSV_ASSIGNMENT_DELAY uart_rXmitBitCount$D_IN;
if (uart_rXmitCellCount$EN)
uart_rXmitCellCount <= `BSV_ASSIGNMENT_DELAY uart_rXmitCellCount$D_IN;
if (uart_rXmitDataOut$EN)
uart_rXmitDataOut <= `BSV_ASSIGNMENT_DELAY uart_rXmitDataOut$D_IN;
if (uart_rXmitState$EN)
uart_rXmitState <= `BSV_ASSIGNMENT_DELAY uart_rXmitState$D_IN;
end
// handling of system tasks
endmodule // mkRule30Driver
//
// Generated by Bluespec Compiler, version 2024.01-1-g4d953407 (build 4d953407)
//
// On Thu Apr 18 23:03:51 EDT 2024
//
//
// Ports:
// Name I/O size props
// RDY_start O 1
// getResult O 8 reg
// RDY_getResult O 1
// CLK I 1 clock
// RST_N I 1 reset
// start_a I 8
// EN_start I 1
// EN_getResult I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkRule30(CLK,
RST_N,
start_a,
EN_start,
RDY_start,
EN_getResult,
getResult,
RDY_getResult);
input CLK;
input RST_N;
// action method start
input [7 : 0] start_a;
input EN_start;
output RDY_start;
// actionvalue method getResult
input EN_getResult;
output [7 : 0] getResult;
output RDY_getResult;
// signals for module outputs
wire [7 : 0] getResult;
wire RDY_getResult, RDY_start;
// register busy_flag
reg busy_flag;
wire busy_flag$D_IN, busy_flag$EN;
// register r30
reg [7 : 0] r30;
wire [7 : 0] r30$D_IN;
wire r30$EN;
// register step_complete
reg step_complete;
wire step_complete$D_IN, step_complete$EN;
// register x
reg [55 : 0] x;
wire [55 : 0] x$D_IN;
wire x$EN;
// rule scheduling signals
wire CAN_FIRE_RL_stepper,
CAN_FIRE_getResult,
CAN_FIRE_start,
WILL_FIRE_RL_stepper,
WILL_FIRE_getResult,
WILL_FIRE_start;
// inputs to muxes for submodule ports
wire [55 : 0] MUX_x$write_1__VAL_1, MUX_x$write_1__VAL_2;
// remaining internal signals
wire [51 : 0] r30_BIT_x_BITS_52_TO_50_6_7_CONCAT_r30_BIT_x_B_ETC___d146;
wire [47 : 0] r30_BIT_x_BITS_48_TO_46_4_5_CONCAT_r30_BIT_x_B_ETC___d144;
wire [43 : 0] r30_BIT_x_BITS_44_TO_42_2_3_CONCAT_r30_BIT_x_B_ETC___d142;
wire [39 : 0] r30_BIT_x_BITS_40_TO_38_0_1_CONCAT_r30_BIT_x_B_ETC___d140;
wire [35 : 0] r30_BIT_x_BITS_36_TO_34_8_9_CONCAT_r30_BIT_x_B_ETC___d138;
wire [31 : 0] r30_BIT_x_BITS_32_TO_30_6_7_CONCAT_r30_BIT_x_B_ETC___d136;
wire [27 : 0] r30_BIT_x_BITS_28_TO_26_4_5_CONCAT_r30_BIT_x_B_ETC___d134;
wire [23 : 0] r30_BIT_x_BITS_24_TO_22_2_3_CONCAT_r30_BIT_x_B_ETC___d132;
wire [19 : 0] r30_BIT_x_BITS_20_TO_18_0_1_CONCAT_r30_BIT_x_B_ETC___d130;
wire [15 : 0] r30_BIT_x_BITS_16_TO_14_8_9_CONCAT_r30_BIT_x_B_ETC___d128;
wire [11 : 0] r30_BIT_x_BITS_12_TO_10_6_7_CONCAT_r30_BIT_x_B_ETC___d126;
wire [7 : 0] r30_BIT_x_BITS_8_TO_6_04_05_CONCAT_r30_BIT_x_B_ETC___d124;
wire [3 : 0] r30_BIT_x_BITS_4_TO_2_12_13_CONCAT_r30_BIT_x_B_ETC___d122;
wire [2 : 0] b0__h167, b55__h222;
// action method start
assign RDY_start = !busy_flag ;
assign CAN_FIRE_start = !busy_flag ;
assign WILL_FIRE_start = EN_start ;
// actionvalue method getResult
assign getResult = x[31:24] ;
assign RDY_getResult = busy_flag && step_complete ;
assign CAN_FIRE_getResult = busy_flag && step_complete ;
assign WILL_FIRE_getResult = EN_getResult ;
// rule RL_stepper
assign CAN_FIRE_RL_stepper = busy_flag && !step_complete ;
assign WILL_FIRE_RL_stepper = CAN_FIRE_RL_stepper ;
// inputs to muxes for submodule ports
assign MUX_x$write_1__VAL_1 =
{ r30[b55__h222],
r30[x[55:53]],
r30[x[54:52]],
r30[x[53:51]],
r30_BIT_x_BITS_52_TO_50_6_7_CONCAT_r30_BIT_x_B_ETC___d146 } ;
assign MUX_x$write_1__VAL_2 = { x[55:32], start_a, x[23:0] } ;
// register busy_flag
assign busy_flag$D_IN = !EN_getResult ;
assign busy_flag$EN = EN_getResult || EN_start ;
// register r30
assign r30$D_IN = 8'h0 ;
assign r30$EN = 1'b0 ;
// register step_complete
assign step_complete$D_IN = !EN_start ;
assign step_complete$EN = EN_start || WILL_FIRE_RL_stepper ;
// register x
assign x$D_IN =
WILL_FIRE_RL_stepper ?
MUX_x$write_1__VAL_1 :
MUX_x$write_1__VAL_2 ;
assign x$EN = WILL_FIRE_RL_stepper || EN_start ;
// remaining internal signals
assign b0__h167 = { x[1:0], 1'b0 } ;
assign b55__h222 = { 1'b0, x[55:54] } ;
assign r30_BIT_x_BITS_12_TO_10_6_7_CONCAT_r30_BIT_x_B_ETC___d126 =
{ r30[x[12:10]],
r30[x[11:9]],
r30[x[10:8]],
r30[x[9:7]],
r30_BIT_x_BITS_8_TO_6_04_05_CONCAT_r30_BIT_x_B_ETC___d124 } ;
assign r30_BIT_x_BITS_16_TO_14_8_9_CONCAT_r30_BIT_x_B_ETC___d128 =
{ r30[x[16:14]],
r30[x[15:13]],
r30[x[14:12]],
r30[x[13:11]],
r30_BIT_x_BITS_12_TO_10_6_7_CONCAT_r30_BIT_x_B_ETC___d126 } ;
assign r30_BIT_x_BITS_20_TO_18_0_1_CONCAT_r30_BIT_x_B_ETC___d130 =
{ r30[x[20:18]],
r30[x[19:17]],
r30[x[18:16]],
r30[x[17:15]],
r30_BIT_x_BITS_16_TO_14_8_9_CONCAT_r30_BIT_x_B_ETC___d128 } ;
assign r30_BIT_x_BITS_24_TO_22_2_3_CONCAT_r30_BIT_x_B_ETC___d132 =
{ r30[x[24:22]],
r30[x[23:21]],
r30[x[22:20]],
r30[x[21:19]],
r30_BIT_x_BITS_20_TO_18_0_1_CONCAT_r30_BIT_x_B_ETC___d130 } ;
assign r30_BIT_x_BITS_28_TO_26_4_5_CONCAT_r30_BIT_x_B_ETC___d134 =
{ r30[x[28:26]],
r30[x[27:25]],
r30[x[26:24]],
r30[x[25:23]],
r30_BIT_x_BITS_24_TO_22_2_3_CONCAT_r30_BIT_x_B_ETC___d132 } ;
assign r30_BIT_x_BITS_32_TO_30_6_7_CONCAT_r30_BIT_x_B_ETC___d136 =
{ r30[x[32:30]],
r30[x[31:29]],
r30[x[30:28]],
r30[x[29:27]],
r30_BIT_x_BITS_28_TO_26_4_5_CONCAT_r30_BIT_x_B_ETC___d134 } ;
assign r30_BIT_x_BITS_36_TO_34_8_9_CONCAT_r30_BIT_x_B_ETC___d138 =
{ r30[x[36:34]],
r30[x[35:33]],
r30[x[34:32]],
r30[x[33:31]],
r30_BIT_x_BITS_32_TO_30_6_7_CONCAT_r30_BIT_x_B_ETC___d136 } ;
assign r30_BIT_x_BITS_40_TO_38_0_1_CONCAT_r30_BIT_x_B_ETC___d140 =
{ r30[x[40:38]],
r30[x[39:37]],
r30[x[38:36]],
r30[x[37:35]],
r30_BIT_x_BITS_36_TO_34_8_9_CONCAT_r30_BIT_x_B_ETC___d138 } ;
assign r30_BIT_x_BITS_44_TO_42_2_3_CONCAT_r30_BIT_x_B_ETC___d142 =
{ r30[x[44:42]],
r30[x[43:41]],
r30[x[42:40]],
r30[x[41:39]],
r30_BIT_x_BITS_40_TO_38_0_1_CONCAT_r30_BIT_x_B_ETC___d140 } ;
assign r30_BIT_x_BITS_48_TO_46_4_5_CONCAT_r30_BIT_x_B_ETC___d144 =
{ r30[x[48:46]],
r30[x[47:45]],
r30[x[46:44]],
r30[x[45:43]],
r30_BIT_x_BITS_44_TO_42_2_3_CONCAT_r30_BIT_x_B_ETC___d142 } ;
assign r30_BIT_x_BITS_4_TO_2_12_13_CONCAT_r30_BIT_x_B_ETC___d122 =
{ r30[x[4:2]], r30[x[3:1]], r30[x[2:0]], r30[b0__h167] } ;
assign r30_BIT_x_BITS_52_TO_50_6_7_CONCAT_r30_BIT_x_B_ETC___d146 =
{ r30[x[52:50]],
r30[x[51:49]],
r30[x[50:48]],
r30[x[49:47]],
r30_BIT_x_BITS_48_TO_46_4_5_CONCAT_r30_BIT_x_B_ETC___d144 } ;
assign r30_BIT_x_BITS_8_TO_6_04_05_CONCAT_r30_BIT_x_B_ETC___d124 =
{ r30[x[8:6]],
r30[x[7:5]],
r30[x[6:4]],
r30[x[5:3]],
r30_BIT_x_BITS_4_TO_2_12_13_CONCAT_r30_BIT_x_B_ETC___d122 } ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
busy_flag <= `BSV_ASSIGNMENT_DELAY 1'd0;
r30 <= `BSV_ASSIGNMENT_DELAY 8'd30;
step_complete <= `BSV_ASSIGNMENT_DELAY 1'd0;
x <= `BSV_ASSIGNMENT_DELAY 56'd0;
end
else
begin
if (busy_flag$EN) busy_flag <= `BSV_ASSIGNMENT_DELAY busy_flag$D_IN;
if (r30$EN) r30 <= `BSV_ASSIGNMENT_DELAY r30$D_IN;
if (step_complete$EN)
step_complete <= `BSV_ASSIGNMENT_DELAY step_complete$D_IN;
if (x$EN) x <= `BSV_ASSIGNMENT_DELAY x$D_IN;
end
end
endmodule // mkRule30
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
// N -bit counter with load, set and 2 increment
module Counter(CLK,
RST,
Q_OUT,
DATA_A, ADDA,
DATA_B, ADDB,
DATA_C, SETC,
DATA_F, SETF);
parameter width = 1;
parameter init = 0;
input CLK;
input RST;
input [width - 1 : 0] DATA_A;
input ADDA;
input [width - 1 : 0] DATA_B;
input ADDB;
input [width - 1 : 0] DATA_C;
input SETC;
input [width - 1 : 0] DATA_F;
input SETF;
output [width - 1 : 0] Q_OUT;
reg [width - 1 : 0] q_state ;
assign Q_OUT = q_state ;
always@(posedge CLK `BSV_ARESET_EDGE_META) begin
if (RST == `BSV_RESET_VALUE)
q_state <= `BSV_ASSIGNMENT_DELAY init;
else
begin
if ( SETF )
q_state <= `BSV_ASSIGNMENT_DELAY DATA_F ;
else
q_state <= `BSV_ASSIGNMENT_DELAY (SETC ? DATA_C : q_state ) + (ADDA ? DATA_A : {width {1'b0}}) + (ADDB ? DATA_B : {width {1'b0}} ) ;
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK)
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial begin
q_state = {((width + 1)/2){2'b10}} ;
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
`ifdef BSV_RESET_FIFO_HEAD
`define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_HEAD
`endif
`ifdef BSV_RESET_FIFO_ARRAY
`define BSV_ARESET_EDGE_ARRAY `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_ARRAY
`endif
// Sized fifo. Model has output register which improves timing
module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR);
parameter p1width = 1; // data width
parameter p2depth = 3;
parameter p3cntr_width = 1; // log(p2depth-1)
// The -1 is allowed since this model has a fast output register
parameter guarded = 1'b1;
localparam p2depth2 = (p2depth >= 2) ? (p2depth -2) : 0 ;
input CLK;
input RST;
input CLR;
input [p1width - 1 : 0] D_IN;
input ENQ;
input DEQ;
output FULL_N;
output EMPTY_N;
output [p1width - 1 : 0] D_OUT;
reg not_ring_full;
reg ring_empty;
reg [p3cntr_width-1 : 0] head;
wire [p3cntr_width-1 : 0] next_head;
reg [p3cntr_width-1 : 0] tail;
wire [p3cntr_width-1 : 0] next_tail;
// if the depth is too small, don't create an ill-sized array;
// instead, make a 1-sized array and let the initial block report an error
reg [p1width - 1 : 0] arr[0: p2depth2];
reg [p1width - 1 : 0] D_OUT;
reg hasodata;
wire [p3cntr_width-1:0] depthLess2 = p2depth2[p3cntr_width-1:0] ;
wire [p3cntr_width-1 : 0] incr_tail;
wire [p3cntr_width-1 : 0] incr_head;
assign incr_tail = tail + 1'b1 ;
assign incr_head = head + 1'b1 ;
assign next_head = (head == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_head ;
assign next_tail = (tail == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_tail ;
assign EMPTY_N = hasodata;
assign FULL_N = not_ring_full;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin : initial_block
integer i;
D_OUT = {((p1width + 1)/2){2'b10}} ;
ring_empty = 1'b1;
not_ring_full = 1'b1;
hasodata = 1'b0;
head = {p3cntr_width {1'b0}} ;
tail = {p3cntr_width {1'b0}} ;
for (i = 0; i <= p2depth2; i = i + 1)
begin
arr[i] = D_OUT ;
end
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
always @(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (RST == `BSV_RESET_VALUE)
else
begin
casez ({CLR, DEQ, ENQ, hasodata, ring_empty})
// Clear operation
5'b1????: begin
head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
// -----------------------
// DEQ && ENQ case -- change head and tail if added to ring
5'b011?0: begin
tail <= `BSV_ASSIGNMENT_DELAY next_tail;
head <= `BSV_ASSIGNMENT_DELAY next_head;
end
// -----------------------
// DEQ only and NO data is in ring
5'b010?1: begin
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
// DEQ only and data is in ring (move the head pointer)
5'b010?0: begin
head <= `BSV_ASSIGNMENT_DELAY next_head;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
ring_empty <= `BSV_ASSIGNMENT_DELAY next_head == tail ;
end
// -----------------------
// ENQ only when empty
5'b0010?: begin
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b1;
end
// ENQ only when not empty
5'b0011?: begin
if ( not_ring_full ) // Drop this test to save redundant test
// but be warnned that with test fifo overflow causes loss of new data
// while without test fifo drops all but head entry! (pointer overflow)
begin
tail <= `BSV_ASSIGNMENT_DELAY next_tail;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b0;
not_ring_full <= `BSV_ASSIGNMENT_DELAY ! (next_tail == head) ;
end
end
endcase
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// Update the fast data out register
always @(posedge CLK `BSV_ARESET_EDGE_HEAD)
begin
`ifdef BSV_RESET_FIFO_HEAD
if (RST == `BSV_RESET_VALUE)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
end // if (RST == `BSV_RESET_VALUE)
else
`endif
begin
casez ({CLR, DEQ, ENQ, hasodata, ring_empty})
// DEQ && ENQ cases
5'b011?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end
5'b011?1: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end
// DEQ only and data is in ring
5'b010?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end
// ENQ only when empty
5'b0010?: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end
endcase
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// Update the memory array reset is OFF
always @(posedge CLK `BSV_ARESET_EDGE_ARRAY)
begin: array
`ifdef BSV_RESET_FIFO_ARRAY
if (RST == `BSV_RESET_VALUE)
begin: rst_array
integer i;
for (i = 0; i <= p2depth2 && p2depth > 2; i = i + 1)
begin
arr[i] <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
end
end // if (RST == `BSV_RESET_VALUE)
else
`endif
begin
if (!CLR && ENQ && ((DEQ && !ring_empty) || (!DEQ && hasodata && not_ring_full)))
begin
arr[tail] <= `BSV_ASSIGNMENT_DELAY D_IN;
end
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if (RST == ! `BSV_RESET_VALUE)
begin
if ( ! EMPTY_N && DEQ )
begin
deqerror = 1 ;
$display( "Warning: SizedFIFO: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && (!DEQ || guarded) )
begin
enqerror = 1 ;
$display( "Warning: SizedFIFO: %m -- Enqueuing to a full fifo" ) ;
end
end
end // block: error_checks
// synopsys translate_on
// synopsys translate_off
// Some assertions about parameter values
initial
begin : parameter_assertions
integer ok ;
ok = 1 ;
if ( p2depth <= 1)
begin
ok = 0;
$display ( "Warning SizedFIFO: %m -- depth parameter increased from %0d to 2", p2depth);
end
if ( p3cntr_width <= 0 )
begin
ok = 0;
$display ( "ERROR SizedFIFO: %m -- width parameter must be greater than 0" ) ;
end
if ( ok == 0 ) $finish ;
end // initial begin
// synopsys translate_on
endmodule
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
`ifdef BSV_RESET_FIFO_HEAD
`define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_HEAD
`endif
// Depth 1 FIFO
module FIFO1(CLK,
RST,
D_IN,
ENQ,
FULL_N,
D_OUT,
DEQ,
EMPTY_N,
CLR
);
parameter width = 1;
parameter guarded = 1'b1;
input CLK;
input RST;
input [width - 1 : 0] D_IN;
input ENQ;
input DEQ;
input CLR ;
output FULL_N;
output [width - 1 : 0] D_OUT;
output EMPTY_N;
reg [width - 1 : 0] D_OUT;
reg empty_reg ;
assign EMPTY_N = empty_reg ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
D_OUT = {((width + 1)/2) {2'b10}} ;
empty_reg = 1'b0 ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
assign FULL_N = !empty_reg;
always@(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (RST == `BSV_RESET_VALUE)
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (CLR)
else if (ENQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // if (ENQ)
else if (DEQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (DEQ)
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
always@(posedge CLK `BSV_ARESET_EDGE_HEAD)
begin
`ifdef BSV_RESET_FIFO_HEAD
if (RST == `BSV_RESET_VALUE)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
end
else
`endif
begin
if (ENQ)
D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN;
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if (RST == ! `BSV_RESET_VALUE)
begin
if ( ! empty_reg && DEQ )
begin
deqerror = 1 ;
$display( "Warning: FIFO1: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && (!DEQ || guarded) )
begin
enqerror = 1 ;
$display( "Warning: FIFO1: %m -- Enqueuing to a full fifo" ) ;
end
end // if (RST == ! `BSV_RESET_VALUE)
end
// synopsys translate_on
endmodule
|
module tt_um_andrewtron3000 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// Held in reset while ena is not set
wire reset_n;
assign reset_n = rst_n & ena;
assign uio_oe = 8'b00000000; // All bidirectional outputs disabled
assign uio_out = 0;
// Assign output
assign uo_out[0] = 0;
assign uo_out[1] = 0;
assign uo_out[2] = 0;
assign uo_out[3] = 0;
assign uo_out[4] = driver_sout; // uo_out[4] is UART TX
assign uo_out[5] = 0;
assign uo_out[6] = 0;
assign uo_out[7] = 0;
// ports of submodule driver
wire driver_sin, driver_sout;
assign driver_sin = 0;
wire startup_input_ready;
wire startup_input_enable;
wire operation_mode_ready;
wire operation_mode_enable;
// submodule rule_30_driver
mkRule30Driver rule_30_driver(.CLK(clk),
.RST_N(reset_n),
.operation_mode_arg(uio_in),
.EN_operation_mode(operation_mode_enable),
.RDY_operation_mode(operation_mode_ready),
.startup_value_v(ui_in),
.EN_startup_value(startup_input_enable),
.RDY_startup_value(startup_input_ready),
.txrx_SIN(driver_sin),
.txrx_SOUT(driver_sout));
assign startup_input_enable = startup_input_ready;
assign operation_mode_enable = operation_mode_ready;
endmodule
|
tt06-finale_0056
|
tt06-finale
|
couchand-tt06-cora16
|
task_alu
|
tt_um_couchand_cora16
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Andrew Dona-Couch
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_couchand_cora16 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// Allow external SPI RAM programming on reset
assign uio_oe = rst_n ? 8'b11100111 : 8'b11100000;
assign uio_out[4:3] = 0;
wire spi_miso, spi_select, spi_clk, spi_mosi;
assign spi_miso = uio_in[3];
assign uio_out[1] = spi_select;
assign uio_out[2] = spi_clk;
assign uio_out[0] = spi_mosi;
wire step, busy, halt, trap;
assign step = uio_in[4];
assign uio_out[5] = busy;
assign uio_out[6] = halt;
assign uio_out[7] = trap;
cpu cpu_instance(
.clk(clk),
.rst_n(rst_n),
.spi_mosi(spi_mosi),
.spi_select(spi_select),
.spi_clk(spi_clk),
.spi_miso(spi_miso),
.step(step),
.busy(busy),
.halt(halt),
.trap(trap),
.data_in(ui_in),
.data_out(uo_out)
);
endmodule
/*
* Copyright (c) 2024 Andrew Dona-Couch
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module cpu (
input wire clk,
input wire rst_n,
output wire spi_mosi,
output wire spi_select,
output wire spi_clk,
input wire spi_miso,
input wire step,
output wire busy,
output wire halt,
output wire trap,
input wire [7:0] data_in,
output reg [7:0] data_out
);
reg [15:0] pc;
reg [15:0] inst;
reg [15:0] accum;
reg [15:0] dp;
reg [15:0] sp;
reg zero;
reg neg;
reg carry;
reg skip;
reg skipped;
wire [15:0] alu_rhs = (state == ST_INST_EXEC0) ? rhs : ram_data_out;
wire [15:0] alu_result;
wire alu_zero, alu_neg, alu_carry, is_alu_inst;
alu alu_instance(
.accum(accum),
.rhs(alu_rhs),
.result(alu_result),
.zero(alu_zero),
.neg(alu_neg),
.carry(alu_carry),
.is_alu_inst(is_alu_inst),
.inst_add(inst_add),
.inst_sub(inst_sub),
.inst_test(inst_test),
.inst_and(inst_and),
.inst_or(inst_or),
.inst_xor(inst_xor),
.inst_not(inst_not),
.inst_shl(inst_shl),
.inst_shr(inst_shr)
);
wire [15:0] rhs;
wire [1:0] inst_bytes_raw;
wire [15:0] inst_bytes = {14'b0, inst_bytes_raw};
wire inst_load, inst_store, inst_add, inst_sub, inst_test, inst_status;
wire inst_and, inst_or, inst_xor, inst_not, inst_shl, inst_shr;
wire inst_branch, inst_call, inst_if, inst_push, inst_pop, inst_drop, inst_return;
wire inst_nop, inst_out_lo, inst_out_hi, inst_halt, inst_trap, inst_set_dp;
wire inst_call_word, inst_load_word;
wire source_imm, source_ram, source_indirect;
wire relative_stack, relative_data;
wire if_zero, if_not_zero, if_else, if_not_else, if_neg, if_not_neg, if_carry, if_not_carry;
wire decoding = (state == ST_INST_EXEC0) | (state == ST_INST_EXEC1)
| (state == ST_INST_EXEC2) | (state == ST_INST_EXEC3);
decoder inst_decoder(
.en(decoding),
.inst(inst),
.accum(accum),
.data(data_in),
.rhs(rhs),
.bytes(inst_bytes_raw),
.inst_nop(inst_nop),
.inst_halt(inst_halt),
.inst_trap(inst_trap),
.inst_load(inst_load),
.inst_store(inst_store),
.inst_add(inst_add),
.inst_sub(inst_sub),
.inst_and(inst_and),
.inst_or(inst_or),
.inst_xor(inst_xor),
.inst_shl(inst_shl),
.inst_shr(inst_shr),
.inst_not(inst_not),
.inst_branch(inst_branch),
.inst_call(inst_call),
.inst_if(inst_if),
.inst_push(inst_push),
.inst_pop(inst_pop),
.inst_drop(inst_drop),
.inst_return(inst_return),
.inst_out_lo(inst_out_lo),
.inst_out_hi(inst_out_hi),
.inst_set_dp(inst_set_dp),
.inst_test(inst_test),
.inst_status(inst_status),
.inst_call_word(inst_call_word),
.inst_load_word(inst_load_word),
.source_imm(source_imm),
.source_ram(source_ram),
.source_indirect(source_indirect),
.relative_stack(relative_stack),
.relative_data(relative_data),
.if_zero(if_zero),
.if_not_zero(if_not_zero),
.if_else(if_else),
.if_not_else(if_not_else),
.if_neg(if_neg),
.if_not_neg(if_not_neg),
.if_carry(if_carry),
.if_not_carry(if_not_carry)
);
reg [8:0] state;
localparam ST_INIT = 0;
localparam ST_HALT = 1;
localparam ST_TRAP = 2;
localparam ST_LOAD_INST0 = 3;
localparam ST_LOAD_INST1 = 4;
localparam ST_INST_EXEC0 = 5;
localparam ST_INST_EXEC1 = 6;
localparam ST_INST_EXEC2 = 7;
localparam ST_INST_EXEC3 = 8;
localparam ST_UNTRAP = 9;
localparam ST_FAULT = 10;
assign busy = state != ST_INIT & state != ST_HALT & state != ST_TRAP & state != ST_FAULT;
assign halt = (state == ST_HALT) | (state == ST_FAULT);
assign trap = (state == ST_TRAP) | (state == ST_FAULT);
wire [15:0] sp_minus_two = sp - 2;
wire [15:0] ram_addr = (state == ST_LOAD_INST0) ? pc
: ((state == ST_INST_EXEC0) & (inst_push | inst_call | inst_call_word)) ? sp_minus_two
: ((state == ST_INST_EXEC0) & (inst_pop | inst_return)) ? sp
: ((state == ST_INST_EXEC0) & inst_load_word) ? (pc + inst_bytes)
: ((state == ST_INST_EXEC0) & (source_ram | source_indirect))
? ((relative_stack ? sp : relative_data ? dp : 0) + rhs)
: ((state == ST_INST_EXEC2) & inst_call_word) ? (pc + inst_bytes)
: ((state == ST_INST_EXEC2) & source_indirect) ? ram_data_out
: 0;
wire ram_start_read = (state == ST_LOAD_INST0) ? 1
: ((state == ST_INST_EXEC0) & ((source_ram & ~inst_store) | source_indirect)) ? ~skip
: ((state == ST_INST_EXEC0) & (inst_pop | inst_return)) ? ~skip
: ((state == ST_INST_EXEC0) & inst_load_word) ? ~skip
: ((state == ST_INST_EXEC2) & inst_call_word) ? ~skip
: ((state == ST_INST_EXEC2) & source_indirect) ? ~skip
: 0;
wire [15:0] ram_data_in = ((state == ST_INST_EXEC0) & source_ram & inst_store) ? accum
: ((state == ST_INST_EXEC0) & inst_push) ? accum
: ((state == ST_INST_EXEC0) & inst_call) ? (pc + inst_bytes)
: ((state == ST_INST_EXEC0) & inst_call_word) ? (pc + inst_bytes + 2)
: ((state == ST_INST_EXEC2) & source_indirect & inst_store) ? accum
: 0;
wire ram_start_write = ((state == ST_INST_EXEC0) & source_ram & inst_store) ? ~skip
: ((state == ST_INST_EXEC0) & (inst_push | inst_call | inst_call_word)) ? ~skip
: ((state == ST_INST_EXEC2) & source_indirect & inst_store) ? ~skip
: 0;
wire [15:0] ram_data_out;
wire ram_busy;
spi_ram_controller #(
.DATA_WIDTH_BYTES(2),
.ADDR_BITS(16)
) spi_ram (
.clk(clk),
.rstn(rst_n),
.spi_miso(spi_miso),
.spi_select(spi_select),
.spi_clk_out(spi_clk),
.spi_mosi(spi_mosi),
.addr_in(ram_addr),
.data_in(ram_data_in),
.start_read(ram_start_read),
.start_write(ram_start_write),
.data_out(ram_data_out),
.busy(ram_busy)
);
always @(posedge clk) begin
if (!rst_n) begin
state <= ST_INIT;
pc <= 0;
inst <= 0;
accum <= 0;
dp <= 0;
sp <= 0;
zero <= 0;
neg <= 0;
carry <= 0;
skip <= 0;
skipped <= 0;
data_out <= 0;
end else if (~halt) begin
if (state == ST_INIT) begin
if (step) begin
state <= ST_LOAD_INST0;
end
end else if (state == ST_TRAP) begin
if (step) begin
state <= ST_UNTRAP;
end
end else if (state == ST_UNTRAP) begin
if (~step) begin
state <= ST_INIT;
end
end else if (state == ST_LOAD_INST0) begin
state <= ST_LOAD_INST1;
end else if (state == ST_LOAD_INST1) begin
if (!ram_busy) begin
inst <= ram_data_out;
state <= ST_INST_EXEC0;
end
end else if (state == ST_INST_EXEC0) begin
if (inst_nop) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (inst_halt) begin
pc <= pc + inst_bytes;
if (skip) begin
state <= ST_INIT;
end else begin
state <= ST_HALT;
end
end else if (inst_trap) begin
pc <= pc + inst_bytes;
if (skip) begin
state <= ST_INIT;
end else begin
state <= ST_TRAP;
end
end else if (inst_set_dp) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
if (~skip) begin
dp <= accum;
end
end else if (inst_status) begin
accum <= {8'b0, 2'b0, skipped, 2'b0, carry, neg, zero};
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (inst_drop) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
if (~skip) begin
sp <= sp + 2;
end
end else if (inst_push | inst_pop) begin
if (skip) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else begin
state <= ST_INST_EXEC1;
end
end else if (inst_call_word | inst_load_word) begin
if (skip) begin
pc <= pc + inst_bytes + 2;
state <= ST_INIT;
end else begin
state <= ST_INST_EXEC1;
end
end else if (inst_load) begin
if (skip) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (source_imm) begin
accum <= rhs;
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (source_ram | source_indirect) begin
state <= ST_INST_EXEC1;
end else begin
state <= ST_FAULT;
end
end else if (inst_store) begin
if (skip) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (source_imm) begin
state <= ST_FAULT;
end else if (source_ram | source_indirect) begin
state <= ST_INST_EXEC1;
end else begin
state <= ST_FAULT;
end
end else if (is_alu_inst) begin
if (skip) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (source_imm) begin
accum <= alu_result;
zero <= alu_zero;
neg <= alu_neg;
carry <= alu_carry;
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (source_ram | source_indirect) begin
state <= ST_INST_EXEC1;
end else begin
state <= ST_FAULT;
end
end else if (inst_branch) begin
state <= ST_INIT;
if (skip) begin
pc <= pc + inst_bytes;
end else begin
pc <= pc + inst_bytes + rhs;
end
end else if (inst_call) begin
if (skip) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else begin
state <= ST_INST_EXEC1;
end
end else if (inst_return) begin
if (skip) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else begin
state <= ST_INST_EXEC1;
end
end else if (inst_if) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (inst_out_lo) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
if (~skip) begin
data_out <= accum[7:0];
end
end else if (inst_out_hi) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
if (~skip) begin
data_out <= accum[15:8];
end
end else begin
state <= ST_FAULT;
end
if (inst_if) begin
if (if_zero) begin
skip <= ~zero;
end else if (if_not_zero) begin
skip <= zero;
end else if (if_else) begin
skip <= ~skipped;
end else if (if_not_else) begin
skip <= skipped;
end else if (if_neg) begin
skip <= ~neg;
end else if (if_not_neg) begin
skip <= neg;
end else if (if_carry) begin
skip <= ~carry;
end else if (if_not_carry) begin
skip <= carry;
end else begin
state <= ST_FAULT;
end
end else begin
skip <= 0;
end
skipped <= skip;
end else if (state == ST_INST_EXEC1) begin
if (!ram_busy) begin
if (inst_push) begin
sp <= sp_minus_two;
state <= ST_INIT;
pc <= pc + inst_bytes;
end else if (inst_pop) begin
sp <= sp + 2;
accum <= ram_data_out;
state <= ST_INIT;
pc <= pc + inst_bytes;
end else if (inst_call) begin
sp <= sp_minus_two;
state <= ST_INIT;
pc <= rhs;
end else if (inst_return) begin
sp <= sp + 2;
state <= ST_INIT;
pc <= ram_data_out;
end else if (inst_call_word) begin
sp <= sp_minus_two;
state <= ST_INST_EXEC2;
end else if (inst_load_word) begin
accum <= ram_data_out;
pc <= pc + inst_bytes + 2;
state <= ST_INIT;
end else if (source_ram) begin
if (inst_load) begin
accum <= ram_data_out;
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (is_alu_inst) begin
accum <= alu_result;
zero <= alu_zero;
neg <= alu_neg;
carry <= alu_carry;
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (inst_store) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else begin
state <= ST_FAULT;
end
end else if (source_indirect) begin
if (!ram_busy) begin
state <= ST_INST_EXEC2;
end
end else begin
state <= ST_FAULT;
end
end
end else if (state == ST_INST_EXEC2) begin
state <= ST_INST_EXEC3;
end else if (state == ST_INST_EXEC3) begin
if (!ram_busy) begin
if (inst_load) begin
accum <= ram_data_out;
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (is_alu_inst) begin
accum <= alu_result;
zero <= alu_zero;
neg <= alu_neg;
carry <= alu_carry;
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (inst_store) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (inst_call_word) begin
pc <= ram_data_out;
state <= ST_INIT;
end else begin
state <= ST_FAULT;
end
end
end else begin
state <= ST_FAULT;
end
end
end
endmodule
/*
* Copyright (c) 2024 Andrew Dona-Couch
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module decoder (
input wire en,
input wire [15:0] inst,
input wire [15:0] accum,
input wire [7:0] data,
output wire [15:0] rhs,
output wire [1:0] bytes,
output wire inst_nop,
output wire inst_halt,
output wire inst_trap,
output wire inst_load,
output wire inst_store,
output wire inst_add,
output wire inst_sub,
output wire inst_and,
output wire inst_or,
output wire inst_xor,
output wire inst_shl,
output wire inst_shr,
output wire inst_not,
output wire inst_branch,
output wire inst_call,
output wire inst_if,
output wire inst_push,
output wire inst_pop,
output wire inst_drop,
output wire inst_return,
output wire inst_out_lo,
output wire inst_out_hi,
output wire inst_set_dp,
output wire inst_test,
output wire inst_status,
output wire inst_call_word,
output wire inst_load_word,
output wire source_imm,
output wire source_ram,
output wire source_indirect,
output wire relative_data,
output wire relative_stack,
output wire if_zero,
output wire if_not_zero,
output wire if_else,
output wire if_not_else,
output wire if_neg,
output wire if_not_neg,
output wire if_carry,
output wire if_not_carry
);
wire zero_arg = en & ((inst & 16'h8000) == 16'h0000);
assign inst_nop = en & ((inst >> 8) == 16'h0000);
assign inst_halt = en & ((inst >> 8) == 16'h0001);
assign inst_trap = en & ((inst >> 8) == 16'h0002);
assign inst_drop = en & ((inst >> 8) == 16'h0003);
assign inst_push = en & ((inst >> 8) == 16'h0004);
assign inst_pop = en & ((inst >> 8) == 16'h0005);
assign inst_return = en & ((inst >> 8) == 16'h0006);
assign inst_not = en & ((inst >> 8) == 16'h0007);
assign inst_out_lo = en & ((inst >> 8) == 16'h0008);
assign inst_out_hi = en & ((inst >> 8) == 16'h0009);
assign inst_set_dp = en & ((inst >> 8) == 16'h000A);
assign inst_test = en & ((inst >> 8) == 16'h000B);
assign inst_status = en & ((inst >> 8) == 16'h0010);
assign inst_call_word = en & ((inst >> 8) == 16'h003E);
assign inst_load_word = en & ((inst >> 8) == 16'h003F);
wire inst_load_indirect = en & (((inst >> 8) & 16'h00FC) == 16'h0044);
assign bytes = zero_arg ? 1 : 2;
wire one_arg = en & ((inst & 16'hC000) == 16'h8000);
wire inst_load_direct = en & ((inst & 16'hF800) == 16'h8000);
assign inst_load = inst_load_direct | inst_load_indirect;
assign inst_store = en & ((inst & 16'hF800) == 16'h9000);
assign inst_add = en & ((inst & 16'hF800) == 16'h8800);
assign inst_sub = en & ((inst & 16'hF800) == 16'h9800);
assign inst_and = en & ((inst & 16'hF800) == 16'hA000);
assign inst_or = en & ((inst & 16'hF800) == 16'hA800);
assign inst_xor = en & ((inst & 16'hF800) == 16'hB000);
wire inst_sh = en & ((inst & 16'hF800) == 16'hB800);
assign inst_shl = ~inst_sh ? 0
: source_ram ? ((inst & 16'h0001) == 16'h0000)
: ((inst & 16'h0100) == 16'h0000);
assign inst_shr = ~inst_sh ? 0
: source_ram ? ((inst & 16'h0001) == 16'h0001)
: ((inst & 16'h0100) == 16'h0100);
wire inst_branch_direct = en & ((inst & 16'hF800) == 16'hC000);
wire inst_branch_indirect = en & ((inst >> 8) == 16'h000C);
assign inst_branch = inst_branch_direct | inst_branch_indirect;
wire inst_call_direct = en & ((inst & 16'hF800) == 16'hD000);
wire inst_call_indirect = en & ((inst >> 8) == 16'h000D);
assign inst_call = inst_call_direct | inst_call_indirect;
assign inst_if = en & ((inst & 16'hF800) == 16'hF000);
wire source_const = !one_arg ? 0 : (inst & 16'h0600) == 16'h0000;
wire source_data = !one_arg ? 0 : (inst & 16'h0600) == 16'h0200;
wire source_none = inst_not | inst_test;
assign source_imm = source_const | source_data | source_none;
assign source_ram = (one_arg | inst_load_indirect) & ((inst & 16'h0500) == 16'h0400);
assign source_indirect = (one_arg | inst_load_indirect) & ((inst & 16'h0500) == 16'h0500);
assign relative_data = (source_ram | source_indirect)
? (inst & 16'h0200) == 16'h0000
: 0;
assign relative_stack = (source_ram | source_indirect)
? (inst & 16'h0200) == 16'h0200
: 0;
assign rhs = !en ? 0
: (inst_branch_direct | inst_call_direct) ? {{5{inst[10]}}, inst[10:0]}
: (inst_load_indirect | inst_branch_indirect | inst_call_indirect) ? accum
: (((inst & 16'h0600) == 16'h0000) & inst_sh) ? {8'h00, inst[7:0]}
: (((inst & 16'h0600) == 16'h0200) & inst_sh) ? {8'h00, data}
: (inst & 16'h0700) == 16'h0000 ? {8'h00, inst[7:0]}
: (inst & 16'h0700) == 16'h0100 ? {inst[7:0], 8'h00}
: (inst & 16'h0700) == 16'h0200 ? {8'h00, data}
: (inst & 16'h0700) == 16'h0300 ? {data, 8'h00}
: (((inst & 16'h0400) == 16'h0400) & inst_sh) ? {8'h00, inst[7:1], 1'b0}
: (inst & 16'h0400) == 16'h0400 ? {8'h00, inst[7:0]}
: 0;
assign if_zero = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0000;
assign if_not_zero = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0001;
assign if_else = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0002;
assign if_not_else = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0003;
assign if_neg = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0004;
assign if_not_neg = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0005;
assign if_carry = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0006;
assign if_not_carry = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0007;
endmodule
/*
* Copyright (c) 2024 Andrew Dona-Couch
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module alu (
input wire [15:0] accum,
input wire [15:0] rhs,
output wire [15:0] result,
output wire zero,
output wire neg,
output wire carry,
output wire is_alu_inst,
input wire inst_add,
input wire inst_sub,
input wire inst_test,
input wire inst_and,
input wire inst_or,
input wire inst_xor,
input wire inst_not,
input wire inst_shl,
input wire inst_shr
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
/* Copyright 2023 (c) Michael Bell
A simple SPI RAM controller
To perform a read:
- Set addr_in and set start_read high for 1 cycle
- Wait for busy to go low
- The read data is now available on data_out
To perform a write:
- Set addr_in, data_in and set start_write high for 1 cycle
- Wait for busy to go low before starting another operation
If the controller is configured to transfer multiple bytes, then
note that the word transferred in data_in/data_out is in big
endian order, i.e. the byte with the lowest address is aligned to
the MSB of the word.
*/
module spi_ram_controller #(parameter DATA_WIDTH_BYTES=4, parameter ADDR_BITS=16) (
input clk,
input rstn,
// External SPI interface
input spi_miso,
output spi_select,
output spi_clk_out,
output spi_mosi,
// Internal interface for reading/writing data
input [ADDR_BITS-1:0] addr_in,
input [DATA_WIDTH_BYTES*8-1:0] data_in,
input start_read,
input start_write,
output [DATA_WIDTH_BYTES*8-1:0] data_out,
output busy
);
//`ifdef COCOTB_SIM
//initial begin
// $dumpfile ("spi.vcd");
// $dumpvars (0, spi_ram_controller);
// #1;
//end
//`endif
`define max(a, b) (a > b) ? a : b
localparam DATA_WIDTH_BITS = DATA_WIDTH_BYTES * 8;
localparam FSM_IDLE = 0;
localparam FSM_CMD = 1;
localparam FSM_ADDR = 2;
localparam FSM_DATA = 3;
reg [1:0] fsm_state;
reg writing;
reg spi_miso_buf;
reg [ADDR_BITS-1:0] addr;
reg [DATA_WIDTH_BITS-1:0] data;
reg [$clog2(`max(DATA_WIDTH_BITS,ADDR_BITS))-1:0] bits_remaining;
assign data_out = data;
assign busy = fsm_state != FSM_IDLE;
always @(posedge clk) begin
if (!rstn) begin
fsm_state <= FSM_IDLE;
bits_remaining <= 0;
end else begin
if (fsm_state == FSM_IDLE) begin
if (start_read || start_write) begin
fsm_state <= FSM_CMD;
bits_remaining <= 8-1;
end
end else begin
if (bits_remaining == 0) begin
fsm_state <= fsm_state + 1;
if (fsm_state == FSM_CMD) bits_remaining <= ADDR_BITS-1;
else if (fsm_state == FSM_ADDR) bits_remaining <= DATA_WIDTH_BITS-1;
end else begin
bits_remaining <= bits_remaining - 1;
end
end
end
end
always @(posedge clk) begin
if (fsm_state == FSM_IDLE && (start_read || start_write)) begin
addr <= addr_in;
writing <= start_write;
end else if (fsm_state == FSM_ADDR) begin
addr <= {addr[ADDR_BITS-2:0], 1'b0};
end
end
always @(negedge clk) begin
spi_miso_buf <= spi_miso;
end
always @(posedge clk) begin
if (fsm_state == FSM_IDLE && start_write) begin
data <= data_in;
end else if (fsm_state == FSM_DATA) begin
data <= {data[DATA_WIDTH_BITS-2:0], spi_miso_buf};
end
end
assign spi_select = fsm_state == FSM_IDLE;
assign spi_clk_out = !clk;
assign spi_mosi = fsm_state == FSM_IDLE ? 1'b0 :
fsm_state == FSM_CMD ? (bits_remaining == 1 || (bits_remaining == 0 && !writing)) :
fsm_state == FSM_ADDR ? addr[ADDR_BITS-1] :
data[DATA_WIDTH_BITS-1];
endmodule
|
module alu (
input wire [15:0] accum,
input wire [15:0] rhs,
output wire [15:0] result,
output wire zero,
output wire neg,
output wire carry,
output wire is_alu_inst,
input wire inst_add,
input wire inst_sub,
input wire inst_test,
input wire inst_and,
input wire inst_or,
input wire inst_xor,
input wire inst_not,
input wire inst_shl,
input wire inst_shr
);
assign is_alu_inst = inst_add | inst_sub | inst_test
| inst_and | inst_or | inst_xor | inst_not | inst_shl | inst_shr;
assign result = inst_add ? (accum + rhs)
: inst_sub ? (accum - rhs)
: inst_test ? accum
: inst_and ? (accum & rhs)
: inst_or ? (accum | rhs)
: inst_xor ? (accum ^ rhs)
: inst_not ? (~accum)
: inst_shl ? (accum << rhs)
: inst_shr ? (accum >> rhs)
: 0;
assign carry = inst_add ? ((accum[15] & rhs[15]) | (rhs[15] & ~result[15]) | (~result[15] & accum[15]))
: inst_sub ? ((~accum[15] & rhs[15]) | (rhs[15] & result[15]) | (result[15] & ~accum[15]))
: inst_not ? 1
: inst_shl ? accum[16 - rhs]
: inst_shr ? accum[rhs - 1]
: 0;
assign zero = is_alu_inst & (result == 0);
assign neg = is_alu_inst & result[15];
endmodule
|
tt06-finale_0057
|
tt06-finale
|
couchand-tt06-cora16
|
task_cpu
|
tt_um_couchand_cora16
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Andrew Dona-Couch
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_couchand_cora16 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// Allow external SPI RAM programming on reset
assign uio_oe = rst_n ? 8'b11100111 : 8'b11100000;
assign uio_out[4:3] = 0;
wire spi_miso, spi_select, spi_clk, spi_mosi;
assign spi_miso = uio_in[3];
assign uio_out[1] = spi_select;
assign uio_out[2] = spi_clk;
assign uio_out[0] = spi_mosi;
wire step, busy, halt, trap;
assign step = uio_in[4];
assign uio_out[5] = busy;
assign uio_out[6] = halt;
assign uio_out[7] = trap;
cpu cpu_instance(
.clk(clk),
.rst_n(rst_n),
.spi_mosi(spi_mosi),
.spi_select(spi_select),
.spi_clk(spi_clk),
.spi_miso(spi_miso),
.step(step),
.busy(busy),
.halt(halt),
.trap(trap),
.data_in(ui_in),
.data_out(uo_out)
);
endmodule
/*
* Copyright (c) 2024 Andrew Dona-Couch
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module cpu (
input wire clk,
input wire rst_n,
output wire spi_mosi,
output wire spi_select,
output wire spi_clk,
input wire spi_miso,
input wire step,
output wire busy,
output wire halt,
output wire trap,
input wire [7:0] data_in,
output reg [7:0] data_out
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
/*
* Copyright (c) 2024 Andrew Dona-Couch
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module decoder (
input wire en,
input wire [15:0] inst,
input wire [15:0] accum,
input wire [7:0] data,
output wire [15:0] rhs,
output wire [1:0] bytes,
output wire inst_nop,
output wire inst_halt,
output wire inst_trap,
output wire inst_load,
output wire inst_store,
output wire inst_add,
output wire inst_sub,
output wire inst_and,
output wire inst_or,
output wire inst_xor,
output wire inst_shl,
output wire inst_shr,
output wire inst_not,
output wire inst_branch,
output wire inst_call,
output wire inst_if,
output wire inst_push,
output wire inst_pop,
output wire inst_drop,
output wire inst_return,
output wire inst_out_lo,
output wire inst_out_hi,
output wire inst_set_dp,
output wire inst_test,
output wire inst_status,
output wire inst_call_word,
output wire inst_load_word,
output wire source_imm,
output wire source_ram,
output wire source_indirect,
output wire relative_data,
output wire relative_stack,
output wire if_zero,
output wire if_not_zero,
output wire if_else,
output wire if_not_else,
output wire if_neg,
output wire if_not_neg,
output wire if_carry,
output wire if_not_carry
);
wire zero_arg = en & ((inst & 16'h8000) == 16'h0000);
assign inst_nop = en & ((inst >> 8) == 16'h0000);
assign inst_halt = en & ((inst >> 8) == 16'h0001);
assign inst_trap = en & ((inst >> 8) == 16'h0002);
assign inst_drop = en & ((inst >> 8) == 16'h0003);
assign inst_push = en & ((inst >> 8) == 16'h0004);
assign inst_pop = en & ((inst >> 8) == 16'h0005);
assign inst_return = en & ((inst >> 8) == 16'h0006);
assign inst_not = en & ((inst >> 8) == 16'h0007);
assign inst_out_lo = en & ((inst >> 8) == 16'h0008);
assign inst_out_hi = en & ((inst >> 8) == 16'h0009);
assign inst_set_dp = en & ((inst >> 8) == 16'h000A);
assign inst_test = en & ((inst >> 8) == 16'h000B);
assign inst_status = en & ((inst >> 8) == 16'h0010);
assign inst_call_word = en & ((inst >> 8) == 16'h003E);
assign inst_load_word = en & ((inst >> 8) == 16'h003F);
wire inst_load_indirect = en & (((inst >> 8) & 16'h00FC) == 16'h0044);
assign bytes = zero_arg ? 1 : 2;
wire one_arg = en & ((inst & 16'hC000) == 16'h8000);
wire inst_load_direct = en & ((inst & 16'hF800) == 16'h8000);
assign inst_load = inst_load_direct | inst_load_indirect;
assign inst_store = en & ((inst & 16'hF800) == 16'h9000);
assign inst_add = en & ((inst & 16'hF800) == 16'h8800);
assign inst_sub = en & ((inst & 16'hF800) == 16'h9800);
assign inst_and = en & ((inst & 16'hF800) == 16'hA000);
assign inst_or = en & ((inst & 16'hF800) == 16'hA800);
assign inst_xor = en & ((inst & 16'hF800) == 16'hB000);
wire inst_sh = en & ((inst & 16'hF800) == 16'hB800);
assign inst_shl = ~inst_sh ? 0
: source_ram ? ((inst & 16'h0001) == 16'h0000)
: ((inst & 16'h0100) == 16'h0000);
assign inst_shr = ~inst_sh ? 0
: source_ram ? ((inst & 16'h0001) == 16'h0001)
: ((inst & 16'h0100) == 16'h0100);
wire inst_branch_direct = en & ((inst & 16'hF800) == 16'hC000);
wire inst_branch_indirect = en & ((inst >> 8) == 16'h000C);
assign inst_branch = inst_branch_direct | inst_branch_indirect;
wire inst_call_direct = en & ((inst & 16'hF800) == 16'hD000);
wire inst_call_indirect = en & ((inst >> 8) == 16'h000D);
assign inst_call = inst_call_direct | inst_call_indirect;
assign inst_if = en & ((inst & 16'hF800) == 16'hF000);
wire source_const = !one_arg ? 0 : (inst & 16'h0600) == 16'h0000;
wire source_data = !one_arg ? 0 : (inst & 16'h0600) == 16'h0200;
wire source_none = inst_not | inst_test;
assign source_imm = source_const | source_data | source_none;
assign source_ram = (one_arg | inst_load_indirect) & ((inst & 16'h0500) == 16'h0400);
assign source_indirect = (one_arg | inst_load_indirect) & ((inst & 16'h0500) == 16'h0500);
assign relative_data = (source_ram | source_indirect)
? (inst & 16'h0200) == 16'h0000
: 0;
assign relative_stack = (source_ram | source_indirect)
? (inst & 16'h0200) == 16'h0200
: 0;
assign rhs = !en ? 0
: (inst_branch_direct | inst_call_direct) ? {{5{inst[10]}}, inst[10:0]}
: (inst_load_indirect | inst_branch_indirect | inst_call_indirect) ? accum
: (((inst & 16'h0600) == 16'h0000) & inst_sh) ? {8'h00, inst[7:0]}
: (((inst & 16'h0600) == 16'h0200) & inst_sh) ? {8'h00, data}
: (inst & 16'h0700) == 16'h0000 ? {8'h00, inst[7:0]}
: (inst & 16'h0700) == 16'h0100 ? {inst[7:0], 8'h00}
: (inst & 16'h0700) == 16'h0200 ? {8'h00, data}
: (inst & 16'h0700) == 16'h0300 ? {data, 8'h00}
: (((inst & 16'h0400) == 16'h0400) & inst_sh) ? {8'h00, inst[7:1], 1'b0}
: (inst & 16'h0400) == 16'h0400 ? {8'h00, inst[7:0]}
: 0;
assign if_zero = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0000;
assign if_not_zero = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0001;
assign if_else = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0002;
assign if_not_else = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0003;
assign if_neg = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0004;
assign if_not_neg = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0005;
assign if_carry = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0006;
assign if_not_carry = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0007;
endmodule
/*
* Copyright (c) 2024 Andrew Dona-Couch
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module alu (
input wire [15:0] accum,
input wire [15:0] rhs,
output wire [15:0] result,
output wire zero,
output wire neg,
output wire carry,
output wire is_alu_inst,
input wire inst_add,
input wire inst_sub,
input wire inst_test,
input wire inst_and,
input wire inst_or,
input wire inst_xor,
input wire inst_not,
input wire inst_shl,
input wire inst_shr
);
assign is_alu_inst = inst_add | inst_sub | inst_test
| inst_and | inst_or | inst_xor | inst_not | inst_shl | inst_shr;
assign result = inst_add ? (accum + rhs)
: inst_sub ? (accum - rhs)
: inst_test ? accum
: inst_and ? (accum & rhs)
: inst_or ? (accum | rhs)
: inst_xor ? (accum ^ rhs)
: inst_not ? (~accum)
: inst_shl ? (accum << rhs)
: inst_shr ? (accum >> rhs)
: 0;
assign carry = inst_add ? ((accum[15] & rhs[15]) | (rhs[15] & ~result[15]) | (~result[15] & accum[15]))
: inst_sub ? ((~accum[15] & rhs[15]) | (rhs[15] & result[15]) | (result[15] & ~accum[15]))
: inst_not ? 1
: inst_shl ? accum[16 - rhs]
: inst_shr ? accum[rhs - 1]
: 0;
assign zero = is_alu_inst & (result == 0);
assign neg = is_alu_inst & result[15];
endmodule
/* Copyright 2023 (c) Michael Bell
A simple SPI RAM controller
To perform a read:
- Set addr_in and set start_read high for 1 cycle
- Wait for busy to go low
- The read data is now available on data_out
To perform a write:
- Set addr_in, data_in and set start_write high for 1 cycle
- Wait for busy to go low before starting another operation
If the controller is configured to transfer multiple bytes, then
note that the word transferred in data_in/data_out is in big
endian order, i.e. the byte with the lowest address is aligned to
the MSB of the word.
*/
module spi_ram_controller #(parameter DATA_WIDTH_BYTES=4, parameter ADDR_BITS=16) (
input clk,
input rstn,
// External SPI interface
input spi_miso,
output spi_select,
output spi_clk_out,
output spi_mosi,
// Internal interface for reading/writing data
input [ADDR_BITS-1:0] addr_in,
input [DATA_WIDTH_BYTES*8-1:0] data_in,
input start_read,
input start_write,
output [DATA_WIDTH_BYTES*8-1:0] data_out,
output busy
);
//`ifdef COCOTB_SIM
//initial begin
// $dumpfile ("spi.vcd");
// $dumpvars (0, spi_ram_controller);
// #1;
//end
//`endif
`define max(a, b) (a > b) ? a : b
localparam DATA_WIDTH_BITS = DATA_WIDTH_BYTES * 8;
localparam FSM_IDLE = 0;
localparam FSM_CMD = 1;
localparam FSM_ADDR = 2;
localparam FSM_DATA = 3;
reg [1:0] fsm_state;
reg writing;
reg spi_miso_buf;
reg [ADDR_BITS-1:0] addr;
reg [DATA_WIDTH_BITS-1:0] data;
reg [$clog2(`max(DATA_WIDTH_BITS,ADDR_BITS))-1:0] bits_remaining;
assign data_out = data;
assign busy = fsm_state != FSM_IDLE;
always @(posedge clk) begin
if (!rstn) begin
fsm_state <= FSM_IDLE;
bits_remaining <= 0;
end else begin
if (fsm_state == FSM_IDLE) begin
if (start_read || start_write) begin
fsm_state <= FSM_CMD;
bits_remaining <= 8-1;
end
end else begin
if (bits_remaining == 0) begin
fsm_state <= fsm_state + 1;
if (fsm_state == FSM_CMD) bits_remaining <= ADDR_BITS-1;
else if (fsm_state == FSM_ADDR) bits_remaining <= DATA_WIDTH_BITS-1;
end else begin
bits_remaining <= bits_remaining - 1;
end
end
end
end
always @(posedge clk) begin
if (fsm_state == FSM_IDLE && (start_read || start_write)) begin
addr <= addr_in;
writing <= start_write;
end else if (fsm_state == FSM_ADDR) begin
addr <= {addr[ADDR_BITS-2:0], 1'b0};
end
end
always @(negedge clk) begin
spi_miso_buf <= spi_miso;
end
always @(posedge clk) begin
if (fsm_state == FSM_IDLE && start_write) begin
data <= data_in;
end else if (fsm_state == FSM_DATA) begin
data <= {data[DATA_WIDTH_BITS-2:0], spi_miso_buf};
end
end
assign spi_select = fsm_state == FSM_IDLE;
assign spi_clk_out = !clk;
assign spi_mosi = fsm_state == FSM_IDLE ? 1'b0 :
fsm_state == FSM_CMD ? (bits_remaining == 1 || (bits_remaining == 0 && !writing)) :
fsm_state == FSM_ADDR ? addr[ADDR_BITS-1] :
data[DATA_WIDTH_BITS-1];
endmodule
|
module cpu (
input wire clk,
input wire rst_n,
output wire spi_mosi,
output wire spi_select,
output wire spi_clk,
input wire spi_miso,
input wire step,
output wire busy,
output wire halt,
output wire trap,
input wire [7:0] data_in,
output reg [7:0] data_out
);
reg [15:0] pc;
reg [15:0] inst;
reg [15:0] accum;
reg [15:0] dp;
reg [15:0] sp;
reg zero;
reg neg;
reg carry;
reg skip;
reg skipped;
wire [15:0] alu_rhs = (state == ST_INST_EXEC0) ? rhs : ram_data_out;
wire [15:0] alu_result;
wire alu_zero, alu_neg, alu_carry, is_alu_inst;
alu alu_instance(
.accum(accum),
.rhs(alu_rhs),
.result(alu_result),
.zero(alu_zero),
.neg(alu_neg),
.carry(alu_carry),
.is_alu_inst(is_alu_inst),
.inst_add(inst_add),
.inst_sub(inst_sub),
.inst_test(inst_test),
.inst_and(inst_and),
.inst_or(inst_or),
.inst_xor(inst_xor),
.inst_not(inst_not),
.inst_shl(inst_shl),
.inst_shr(inst_shr)
);
wire [15:0] rhs;
wire [1:0] inst_bytes_raw;
wire [15:0] inst_bytes = {14'b0, inst_bytes_raw};
wire inst_load, inst_store, inst_add, inst_sub, inst_test, inst_status;
wire inst_and, inst_or, inst_xor, inst_not, inst_shl, inst_shr;
wire inst_branch, inst_call, inst_if, inst_push, inst_pop, inst_drop, inst_return;
wire inst_nop, inst_out_lo, inst_out_hi, inst_halt, inst_trap, inst_set_dp;
wire inst_call_word, inst_load_word;
wire source_imm, source_ram, source_indirect;
wire relative_stack, relative_data;
wire if_zero, if_not_zero, if_else, if_not_else, if_neg, if_not_neg, if_carry, if_not_carry;
wire decoding = (state == ST_INST_EXEC0) | (state == ST_INST_EXEC1)
| (state == ST_INST_EXEC2) | (state == ST_INST_EXEC3);
decoder inst_decoder(
.en(decoding),
.inst(inst),
.accum(accum),
.data(data_in),
.rhs(rhs),
.bytes(inst_bytes_raw),
.inst_nop(inst_nop),
.inst_halt(inst_halt),
.inst_trap(inst_trap),
.inst_load(inst_load),
.inst_store(inst_store),
.inst_add(inst_add),
.inst_sub(inst_sub),
.inst_and(inst_and),
.inst_or(inst_or),
.inst_xor(inst_xor),
.inst_shl(inst_shl),
.inst_shr(inst_shr),
.inst_not(inst_not),
.inst_branch(inst_branch),
.inst_call(inst_call),
.inst_if(inst_if),
.inst_push(inst_push),
.inst_pop(inst_pop),
.inst_drop(inst_drop),
.inst_return(inst_return),
.inst_out_lo(inst_out_lo),
.inst_out_hi(inst_out_hi),
.inst_set_dp(inst_set_dp),
.inst_test(inst_test),
.inst_status(inst_status),
.inst_call_word(inst_call_word),
.inst_load_word(inst_load_word),
.source_imm(source_imm),
.source_ram(source_ram),
.source_indirect(source_indirect),
.relative_stack(relative_stack),
.relative_data(relative_data),
.if_zero(if_zero),
.if_not_zero(if_not_zero),
.if_else(if_else),
.if_not_else(if_not_else),
.if_neg(if_neg),
.if_not_neg(if_not_neg),
.if_carry(if_carry),
.if_not_carry(if_not_carry)
);
reg [8:0] state;
localparam ST_INIT = 0;
localparam ST_HALT = 1;
localparam ST_TRAP = 2;
localparam ST_LOAD_INST0 = 3;
localparam ST_LOAD_INST1 = 4;
localparam ST_INST_EXEC0 = 5;
localparam ST_INST_EXEC1 = 6;
localparam ST_INST_EXEC2 = 7;
localparam ST_INST_EXEC3 = 8;
localparam ST_UNTRAP = 9;
localparam ST_FAULT = 10;
assign busy = state != ST_INIT & state != ST_HALT & state != ST_TRAP & state != ST_FAULT;
assign halt = (state == ST_HALT) | (state == ST_FAULT);
assign trap = (state == ST_TRAP) | (state == ST_FAULT);
wire [15:0] sp_minus_two = sp - 2;
wire [15:0] ram_addr = (state == ST_LOAD_INST0) ? pc
: ((state == ST_INST_EXEC0) & (inst_push | inst_call | inst_call_word)) ? sp_minus_two
: ((state == ST_INST_EXEC0) & (inst_pop | inst_return)) ? sp
: ((state == ST_INST_EXEC0) & inst_load_word) ? (pc + inst_bytes)
: ((state == ST_INST_EXEC0) & (source_ram | source_indirect))
? ((relative_stack ? sp : relative_data ? dp : 0) + rhs)
: ((state == ST_INST_EXEC2) & inst_call_word) ? (pc + inst_bytes)
: ((state == ST_INST_EXEC2) & source_indirect) ? ram_data_out
: 0;
wire ram_start_read = (state == ST_LOAD_INST0) ? 1
: ((state == ST_INST_EXEC0) & ((source_ram & ~inst_store) | source_indirect)) ? ~skip
: ((state == ST_INST_EXEC0) & (inst_pop | inst_return)) ? ~skip
: ((state == ST_INST_EXEC0) & inst_load_word) ? ~skip
: ((state == ST_INST_EXEC2) & inst_call_word) ? ~skip
: ((state == ST_INST_EXEC2) & source_indirect) ? ~skip
: 0;
wire [15:0] ram_data_in = ((state == ST_INST_EXEC0) & source_ram & inst_store) ? accum
: ((state == ST_INST_EXEC0) & inst_push) ? accum
: ((state == ST_INST_EXEC0) & inst_call) ? (pc + inst_bytes)
: ((state == ST_INST_EXEC0) & inst_call_word) ? (pc + inst_bytes + 2)
: ((state == ST_INST_EXEC2) & source_indirect & inst_store) ? accum
: 0;
wire ram_start_write = ((state == ST_INST_EXEC0) & source_ram & inst_store) ? ~skip
: ((state == ST_INST_EXEC0) & (inst_push | inst_call | inst_call_word)) ? ~skip
: ((state == ST_INST_EXEC2) & source_indirect & inst_store) ? ~skip
: 0;
wire [15:0] ram_data_out;
wire ram_busy;
spi_ram_controller #(
.DATA_WIDTH_BYTES(2),
.ADDR_BITS(16)
) spi_ram (
.clk(clk),
.rstn(rst_n),
.spi_miso(spi_miso),
.spi_select(spi_select),
.spi_clk_out(spi_clk),
.spi_mosi(spi_mosi),
.addr_in(ram_addr),
.data_in(ram_data_in),
.start_read(ram_start_read),
.start_write(ram_start_write),
.data_out(ram_data_out),
.busy(ram_busy)
);
always @(posedge clk) begin
if (!rst_n) begin
state <= ST_INIT;
pc <= 0;
inst <= 0;
accum <= 0;
dp <= 0;
sp <= 0;
zero <= 0;
neg <= 0;
carry <= 0;
skip <= 0;
skipped <= 0;
data_out <= 0;
end else if (~halt) begin
if (state == ST_INIT) begin
if (step) begin
state <= ST_LOAD_INST0;
end
end else if (state == ST_TRAP) begin
if (step) begin
state <= ST_UNTRAP;
end
end else if (state == ST_UNTRAP) begin
if (~step) begin
state <= ST_INIT;
end
end else if (state == ST_LOAD_INST0) begin
state <= ST_LOAD_INST1;
end else if (state == ST_LOAD_INST1) begin
if (!ram_busy) begin
inst <= ram_data_out;
state <= ST_INST_EXEC0;
end
end else if (state == ST_INST_EXEC0) begin
if (inst_nop) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (inst_halt) begin
pc <= pc + inst_bytes;
if (skip) begin
state <= ST_INIT;
end else begin
state <= ST_HALT;
end
end else if (inst_trap) begin
pc <= pc + inst_bytes;
if (skip) begin
state <= ST_INIT;
end else begin
state <= ST_TRAP;
end
end else if (inst_set_dp) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
if (~skip) begin
dp <= accum;
end
end else if (inst_status) begin
accum <= {8'b0, 2'b0, skipped, 2'b0, carry, neg, zero};
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (inst_drop) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
if (~skip) begin
sp <= sp + 2;
end
end else if (inst_push | inst_pop) begin
if (skip) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else begin
state <= ST_INST_EXEC1;
end
end else if (inst_call_word | inst_load_word) begin
if (skip) begin
pc <= pc + inst_bytes + 2;
state <= ST_INIT;
end else begin
state <= ST_INST_EXEC1;
end
end else if (inst_load) begin
if (skip) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (source_imm) begin
accum <= rhs;
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (source_ram | source_indirect) begin
state <= ST_INST_EXEC1;
end else begin
state <= ST_FAULT;
end
end else if (inst_store) begin
if (skip) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (source_imm) begin
state <= ST_FAULT;
end else if (source_ram | source_indirect) begin
state <= ST_INST_EXEC1;
end else begin
state <= ST_FAULT;
end
end else if (is_alu_inst) begin
if (skip) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (source_imm) begin
accum <= alu_result;
zero <= alu_zero;
neg <= alu_neg;
carry <= alu_carry;
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (source_ram | source_indirect) begin
state <= ST_INST_EXEC1;
end else begin
state <= ST_FAULT;
end
end else if (inst_branch) begin
state <= ST_INIT;
if (skip) begin
pc <= pc + inst_bytes;
end else begin
pc <= pc + inst_bytes + rhs;
end
end else if (inst_call) begin
if (skip) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else begin
state <= ST_INST_EXEC1;
end
end else if (inst_return) begin
if (skip) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else begin
state <= ST_INST_EXEC1;
end
end else if (inst_if) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (inst_out_lo) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
if (~skip) begin
data_out <= accum[7:0];
end
end else if (inst_out_hi) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
if (~skip) begin
data_out <= accum[15:8];
end
end else begin
state <= ST_FAULT;
end
if (inst_if) begin
if (if_zero) begin
skip <= ~zero;
end else if (if_not_zero) begin
skip <= zero;
end else if (if_else) begin
skip <= ~skipped;
end else if (if_not_else) begin
skip <= skipped;
end else if (if_neg) begin
skip <= ~neg;
end else if (if_not_neg) begin
skip <= neg;
end else if (if_carry) begin
skip <= ~carry;
end else if (if_not_carry) begin
skip <= carry;
end else begin
state <= ST_FAULT;
end
end else begin
skip <= 0;
end
skipped <= skip;
end else if (state == ST_INST_EXEC1) begin
if (!ram_busy) begin
if (inst_push) begin
sp <= sp_minus_two;
state <= ST_INIT;
pc <= pc + inst_bytes;
end else if (inst_pop) begin
sp <= sp + 2;
accum <= ram_data_out;
state <= ST_INIT;
pc <= pc + inst_bytes;
end else if (inst_call) begin
sp <= sp_minus_two;
state <= ST_INIT;
pc <= rhs;
end else if (inst_return) begin
sp <= sp + 2;
state <= ST_INIT;
pc <= ram_data_out;
end else if (inst_call_word) begin
sp <= sp_minus_two;
state <= ST_INST_EXEC2;
end else if (inst_load_word) begin
accum <= ram_data_out;
pc <= pc + inst_bytes + 2;
state <= ST_INIT;
end else if (source_ram) begin
if (inst_load) begin
accum <= ram_data_out;
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (is_alu_inst) begin
accum <= alu_result;
zero <= alu_zero;
neg <= alu_neg;
carry <= alu_carry;
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (inst_store) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else begin
state <= ST_FAULT;
end
end else if (source_indirect) begin
if (!ram_busy) begin
state <= ST_INST_EXEC2;
end
end else begin
state <= ST_FAULT;
end
end
end else if (state == ST_INST_EXEC2) begin
state <= ST_INST_EXEC3;
end else if (state == ST_INST_EXEC3) begin
if (!ram_busy) begin
if (inst_load) begin
accum <= ram_data_out;
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (is_alu_inst) begin
accum <= alu_result;
zero <= alu_zero;
neg <= alu_neg;
carry <= alu_carry;
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (inst_store) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (inst_call_word) begin
pc <= ram_data_out;
state <= ST_INIT;
end else begin
state <= ST_FAULT;
end
end
end else begin
state <= ST_FAULT;
end
end
end
endmodule
|
tt06-finale_0058
|
tt06-finale
|
couchand-tt06-cora16
|
task_decoder
|
tt_um_couchand_cora16
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Andrew Dona-Couch
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_couchand_cora16 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// Allow external SPI RAM programming on reset
assign uio_oe = rst_n ? 8'b11100111 : 8'b11100000;
assign uio_out[4:3] = 0;
wire spi_miso, spi_select, spi_clk, spi_mosi;
assign spi_miso = uio_in[3];
assign uio_out[1] = spi_select;
assign uio_out[2] = spi_clk;
assign uio_out[0] = spi_mosi;
wire step, busy, halt, trap;
assign step = uio_in[4];
assign uio_out[5] = busy;
assign uio_out[6] = halt;
assign uio_out[7] = trap;
cpu cpu_instance(
.clk(clk),
.rst_n(rst_n),
.spi_mosi(spi_mosi),
.spi_select(spi_select),
.spi_clk(spi_clk),
.spi_miso(spi_miso),
.step(step),
.busy(busy),
.halt(halt),
.trap(trap),
.data_in(ui_in),
.data_out(uo_out)
);
endmodule
/*
* Copyright (c) 2024 Andrew Dona-Couch
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module cpu (
input wire clk,
input wire rst_n,
output wire spi_mosi,
output wire spi_select,
output wire spi_clk,
input wire spi_miso,
input wire step,
output wire busy,
output wire halt,
output wire trap,
input wire [7:0] data_in,
output reg [7:0] data_out
);
reg [15:0] pc;
reg [15:0] inst;
reg [15:0] accum;
reg [15:0] dp;
reg [15:0] sp;
reg zero;
reg neg;
reg carry;
reg skip;
reg skipped;
wire [15:0] alu_rhs = (state == ST_INST_EXEC0) ? rhs : ram_data_out;
wire [15:0] alu_result;
wire alu_zero, alu_neg, alu_carry, is_alu_inst;
alu alu_instance(
.accum(accum),
.rhs(alu_rhs),
.result(alu_result),
.zero(alu_zero),
.neg(alu_neg),
.carry(alu_carry),
.is_alu_inst(is_alu_inst),
.inst_add(inst_add),
.inst_sub(inst_sub),
.inst_test(inst_test),
.inst_and(inst_and),
.inst_or(inst_or),
.inst_xor(inst_xor),
.inst_not(inst_not),
.inst_shl(inst_shl),
.inst_shr(inst_shr)
);
wire [15:0] rhs;
wire [1:0] inst_bytes_raw;
wire [15:0] inst_bytes = {14'b0, inst_bytes_raw};
wire inst_load, inst_store, inst_add, inst_sub, inst_test, inst_status;
wire inst_and, inst_or, inst_xor, inst_not, inst_shl, inst_shr;
wire inst_branch, inst_call, inst_if, inst_push, inst_pop, inst_drop, inst_return;
wire inst_nop, inst_out_lo, inst_out_hi, inst_halt, inst_trap, inst_set_dp;
wire inst_call_word, inst_load_word;
wire source_imm, source_ram, source_indirect;
wire relative_stack, relative_data;
wire if_zero, if_not_zero, if_else, if_not_else, if_neg, if_not_neg, if_carry, if_not_carry;
wire decoding = (state == ST_INST_EXEC0) | (state == ST_INST_EXEC1)
| (state == ST_INST_EXEC2) | (state == ST_INST_EXEC3);
decoder inst_decoder(
.en(decoding),
.inst(inst),
.accum(accum),
.data(data_in),
.rhs(rhs),
.bytes(inst_bytes_raw),
.inst_nop(inst_nop),
.inst_halt(inst_halt),
.inst_trap(inst_trap),
.inst_load(inst_load),
.inst_store(inst_store),
.inst_add(inst_add),
.inst_sub(inst_sub),
.inst_and(inst_and),
.inst_or(inst_or),
.inst_xor(inst_xor),
.inst_shl(inst_shl),
.inst_shr(inst_shr),
.inst_not(inst_not),
.inst_branch(inst_branch),
.inst_call(inst_call),
.inst_if(inst_if),
.inst_push(inst_push),
.inst_pop(inst_pop),
.inst_drop(inst_drop),
.inst_return(inst_return),
.inst_out_lo(inst_out_lo),
.inst_out_hi(inst_out_hi),
.inst_set_dp(inst_set_dp),
.inst_test(inst_test),
.inst_status(inst_status),
.inst_call_word(inst_call_word),
.inst_load_word(inst_load_word),
.source_imm(source_imm),
.source_ram(source_ram),
.source_indirect(source_indirect),
.relative_stack(relative_stack),
.relative_data(relative_data),
.if_zero(if_zero),
.if_not_zero(if_not_zero),
.if_else(if_else),
.if_not_else(if_not_else),
.if_neg(if_neg),
.if_not_neg(if_not_neg),
.if_carry(if_carry),
.if_not_carry(if_not_carry)
);
reg [8:0] state;
localparam ST_INIT = 0;
localparam ST_HALT = 1;
localparam ST_TRAP = 2;
localparam ST_LOAD_INST0 = 3;
localparam ST_LOAD_INST1 = 4;
localparam ST_INST_EXEC0 = 5;
localparam ST_INST_EXEC1 = 6;
localparam ST_INST_EXEC2 = 7;
localparam ST_INST_EXEC3 = 8;
localparam ST_UNTRAP = 9;
localparam ST_FAULT = 10;
assign busy = state != ST_INIT & state != ST_HALT & state != ST_TRAP & state != ST_FAULT;
assign halt = (state == ST_HALT) | (state == ST_FAULT);
assign trap = (state == ST_TRAP) | (state == ST_FAULT);
wire [15:0] sp_minus_two = sp - 2;
wire [15:0] ram_addr = (state == ST_LOAD_INST0) ? pc
: ((state == ST_INST_EXEC0) & (inst_push | inst_call | inst_call_word)) ? sp_minus_two
: ((state == ST_INST_EXEC0) & (inst_pop | inst_return)) ? sp
: ((state == ST_INST_EXEC0) & inst_load_word) ? (pc + inst_bytes)
: ((state == ST_INST_EXEC0) & (source_ram | source_indirect))
? ((relative_stack ? sp : relative_data ? dp : 0) + rhs)
: ((state == ST_INST_EXEC2) & inst_call_word) ? (pc + inst_bytes)
: ((state == ST_INST_EXEC2) & source_indirect) ? ram_data_out
: 0;
wire ram_start_read = (state == ST_LOAD_INST0) ? 1
: ((state == ST_INST_EXEC0) & ((source_ram & ~inst_store) | source_indirect)) ? ~skip
: ((state == ST_INST_EXEC0) & (inst_pop | inst_return)) ? ~skip
: ((state == ST_INST_EXEC0) & inst_load_word) ? ~skip
: ((state == ST_INST_EXEC2) & inst_call_word) ? ~skip
: ((state == ST_INST_EXEC2) & source_indirect) ? ~skip
: 0;
wire [15:0] ram_data_in = ((state == ST_INST_EXEC0) & source_ram & inst_store) ? accum
: ((state == ST_INST_EXEC0) & inst_push) ? accum
: ((state == ST_INST_EXEC0) & inst_call) ? (pc + inst_bytes)
: ((state == ST_INST_EXEC0) & inst_call_word) ? (pc + inst_bytes + 2)
: ((state == ST_INST_EXEC2) & source_indirect & inst_store) ? accum
: 0;
wire ram_start_write = ((state == ST_INST_EXEC0) & source_ram & inst_store) ? ~skip
: ((state == ST_INST_EXEC0) & (inst_push | inst_call | inst_call_word)) ? ~skip
: ((state == ST_INST_EXEC2) & source_indirect & inst_store) ? ~skip
: 0;
wire [15:0] ram_data_out;
wire ram_busy;
spi_ram_controller #(
.DATA_WIDTH_BYTES(2),
.ADDR_BITS(16)
) spi_ram (
.clk(clk),
.rstn(rst_n),
.spi_miso(spi_miso),
.spi_select(spi_select),
.spi_clk_out(spi_clk),
.spi_mosi(spi_mosi),
.addr_in(ram_addr),
.data_in(ram_data_in),
.start_read(ram_start_read),
.start_write(ram_start_write),
.data_out(ram_data_out),
.busy(ram_busy)
);
always @(posedge clk) begin
if (!rst_n) begin
state <= ST_INIT;
pc <= 0;
inst <= 0;
accum <= 0;
dp <= 0;
sp <= 0;
zero <= 0;
neg <= 0;
carry <= 0;
skip <= 0;
skipped <= 0;
data_out <= 0;
end else if (~halt) begin
if (state == ST_INIT) begin
if (step) begin
state <= ST_LOAD_INST0;
end
end else if (state == ST_TRAP) begin
if (step) begin
state <= ST_UNTRAP;
end
end else if (state == ST_UNTRAP) begin
if (~step) begin
state <= ST_INIT;
end
end else if (state == ST_LOAD_INST0) begin
state <= ST_LOAD_INST1;
end else if (state == ST_LOAD_INST1) begin
if (!ram_busy) begin
inst <= ram_data_out;
state <= ST_INST_EXEC0;
end
end else if (state == ST_INST_EXEC0) begin
if (inst_nop) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (inst_halt) begin
pc <= pc + inst_bytes;
if (skip) begin
state <= ST_INIT;
end else begin
state <= ST_HALT;
end
end else if (inst_trap) begin
pc <= pc + inst_bytes;
if (skip) begin
state <= ST_INIT;
end else begin
state <= ST_TRAP;
end
end else if (inst_set_dp) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
if (~skip) begin
dp <= accum;
end
end else if (inst_status) begin
accum <= {8'b0, 2'b0, skipped, 2'b0, carry, neg, zero};
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (inst_drop) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
if (~skip) begin
sp <= sp + 2;
end
end else if (inst_push | inst_pop) begin
if (skip) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else begin
state <= ST_INST_EXEC1;
end
end else if (inst_call_word | inst_load_word) begin
if (skip) begin
pc <= pc + inst_bytes + 2;
state <= ST_INIT;
end else begin
state <= ST_INST_EXEC1;
end
end else if (inst_load) begin
if (skip) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (source_imm) begin
accum <= rhs;
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (source_ram | source_indirect) begin
state <= ST_INST_EXEC1;
end else begin
state <= ST_FAULT;
end
end else if (inst_store) begin
if (skip) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (source_imm) begin
state <= ST_FAULT;
end else if (source_ram | source_indirect) begin
state <= ST_INST_EXEC1;
end else begin
state <= ST_FAULT;
end
end else if (is_alu_inst) begin
if (skip) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (source_imm) begin
accum <= alu_result;
zero <= alu_zero;
neg <= alu_neg;
carry <= alu_carry;
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (source_ram | source_indirect) begin
state <= ST_INST_EXEC1;
end else begin
state <= ST_FAULT;
end
end else if (inst_branch) begin
state <= ST_INIT;
if (skip) begin
pc <= pc + inst_bytes;
end else begin
pc <= pc + inst_bytes + rhs;
end
end else if (inst_call) begin
if (skip) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else begin
state <= ST_INST_EXEC1;
end
end else if (inst_return) begin
if (skip) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else begin
state <= ST_INST_EXEC1;
end
end else if (inst_if) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (inst_out_lo) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
if (~skip) begin
data_out <= accum[7:0];
end
end else if (inst_out_hi) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
if (~skip) begin
data_out <= accum[15:8];
end
end else begin
state <= ST_FAULT;
end
if (inst_if) begin
if (if_zero) begin
skip <= ~zero;
end else if (if_not_zero) begin
skip <= zero;
end else if (if_else) begin
skip <= ~skipped;
end else if (if_not_else) begin
skip <= skipped;
end else if (if_neg) begin
skip <= ~neg;
end else if (if_not_neg) begin
skip <= neg;
end else if (if_carry) begin
skip <= ~carry;
end else if (if_not_carry) begin
skip <= carry;
end else begin
state <= ST_FAULT;
end
end else begin
skip <= 0;
end
skipped <= skip;
end else if (state == ST_INST_EXEC1) begin
if (!ram_busy) begin
if (inst_push) begin
sp <= sp_minus_two;
state <= ST_INIT;
pc <= pc + inst_bytes;
end else if (inst_pop) begin
sp <= sp + 2;
accum <= ram_data_out;
state <= ST_INIT;
pc <= pc + inst_bytes;
end else if (inst_call) begin
sp <= sp_minus_two;
state <= ST_INIT;
pc <= rhs;
end else if (inst_return) begin
sp <= sp + 2;
state <= ST_INIT;
pc <= ram_data_out;
end else if (inst_call_word) begin
sp <= sp_minus_two;
state <= ST_INST_EXEC2;
end else if (inst_load_word) begin
accum <= ram_data_out;
pc <= pc + inst_bytes + 2;
state <= ST_INIT;
end else if (source_ram) begin
if (inst_load) begin
accum <= ram_data_out;
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (is_alu_inst) begin
accum <= alu_result;
zero <= alu_zero;
neg <= alu_neg;
carry <= alu_carry;
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (inst_store) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else begin
state <= ST_FAULT;
end
end else if (source_indirect) begin
if (!ram_busy) begin
state <= ST_INST_EXEC2;
end
end else begin
state <= ST_FAULT;
end
end
end else if (state == ST_INST_EXEC2) begin
state <= ST_INST_EXEC3;
end else if (state == ST_INST_EXEC3) begin
if (!ram_busy) begin
if (inst_load) begin
accum <= ram_data_out;
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (is_alu_inst) begin
accum <= alu_result;
zero <= alu_zero;
neg <= alu_neg;
carry <= alu_carry;
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (inst_store) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (inst_call_word) begin
pc <= ram_data_out;
state <= ST_INIT;
end else begin
state <= ST_FAULT;
end
end
end else begin
state <= ST_FAULT;
end
end
end
endmodule
/*
* Copyright (c) 2024 Andrew Dona-Couch
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module decoder (
input wire en,
input wire [15:0] inst,
input wire [15:0] accum,
input wire [7:0] data,
output wire [15:0] rhs,
output wire [1:0] bytes,
output wire inst_nop,
output wire inst_halt,
output wire inst_trap,
output wire inst_load,
output wire inst_store,
output wire inst_add,
output wire inst_sub,
output wire inst_and,
output wire inst_or,
output wire inst_xor,
output wire inst_shl,
output wire inst_shr,
output wire inst_not,
output wire inst_branch,
output wire inst_call,
output wire inst_if,
output wire inst_push,
output wire inst_pop,
output wire inst_drop,
output wire inst_return,
output wire inst_out_lo,
output wire inst_out_hi,
output wire inst_set_dp,
output wire inst_test,
output wire inst_status,
output wire inst_call_word,
output wire inst_load_word,
output wire source_imm,
output wire source_ram,
output wire source_indirect,
output wire relative_data,
output wire relative_stack,
output wire if_zero,
output wire if_not_zero,
output wire if_else,
output wire if_not_else,
output wire if_neg,
output wire if_not_neg,
output wire if_carry,
output wire if_not_carry
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
/*
* Copyright (c) 2024 Andrew Dona-Couch
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module alu (
input wire [15:0] accum,
input wire [15:0] rhs,
output wire [15:0] result,
output wire zero,
output wire neg,
output wire carry,
output wire is_alu_inst,
input wire inst_add,
input wire inst_sub,
input wire inst_test,
input wire inst_and,
input wire inst_or,
input wire inst_xor,
input wire inst_not,
input wire inst_shl,
input wire inst_shr
);
assign is_alu_inst = inst_add | inst_sub | inst_test
| inst_and | inst_or | inst_xor | inst_not | inst_shl | inst_shr;
assign result = inst_add ? (accum + rhs)
: inst_sub ? (accum - rhs)
: inst_test ? accum
: inst_and ? (accum & rhs)
: inst_or ? (accum | rhs)
: inst_xor ? (accum ^ rhs)
: inst_not ? (~accum)
: inst_shl ? (accum << rhs)
: inst_shr ? (accum >> rhs)
: 0;
assign carry = inst_add ? ((accum[15] & rhs[15]) | (rhs[15] & ~result[15]) | (~result[15] & accum[15]))
: inst_sub ? ((~accum[15] & rhs[15]) | (rhs[15] & result[15]) | (result[15] & ~accum[15]))
: inst_not ? 1
: inst_shl ? accum[16 - rhs]
: inst_shr ? accum[rhs - 1]
: 0;
assign zero = is_alu_inst & (result == 0);
assign neg = is_alu_inst & result[15];
endmodule
/* Copyright 2023 (c) Michael Bell
A simple SPI RAM controller
To perform a read:
- Set addr_in and set start_read high for 1 cycle
- Wait for busy to go low
- The read data is now available on data_out
To perform a write:
- Set addr_in, data_in and set start_write high for 1 cycle
- Wait for busy to go low before starting another operation
If the controller is configured to transfer multiple bytes, then
note that the word transferred in data_in/data_out is in big
endian order, i.e. the byte with the lowest address is aligned to
the MSB of the word.
*/
module spi_ram_controller #(parameter DATA_WIDTH_BYTES=4, parameter ADDR_BITS=16) (
input clk,
input rstn,
// External SPI interface
input spi_miso,
output spi_select,
output spi_clk_out,
output spi_mosi,
// Internal interface for reading/writing data
input [ADDR_BITS-1:0] addr_in,
input [DATA_WIDTH_BYTES*8-1:0] data_in,
input start_read,
input start_write,
output [DATA_WIDTH_BYTES*8-1:0] data_out,
output busy
);
//`ifdef COCOTB_SIM
//initial begin
// $dumpfile ("spi.vcd");
// $dumpvars (0, spi_ram_controller);
// #1;
//end
//`endif
`define max(a, b) (a > b) ? a : b
localparam DATA_WIDTH_BITS = DATA_WIDTH_BYTES * 8;
localparam FSM_IDLE = 0;
localparam FSM_CMD = 1;
localparam FSM_ADDR = 2;
localparam FSM_DATA = 3;
reg [1:0] fsm_state;
reg writing;
reg spi_miso_buf;
reg [ADDR_BITS-1:0] addr;
reg [DATA_WIDTH_BITS-1:0] data;
reg [$clog2(`max(DATA_WIDTH_BITS,ADDR_BITS))-1:0] bits_remaining;
assign data_out = data;
assign busy = fsm_state != FSM_IDLE;
always @(posedge clk) begin
if (!rstn) begin
fsm_state <= FSM_IDLE;
bits_remaining <= 0;
end else begin
if (fsm_state == FSM_IDLE) begin
if (start_read || start_write) begin
fsm_state <= FSM_CMD;
bits_remaining <= 8-1;
end
end else begin
if (bits_remaining == 0) begin
fsm_state <= fsm_state + 1;
if (fsm_state == FSM_CMD) bits_remaining <= ADDR_BITS-1;
else if (fsm_state == FSM_ADDR) bits_remaining <= DATA_WIDTH_BITS-1;
end else begin
bits_remaining <= bits_remaining - 1;
end
end
end
end
always @(posedge clk) begin
if (fsm_state == FSM_IDLE && (start_read || start_write)) begin
addr <= addr_in;
writing <= start_write;
end else if (fsm_state == FSM_ADDR) begin
addr <= {addr[ADDR_BITS-2:0], 1'b0};
end
end
always @(negedge clk) begin
spi_miso_buf <= spi_miso;
end
always @(posedge clk) begin
if (fsm_state == FSM_IDLE && start_write) begin
data <= data_in;
end else if (fsm_state == FSM_DATA) begin
data <= {data[DATA_WIDTH_BITS-2:0], spi_miso_buf};
end
end
assign spi_select = fsm_state == FSM_IDLE;
assign spi_clk_out = !clk;
assign spi_mosi = fsm_state == FSM_IDLE ? 1'b0 :
fsm_state == FSM_CMD ? (bits_remaining == 1 || (bits_remaining == 0 && !writing)) :
fsm_state == FSM_ADDR ? addr[ADDR_BITS-1] :
data[DATA_WIDTH_BITS-1];
endmodule
|
module decoder (
input wire en,
input wire [15:0] inst,
input wire [15:0] accum,
input wire [7:0] data,
output wire [15:0] rhs,
output wire [1:0] bytes,
output wire inst_nop,
output wire inst_halt,
output wire inst_trap,
output wire inst_load,
output wire inst_store,
output wire inst_add,
output wire inst_sub,
output wire inst_and,
output wire inst_or,
output wire inst_xor,
output wire inst_shl,
output wire inst_shr,
output wire inst_not,
output wire inst_branch,
output wire inst_call,
output wire inst_if,
output wire inst_push,
output wire inst_pop,
output wire inst_drop,
output wire inst_return,
output wire inst_out_lo,
output wire inst_out_hi,
output wire inst_set_dp,
output wire inst_test,
output wire inst_status,
output wire inst_call_word,
output wire inst_load_word,
output wire source_imm,
output wire source_ram,
output wire source_indirect,
output wire relative_data,
output wire relative_stack,
output wire if_zero,
output wire if_not_zero,
output wire if_else,
output wire if_not_else,
output wire if_neg,
output wire if_not_neg,
output wire if_carry,
output wire if_not_carry
);
wire zero_arg = en & ((inst & 16'h8000) == 16'h0000);
assign inst_nop = en & ((inst >> 8) == 16'h0000);
assign inst_halt = en & ((inst >> 8) == 16'h0001);
assign inst_trap = en & ((inst >> 8) == 16'h0002);
assign inst_drop = en & ((inst >> 8) == 16'h0003);
assign inst_push = en & ((inst >> 8) == 16'h0004);
assign inst_pop = en & ((inst >> 8) == 16'h0005);
assign inst_return = en & ((inst >> 8) == 16'h0006);
assign inst_not = en & ((inst >> 8) == 16'h0007);
assign inst_out_lo = en & ((inst >> 8) == 16'h0008);
assign inst_out_hi = en & ((inst >> 8) == 16'h0009);
assign inst_set_dp = en & ((inst >> 8) == 16'h000A);
assign inst_test = en & ((inst >> 8) == 16'h000B);
assign inst_status = en & ((inst >> 8) == 16'h0010);
assign inst_call_word = en & ((inst >> 8) == 16'h003E);
assign inst_load_word = en & ((inst >> 8) == 16'h003F);
wire inst_load_indirect = en & (((inst >> 8) & 16'h00FC) == 16'h0044);
assign bytes = zero_arg ? 1 : 2;
wire one_arg = en & ((inst & 16'hC000) == 16'h8000);
wire inst_load_direct = en & ((inst & 16'hF800) == 16'h8000);
assign inst_load = inst_load_direct | inst_load_indirect;
assign inst_store = en & ((inst & 16'hF800) == 16'h9000);
assign inst_add = en & ((inst & 16'hF800) == 16'h8800);
assign inst_sub = en & ((inst & 16'hF800) == 16'h9800);
assign inst_and = en & ((inst & 16'hF800) == 16'hA000);
assign inst_or = en & ((inst & 16'hF800) == 16'hA800);
assign inst_xor = en & ((inst & 16'hF800) == 16'hB000);
wire inst_sh = en & ((inst & 16'hF800) == 16'hB800);
assign inst_shl = ~inst_sh ? 0
: source_ram ? ((inst & 16'h0001) == 16'h0000)
: ((inst & 16'h0100) == 16'h0000);
assign inst_shr = ~inst_sh ? 0
: source_ram ? ((inst & 16'h0001) == 16'h0001)
: ((inst & 16'h0100) == 16'h0100);
wire inst_branch_direct = en & ((inst & 16'hF800) == 16'hC000);
wire inst_branch_indirect = en & ((inst >> 8) == 16'h000C);
assign inst_branch = inst_branch_direct | inst_branch_indirect;
wire inst_call_direct = en & ((inst & 16'hF800) == 16'hD000);
wire inst_call_indirect = en & ((inst >> 8) == 16'h000D);
assign inst_call = inst_call_direct | inst_call_indirect;
assign inst_if = en & ((inst & 16'hF800) == 16'hF000);
wire source_const = !one_arg ? 0 : (inst & 16'h0600) == 16'h0000;
wire source_data = !one_arg ? 0 : (inst & 16'h0600) == 16'h0200;
wire source_none = inst_not | inst_test;
assign source_imm = source_const | source_data | source_none;
assign source_ram = (one_arg | inst_load_indirect) & ((inst & 16'h0500) == 16'h0400);
assign source_indirect = (one_arg | inst_load_indirect) & ((inst & 16'h0500) == 16'h0500);
assign relative_data = (source_ram | source_indirect)
? (inst & 16'h0200) == 16'h0000
: 0;
assign relative_stack = (source_ram | source_indirect)
? (inst & 16'h0200) == 16'h0200
: 0;
assign rhs = !en ? 0
: (inst_branch_direct | inst_call_direct) ? {{5{inst[10]}}, inst[10:0]}
: (inst_load_indirect | inst_branch_indirect | inst_call_indirect) ? accum
: (((inst & 16'h0600) == 16'h0000) & inst_sh) ? {8'h00, inst[7:0]}
: (((inst & 16'h0600) == 16'h0200) & inst_sh) ? {8'h00, data}
: (inst & 16'h0700) == 16'h0000 ? {8'h00, inst[7:0]}
: (inst & 16'h0700) == 16'h0100 ? {inst[7:0], 8'h00}
: (inst & 16'h0700) == 16'h0200 ? {8'h00, data}
: (inst & 16'h0700) == 16'h0300 ? {data, 8'h00}
: (((inst & 16'h0400) == 16'h0400) & inst_sh) ? {8'h00, inst[7:1], 1'b0}
: (inst & 16'h0400) == 16'h0400 ? {8'h00, inst[7:0]}
: 0;
assign if_zero = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0000;
assign if_not_zero = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0001;
assign if_else = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0002;
assign if_not_else = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0003;
assign if_neg = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0004;
assign if_not_neg = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0005;
assign if_carry = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0006;
assign if_not_carry = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0007;
endmodule
|
tt06-finale_0059
|
tt06-finale
|
couchand-tt06-cora16
|
task_tt_um_couchand_cora16
|
tt_um_couchand_cora16
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Andrew Dona-Couch
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_couchand_cora16 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
/*
* Copyright (c) 2024 Andrew Dona-Couch
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module cpu (
input wire clk,
input wire rst_n,
output wire spi_mosi,
output wire spi_select,
output wire spi_clk,
input wire spi_miso,
input wire step,
output wire busy,
output wire halt,
output wire trap,
input wire [7:0] data_in,
output reg [7:0] data_out
);
reg [15:0] pc;
reg [15:0] inst;
reg [15:0] accum;
reg [15:0] dp;
reg [15:0] sp;
reg zero;
reg neg;
reg carry;
reg skip;
reg skipped;
wire [15:0] alu_rhs = (state == ST_INST_EXEC0) ? rhs : ram_data_out;
wire [15:0] alu_result;
wire alu_zero, alu_neg, alu_carry, is_alu_inst;
alu alu_instance(
.accum(accum),
.rhs(alu_rhs),
.result(alu_result),
.zero(alu_zero),
.neg(alu_neg),
.carry(alu_carry),
.is_alu_inst(is_alu_inst),
.inst_add(inst_add),
.inst_sub(inst_sub),
.inst_test(inst_test),
.inst_and(inst_and),
.inst_or(inst_or),
.inst_xor(inst_xor),
.inst_not(inst_not),
.inst_shl(inst_shl),
.inst_shr(inst_shr)
);
wire [15:0] rhs;
wire [1:0] inst_bytes_raw;
wire [15:0] inst_bytes = {14'b0, inst_bytes_raw};
wire inst_load, inst_store, inst_add, inst_sub, inst_test, inst_status;
wire inst_and, inst_or, inst_xor, inst_not, inst_shl, inst_shr;
wire inst_branch, inst_call, inst_if, inst_push, inst_pop, inst_drop, inst_return;
wire inst_nop, inst_out_lo, inst_out_hi, inst_halt, inst_trap, inst_set_dp;
wire inst_call_word, inst_load_word;
wire source_imm, source_ram, source_indirect;
wire relative_stack, relative_data;
wire if_zero, if_not_zero, if_else, if_not_else, if_neg, if_not_neg, if_carry, if_not_carry;
wire decoding = (state == ST_INST_EXEC0) | (state == ST_INST_EXEC1)
| (state == ST_INST_EXEC2) | (state == ST_INST_EXEC3);
decoder inst_decoder(
.en(decoding),
.inst(inst),
.accum(accum),
.data(data_in),
.rhs(rhs),
.bytes(inst_bytes_raw),
.inst_nop(inst_nop),
.inst_halt(inst_halt),
.inst_trap(inst_trap),
.inst_load(inst_load),
.inst_store(inst_store),
.inst_add(inst_add),
.inst_sub(inst_sub),
.inst_and(inst_and),
.inst_or(inst_or),
.inst_xor(inst_xor),
.inst_shl(inst_shl),
.inst_shr(inst_shr),
.inst_not(inst_not),
.inst_branch(inst_branch),
.inst_call(inst_call),
.inst_if(inst_if),
.inst_push(inst_push),
.inst_pop(inst_pop),
.inst_drop(inst_drop),
.inst_return(inst_return),
.inst_out_lo(inst_out_lo),
.inst_out_hi(inst_out_hi),
.inst_set_dp(inst_set_dp),
.inst_test(inst_test),
.inst_status(inst_status),
.inst_call_word(inst_call_word),
.inst_load_word(inst_load_word),
.source_imm(source_imm),
.source_ram(source_ram),
.source_indirect(source_indirect),
.relative_stack(relative_stack),
.relative_data(relative_data),
.if_zero(if_zero),
.if_not_zero(if_not_zero),
.if_else(if_else),
.if_not_else(if_not_else),
.if_neg(if_neg),
.if_not_neg(if_not_neg),
.if_carry(if_carry),
.if_not_carry(if_not_carry)
);
reg [8:0] state;
localparam ST_INIT = 0;
localparam ST_HALT = 1;
localparam ST_TRAP = 2;
localparam ST_LOAD_INST0 = 3;
localparam ST_LOAD_INST1 = 4;
localparam ST_INST_EXEC0 = 5;
localparam ST_INST_EXEC1 = 6;
localparam ST_INST_EXEC2 = 7;
localparam ST_INST_EXEC3 = 8;
localparam ST_UNTRAP = 9;
localparam ST_FAULT = 10;
assign busy = state != ST_INIT & state != ST_HALT & state != ST_TRAP & state != ST_FAULT;
assign halt = (state == ST_HALT) | (state == ST_FAULT);
assign trap = (state == ST_TRAP) | (state == ST_FAULT);
wire [15:0] sp_minus_two = sp - 2;
wire [15:0] ram_addr = (state == ST_LOAD_INST0) ? pc
: ((state == ST_INST_EXEC0) & (inst_push | inst_call | inst_call_word)) ? sp_minus_two
: ((state == ST_INST_EXEC0) & (inst_pop | inst_return)) ? sp
: ((state == ST_INST_EXEC0) & inst_load_word) ? (pc + inst_bytes)
: ((state == ST_INST_EXEC0) & (source_ram | source_indirect))
? ((relative_stack ? sp : relative_data ? dp : 0) + rhs)
: ((state == ST_INST_EXEC2) & inst_call_word) ? (pc + inst_bytes)
: ((state == ST_INST_EXEC2) & source_indirect) ? ram_data_out
: 0;
wire ram_start_read = (state == ST_LOAD_INST0) ? 1
: ((state == ST_INST_EXEC0) & ((source_ram & ~inst_store) | source_indirect)) ? ~skip
: ((state == ST_INST_EXEC0) & (inst_pop | inst_return)) ? ~skip
: ((state == ST_INST_EXEC0) & inst_load_word) ? ~skip
: ((state == ST_INST_EXEC2) & inst_call_word) ? ~skip
: ((state == ST_INST_EXEC2) & source_indirect) ? ~skip
: 0;
wire [15:0] ram_data_in = ((state == ST_INST_EXEC0) & source_ram & inst_store) ? accum
: ((state == ST_INST_EXEC0) & inst_push) ? accum
: ((state == ST_INST_EXEC0) & inst_call) ? (pc + inst_bytes)
: ((state == ST_INST_EXEC0) & inst_call_word) ? (pc + inst_bytes + 2)
: ((state == ST_INST_EXEC2) & source_indirect & inst_store) ? accum
: 0;
wire ram_start_write = ((state == ST_INST_EXEC0) & source_ram & inst_store) ? ~skip
: ((state == ST_INST_EXEC0) & (inst_push | inst_call | inst_call_word)) ? ~skip
: ((state == ST_INST_EXEC2) & source_indirect & inst_store) ? ~skip
: 0;
wire [15:0] ram_data_out;
wire ram_busy;
spi_ram_controller #(
.DATA_WIDTH_BYTES(2),
.ADDR_BITS(16)
) spi_ram (
.clk(clk),
.rstn(rst_n),
.spi_miso(spi_miso),
.spi_select(spi_select),
.spi_clk_out(spi_clk),
.spi_mosi(spi_mosi),
.addr_in(ram_addr),
.data_in(ram_data_in),
.start_read(ram_start_read),
.start_write(ram_start_write),
.data_out(ram_data_out),
.busy(ram_busy)
);
always @(posedge clk) begin
if (!rst_n) begin
state <= ST_INIT;
pc <= 0;
inst <= 0;
accum <= 0;
dp <= 0;
sp <= 0;
zero <= 0;
neg <= 0;
carry <= 0;
skip <= 0;
skipped <= 0;
data_out <= 0;
end else if (~halt) begin
if (state == ST_INIT) begin
if (step) begin
state <= ST_LOAD_INST0;
end
end else if (state == ST_TRAP) begin
if (step) begin
state <= ST_UNTRAP;
end
end else if (state == ST_UNTRAP) begin
if (~step) begin
state <= ST_INIT;
end
end else if (state == ST_LOAD_INST0) begin
state <= ST_LOAD_INST1;
end else if (state == ST_LOAD_INST1) begin
if (!ram_busy) begin
inst <= ram_data_out;
state <= ST_INST_EXEC0;
end
end else if (state == ST_INST_EXEC0) begin
if (inst_nop) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (inst_halt) begin
pc <= pc + inst_bytes;
if (skip) begin
state <= ST_INIT;
end else begin
state <= ST_HALT;
end
end else if (inst_trap) begin
pc <= pc + inst_bytes;
if (skip) begin
state <= ST_INIT;
end else begin
state <= ST_TRAP;
end
end else if (inst_set_dp) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
if (~skip) begin
dp <= accum;
end
end else if (inst_status) begin
accum <= {8'b0, 2'b0, skipped, 2'b0, carry, neg, zero};
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (inst_drop) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
if (~skip) begin
sp <= sp + 2;
end
end else if (inst_push | inst_pop) begin
if (skip) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else begin
state <= ST_INST_EXEC1;
end
end else if (inst_call_word | inst_load_word) begin
if (skip) begin
pc <= pc + inst_bytes + 2;
state <= ST_INIT;
end else begin
state <= ST_INST_EXEC1;
end
end else if (inst_load) begin
if (skip) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (source_imm) begin
accum <= rhs;
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (source_ram | source_indirect) begin
state <= ST_INST_EXEC1;
end else begin
state <= ST_FAULT;
end
end else if (inst_store) begin
if (skip) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (source_imm) begin
state <= ST_FAULT;
end else if (source_ram | source_indirect) begin
state <= ST_INST_EXEC1;
end else begin
state <= ST_FAULT;
end
end else if (is_alu_inst) begin
if (skip) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (source_imm) begin
accum <= alu_result;
zero <= alu_zero;
neg <= alu_neg;
carry <= alu_carry;
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (source_ram | source_indirect) begin
state <= ST_INST_EXEC1;
end else begin
state <= ST_FAULT;
end
end else if (inst_branch) begin
state <= ST_INIT;
if (skip) begin
pc <= pc + inst_bytes;
end else begin
pc <= pc + inst_bytes + rhs;
end
end else if (inst_call) begin
if (skip) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else begin
state <= ST_INST_EXEC1;
end
end else if (inst_return) begin
if (skip) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else begin
state <= ST_INST_EXEC1;
end
end else if (inst_if) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (inst_out_lo) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
if (~skip) begin
data_out <= accum[7:0];
end
end else if (inst_out_hi) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
if (~skip) begin
data_out <= accum[15:8];
end
end else begin
state <= ST_FAULT;
end
if (inst_if) begin
if (if_zero) begin
skip <= ~zero;
end else if (if_not_zero) begin
skip <= zero;
end else if (if_else) begin
skip <= ~skipped;
end else if (if_not_else) begin
skip <= skipped;
end else if (if_neg) begin
skip <= ~neg;
end else if (if_not_neg) begin
skip <= neg;
end else if (if_carry) begin
skip <= ~carry;
end else if (if_not_carry) begin
skip <= carry;
end else begin
state <= ST_FAULT;
end
end else begin
skip <= 0;
end
skipped <= skip;
end else if (state == ST_INST_EXEC1) begin
if (!ram_busy) begin
if (inst_push) begin
sp <= sp_minus_two;
state <= ST_INIT;
pc <= pc + inst_bytes;
end else if (inst_pop) begin
sp <= sp + 2;
accum <= ram_data_out;
state <= ST_INIT;
pc <= pc + inst_bytes;
end else if (inst_call) begin
sp <= sp_minus_two;
state <= ST_INIT;
pc <= rhs;
end else if (inst_return) begin
sp <= sp + 2;
state <= ST_INIT;
pc <= ram_data_out;
end else if (inst_call_word) begin
sp <= sp_minus_two;
state <= ST_INST_EXEC2;
end else if (inst_load_word) begin
accum <= ram_data_out;
pc <= pc + inst_bytes + 2;
state <= ST_INIT;
end else if (source_ram) begin
if (inst_load) begin
accum <= ram_data_out;
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (is_alu_inst) begin
accum <= alu_result;
zero <= alu_zero;
neg <= alu_neg;
carry <= alu_carry;
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (inst_store) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else begin
state <= ST_FAULT;
end
end else if (source_indirect) begin
if (!ram_busy) begin
state <= ST_INST_EXEC2;
end
end else begin
state <= ST_FAULT;
end
end
end else if (state == ST_INST_EXEC2) begin
state <= ST_INST_EXEC3;
end else if (state == ST_INST_EXEC3) begin
if (!ram_busy) begin
if (inst_load) begin
accum <= ram_data_out;
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (is_alu_inst) begin
accum <= alu_result;
zero <= alu_zero;
neg <= alu_neg;
carry <= alu_carry;
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (inst_store) begin
pc <= pc + inst_bytes;
state <= ST_INIT;
end else if (inst_call_word) begin
pc <= ram_data_out;
state <= ST_INIT;
end else begin
state <= ST_FAULT;
end
end
end else begin
state <= ST_FAULT;
end
end
end
endmodule
/*
* Copyright (c) 2024 Andrew Dona-Couch
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module decoder (
input wire en,
input wire [15:0] inst,
input wire [15:0] accum,
input wire [7:0] data,
output wire [15:0] rhs,
output wire [1:0] bytes,
output wire inst_nop,
output wire inst_halt,
output wire inst_trap,
output wire inst_load,
output wire inst_store,
output wire inst_add,
output wire inst_sub,
output wire inst_and,
output wire inst_or,
output wire inst_xor,
output wire inst_shl,
output wire inst_shr,
output wire inst_not,
output wire inst_branch,
output wire inst_call,
output wire inst_if,
output wire inst_push,
output wire inst_pop,
output wire inst_drop,
output wire inst_return,
output wire inst_out_lo,
output wire inst_out_hi,
output wire inst_set_dp,
output wire inst_test,
output wire inst_status,
output wire inst_call_word,
output wire inst_load_word,
output wire source_imm,
output wire source_ram,
output wire source_indirect,
output wire relative_data,
output wire relative_stack,
output wire if_zero,
output wire if_not_zero,
output wire if_else,
output wire if_not_else,
output wire if_neg,
output wire if_not_neg,
output wire if_carry,
output wire if_not_carry
);
wire zero_arg = en & ((inst & 16'h8000) == 16'h0000);
assign inst_nop = en & ((inst >> 8) == 16'h0000);
assign inst_halt = en & ((inst >> 8) == 16'h0001);
assign inst_trap = en & ((inst >> 8) == 16'h0002);
assign inst_drop = en & ((inst >> 8) == 16'h0003);
assign inst_push = en & ((inst >> 8) == 16'h0004);
assign inst_pop = en & ((inst >> 8) == 16'h0005);
assign inst_return = en & ((inst >> 8) == 16'h0006);
assign inst_not = en & ((inst >> 8) == 16'h0007);
assign inst_out_lo = en & ((inst >> 8) == 16'h0008);
assign inst_out_hi = en & ((inst >> 8) == 16'h0009);
assign inst_set_dp = en & ((inst >> 8) == 16'h000A);
assign inst_test = en & ((inst >> 8) == 16'h000B);
assign inst_status = en & ((inst >> 8) == 16'h0010);
assign inst_call_word = en & ((inst >> 8) == 16'h003E);
assign inst_load_word = en & ((inst >> 8) == 16'h003F);
wire inst_load_indirect = en & (((inst >> 8) & 16'h00FC) == 16'h0044);
assign bytes = zero_arg ? 1 : 2;
wire one_arg = en & ((inst & 16'hC000) == 16'h8000);
wire inst_load_direct = en & ((inst & 16'hF800) == 16'h8000);
assign inst_load = inst_load_direct | inst_load_indirect;
assign inst_store = en & ((inst & 16'hF800) == 16'h9000);
assign inst_add = en & ((inst & 16'hF800) == 16'h8800);
assign inst_sub = en & ((inst & 16'hF800) == 16'h9800);
assign inst_and = en & ((inst & 16'hF800) == 16'hA000);
assign inst_or = en & ((inst & 16'hF800) == 16'hA800);
assign inst_xor = en & ((inst & 16'hF800) == 16'hB000);
wire inst_sh = en & ((inst & 16'hF800) == 16'hB800);
assign inst_shl = ~inst_sh ? 0
: source_ram ? ((inst & 16'h0001) == 16'h0000)
: ((inst & 16'h0100) == 16'h0000);
assign inst_shr = ~inst_sh ? 0
: source_ram ? ((inst & 16'h0001) == 16'h0001)
: ((inst & 16'h0100) == 16'h0100);
wire inst_branch_direct = en & ((inst & 16'hF800) == 16'hC000);
wire inst_branch_indirect = en & ((inst >> 8) == 16'h000C);
assign inst_branch = inst_branch_direct | inst_branch_indirect;
wire inst_call_direct = en & ((inst & 16'hF800) == 16'hD000);
wire inst_call_indirect = en & ((inst >> 8) == 16'h000D);
assign inst_call = inst_call_direct | inst_call_indirect;
assign inst_if = en & ((inst & 16'hF800) == 16'hF000);
wire source_const = !one_arg ? 0 : (inst & 16'h0600) == 16'h0000;
wire source_data = !one_arg ? 0 : (inst & 16'h0600) == 16'h0200;
wire source_none = inst_not | inst_test;
assign source_imm = source_const | source_data | source_none;
assign source_ram = (one_arg | inst_load_indirect) & ((inst & 16'h0500) == 16'h0400);
assign source_indirect = (one_arg | inst_load_indirect) & ((inst & 16'h0500) == 16'h0500);
assign relative_data = (source_ram | source_indirect)
? (inst & 16'h0200) == 16'h0000
: 0;
assign relative_stack = (source_ram | source_indirect)
? (inst & 16'h0200) == 16'h0200
: 0;
assign rhs = !en ? 0
: (inst_branch_direct | inst_call_direct) ? {{5{inst[10]}}, inst[10:0]}
: (inst_load_indirect | inst_branch_indirect | inst_call_indirect) ? accum
: (((inst & 16'h0600) == 16'h0000) & inst_sh) ? {8'h00, inst[7:0]}
: (((inst & 16'h0600) == 16'h0200) & inst_sh) ? {8'h00, data}
: (inst & 16'h0700) == 16'h0000 ? {8'h00, inst[7:0]}
: (inst & 16'h0700) == 16'h0100 ? {inst[7:0], 8'h00}
: (inst & 16'h0700) == 16'h0200 ? {8'h00, data}
: (inst & 16'h0700) == 16'h0300 ? {data, 8'h00}
: (((inst & 16'h0400) == 16'h0400) & inst_sh) ? {8'h00, inst[7:1], 1'b0}
: (inst & 16'h0400) == 16'h0400 ? {8'h00, inst[7:0]}
: 0;
assign if_zero = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0000;
assign if_not_zero = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0001;
assign if_else = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0002;
assign if_not_else = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0003;
assign if_neg = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0004;
assign if_not_neg = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0005;
assign if_carry = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0006;
assign if_not_carry = !inst_if ? 0
: (inst & 16'h07FF) == 16'h0007;
endmodule
/*
* Copyright (c) 2024 Andrew Dona-Couch
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module alu (
input wire [15:0] accum,
input wire [15:0] rhs,
output wire [15:0] result,
output wire zero,
output wire neg,
output wire carry,
output wire is_alu_inst,
input wire inst_add,
input wire inst_sub,
input wire inst_test,
input wire inst_and,
input wire inst_or,
input wire inst_xor,
input wire inst_not,
input wire inst_shl,
input wire inst_shr
);
assign is_alu_inst = inst_add | inst_sub | inst_test
| inst_and | inst_or | inst_xor | inst_not | inst_shl | inst_shr;
assign result = inst_add ? (accum + rhs)
: inst_sub ? (accum - rhs)
: inst_test ? accum
: inst_and ? (accum & rhs)
: inst_or ? (accum | rhs)
: inst_xor ? (accum ^ rhs)
: inst_not ? (~accum)
: inst_shl ? (accum << rhs)
: inst_shr ? (accum >> rhs)
: 0;
assign carry = inst_add ? ((accum[15] & rhs[15]) | (rhs[15] & ~result[15]) | (~result[15] & accum[15]))
: inst_sub ? ((~accum[15] & rhs[15]) | (rhs[15] & result[15]) | (result[15] & ~accum[15]))
: inst_not ? 1
: inst_shl ? accum[16 - rhs]
: inst_shr ? accum[rhs - 1]
: 0;
assign zero = is_alu_inst & (result == 0);
assign neg = is_alu_inst & result[15];
endmodule
/* Copyright 2023 (c) Michael Bell
A simple SPI RAM controller
To perform a read:
- Set addr_in and set start_read high for 1 cycle
- Wait for busy to go low
- The read data is now available on data_out
To perform a write:
- Set addr_in, data_in and set start_write high for 1 cycle
- Wait for busy to go low before starting another operation
If the controller is configured to transfer multiple bytes, then
note that the word transferred in data_in/data_out is in big
endian order, i.e. the byte with the lowest address is aligned to
the MSB of the word.
*/
module spi_ram_controller #(parameter DATA_WIDTH_BYTES=4, parameter ADDR_BITS=16) (
input clk,
input rstn,
// External SPI interface
input spi_miso,
output spi_select,
output spi_clk_out,
output spi_mosi,
// Internal interface for reading/writing data
input [ADDR_BITS-1:0] addr_in,
input [DATA_WIDTH_BYTES*8-1:0] data_in,
input start_read,
input start_write,
output [DATA_WIDTH_BYTES*8-1:0] data_out,
output busy
);
//`ifdef COCOTB_SIM
//initial begin
// $dumpfile ("spi.vcd");
// $dumpvars (0, spi_ram_controller);
// #1;
//end
//`endif
`define max(a, b) (a > b) ? a : b
localparam DATA_WIDTH_BITS = DATA_WIDTH_BYTES * 8;
localparam FSM_IDLE = 0;
localparam FSM_CMD = 1;
localparam FSM_ADDR = 2;
localparam FSM_DATA = 3;
reg [1:0] fsm_state;
reg writing;
reg spi_miso_buf;
reg [ADDR_BITS-1:0] addr;
reg [DATA_WIDTH_BITS-1:0] data;
reg [$clog2(`max(DATA_WIDTH_BITS,ADDR_BITS))-1:0] bits_remaining;
assign data_out = data;
assign busy = fsm_state != FSM_IDLE;
always @(posedge clk) begin
if (!rstn) begin
fsm_state <= FSM_IDLE;
bits_remaining <= 0;
end else begin
if (fsm_state == FSM_IDLE) begin
if (start_read || start_write) begin
fsm_state <= FSM_CMD;
bits_remaining <= 8-1;
end
end else begin
if (bits_remaining == 0) begin
fsm_state <= fsm_state + 1;
if (fsm_state == FSM_CMD) bits_remaining <= ADDR_BITS-1;
else if (fsm_state == FSM_ADDR) bits_remaining <= DATA_WIDTH_BITS-1;
end else begin
bits_remaining <= bits_remaining - 1;
end
end
end
end
always @(posedge clk) begin
if (fsm_state == FSM_IDLE && (start_read || start_write)) begin
addr <= addr_in;
writing <= start_write;
end else if (fsm_state == FSM_ADDR) begin
addr <= {addr[ADDR_BITS-2:0], 1'b0};
end
end
always @(negedge clk) begin
spi_miso_buf <= spi_miso;
end
always @(posedge clk) begin
if (fsm_state == FSM_IDLE && start_write) begin
data <= data_in;
end else if (fsm_state == FSM_DATA) begin
data <= {data[DATA_WIDTH_BITS-2:0], spi_miso_buf};
end
end
assign spi_select = fsm_state == FSM_IDLE;
assign spi_clk_out = !clk;
assign spi_mosi = fsm_state == FSM_IDLE ? 1'b0 :
fsm_state == FSM_CMD ? (bits_remaining == 1 || (bits_remaining == 0 && !writing)) :
fsm_state == FSM_ADDR ? addr[ADDR_BITS-1] :
data[DATA_WIDTH_BITS-1];
endmodule
|
module tt_um_couchand_cora16 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// Allow external SPI RAM programming on reset
assign uio_oe = rst_n ? 8'b11100111 : 8'b11100000;
assign uio_out[4:3] = 0;
wire spi_miso, spi_select, spi_clk, spi_mosi;
assign spi_miso = uio_in[3];
assign uio_out[1] = spi_select;
assign uio_out[2] = spi_clk;
assign uio_out[0] = spi_mosi;
wire step, busy, halt, trap;
assign step = uio_in[4];
assign uio_out[5] = busy;
assign uio_out[6] = halt;
assign uio_out[7] = trap;
cpu cpu_instance(
.clk(clk),
.rst_n(rst_n),
.spi_mosi(spi_mosi),
.spi_select(spi_select),
.spi_clk(spi_clk),
.spi_miso(spi_miso),
.step(step),
.busy(busy),
.halt(halt),
.trap(trap),
.data_in(ui_in),
.data_out(uo_out)
);
endmodule
|
tt06-finale_0060
|
tt06-finale
|
drburke3-SADdiff_v1
|
task_black_cell
|
tt_um_drburke3_top
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Daniel Burke
* SPDX-License-Identifier: Apache-2.0
*/
`timescale 1ns / 1ps
`default_nettype none
module tt_um_drburke3_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
/// assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in
assign uio_out = 0;
assign uio_oe = 0;
sklansky_adder_8bit diff_1(
.a (ui_in[7:0]), // input a
.sum (uo_out[7:0]), // addition out
.b (uio_in[7:0]), // input b
.enable (ena), // will go high when the design is enabled
.clock (clk), // clock
.reset_n (rst_n) // reset
);
endmodule
//////////////////////////////////////////////////////////////////////////////////
// Company: Berkeley Neuromorphic
// Engineer: Daniel Burke
//
// Create Date: 09/14/2022 10:16:27 AM
// Design Name:
// Module Name: sklansky_adder_8bit
// Project Name:
// Target Devices:
// Tool Versions:
// Description: 8-bit generated fast adder with black, gray, and generate-propagate included at bottom
// naming changed, truncated at 8-bits, and 'multiple packed array wires' error fixed.
//
// Dependencies: self-contained
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// from fluffybird2323 generator
// https://github.com/fluffybird2323/n-bit-sklansky-adder-code-generator-notebook/blob/master/README.Black
//////////////////////////////////////////////////////////////////////////////////
/* Generated 8 bit sklansky adder
In this adder, binary tree of propagate and generate
cells will first simultaneously generate all the carries, Cin.
It builds recursively 2-bit adders then 4-bit adders, 8-bit adders,
16-bit adder and so on by abutting each time two smaller adders.
*/
module sklansky_adder_8bit(a,b,sum,enable,clock,reset_n);
input [7:0] a;
input [7:0] b;
output reg [7:0] sum;
input enable;
input clock;
input reset_n;
// declare array wires
wire [8:0] g [8:0];
wire [8:0] p [8:0];
assign g[0][0]=1'b0;
assign p[0][0]=1'b0;
generate_propagate GeneratePropagate_00(a[0],b[0],g[1][1],p[1][1]);
generate_propagate GeneratePropagate_01(a[1],b[1],g[2][2],p[2][2]);
generate_propagate GeneratePropagate_02(a[2],b[2],g[3][3],p[3][3]);
generate_propagate GeneratePropagate_03(a[3],b[3],g[4][4],p[4][4]);
generate_propagate GeneratePropagate_04(a[4],b[4],g[5][5],p[5][5]);
generate_propagate GeneratePropagate_05(a[5],b[5],g[6][6],p[6][6]);
generate_propagate GeneratePropagate_06(a[6],b[6],g[7][7],p[7][7]);
generate_propagate GeneratePropagate_07(a[7],b[7],g[8][8],p[8][8]);
/// nomenclature is first number is clock level (1 is highest)
/// nomenclature is second number is bit position (0 is rightmost)
/// Level 1:
gray_cell GrayCell_1_1(g[1][1],p[1][1],g[0][0],g[1][0]);
black_cell BlackCell_1_3(g[3][3],p[3][3],g[2][2],p[2][2],g[3][2],p[3][2]);
black_cell BlackCell_1_5(g[5][5],p[5][5],g[4][4],p[4][4],g[5][4],p[5][4]);
black_cell BlackCell_1_7(g[7][7],p[7][7],g[6][6],p[6][6],g[7][6],p[7][6]);
/// Level 2:
gray_cell grayCell_2_2(g[2][2],p[2][2],g[1][0],g[2][0]);
gray_cell grayCell_2_3(g[3][2],p[3][2],g[1][0],g[3][0]);
black_cell BlackCell_2_6(g[6][6],p[6][6],g[5][4],p[5][4],g[6][4],p[6][4]);
black_cell BlackCell_2_7(g[7][6],p[7][6],g[5][4],p[5][4],g[7][4],p[7][4]);
/// Level 3:
gray_cell GrayCell_3_4(g[4][4],p[4][4],g[3][0],g[4][0]);
gray_cell grayCell_3_5(g[5][4],p[5][4],g[3][0],g[5][0]);
gray_cell grayCell_3_6(g[6][4],p[6][4],g[3][0],g[6][0]);
gray_cell grayCell_3_7(g[7][4],p[7][4],g[3][0],g[7][0]);
/// Level 4: (if carry out needed)
/// gray cell_4_8(g[8][8],p[8][8],g[7][0],g[8][0]);
always @(posedge clock)
begin
if(reset_n == 1'b0)
begin
sum <= 8'b00000000;
end
else if(enable == 1'b1)
begin
sum[0] <= g[0][0]^p[1][1];
sum[1] <= g[1][0]^p[2][2];
sum[2] <= g[2][0]^p[3][3];
sum[3] <= g[3][0]^p[4][4];
sum[4] <= g[4][0]^p[5][5];
sum[5] <= g[5][0]^p[6][6];
sum[6] <= g[6][0]^p[7][7];
sum[7] <= g[7][0]^p[8][8];
end
end
endmodule
// Generate Propagate code
module generate_propagate(A,B,G,P);
input A,B;
output G,P;
assign G = A&B;
assign P = A^B;
endmodule
// Gray module code
module gray_cell(G4_3,P4_3,G2_2,G4_2);
input G4_3,P4_3,G2_2;
output G4_2;
wire signal;
assign signal = P4_3 & G2_2;
assign G4_2=signal | G4_3;
endmodule
// Black module code
module black_cell(G6_8,P6_8,G7_10,P7_10,G6_10,P6_10);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
|
module black_cell(G6_8,P6_8,G7_10,P7_10,G6_10,P6_10);
input G6_8,P6_8,G7_10,P7_10;
output G6_10,P6_10;
wire signal;
assign signal = P6_8 & G7_10;
assign G6_10=signal | G6_8;
assign P6_10=P6_8 & P7_10;
endmodule
|
tt06-finale_0061
|
tt06-finale
|
drburke3-SADdiff_v1
|
task_generate_propagate
|
tt_um_drburke3_top
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Daniel Burke
* SPDX-License-Identifier: Apache-2.0
*/
`timescale 1ns / 1ps
`default_nettype none
module tt_um_drburke3_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
/// assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in
assign uio_out = 0;
assign uio_oe = 0;
sklansky_adder_8bit diff_1(
.a (ui_in[7:0]), // input a
.sum (uo_out[7:0]), // addition out
.b (uio_in[7:0]), // input b
.enable (ena), // will go high when the design is enabled
.clock (clk), // clock
.reset_n (rst_n) // reset
);
endmodule
//////////////////////////////////////////////////////////////////////////////////
// Company: Berkeley Neuromorphic
// Engineer: Daniel Burke
//
// Create Date: 09/14/2022 10:16:27 AM
// Design Name:
// Module Name: sklansky_adder_8bit
// Project Name:
// Target Devices:
// Tool Versions:
// Description: 8-bit generated fast adder with black, gray, and generate-propagate included at bottom
// naming changed, truncated at 8-bits, and 'multiple packed array wires' error fixed.
//
// Dependencies: self-contained
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// from fluffybird2323 generator
// https://github.com/fluffybird2323/n-bit-sklansky-adder-code-generator-notebook/blob/master/README.Black
//////////////////////////////////////////////////////////////////////////////////
/* Generated 8 bit sklansky adder
In this adder, binary tree of propagate and generate
cells will first simultaneously generate all the carries, Cin.
It builds recursively 2-bit adders then 4-bit adders, 8-bit adders,
16-bit adder and so on by abutting each time two smaller adders.
*/
module sklansky_adder_8bit(a,b,sum,enable,clock,reset_n);
input [7:0] a;
input [7:0] b;
output reg [7:0] sum;
input enable;
input clock;
input reset_n;
// declare array wires
wire [8:0] g [8:0];
wire [8:0] p [8:0];
assign g[0][0]=1'b0;
assign p[0][0]=1'b0;
generate_propagate GeneratePropagate_00(a[0],b[0],g[1][1],p[1][1]);
generate_propagate GeneratePropagate_01(a[1],b[1],g[2][2],p[2][2]);
generate_propagate GeneratePropagate_02(a[2],b[2],g[3][3],p[3][3]);
generate_propagate GeneratePropagate_03(a[3],b[3],g[4][4],p[4][4]);
generate_propagate GeneratePropagate_04(a[4],b[4],g[5][5],p[5][5]);
generate_propagate GeneratePropagate_05(a[5],b[5],g[6][6],p[6][6]);
generate_propagate GeneratePropagate_06(a[6],b[6],g[7][7],p[7][7]);
generate_propagate GeneratePropagate_07(a[7],b[7],g[8][8],p[8][8]);
/// nomenclature is first number is clock level (1 is highest)
/// nomenclature is second number is bit position (0 is rightmost)
/// Level 1:
gray_cell GrayCell_1_1(g[1][1],p[1][1],g[0][0],g[1][0]);
black_cell BlackCell_1_3(g[3][3],p[3][3],g[2][2],p[2][2],g[3][2],p[3][2]);
black_cell BlackCell_1_5(g[5][5],p[5][5],g[4][4],p[4][4],g[5][4],p[5][4]);
black_cell BlackCell_1_7(g[7][7],p[7][7],g[6][6],p[6][6],g[7][6],p[7][6]);
/// Level 2:
gray_cell grayCell_2_2(g[2][2],p[2][2],g[1][0],g[2][0]);
gray_cell grayCell_2_3(g[3][2],p[3][2],g[1][0],g[3][0]);
black_cell BlackCell_2_6(g[6][6],p[6][6],g[5][4],p[5][4],g[6][4],p[6][4]);
black_cell BlackCell_2_7(g[7][6],p[7][6],g[5][4],p[5][4],g[7][4],p[7][4]);
/// Level 3:
gray_cell GrayCell_3_4(g[4][4],p[4][4],g[3][0],g[4][0]);
gray_cell grayCell_3_5(g[5][4],p[5][4],g[3][0],g[5][0]);
gray_cell grayCell_3_6(g[6][4],p[6][4],g[3][0],g[6][0]);
gray_cell grayCell_3_7(g[7][4],p[7][4],g[3][0],g[7][0]);
/// Level 4: (if carry out needed)
/// gray cell_4_8(g[8][8],p[8][8],g[7][0],g[8][0]);
always @(posedge clock)
begin
if(reset_n == 1'b0)
begin
sum <= 8'b00000000;
end
else if(enable == 1'b1)
begin
sum[0] <= g[0][0]^p[1][1];
sum[1] <= g[1][0]^p[2][2];
sum[2] <= g[2][0]^p[3][3];
sum[3] <= g[3][0]^p[4][4];
sum[4] <= g[4][0]^p[5][5];
sum[5] <= g[5][0]^p[6][6];
sum[6] <= g[6][0]^p[7][7];
sum[7] <= g[7][0]^p[8][8];
end
end
endmodule
// Generate Propagate code
module generate_propagate(A,B,G,P);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
// Gray module code
module gray_cell(G4_3,P4_3,G2_2,G4_2);
input G4_3,P4_3,G2_2;
output G4_2;
wire signal;
assign signal = P4_3 & G2_2;
assign G4_2=signal | G4_3;
endmodule
// Black module code
module black_cell(G6_8,P6_8,G7_10,P7_10,G6_10,P6_10);
input G6_8,P6_8,G7_10,P7_10;
output G6_10,P6_10;
wire signal;
assign signal = P6_8 & G7_10;
assign G6_10=signal | G6_8;
assign P6_10=P6_8 & P7_10;
endmodule
|
module generate_propagate(A,B,G,P);
input A,B;
output G,P;
assign G = A&B;
assign P = A^B;
endmodule
|
tt06-finale_0062
|
tt06-finale
|
drburke3-SADdiff_v1
|
task_gray_cell
|
tt_um_drburke3_top
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Daniel Burke
* SPDX-License-Identifier: Apache-2.0
*/
`timescale 1ns / 1ps
`default_nettype none
module tt_um_drburke3_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
/// assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in
assign uio_out = 0;
assign uio_oe = 0;
sklansky_adder_8bit diff_1(
.a (ui_in[7:0]), // input a
.sum (uo_out[7:0]), // addition out
.b (uio_in[7:0]), // input b
.enable (ena), // will go high when the design is enabled
.clock (clk), // clock
.reset_n (rst_n) // reset
);
endmodule
//////////////////////////////////////////////////////////////////////////////////
// Company: Berkeley Neuromorphic
// Engineer: Daniel Burke
//
// Create Date: 09/14/2022 10:16:27 AM
// Design Name:
// Module Name: sklansky_adder_8bit
// Project Name:
// Target Devices:
// Tool Versions:
// Description: 8-bit generated fast adder with black, gray, and generate-propagate included at bottom
// naming changed, truncated at 8-bits, and 'multiple packed array wires' error fixed.
//
// Dependencies: self-contained
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// from fluffybird2323 generator
// https://github.com/fluffybird2323/n-bit-sklansky-adder-code-generator-notebook/blob/master/README.Black
//////////////////////////////////////////////////////////////////////////////////
/* Generated 8 bit sklansky adder
In this adder, binary tree of propagate and generate
cells will first simultaneously generate all the carries, Cin.
It builds recursively 2-bit adders then 4-bit adders, 8-bit adders,
16-bit adder and so on by abutting each time two smaller adders.
*/
module sklansky_adder_8bit(a,b,sum,enable,clock,reset_n);
input [7:0] a;
input [7:0] b;
output reg [7:0] sum;
input enable;
input clock;
input reset_n;
// declare array wires
wire [8:0] g [8:0];
wire [8:0] p [8:0];
assign g[0][0]=1'b0;
assign p[0][0]=1'b0;
generate_propagate GeneratePropagate_00(a[0],b[0],g[1][1],p[1][1]);
generate_propagate GeneratePropagate_01(a[1],b[1],g[2][2],p[2][2]);
generate_propagate GeneratePropagate_02(a[2],b[2],g[3][3],p[3][3]);
generate_propagate GeneratePropagate_03(a[3],b[3],g[4][4],p[4][4]);
generate_propagate GeneratePropagate_04(a[4],b[4],g[5][5],p[5][5]);
generate_propagate GeneratePropagate_05(a[5],b[5],g[6][6],p[6][6]);
generate_propagate GeneratePropagate_06(a[6],b[6],g[7][7],p[7][7]);
generate_propagate GeneratePropagate_07(a[7],b[7],g[8][8],p[8][8]);
/// nomenclature is first number is clock level (1 is highest)
/// nomenclature is second number is bit position (0 is rightmost)
/// Level 1:
gray_cell GrayCell_1_1(g[1][1],p[1][1],g[0][0],g[1][0]);
black_cell BlackCell_1_3(g[3][3],p[3][3],g[2][2],p[2][2],g[3][2],p[3][2]);
black_cell BlackCell_1_5(g[5][5],p[5][5],g[4][4],p[4][4],g[5][4],p[5][4]);
black_cell BlackCell_1_7(g[7][7],p[7][7],g[6][6],p[6][6],g[7][6],p[7][6]);
/// Level 2:
gray_cell grayCell_2_2(g[2][2],p[2][2],g[1][0],g[2][0]);
gray_cell grayCell_2_3(g[3][2],p[3][2],g[1][0],g[3][0]);
black_cell BlackCell_2_6(g[6][6],p[6][6],g[5][4],p[5][4],g[6][4],p[6][4]);
black_cell BlackCell_2_7(g[7][6],p[7][6],g[5][4],p[5][4],g[7][4],p[7][4]);
/// Level 3:
gray_cell GrayCell_3_4(g[4][4],p[4][4],g[3][0],g[4][0]);
gray_cell grayCell_3_5(g[5][4],p[5][4],g[3][0],g[5][0]);
gray_cell grayCell_3_6(g[6][4],p[6][4],g[3][0],g[6][0]);
gray_cell grayCell_3_7(g[7][4],p[7][4],g[3][0],g[7][0]);
/// Level 4: (if carry out needed)
/// gray cell_4_8(g[8][8],p[8][8],g[7][0],g[8][0]);
always @(posedge clock)
begin
if(reset_n == 1'b0)
begin
sum <= 8'b00000000;
end
else if(enable == 1'b1)
begin
sum[0] <= g[0][0]^p[1][1];
sum[1] <= g[1][0]^p[2][2];
sum[2] <= g[2][0]^p[3][3];
sum[3] <= g[3][0]^p[4][4];
sum[4] <= g[4][0]^p[5][5];
sum[5] <= g[5][0]^p[6][6];
sum[6] <= g[6][0]^p[7][7];
sum[7] <= g[7][0]^p[8][8];
end
end
endmodule
// Generate Propagate code
module generate_propagate(A,B,G,P);
input A,B;
output G,P;
assign G = A&B;
assign P = A^B;
endmodule
// Gray module code
module gray_cell(G4_3,P4_3,G2_2,G4_2);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
// Black module code
module black_cell(G6_8,P6_8,G7_10,P7_10,G6_10,P6_10);
input G6_8,P6_8,G7_10,P7_10;
output G6_10,P6_10;
wire signal;
assign signal = P6_8 & G7_10;
assign G6_10=signal | G6_8;
assign P6_10=P6_8 & P7_10;
endmodule
|
module gray_cell(G4_3,P4_3,G2_2,G4_2);
input G4_3,P4_3,G2_2;
output G4_2;
wire signal;
assign signal = P4_3 & G2_2;
assign G4_2=signal | G4_3;
endmodule
|
tt06-finale_0063
|
tt06-finale
|
drburke3-SADdiff_v1
|
task_sklansky_adder_8bit
|
tt_um_drburke3_top
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Daniel Burke
* SPDX-License-Identifier: Apache-2.0
*/
`timescale 1ns / 1ps
`default_nettype none
module tt_um_drburke3_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
/// assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in
assign uio_out = 0;
assign uio_oe = 0;
sklansky_adder_8bit diff_1(
.a (ui_in[7:0]), // input a
.sum (uo_out[7:0]), // addition out
.b (uio_in[7:0]), // input b
.enable (ena), // will go high when the design is enabled
.clock (clk), // clock
.reset_n (rst_n) // reset
);
endmodule
//////////////////////////////////////////////////////////////////////////////////
// Company: Berkeley Neuromorphic
// Engineer: Daniel Burke
//
// Create Date: 09/14/2022 10:16:27 AM
// Design Name:
// Module Name: sklansky_adder_8bit
// Project Name:
// Target Devices:
// Tool Versions:
// Description: 8-bit generated fast adder with black, gray, and generate-propagate included at bottom
// naming changed, truncated at 8-bits, and 'multiple packed array wires' error fixed.
//
// Dependencies: self-contained
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// from fluffybird2323 generator
// https://github.com/fluffybird2323/n-bit-sklansky-adder-code-generator-notebook/blob/master/README.Black
//////////////////////////////////////////////////////////////////////////////////
/* Generated 8 bit sklansky adder
In this adder, binary tree of propagate and generate
cells will first simultaneously generate all the carries, Cin.
It builds recursively 2-bit adders then 4-bit adders, 8-bit adders,
16-bit adder and so on by abutting each time two smaller adders.
*/
module sklansky_adder_8bit(a,b,sum,enable,clock,reset_n);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
// Generate Propagate code
module generate_propagate(A,B,G,P);
input A,B;
output G,P;
assign G = A&B;
assign P = A^B;
endmodule
// Gray module code
module gray_cell(G4_3,P4_3,G2_2,G4_2);
input G4_3,P4_3,G2_2;
output G4_2;
wire signal;
assign signal = P4_3 & G2_2;
assign G4_2=signal | G4_3;
endmodule
// Black module code
module black_cell(G6_8,P6_8,G7_10,P7_10,G6_10,P6_10);
input G6_8,P6_8,G7_10,P7_10;
output G6_10,P6_10;
wire signal;
assign signal = P6_8 & G7_10;
assign G6_10=signal | G6_8;
assign P6_10=P6_8 & P7_10;
endmodule
|
module sklansky_adder_8bit(a,b,sum,enable,clock,reset_n);
input [7:0] a;
input [7:0] b;
output reg [7:0] sum;
input enable;
input clock;
input reset_n;
// declare array wires
wire [8:0] g [8:0];
wire [8:0] p [8:0];
assign g[0][0]=1'b0;
assign p[0][0]=1'b0;
generate_propagate GeneratePropagate_00(a[0],b[0],g[1][1],p[1][1]);
generate_propagate GeneratePropagate_01(a[1],b[1],g[2][2],p[2][2]);
generate_propagate GeneratePropagate_02(a[2],b[2],g[3][3],p[3][3]);
generate_propagate GeneratePropagate_03(a[3],b[3],g[4][4],p[4][4]);
generate_propagate GeneratePropagate_04(a[4],b[4],g[5][5],p[5][5]);
generate_propagate GeneratePropagate_05(a[5],b[5],g[6][6],p[6][6]);
generate_propagate GeneratePropagate_06(a[6],b[6],g[7][7],p[7][7]);
generate_propagate GeneratePropagate_07(a[7],b[7],g[8][8],p[8][8]);
/// nomenclature is first number is clock level (1 is highest)
/// nomenclature is second number is bit position (0 is rightmost)
/// Level 1:
gray_cell GrayCell_1_1(g[1][1],p[1][1],g[0][0],g[1][0]);
black_cell BlackCell_1_3(g[3][3],p[3][3],g[2][2],p[2][2],g[3][2],p[3][2]);
black_cell BlackCell_1_5(g[5][5],p[5][5],g[4][4],p[4][4],g[5][4],p[5][4]);
black_cell BlackCell_1_7(g[7][7],p[7][7],g[6][6],p[6][6],g[7][6],p[7][6]);
/// Level 2:
gray_cell grayCell_2_2(g[2][2],p[2][2],g[1][0],g[2][0]);
gray_cell grayCell_2_3(g[3][2],p[3][2],g[1][0],g[3][0]);
black_cell BlackCell_2_6(g[6][6],p[6][6],g[5][4],p[5][4],g[6][4],p[6][4]);
black_cell BlackCell_2_7(g[7][6],p[7][6],g[5][4],p[5][4],g[7][4],p[7][4]);
/// Level 3:
gray_cell GrayCell_3_4(g[4][4],p[4][4],g[3][0],g[4][0]);
gray_cell grayCell_3_5(g[5][4],p[5][4],g[3][0],g[5][0]);
gray_cell grayCell_3_6(g[6][4],p[6][4],g[3][0],g[6][0]);
gray_cell grayCell_3_7(g[7][4],p[7][4],g[3][0],g[7][0]);
/// Level 4: (if carry out needed)
/// gray cell_4_8(g[8][8],p[8][8],g[7][0],g[8][0]);
always @(posedge clock)
begin
if(reset_n == 1'b0)
begin
sum <= 8'b00000000;
end
else if(enable == 1'b1)
begin
sum[0] <= g[0][0]^p[1][1];
sum[1] <= g[1][0]^p[2][2];
sum[2] <= g[2][0]^p[3][3];
sum[3] <= g[3][0]^p[4][4];
sum[4] <= g[4][0]^p[5][5];
sum[5] <= g[5][0]^p[6][6];
sum[6] <= g[6][0]^p[7][7];
sum[7] <= g[7][0]^p[8][8];
end
end
endmodule
|
tt06-finale_0064
|
tt06-finale
|
existential-ai-izhekevich_neuron
|
task_signed_mult
|
tt_um_exai_izhikevich_neuron
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Dmitri Lyalikov
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
/**
| Behavior | A | B | C | D |
| --------------------------- | --- | ---- | --- | --- |
0| RS (Regular Spiking) | .02 | .02 | -65 | 8 |
1| IB (Intrinsically Bursting) | .02 | .02 | -55 | 4 |
2| CH (Chattering) | .02 | .02 | -50 | 2 |
3| FS (Fast Spiking) | 0.1 | 0.2 | -65 | 2 |
4| TC (Thalamo-Cortical) | .02 | 0.25 | -65 | .05 |
5| RZ (Resonator) | 0.1 | 0.25 | -65 | 2 |
6| LTS (Low Threshold Spiking) | .02 | 0.25 | -65 | 2 |
*/
// Top Level Module
module tt_um_exai_izhikevich_neuron (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
assign uio_out = uio_in; // We do not use second output pin, assign so Verilator doesn't yell at us
assign uio_oe = 0; // Config uio_in output enable to 0: Input mode
reg [3:0] a, b;
reg signed [17:0] v1, u1;
wire signed [17:0] u1reset, v1new, u1new, du1;
wire signed [17:0] v1xv1, v1xb;
wire signed [17:0] p, c14;
reg signed [17:0] c, d;
wire signed [17:0] I; // uio_in[3:0];
assign p = 18'sh0_4CCC; // 30
assign c14 = 18'sh1_6666; // 1.4
// 8-bit signed integer precision of input current
assign I = {1'b0, ui_in[4:0], 12'h0};
// Update logic
always @ (posedge clk)
begin
if (!rst_n) // Reset state
begin
v1 <= 18'sh3_4CCD; // -0.7v
u1 <= 18'sh3_CCCD; // -0.2
a <= 1; // .02
b <= 1; // .02
c <= 18'sh3_A666; // -.065
d <= 18'sh0_147A; // .08
// Switch case for different neuron types
case (uio_in[2:0])
// RS (Regular Spiking) a = 0.02, b = 0.02, c = -.065, d = .08
3'b000: begin
a <= 1; // .02
b <= 1; // .02
c <= 18'sh3_A666; // -.065
d <= 18'sh0_147A; // .08
end
// IB (Intrinsically Bursting) a = 0.02, b = 0.02, c = -.055, d = .04
3'b001: begin
a <= 1; // .02
b <= 1; // .02
c <= 18'sh3_8CCC; // -.055
d <= 18'sh0_0A3D; // .04
end
// CH (Chattering) a = 0.02, b = 0.02, c = -.050, d = .02
3'b010: begin
a <= 1; // .02
b <= 1; // .02
c <= 18'sh3_8000; // -.050
d <= 18'sh0_051E; // .02
end
// FS (Fast Spiking) a = 0.1, b = 0.2, c = -.065, d = .02
3'b011: begin
a <= 2; // .1
b <= 4; // .2
c <= 18'sh3_A666; // -.065
d <= 18'sh0_051E; // .02
end
// TC (Thalamo-Cortical) a = 0.02, b = 0.25, c = -.065, d = .05
3'b100: begin
a <= 1; // .02
b <= 4; // .25
c <= 18'sh3_A666; // -.065
d <= 18'sh0_0020; // .05
end
// RZ (Resonator) a = 0.1, b = 0.25, c = -.065, d = .02
3'b101: begin
a <= 2; // .1
b <= 4; // .25
c <= 18'sh3_A666; // -.065
d <= 18'sh0_051E; // .02
end
// LTS (Low Threshold Spiking) a = 0.02, b = 0.25, c = -.065, d = .02
3'b110: begin
a <= 1; // .02
b <= 4; // .25
c <= 18'sh3_A666; // -.065
d <= 18'sh0_051E; // .02
end
3'b111: begin
a <= {uio_in[3], ui_in[7:5]};
b <= uio_in[7:4];
end
default: begin
a <= 1; // .02
b <= 1; // .02
c <= 18'sh3_A666; // -.065
d <= 18'sh0_147A; // .08
end
endcase
end
else
if (ena)
begin
if ((v1 > p)) // This is a spike above threshold (30mv)
begin
v1 <= c;
u1 <= u1reset;
end
else
begin
v1 <= v1new;
u1 <= u1new;
end
end
end
// Push out signed 8-bit integer to output pin (membrane voltage)
assign uo_out = v1[17:10];
// v1(n+1) = v1(n) + (v1(n)^2) + 5/4*v1(n) +1.40/4 - u1(n)/4 + I/4)/4
signed_mult v1sq(v1xv1, v1, v1);
assign v1new = v1 + ((v1xv1 + v1+(v1>>>2) + (c14>>>2) - (u1>>>2) + (I>>>2))>>>2);
// u1(n+1) = u1 + dt*a*(b*v1(n) - u1(n))
assign v1xb = v1>>>b; //mult (v1xb, v1, b);
assign du1 = (v1xb-u1)>>>a ; //mult (du1, (v1xb-u1), a);
assign u1new = u1 + (du1>>>4) ;
assign u1reset = u1 + d ;
endmodule
// signed mult of 2.16 format 2'comp
module signed_mult (out, a, b);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
|
module signed_mult (out, a, b);
output [17:0] out;
input signed [17:0] a;
input signed [17:0] b;
wire signed [17:0] out;
/* verilator lint_off UNUSEDSIGNAL */
wire signed [35:0] mult_out;
// Remove linter warning of unused bits
assign mult_out = a * b;
//assign out = mult_out[33:17];
assign out = {mult_out[35], mult_out[32:16]};
endmodule
|
tt06-finale_0065
|
tt06-finale
|
existential-ai-izhekevich_neuron
|
task_tt_um_exai_izhikevich_neuron
|
tt_um_exai_izhikevich_neuron
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Dmitri Lyalikov
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
/**
| Behavior | A | B | C | D |
| --------------------------- | --- | ---- | --- | --- |
0| RS (Regular Spiking) | .02 | .02 | -65 | 8 |
1| IB (Intrinsically Bursting) | .02 | .02 | -55 | 4 |
2| CH (Chattering) | .02 | .02 | -50 | 2 |
3| FS (Fast Spiking) | 0.1 | 0.2 | -65 | 2 |
4| TC (Thalamo-Cortical) | .02 | 0.25 | -65 | .05 |
5| RZ (Resonator) | 0.1 | 0.25 | -65 | 2 |
6| LTS (Low Threshold Spiking) | .02 | 0.25 | -65 | 2 |
*/
// Top Level Module
module tt_um_exai_izhikevich_neuron (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
// signed mult of 2.16 format 2'comp
module signed_mult (out, a, b);
output [17:0] out;
input signed [17:0] a;
input signed [17:0] b;
wire signed [17:0] out;
/* verilator lint_off UNUSEDSIGNAL */
wire signed [35:0] mult_out;
// Remove linter warning of unused bits
assign mult_out = a * b;
//assign out = mult_out[33:17];
assign out = {mult_out[35], mult_out[32:16]};
endmodule
|
module tt_um_exai_izhikevich_neuron (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
assign uio_out = uio_in; // We do not use second output pin, assign so Verilator doesn't yell at us
assign uio_oe = 0; // Config uio_in output enable to 0: Input mode
reg [3:0] a, b;
reg signed [17:0] v1, u1;
wire signed [17:0] u1reset, v1new, u1new, du1;
wire signed [17:0] v1xv1, v1xb;
wire signed [17:0] p, c14;
reg signed [17:0] c, d;
wire signed [17:0] I; // uio_in[3:0];
assign p = 18'sh0_4CCC; // 30
assign c14 = 18'sh1_6666; // 1.4
// 8-bit signed integer precision of input current
assign I = {1'b0, ui_in[4:0], 12'h0};
// Update logic
always @ (posedge clk)
begin
if (!rst_n) // Reset state
begin
v1 <= 18'sh3_4CCD; // -0.7v
u1 <= 18'sh3_CCCD; // -0.2
a <= 1; // .02
b <= 1; // .02
c <= 18'sh3_A666; // -.065
d <= 18'sh0_147A; // .08
// Switch case for different neuron types
case (uio_in[2:0])
// RS (Regular Spiking) a = 0.02, b = 0.02, c = -.065, d = .08
3'b000: begin
a <= 1; // .02
b <= 1; // .02
c <= 18'sh3_A666; // -.065
d <= 18'sh0_147A; // .08
end
// IB (Intrinsically Bursting) a = 0.02, b = 0.02, c = -.055, d = .04
3'b001: begin
a <= 1; // .02
b <= 1; // .02
c <= 18'sh3_8CCC; // -.055
d <= 18'sh0_0A3D; // .04
end
// CH (Chattering) a = 0.02, b = 0.02, c = -.050, d = .02
3'b010: begin
a <= 1; // .02
b <= 1; // .02
c <= 18'sh3_8000; // -.050
d <= 18'sh0_051E; // .02
end
// FS (Fast Spiking) a = 0.1, b = 0.2, c = -.065, d = .02
3'b011: begin
a <= 2; // .1
b <= 4; // .2
c <= 18'sh3_A666; // -.065
d <= 18'sh0_051E; // .02
end
// TC (Thalamo-Cortical) a = 0.02, b = 0.25, c = -.065, d = .05
3'b100: begin
a <= 1; // .02
b <= 4; // .25
c <= 18'sh3_A666; // -.065
d <= 18'sh0_0020; // .05
end
// RZ (Resonator) a = 0.1, b = 0.25, c = -.065, d = .02
3'b101: begin
a <= 2; // .1
b <= 4; // .25
c <= 18'sh3_A666; // -.065
d <= 18'sh0_051E; // .02
end
// LTS (Low Threshold Spiking) a = 0.02, b = 0.25, c = -.065, d = .02
3'b110: begin
a <= 1; // .02
b <= 4; // .25
c <= 18'sh3_A666; // -.065
d <= 18'sh0_051E; // .02
end
3'b111: begin
a <= {uio_in[3], ui_in[7:5]};
b <= uio_in[7:4];
end
default: begin
a <= 1; // .02
b <= 1; // .02
c <= 18'sh3_A666; // -.065
d <= 18'sh0_147A; // .08
end
endcase
end
else
if (ena)
begin
if ((v1 > p)) // This is a spike above threshold (30mv)
begin
v1 <= c;
u1 <= u1reset;
end
else
begin
v1 <= v1new;
u1 <= u1new;
end
end
end
// Push out signed 8-bit integer to output pin (membrane voltage)
assign uo_out = v1[17:10];
// v1(n+1) = v1(n) + (v1(n)^2) + 5/4*v1(n) +1.40/4 - u1(n)/4 + I/4)/4
signed_mult v1sq(v1xv1, v1, v1);
assign v1new = v1 + ((v1xv1 + v1+(v1>>>2) + (c14>>>2) - (u1>>>2) + (I>>>2))>>>2);
// u1(n+1) = u1 + dt*a*(b*v1(n) - u1(n))
assign v1xb = v1>>>b; //mult (v1xb, v1, b);
assign du1 = (v1xb-u1)>>>a ; //mult (du1, (v1xb-u1), a);
assign u1new = u1 + (du1>>>4) ;
assign u1reset = u1 + d ;
endmodule
|
tt06-finale_0066
|
tt06-finale
|
ignaciosim-tt06-triple-watchdog
|
task_tt_um_triple_watchdog
|
tt_um_triple_watchdog
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
`default_nettype none
`timescale 1ns/1ns
module tt_um_triple_watchdog (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
`default_nettype none
`timescale 1ns/1ns
module watchdog (
input wire clk, // Clock input
input wire rst_n, // Reset input
input wire [7:0] ui_in, // Dedicated inputs
output wire watchdog_expired // Watchdog expiration signal
);
// Parameters
parameter TIMEOUT_VALUE = 100000; // Timeout value (in clock cycles)
// Internal signals
reg [7:0] ui_in_reg;
reg [31:0] counter;
reg [1:0] state;
// Watchdog states
parameter IDLE = 2'b00;
parameter ACTIVE = 2'b01;
// Watchdog expiration flag
reg expired;
// Watchdog expiration detection logic
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
counter <= 0;
state <= IDLE;
expired <= 0;
ui_in_reg<=0;
end else begin
case (state)
IDLE: begin
if (ui_in != ui_in_reg) begin
state <= ACTIVE;
expired <= 0;
counter <= 0;
ui_in_reg <= ui_in;
end
end
ACTIVE: begin
if (ui_in == ui_in_reg) begin
counter <= counter + 1;
if (counter == TIMEOUT_VALUE) begin
expired <= 1;
state<=IDLE;
end
end else begin
counter <= 0;
state <= IDLE;
end
end
endcase
end
end
// Output expiration signal when expired
assign watchdog_expired = expired;
endmodule
|
module tt_um_triple_watchdog (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// Instantiate three watchdog instances
watchdog watchdog1(
.clk(clk),
.rst_n(rst_n),
.ui_in(ui_in),
.watchdog_expired(uo_out[0])
);
watchdog watchdog2(
.clk(clk),
.rst_n(rst_n),
.ui_in(ui_in),
.watchdog_expired(uo_out[1])
);
watchdog watchdog3(
.clk(clk),
.rst_n(rst_n),
.ui_in(ui_in),
.watchdog_expired(uo_out[2])
);
assign uo_out[7:3] = 0; // Clear undriven bits while preserving driven bits
assign uio_out=0;
assign uio_oe=0;
endmodule
|
tt06-finale_0067
|
tt06-finale
|
ignaciosim-tt06-triple-watchdog
|
task_watchdog
|
tt_um_triple_watchdog
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
`default_nettype none
`timescale 1ns/1ns
module tt_um_triple_watchdog (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// Instantiate three watchdog instances
watchdog watchdog1(
.clk(clk),
.rst_n(rst_n),
.ui_in(ui_in),
.watchdog_expired(uo_out[0])
);
watchdog watchdog2(
.clk(clk),
.rst_n(rst_n),
.ui_in(ui_in),
.watchdog_expired(uo_out[1])
);
watchdog watchdog3(
.clk(clk),
.rst_n(rst_n),
.ui_in(ui_in),
.watchdog_expired(uo_out[2])
);
assign uo_out[7:3] = 0; // Clear undriven bits while preserving driven bits
assign uio_out=0;
assign uio_oe=0;
endmodule
`default_nettype none
`timescale 1ns/1ns
module watchdog (
input wire clk, // Clock input
input wire rst_n, // Reset input
input wire [7:0] ui_in, // Dedicated inputs
output wire watchdog_expired // Watchdog expiration signal
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
|
module watchdog (
input wire clk, // Clock input
input wire rst_n, // Reset input
input wire [7:0] ui_in, // Dedicated inputs
output wire watchdog_expired // Watchdog expiration signal
);
// Parameters
parameter TIMEOUT_VALUE = 100000; // Timeout value (in clock cycles)
// Internal signals
reg [7:0] ui_in_reg;
reg [31:0] counter;
reg [1:0] state;
// Watchdog states
parameter IDLE = 2'b00;
parameter ACTIVE = 2'b01;
// Watchdog expiration flag
reg expired;
// Watchdog expiration detection logic
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
counter <= 0;
state <= IDLE;
expired <= 0;
ui_in_reg<=0;
end else begin
case (state)
IDLE: begin
if (ui_in != ui_in_reg) begin
state <= ACTIVE;
expired <= 0;
counter <= 0;
ui_in_reg <= ui_in;
end
end
ACTIVE: begin
if (ui_in == ui_in_reg) begin
counter <= counter + 1;
if (counter == TIMEOUT_VALUE) begin
expired <= 1;
state<=IDLE;
end
end else begin
counter <= 0;
state <= IDLE;
end
end
endcase
end
end
// Output expiration signal when expired
assign watchdog_expired = expired;
endmodule
|
tt06-finale_0068
|
tt06-finale
|
jferrer08-latinpractice
|
task_RS232_TX
|
tt_um_topTDC
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_topTDC (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
//assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in
//assign uio_out = 0;
//assign uio_oe = 0;
topTDC U1 (.clk(clk), .stop(uio_in[7]), .reset(uio_in[6]), .tx(uio_out[1]), .eot(uio_out[0]));
assign uio_oe = 8'b00000011;
assign uio_out[7:2] = 6'b000000;
assign uo_out[7:0] = 8'b00000000;
endmodule
`timescale 1ns / 1ps
module topTDC(clk, stop, reset, tx, eot);
input clk;
input stop;
input reset;
//output [7:0] dato;
output tx,eot;
//estados
reg [2:0] estado, edo_futuro;
parameter s0 = 3'b000;
parameter s1 = 3'b001;
parameter s2 = 3'b010;
parameter s3 = 3'b011;
parameter s4 = 3'b100;
parameter s5 = 3'b101;
reg stc; //start de cuenta
reg stt; //stt para bloque transmisor
wire [7:0] aux;
reg [7:0] temp;
reg bandera;
contadorTDC contador(.start(stc), .clk(clk), .cuenta(aux));
RS232_TX transmisor(.D(temp), .reset(reset), .EOT(eot), .clk(clk), .STT(stt), .TX(tx));
//cambio de estados
always @(posedge clk)
begin
if (reset)
estado <= s0;
else
estado <= edo_futuro;
end
///
always @(*)
begin
case (estado)
s0:
begin
if (stop)
begin
edo_futuro = s1;
stc = 1'b1;
bandera = 1'b0;
stt = 1'b0;
end
else
begin
edo_futuro = s0;
stc = 1'b0;
bandera = 1'b0;
stt = 1'b0;
end
end
s1:
begin
if (stop)
begin
edo_futuro = s1;
stc = 1'b1; //inicio cuenta
bandera = 1'b0;
stt = 1'b0;
end
else
begin
edo_futuro = s2;
stc = 1'b0;
bandera = 1'b1; //almaceno cuenta en variable aux
stt = 1'b0;
end
end
s2:
begin
edo_futuro = s3;
stc = 1'b0; //termino cuenta
stt = 1'b1; //inicio transmision
bandera = 1'b0;
end
s3:
begin
edo_futuro = s4;
stc = 1'b0; //termino cuenta
bandera = 1'b0;
stt = 1'b0;
end
s4:
begin
edo_futuro = s5;
stt = 1'b0; //terminimo transmision
stc = 1'b0; //termino cuenta
bandera = 1'b0;
end
s5:
begin
stt = 1'b0;
if (eot==1'b1)
begin
edo_futuro = s0;
bandera = 1'b0;
stc = 1'b0; //termino cuenta
end
else
begin
edo_futuro = s5;
bandera = 1'b0;
stc = 1'b0; //termino cuenta
end
end
endcase
end
always @(posedge clk)
begin
if(bandera == 1'b1)
temp <= aux;
else
temp <= temp;
end
//assign dato = temp;
endmodule
`timescale 1ns / 1ps
module contadorTDC(start, clk, cuenta);
input start;
input clk;
output reg [7:0] cuenta;
reg [7:0] q;
always @(posedge clk, negedge start)
begin
if (start == 0)
q <= 0;
else
q <= q + 1'b1;
end
always @(posedge clk)
begin
cuenta <= q;
end
endmodule
`timescale 1ns / 1ps
module RS232_TX(D, reset, clk, EOT, STT, TX);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
|
module RS232_TX(D, reset, clk, EOT, STT, TX);
parameter BaudRate=9600;
parameter reloj=50000000;
parameter conta=reloj/BaudRate;
input clk,reset,STT;
input [7:0] D;
output reg TX, EOT;
reg B,enable; //Pulso Buad Rate emisor
reg [12:0] k;
reg [3:0] estado, nex_estado,M;
reg [7:0] Dreg;
wire P;
always @(estado)
begin
if(estado == 0) begin EOT<=1'b1; M<=4'b0000; enable<=1'b0; end
else if(estado == 1) begin EOT<=1'b0; M<=4'b0001; enable<=1'b1; end
else if(estado == 2) begin EOT<=1'b0; M<=4'b0010; enable<=1'b1; end
else if(estado == 3) begin EOT<=1'b0; M<=4'b0011; enable<=1'b1; end
else if(estado == 4) begin EOT<=1'b0; M<=4'b0100; enable<=1'b1; end
else if(estado == 5) begin EOT<=1'b0; M<=4'b0101; enable<=1'b1; end
else if(estado == 6) begin EOT<=1'b0; M<=4'b0110; enable<=1'b1; end
else if(estado == 7) begin EOT<=1'b0; M<=4'b0111; enable<=1'b1; end
else if(estado == 8) begin EOT<=1'b0; M<=4'b1000; enable<=1'b1; end
else if(estado == 9) begin EOT<=1'b0; M<=4'b1001; enable<=1'b1; end
else if(estado == 10) begin EOT<=1'b0; M<=4'b1010; enable<=1'b1; end
else if(estado == 11) begin EOT<=1'b0; M<=4'b0000; enable<=1'b1; end
else begin EOT<=1'b1; M<=4'b0000; enable<=1'b0; end
end
always @(M,Dreg,P)
begin
case (M)
4'b0000: TX<=1'b1;
4'b0001: TX<=1'b0;
4'b0010: TX<=Dreg[0];
4'b0011: TX<=Dreg[1];
4'b0100: TX<=Dreg[2];
4'b0101: TX<=Dreg[3];
4'b0110: TX<=Dreg[4];
4'b0111: TX<=Dreg[5];
4'b1000: TX<=Dreg[6];
4'b1001: TX<=Dreg[7];
4'b1010: TX<=P;
default: TX<=1'b1;
endcase
end
always @(posedge clk) // generación de la señal Baudio
begin
if (enable==1'b1)
begin
if (k>=(conta-1))
begin
k<=0;
B<=1'b1;
end
else
begin
k<=k+1'b1;
B<=1'b0;
end
end
else
begin
k<=0;
B<=0;
end
end
assign P=~(Dreg[0]^Dreg[1]^Dreg[2]^Dreg[3]^Dreg[4]^Dreg[5]^Dreg[6]^Dreg[7]);
always @(posedge clk, posedge reset)
begin
if (reset)
estado<=0;
else
estado<=nex_estado;
end
always @(posedge clk, posedge reset)
begin
if (reset)
Dreg<=0;
else if (estado==1)
Dreg<=D;
else
Dreg<=Dreg;
end
always @(estado or STT or B)
begin
case (estado)
0: begin
if (STT) nex_estado<=1; else nex_estado<=0;
end
1: begin
if (B) nex_estado<=2; else nex_estado<=1;
end
2: begin
if (B) nex_estado<=3; else nex_estado<=2;
end
3: begin
if (B) nex_estado<=4; else nex_estado<=3;
end
4: begin
if (B) nex_estado<=5; else nex_estado<=4;
end
5: begin
if (B) nex_estado<=6; else nex_estado<=5;
end
6: begin
if (B) nex_estado<=7; else nex_estado<=6;
end
7: begin
if (B) nex_estado<=8; else nex_estado<=7;
end
8: begin
if (B) nex_estado<=9; else nex_estado<=8;
end
9: begin
if (B) nex_estado<=10; else nex_estado<=9;
end
10: begin
if (B) nex_estado<=11; else nex_estado<=10;
end
11: begin
if (B) nex_estado<=0; else nex_estado<=11;
end
default: nex_estado<=0;
endcase
end
endmodule
|
tt06-finale_0069
|
tt06-finale
|
jferrer08-latinpractice
|
task_contadorTDC
|
tt_um_topTDC
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_topTDC (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
//assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in
//assign uio_out = 0;
//assign uio_oe = 0;
topTDC U1 (.clk(clk), .stop(uio_in[7]), .reset(uio_in[6]), .tx(uio_out[1]), .eot(uio_out[0]));
assign uio_oe = 8'b00000011;
assign uio_out[7:2] = 6'b000000;
assign uo_out[7:0] = 8'b00000000;
endmodule
`timescale 1ns / 1ps
module topTDC(clk, stop, reset, tx, eot);
input clk;
input stop;
input reset;
//output [7:0] dato;
output tx,eot;
//estados
reg [2:0] estado, edo_futuro;
parameter s0 = 3'b000;
parameter s1 = 3'b001;
parameter s2 = 3'b010;
parameter s3 = 3'b011;
parameter s4 = 3'b100;
parameter s5 = 3'b101;
reg stc; //start de cuenta
reg stt; //stt para bloque transmisor
wire [7:0] aux;
reg [7:0] temp;
reg bandera;
contadorTDC contador(.start(stc), .clk(clk), .cuenta(aux));
RS232_TX transmisor(.D(temp), .reset(reset), .EOT(eot), .clk(clk), .STT(stt), .TX(tx));
//cambio de estados
always @(posedge clk)
begin
if (reset)
estado <= s0;
else
estado <= edo_futuro;
end
///
always @(*)
begin
case (estado)
s0:
begin
if (stop)
begin
edo_futuro = s1;
stc = 1'b1;
bandera = 1'b0;
stt = 1'b0;
end
else
begin
edo_futuro = s0;
stc = 1'b0;
bandera = 1'b0;
stt = 1'b0;
end
end
s1:
begin
if (stop)
begin
edo_futuro = s1;
stc = 1'b1; //inicio cuenta
bandera = 1'b0;
stt = 1'b0;
end
else
begin
edo_futuro = s2;
stc = 1'b0;
bandera = 1'b1; //almaceno cuenta en variable aux
stt = 1'b0;
end
end
s2:
begin
edo_futuro = s3;
stc = 1'b0; //termino cuenta
stt = 1'b1; //inicio transmision
bandera = 1'b0;
end
s3:
begin
edo_futuro = s4;
stc = 1'b0; //termino cuenta
bandera = 1'b0;
stt = 1'b0;
end
s4:
begin
edo_futuro = s5;
stt = 1'b0; //terminimo transmision
stc = 1'b0; //termino cuenta
bandera = 1'b0;
end
s5:
begin
stt = 1'b0;
if (eot==1'b1)
begin
edo_futuro = s0;
bandera = 1'b0;
stc = 1'b0; //termino cuenta
end
else
begin
edo_futuro = s5;
bandera = 1'b0;
stc = 1'b0; //termino cuenta
end
end
endcase
end
always @(posedge clk)
begin
if(bandera == 1'b1)
temp <= aux;
else
temp <= temp;
end
//assign dato = temp;
endmodule
`timescale 1ns / 1ps
module contadorTDC(start, clk, cuenta);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
`timescale 1ns / 1ps
module RS232_TX(D, reset, clk, EOT, STT, TX);
parameter BaudRate=9600;
parameter reloj=50000000;
parameter conta=reloj/BaudRate;
input clk,reset,STT;
input [7:0] D;
output reg TX, EOT;
reg B,enable; //Pulso Buad Rate emisor
reg [12:0] k;
reg [3:0] estado, nex_estado,M;
reg [7:0] Dreg;
wire P;
always @(estado)
begin
if(estado == 0) begin EOT<=1'b1; M<=4'b0000; enable<=1'b0; end
else if(estado == 1) begin EOT<=1'b0; M<=4'b0001; enable<=1'b1; end
else if(estado == 2) begin EOT<=1'b0; M<=4'b0010; enable<=1'b1; end
else if(estado == 3) begin EOT<=1'b0; M<=4'b0011; enable<=1'b1; end
else if(estado == 4) begin EOT<=1'b0; M<=4'b0100; enable<=1'b1; end
else if(estado == 5) begin EOT<=1'b0; M<=4'b0101; enable<=1'b1; end
else if(estado == 6) begin EOT<=1'b0; M<=4'b0110; enable<=1'b1; end
else if(estado == 7) begin EOT<=1'b0; M<=4'b0111; enable<=1'b1; end
else if(estado == 8) begin EOT<=1'b0; M<=4'b1000; enable<=1'b1; end
else if(estado == 9) begin EOT<=1'b0; M<=4'b1001; enable<=1'b1; end
else if(estado == 10) begin EOT<=1'b0; M<=4'b1010; enable<=1'b1; end
else if(estado == 11) begin EOT<=1'b0; M<=4'b0000; enable<=1'b1; end
else begin EOT<=1'b1; M<=4'b0000; enable<=1'b0; end
end
always @(M,Dreg,P)
begin
case (M)
4'b0000: TX<=1'b1;
4'b0001: TX<=1'b0;
4'b0010: TX<=Dreg[0];
4'b0011: TX<=Dreg[1];
4'b0100: TX<=Dreg[2];
4'b0101: TX<=Dreg[3];
4'b0110: TX<=Dreg[4];
4'b0111: TX<=Dreg[5];
4'b1000: TX<=Dreg[6];
4'b1001: TX<=Dreg[7];
4'b1010: TX<=P;
default: TX<=1'b1;
endcase
end
always @(posedge clk) // generación de la señal Baudio
begin
if (enable==1'b1)
begin
if (k>=(conta-1))
begin
k<=0;
B<=1'b1;
end
else
begin
k<=k+1'b1;
B<=1'b0;
end
end
else
begin
k<=0;
B<=0;
end
end
assign P=~(Dreg[0]^Dreg[1]^Dreg[2]^Dreg[3]^Dreg[4]^Dreg[5]^Dreg[6]^Dreg[7]);
always @(posedge clk, posedge reset)
begin
if (reset)
estado<=0;
else
estado<=nex_estado;
end
always @(posedge clk, posedge reset)
begin
if (reset)
Dreg<=0;
else if (estado==1)
Dreg<=D;
else
Dreg<=Dreg;
end
always @(estado or STT or B)
begin
case (estado)
0: begin
if (STT) nex_estado<=1; else nex_estado<=0;
end
1: begin
if (B) nex_estado<=2; else nex_estado<=1;
end
2: begin
if (B) nex_estado<=3; else nex_estado<=2;
end
3: begin
if (B) nex_estado<=4; else nex_estado<=3;
end
4: begin
if (B) nex_estado<=5; else nex_estado<=4;
end
5: begin
if (B) nex_estado<=6; else nex_estado<=5;
end
6: begin
if (B) nex_estado<=7; else nex_estado<=6;
end
7: begin
if (B) nex_estado<=8; else nex_estado<=7;
end
8: begin
if (B) nex_estado<=9; else nex_estado<=8;
end
9: begin
if (B) nex_estado<=10; else nex_estado<=9;
end
10: begin
if (B) nex_estado<=11; else nex_estado<=10;
end
11: begin
if (B) nex_estado<=0; else nex_estado<=11;
end
default: nex_estado<=0;
endcase
end
endmodule
|
module contadorTDC(start, clk, cuenta);
input start;
input clk;
output reg [7:0] cuenta;
reg [7:0] q;
always @(posedge clk, negedge start)
begin
if (start == 0)
q <= 0;
else
q <= q + 1'b1;
end
always @(posedge clk)
begin
cuenta <= q;
end
endmodule
|
tt06-finale_0070
|
tt06-finale
|
jferrer08-latinpractice
|
task_topTDC
|
tt_um_topTDC
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_topTDC (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
//assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in
//assign uio_out = 0;
//assign uio_oe = 0;
topTDC U1 (.clk(clk), .stop(uio_in[7]), .reset(uio_in[6]), .tx(uio_out[1]), .eot(uio_out[0]));
assign uio_oe = 8'b00000011;
assign uio_out[7:2] = 6'b000000;
assign uo_out[7:0] = 8'b00000000;
endmodule
`timescale 1ns / 1ps
module topTDC(clk, stop, reset, tx, eot);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
`timescale 1ns / 1ps
module contadorTDC(start, clk, cuenta);
input start;
input clk;
output reg [7:0] cuenta;
reg [7:0] q;
always @(posedge clk, negedge start)
begin
if (start == 0)
q <= 0;
else
q <= q + 1'b1;
end
always @(posedge clk)
begin
cuenta <= q;
end
endmodule
`timescale 1ns / 1ps
module RS232_TX(D, reset, clk, EOT, STT, TX);
parameter BaudRate=9600;
parameter reloj=50000000;
parameter conta=reloj/BaudRate;
input clk,reset,STT;
input [7:0] D;
output reg TX, EOT;
reg B,enable; //Pulso Buad Rate emisor
reg [12:0] k;
reg [3:0] estado, nex_estado,M;
reg [7:0] Dreg;
wire P;
always @(estado)
begin
if(estado == 0) begin EOT<=1'b1; M<=4'b0000; enable<=1'b0; end
else if(estado == 1) begin EOT<=1'b0; M<=4'b0001; enable<=1'b1; end
else if(estado == 2) begin EOT<=1'b0; M<=4'b0010; enable<=1'b1; end
else if(estado == 3) begin EOT<=1'b0; M<=4'b0011; enable<=1'b1; end
else if(estado == 4) begin EOT<=1'b0; M<=4'b0100; enable<=1'b1; end
else if(estado == 5) begin EOT<=1'b0; M<=4'b0101; enable<=1'b1; end
else if(estado == 6) begin EOT<=1'b0; M<=4'b0110; enable<=1'b1; end
else if(estado == 7) begin EOT<=1'b0; M<=4'b0111; enable<=1'b1; end
else if(estado == 8) begin EOT<=1'b0; M<=4'b1000; enable<=1'b1; end
else if(estado == 9) begin EOT<=1'b0; M<=4'b1001; enable<=1'b1; end
else if(estado == 10) begin EOT<=1'b0; M<=4'b1010; enable<=1'b1; end
else if(estado == 11) begin EOT<=1'b0; M<=4'b0000; enable<=1'b1; end
else begin EOT<=1'b1; M<=4'b0000; enable<=1'b0; end
end
always @(M,Dreg,P)
begin
case (M)
4'b0000: TX<=1'b1;
4'b0001: TX<=1'b0;
4'b0010: TX<=Dreg[0];
4'b0011: TX<=Dreg[1];
4'b0100: TX<=Dreg[2];
4'b0101: TX<=Dreg[3];
4'b0110: TX<=Dreg[4];
4'b0111: TX<=Dreg[5];
4'b1000: TX<=Dreg[6];
4'b1001: TX<=Dreg[7];
4'b1010: TX<=P;
default: TX<=1'b1;
endcase
end
always @(posedge clk) // generación de la señal Baudio
begin
if (enable==1'b1)
begin
if (k>=(conta-1))
begin
k<=0;
B<=1'b1;
end
else
begin
k<=k+1'b1;
B<=1'b0;
end
end
else
begin
k<=0;
B<=0;
end
end
assign P=~(Dreg[0]^Dreg[1]^Dreg[2]^Dreg[3]^Dreg[4]^Dreg[5]^Dreg[6]^Dreg[7]);
always @(posedge clk, posedge reset)
begin
if (reset)
estado<=0;
else
estado<=nex_estado;
end
always @(posedge clk, posedge reset)
begin
if (reset)
Dreg<=0;
else if (estado==1)
Dreg<=D;
else
Dreg<=Dreg;
end
always @(estado or STT or B)
begin
case (estado)
0: begin
if (STT) nex_estado<=1; else nex_estado<=0;
end
1: begin
if (B) nex_estado<=2; else nex_estado<=1;
end
2: begin
if (B) nex_estado<=3; else nex_estado<=2;
end
3: begin
if (B) nex_estado<=4; else nex_estado<=3;
end
4: begin
if (B) nex_estado<=5; else nex_estado<=4;
end
5: begin
if (B) nex_estado<=6; else nex_estado<=5;
end
6: begin
if (B) nex_estado<=7; else nex_estado<=6;
end
7: begin
if (B) nex_estado<=8; else nex_estado<=7;
end
8: begin
if (B) nex_estado<=9; else nex_estado<=8;
end
9: begin
if (B) nex_estado<=10; else nex_estado<=9;
end
10: begin
if (B) nex_estado<=11; else nex_estado<=10;
end
11: begin
if (B) nex_estado<=0; else nex_estado<=11;
end
default: nex_estado<=0;
endcase
end
endmodule
|
module topTDC(clk, stop, reset, tx, eot);
input clk;
input stop;
input reset;
//output [7:0] dato;
output tx,eot;
//estados
reg [2:0] estado, edo_futuro;
parameter s0 = 3'b000;
parameter s1 = 3'b001;
parameter s2 = 3'b010;
parameter s3 = 3'b011;
parameter s4 = 3'b100;
parameter s5 = 3'b101;
reg stc; //start de cuenta
reg stt; //stt para bloque transmisor
wire [7:0] aux;
reg [7:0] temp;
reg bandera;
contadorTDC contador(.start(stc), .clk(clk), .cuenta(aux));
RS232_TX transmisor(.D(temp), .reset(reset), .EOT(eot), .clk(clk), .STT(stt), .TX(tx));
//cambio de estados
always @(posedge clk)
begin
if (reset)
estado <= s0;
else
estado <= edo_futuro;
end
///
always @(*)
begin
case (estado)
s0:
begin
if (stop)
begin
edo_futuro = s1;
stc = 1'b1;
bandera = 1'b0;
stt = 1'b0;
end
else
begin
edo_futuro = s0;
stc = 1'b0;
bandera = 1'b0;
stt = 1'b0;
end
end
s1:
begin
if (stop)
begin
edo_futuro = s1;
stc = 1'b1; //inicio cuenta
bandera = 1'b0;
stt = 1'b0;
end
else
begin
edo_futuro = s2;
stc = 1'b0;
bandera = 1'b1; //almaceno cuenta en variable aux
stt = 1'b0;
end
end
s2:
begin
edo_futuro = s3;
stc = 1'b0; //termino cuenta
stt = 1'b1; //inicio transmision
bandera = 1'b0;
end
s3:
begin
edo_futuro = s4;
stc = 1'b0; //termino cuenta
bandera = 1'b0;
stt = 1'b0;
end
s4:
begin
edo_futuro = s5;
stt = 1'b0; //terminimo transmision
stc = 1'b0; //termino cuenta
bandera = 1'b0;
end
s5:
begin
stt = 1'b0;
if (eot==1'b1)
begin
edo_futuro = s0;
bandera = 1'b0;
stc = 1'b0; //termino cuenta
end
else
begin
edo_futuro = s5;
bandera = 1'b0;
stc = 1'b0; //termino cuenta
end
end
endcase
end
always @(posedge clk)
begin
if(bandera == 1'b1)
temp <= aux;
else
temp <= temp;
end
//assign dato = temp;
endmodule
|
tt06-finale_0071
|
tt06-finale
|
jferrer08-latinpractice
|
task_tt_um_topTDC
|
tt_um_topTDC
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_topTDC (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
`timescale 1ns / 1ps
module topTDC(clk, stop, reset, tx, eot);
input clk;
input stop;
input reset;
//output [7:0] dato;
output tx,eot;
//estados
reg [2:0] estado, edo_futuro;
parameter s0 = 3'b000;
parameter s1 = 3'b001;
parameter s2 = 3'b010;
parameter s3 = 3'b011;
parameter s4 = 3'b100;
parameter s5 = 3'b101;
reg stc; //start de cuenta
reg stt; //stt para bloque transmisor
wire [7:0] aux;
reg [7:0] temp;
reg bandera;
contadorTDC contador(.start(stc), .clk(clk), .cuenta(aux));
RS232_TX transmisor(.D(temp), .reset(reset), .EOT(eot), .clk(clk), .STT(stt), .TX(tx));
//cambio de estados
always @(posedge clk)
begin
if (reset)
estado <= s0;
else
estado <= edo_futuro;
end
///
always @(*)
begin
case (estado)
s0:
begin
if (stop)
begin
edo_futuro = s1;
stc = 1'b1;
bandera = 1'b0;
stt = 1'b0;
end
else
begin
edo_futuro = s0;
stc = 1'b0;
bandera = 1'b0;
stt = 1'b0;
end
end
s1:
begin
if (stop)
begin
edo_futuro = s1;
stc = 1'b1; //inicio cuenta
bandera = 1'b0;
stt = 1'b0;
end
else
begin
edo_futuro = s2;
stc = 1'b0;
bandera = 1'b1; //almaceno cuenta en variable aux
stt = 1'b0;
end
end
s2:
begin
edo_futuro = s3;
stc = 1'b0; //termino cuenta
stt = 1'b1; //inicio transmision
bandera = 1'b0;
end
s3:
begin
edo_futuro = s4;
stc = 1'b0; //termino cuenta
bandera = 1'b0;
stt = 1'b0;
end
s4:
begin
edo_futuro = s5;
stt = 1'b0; //terminimo transmision
stc = 1'b0; //termino cuenta
bandera = 1'b0;
end
s5:
begin
stt = 1'b0;
if (eot==1'b1)
begin
edo_futuro = s0;
bandera = 1'b0;
stc = 1'b0; //termino cuenta
end
else
begin
edo_futuro = s5;
bandera = 1'b0;
stc = 1'b0; //termino cuenta
end
end
endcase
end
always @(posedge clk)
begin
if(bandera == 1'b1)
temp <= aux;
else
temp <= temp;
end
//assign dato = temp;
endmodule
`timescale 1ns / 1ps
module contadorTDC(start, clk, cuenta);
input start;
input clk;
output reg [7:0] cuenta;
reg [7:0] q;
always @(posedge clk, negedge start)
begin
if (start == 0)
q <= 0;
else
q <= q + 1'b1;
end
always @(posedge clk)
begin
cuenta <= q;
end
endmodule
`timescale 1ns / 1ps
module RS232_TX(D, reset, clk, EOT, STT, TX);
parameter BaudRate=9600;
parameter reloj=50000000;
parameter conta=reloj/BaudRate;
input clk,reset,STT;
input [7:0] D;
output reg TX, EOT;
reg B,enable; //Pulso Buad Rate emisor
reg [12:0] k;
reg [3:0] estado, nex_estado,M;
reg [7:0] Dreg;
wire P;
always @(estado)
begin
if(estado == 0) begin EOT<=1'b1; M<=4'b0000; enable<=1'b0; end
else if(estado == 1) begin EOT<=1'b0; M<=4'b0001; enable<=1'b1; end
else if(estado == 2) begin EOT<=1'b0; M<=4'b0010; enable<=1'b1; end
else if(estado == 3) begin EOT<=1'b0; M<=4'b0011; enable<=1'b1; end
else if(estado == 4) begin EOT<=1'b0; M<=4'b0100; enable<=1'b1; end
else if(estado == 5) begin EOT<=1'b0; M<=4'b0101; enable<=1'b1; end
else if(estado == 6) begin EOT<=1'b0; M<=4'b0110; enable<=1'b1; end
else if(estado == 7) begin EOT<=1'b0; M<=4'b0111; enable<=1'b1; end
else if(estado == 8) begin EOT<=1'b0; M<=4'b1000; enable<=1'b1; end
else if(estado == 9) begin EOT<=1'b0; M<=4'b1001; enable<=1'b1; end
else if(estado == 10) begin EOT<=1'b0; M<=4'b1010; enable<=1'b1; end
else if(estado == 11) begin EOT<=1'b0; M<=4'b0000; enable<=1'b1; end
else begin EOT<=1'b1; M<=4'b0000; enable<=1'b0; end
end
always @(M,Dreg,P)
begin
case (M)
4'b0000: TX<=1'b1;
4'b0001: TX<=1'b0;
4'b0010: TX<=Dreg[0];
4'b0011: TX<=Dreg[1];
4'b0100: TX<=Dreg[2];
4'b0101: TX<=Dreg[3];
4'b0110: TX<=Dreg[4];
4'b0111: TX<=Dreg[5];
4'b1000: TX<=Dreg[6];
4'b1001: TX<=Dreg[7];
4'b1010: TX<=P;
default: TX<=1'b1;
endcase
end
always @(posedge clk) // generación de la señal Baudio
begin
if (enable==1'b1)
begin
if (k>=(conta-1))
begin
k<=0;
B<=1'b1;
end
else
begin
k<=k+1'b1;
B<=1'b0;
end
end
else
begin
k<=0;
B<=0;
end
end
assign P=~(Dreg[0]^Dreg[1]^Dreg[2]^Dreg[3]^Dreg[4]^Dreg[5]^Dreg[6]^Dreg[7]);
always @(posedge clk, posedge reset)
begin
if (reset)
estado<=0;
else
estado<=nex_estado;
end
always @(posedge clk, posedge reset)
begin
if (reset)
Dreg<=0;
else if (estado==1)
Dreg<=D;
else
Dreg<=Dreg;
end
always @(estado or STT or B)
begin
case (estado)
0: begin
if (STT) nex_estado<=1; else nex_estado<=0;
end
1: begin
if (B) nex_estado<=2; else nex_estado<=1;
end
2: begin
if (B) nex_estado<=3; else nex_estado<=2;
end
3: begin
if (B) nex_estado<=4; else nex_estado<=3;
end
4: begin
if (B) nex_estado<=5; else nex_estado<=4;
end
5: begin
if (B) nex_estado<=6; else nex_estado<=5;
end
6: begin
if (B) nex_estado<=7; else nex_estado<=6;
end
7: begin
if (B) nex_estado<=8; else nex_estado<=7;
end
8: begin
if (B) nex_estado<=9; else nex_estado<=8;
end
9: begin
if (B) nex_estado<=10; else nex_estado<=9;
end
10: begin
if (B) nex_estado<=11; else nex_estado<=10;
end
11: begin
if (B) nex_estado<=0; else nex_estado<=11;
end
default: nex_estado<=0;
endcase
end
endmodule
|
module tt_um_topTDC (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
//assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in
//assign uio_out = 0;
//assign uio_oe = 0;
topTDC U1 (.clk(clk), .stop(uio_in[7]), .reset(uio_in[6]), .tx(uio_out[1]), .eot(uio_out[0]));
assign uio_oe = 8'b00000011;
assign uio_out[7:2] = 6'b000000;
assign uo_out[7:0] = 8'b00000000;
endmodule
|
tt06-finale_0072
|
tt06-finale
|
mattvenn-tt06-ian-keypad-controller
|
task_decoder
|
tt_um_ian_keypad_controller
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_ian_keypad_controller (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
assign uio_out[7:6] = 0;
assign uio_oe = 8'b00111111;
assign uo_out[7] = 0;
wire reset = !rst_n;
wire [3:0] key;
// the keypad scanner
keypad keypad (
.clk(clk),
.reset(reset),
.rows(ui_in[3:0]), // input
.cols(uio_out[3:0]), // output
.counter_cols(uio_out[5:4]),
.key(key)
);
// the digit decoder
decoder decoder (
.key(key),
.segments(uo_out[6:0])
);
endmodule
`default_nettype none
module keypad(
input wire clk,
input wire reset,
input [3:0] rows, // inputs
output reg [3:0] cols, // outputs
output reg [1:0] counter_cols,
output reg [3:0] key
);
// Debounced Rows
// Instantiate the debounce module for each row
wire [3:0] debounced_rows; // Debounced signals for each row
debounce #(.HIST_LEN(8)) debounce_row0 (
.clk(clk),
.reset(reset),
.button(rows[0]),
.debounced(debounced_rows[0])
);
debounce #(.HIST_LEN(8)) debounce_row1 (
.clk(clk),
.reset(reset),
.button(rows[1]),
.debounced(debounced_rows[1])
);
debounce #(.HIST_LEN(8)) debounce_row2 (
.clk(clk),
.reset(reset),
.button(rows[2]),
.debounced(debounced_rows[2])
);
debounce #(.HIST_LEN(8)) debounce_row3 (
.clk(clk),
.reset(reset),
.button(rows[3]),
.debounced(debounced_rows[3])
);
// Drive power to cols
reg [4:0] col_update_count;
always @(posedge clk or posedge reset) begin
if(reset) begin
col_update_count <= 5'h0;
counter_cols <= 2'b00;
end else begin
col_update_count <= col_update_count + 1;
if (col_update_count == 5'h0)
counter_cols <= counter_cols + 1;
end
end
always @(*) begin
case(counter_cols)
2'b00: cols = 4'b0001;
2'b01: cols = 4'b0010;
2'b10: cols = 4'b0100;
2'b11: cols = 4'b1000;
default: cols = 4'b0000;
endcase
end
task match_one; begin $display("1 was clicked"); end endtask
task match_two; begin $display("2 was clicked"); end endtask
task match_three; begin $display("3 was clicked"); end endtask
task match_a; begin $display("A was clicked"); end endtask
task match_four; begin $display("4 was clicked"); end endtask
task match_five; begin $display("5 was clicked"); end endtask
task match_six; begin $display("6 was clicked"); end endtask
task match_b; begin $display("B was clicked"); end endtask
task match_seven; begin $display("7 was clicked"); end endtask
task match_eight; begin $display("8 was clicked"); end endtask
task match_nine; begin $display("9 was clicked"); end endtask
task match_c; begin $display("C was clicked"); end endtask
task match_star; begin $display("* was clicked"); end endtask
task match_zero; begin $display("0 was clicked"); end endtask
task match_hashtag; begin $display("# was clicked"); end endtask
task match_d; begin $display("D was clicked"); end endtask
always @(*) begin
key = 0;
if (cols == 4'b0001 && debounced_rows == 4'b0001) begin
key = 1;
end else if (cols == 4'b0001 && debounced_rows == 4'b0010) begin
key = 4;
end else if (cols == 4'b0001 && debounced_rows == 4'b0100) begin
key = 7;
end else if (cols == 4'b0001 && debounced_rows == 4'b1000) begin
key = 15;
end else if (cols == 4'b0010 && debounced_rows == 4'b0001) begin
key = 2;
end else if (cols == 4'b0010 && debounced_rows == 4'b0010) begin
key = 5;
end else if (cols == 4'b0010 && debounced_rows == 4'b0100) begin
key = 8;
end else if (cols == 4'b0010 && debounced_rows == 4'b1000) begin
key = 0;
end else if (cols == 4'b0100 && debounced_rows == 4'b0001) begin
key = 3;
end else if (cols == 4'b0100 && debounced_rows == 4'b0010) begin
key = 6;
end else if (cols == 4'b0100 && debounced_rows == 4'b0100) begin
key = 9;
end else if (cols == 4'b0100 && debounced_rows == 4'b1000) begin
key = 14;
end else if (cols == 4'b1000 && debounced_rows == 4'b0001) begin
key = 10;
end else if (cols == 4'b1000 && debounced_rows == 4'b0010) begin
key = 11;
end else if (cols == 4'b1000 && debounced_rows == 4'b0100) begin
key = 12;
end else if (cols == 4'b1000 && debounced_rows == 4'b1000) begin
key = 13;
end
end
endmodule
`default_nettype none
module debounce #(
parameter HIST_LEN = 8
)(
input wire clk,
input wire reset,
input wire button,
output reg debounced
);
localparam on_value = 2 ** HIST_LEN - 1;
reg [HIST_LEN-1:0] button_hist;
always @(posedge clk) begin
if(reset) begin
button_hist <= 0;
debounced <= 1'b0;
end else begin
button_hist <= {button_hist[HIST_LEN-2:0], button};
if(button_hist == on_value)
debounced <= 1'b1;
else if(button_hist == {HIST_LEN{1'b0}})
debounced <= 1'b0;
end
end
endmodule
`default_nettype none
module decoder(
input [3:0] key, // inputs
output reg [6:0] segments // outputs
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
|
module decoder(
input [3:0] key, // inputs
output reg [6:0] segments // outputs
);
always @(*) begin
case(key)
// 7654321
0: segments = 7'b0111111;
1: segments = 7'b0000110;
2: segments = 7'b1011011;
3: segments = 7'b1001111;
4: segments = 7'b1100110;
5: segments = 7'b1101101;
6: segments = 7'b1111100;
7: segments = 7'b0000111;
8: segments = 7'b1111111;
9: segments = 7'b1100111;
default:
segments = 7'b0000000;
endcase
end
endmodule
|
tt06-finale_0073
|
tt06-finale
|
mattvenn-tt06-ian-keypad-controller
|
task_keypad
|
tt_um_ian_keypad_controller
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_ian_keypad_controller (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
assign uio_out[7:6] = 0;
assign uio_oe = 8'b00111111;
assign uo_out[7] = 0;
wire reset = !rst_n;
wire [3:0] key;
// the keypad scanner
keypad keypad (
.clk(clk),
.reset(reset),
.rows(ui_in[3:0]), // input
.cols(uio_out[3:0]), // output
.counter_cols(uio_out[5:4]),
.key(key)
);
// the digit decoder
decoder decoder (
.key(key),
.segments(uo_out[6:0])
);
endmodule
`default_nettype none
module keypad(
input wire clk,
input wire reset,
input [3:0] rows, // inputs
output reg [3:0] cols, // outputs
output reg [1:0] counter_cols,
output reg [3:0] key
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
`default_nettype none
module debounce #(
parameter HIST_LEN = 8
)(
input wire clk,
input wire reset,
input wire button,
output reg debounced
);
localparam on_value = 2 ** HIST_LEN - 1;
reg [HIST_LEN-1:0] button_hist;
always @(posedge clk) begin
if(reset) begin
button_hist <= 0;
debounced <= 1'b0;
end else begin
button_hist <= {button_hist[HIST_LEN-2:0], button};
if(button_hist == on_value)
debounced <= 1'b1;
else if(button_hist == {HIST_LEN{1'b0}})
debounced <= 1'b0;
end
end
endmodule
`default_nettype none
module decoder(
input [3:0] key, // inputs
output reg [6:0] segments // outputs
);
always @(*) begin
case(key)
// 7654321
0: segments = 7'b0111111;
1: segments = 7'b0000110;
2: segments = 7'b1011011;
3: segments = 7'b1001111;
4: segments = 7'b1100110;
5: segments = 7'b1101101;
6: segments = 7'b1111100;
7: segments = 7'b0000111;
8: segments = 7'b1111111;
9: segments = 7'b1100111;
default:
segments = 7'b0000000;
endcase
end
endmodule
|
module keypad(
input wire clk,
input wire reset,
input [3:0] rows, // inputs
output reg [3:0] cols, // outputs
output reg [1:0] counter_cols,
output reg [3:0] key
);
// Debounced Rows
// Instantiate the debounce module for each row
wire [3:0] debounced_rows; // Debounced signals for each row
debounce #(.HIST_LEN(8)) debounce_row0 (
.clk(clk),
.reset(reset),
.button(rows[0]),
.debounced(debounced_rows[0])
);
debounce #(.HIST_LEN(8)) debounce_row1 (
.clk(clk),
.reset(reset),
.button(rows[1]),
.debounced(debounced_rows[1])
);
debounce #(.HIST_LEN(8)) debounce_row2 (
.clk(clk),
.reset(reset),
.button(rows[2]),
.debounced(debounced_rows[2])
);
debounce #(.HIST_LEN(8)) debounce_row3 (
.clk(clk),
.reset(reset),
.button(rows[3]),
.debounced(debounced_rows[3])
);
// Drive power to cols
reg [4:0] col_update_count;
always @(posedge clk or posedge reset) begin
if(reset) begin
col_update_count <= 5'h0;
counter_cols <= 2'b00;
end else begin
col_update_count <= col_update_count + 1;
if (col_update_count == 5'h0)
counter_cols <= counter_cols + 1;
end
end
always @(*) begin
case(counter_cols)
2'b00: cols = 4'b0001;
2'b01: cols = 4'b0010;
2'b10: cols = 4'b0100;
2'b11: cols = 4'b1000;
default: cols = 4'b0000;
endcase
end
task match_one; begin $display("1 was clicked"); end endtask
task match_two; begin $display("2 was clicked"); end endtask
task match_three; begin $display("3 was clicked"); end endtask
task match_a; begin $display("A was clicked"); end endtask
task match_four; begin $display("4 was clicked"); end endtask
task match_five; begin $display("5 was clicked"); end endtask
task match_six; begin $display("6 was clicked"); end endtask
task match_b; begin $display("B was clicked"); end endtask
task match_seven; begin $display("7 was clicked"); end endtask
task match_eight; begin $display("8 was clicked"); end endtask
task match_nine; begin $display("9 was clicked"); end endtask
task match_c; begin $display("C was clicked"); end endtask
task match_star; begin $display("* was clicked"); end endtask
task match_zero; begin $display("0 was clicked"); end endtask
task match_hashtag; begin $display("# was clicked"); end endtask
task match_d; begin $display("D was clicked"); end endtask
always @(*) begin
key = 0;
if (cols == 4'b0001 && debounced_rows == 4'b0001) begin
key = 1;
end else if (cols == 4'b0001 && debounced_rows == 4'b0010) begin
key = 4;
end else if (cols == 4'b0001 && debounced_rows == 4'b0100) begin
key = 7;
end else if (cols == 4'b0001 && debounced_rows == 4'b1000) begin
key = 15;
end else if (cols == 4'b0010 && debounced_rows == 4'b0001) begin
key = 2;
end else if (cols == 4'b0010 && debounced_rows == 4'b0010) begin
key = 5;
end else if (cols == 4'b0010 && debounced_rows == 4'b0100) begin
key = 8;
end else if (cols == 4'b0010 && debounced_rows == 4'b1000) begin
key = 0;
end else if (cols == 4'b0100 && debounced_rows == 4'b0001) begin
key = 3;
end else if (cols == 4'b0100 && debounced_rows == 4'b0010) begin
key = 6;
end else if (cols == 4'b0100 && debounced_rows == 4'b0100) begin
key = 9;
end else if (cols == 4'b0100 && debounced_rows == 4'b1000) begin
key = 14;
end else if (cols == 4'b1000 && debounced_rows == 4'b0001) begin
key = 10;
end else if (cols == 4'b1000 && debounced_rows == 4'b0010) begin
key = 11;
end else if (cols == 4'b1000 && debounced_rows == 4'b0100) begin
key = 12;
end else if (cols == 4'b1000 && debounced_rows == 4'b1000) begin
key = 13;
end
end
endmodule
|
tt06-finale_0074
|
tt06-finale
|
mattvenn-tt06-ian-keypad-controller
|
task_tt_um_ian_keypad_controller
|
tt_um_ian_keypad_controller
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_ian_keypad_controller (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
`default_nettype none
module keypad(
input wire clk,
input wire reset,
input [3:0] rows, // inputs
output reg [3:0] cols, // outputs
output reg [1:0] counter_cols,
output reg [3:0] key
);
// Debounced Rows
// Instantiate the debounce module for each row
wire [3:0] debounced_rows; // Debounced signals for each row
debounce #(.HIST_LEN(8)) debounce_row0 (
.clk(clk),
.reset(reset),
.button(rows[0]),
.debounced(debounced_rows[0])
);
debounce #(.HIST_LEN(8)) debounce_row1 (
.clk(clk),
.reset(reset),
.button(rows[1]),
.debounced(debounced_rows[1])
);
debounce #(.HIST_LEN(8)) debounce_row2 (
.clk(clk),
.reset(reset),
.button(rows[2]),
.debounced(debounced_rows[2])
);
debounce #(.HIST_LEN(8)) debounce_row3 (
.clk(clk),
.reset(reset),
.button(rows[3]),
.debounced(debounced_rows[3])
);
// Drive power to cols
reg [4:0] col_update_count;
always @(posedge clk or posedge reset) begin
if(reset) begin
col_update_count <= 5'h0;
counter_cols <= 2'b00;
end else begin
col_update_count <= col_update_count + 1;
if (col_update_count == 5'h0)
counter_cols <= counter_cols + 1;
end
end
always @(*) begin
case(counter_cols)
2'b00: cols = 4'b0001;
2'b01: cols = 4'b0010;
2'b10: cols = 4'b0100;
2'b11: cols = 4'b1000;
default: cols = 4'b0000;
endcase
end
task match_one; begin $display("1 was clicked"); end endtask
task match_two; begin $display("2 was clicked"); end endtask
task match_three; begin $display("3 was clicked"); end endtask
task match_a; begin $display("A was clicked"); end endtask
task match_four; begin $display("4 was clicked"); end endtask
task match_five; begin $display("5 was clicked"); end endtask
task match_six; begin $display("6 was clicked"); end endtask
task match_b; begin $display("B was clicked"); end endtask
task match_seven; begin $display("7 was clicked"); end endtask
task match_eight; begin $display("8 was clicked"); end endtask
task match_nine; begin $display("9 was clicked"); end endtask
task match_c; begin $display("C was clicked"); end endtask
task match_star; begin $display("* was clicked"); end endtask
task match_zero; begin $display("0 was clicked"); end endtask
task match_hashtag; begin $display("# was clicked"); end endtask
task match_d; begin $display("D was clicked"); end endtask
always @(*) begin
key = 0;
if (cols == 4'b0001 && debounced_rows == 4'b0001) begin
key = 1;
end else if (cols == 4'b0001 && debounced_rows == 4'b0010) begin
key = 4;
end else if (cols == 4'b0001 && debounced_rows == 4'b0100) begin
key = 7;
end else if (cols == 4'b0001 && debounced_rows == 4'b1000) begin
key = 15;
end else if (cols == 4'b0010 && debounced_rows == 4'b0001) begin
key = 2;
end else if (cols == 4'b0010 && debounced_rows == 4'b0010) begin
key = 5;
end else if (cols == 4'b0010 && debounced_rows == 4'b0100) begin
key = 8;
end else if (cols == 4'b0010 && debounced_rows == 4'b1000) begin
key = 0;
end else if (cols == 4'b0100 && debounced_rows == 4'b0001) begin
key = 3;
end else if (cols == 4'b0100 && debounced_rows == 4'b0010) begin
key = 6;
end else if (cols == 4'b0100 && debounced_rows == 4'b0100) begin
key = 9;
end else if (cols == 4'b0100 && debounced_rows == 4'b1000) begin
key = 14;
end else if (cols == 4'b1000 && debounced_rows == 4'b0001) begin
key = 10;
end else if (cols == 4'b1000 && debounced_rows == 4'b0010) begin
key = 11;
end else if (cols == 4'b1000 && debounced_rows == 4'b0100) begin
key = 12;
end else if (cols == 4'b1000 && debounced_rows == 4'b1000) begin
key = 13;
end
end
endmodule
`default_nettype none
module debounce #(
parameter HIST_LEN = 8
)(
input wire clk,
input wire reset,
input wire button,
output reg debounced
);
localparam on_value = 2 ** HIST_LEN - 1;
reg [HIST_LEN-1:0] button_hist;
always @(posedge clk) begin
if(reset) begin
button_hist <= 0;
debounced <= 1'b0;
end else begin
button_hist <= {button_hist[HIST_LEN-2:0], button};
if(button_hist == on_value)
debounced <= 1'b1;
else if(button_hist == {HIST_LEN{1'b0}})
debounced <= 1'b0;
end
end
endmodule
`default_nettype none
module decoder(
input [3:0] key, // inputs
output reg [6:0] segments // outputs
);
always @(*) begin
case(key)
// 7654321
0: segments = 7'b0111111;
1: segments = 7'b0000110;
2: segments = 7'b1011011;
3: segments = 7'b1001111;
4: segments = 7'b1100110;
5: segments = 7'b1101101;
6: segments = 7'b1111100;
7: segments = 7'b0000111;
8: segments = 7'b1111111;
9: segments = 7'b1100111;
default:
segments = 7'b0000000;
endcase
end
endmodule
|
module tt_um_ian_keypad_controller (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
assign uio_out[7:6] = 0;
assign uio_oe = 8'b00111111;
assign uo_out[7] = 0;
wire reset = !rst_n;
wire [3:0] key;
// the keypad scanner
keypad keypad (
.clk(clk),
.reset(reset),
.rows(ui_in[3:0]), // input
.cols(uio_out[3:0]), // output
.counter_cols(uio_out[5:4]),
.key(key)
);
// the digit decoder
decoder decoder (
.key(key),
.segments(uo_out[6:0])
);
endmodule
|
tt06-finale_0075
|
tt06-finale
|
mattvenn-tt06-rgb-mixer
|
task_rgb_mixer
|
tt_um_mattvenn_rgb_mixer
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_mattvenn_rgb_mixer (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
wire rst = ! rst_n;
assign uio_oe = 8'b1111_1111;
assign uo_out[7:3] = 5'b0_0000;
wire [7:0] enc0, enc1, enc2;
wire [1:0] debug_enc = ui_in[7:6];
assign uio_out = debug_enc == 0 ? enc0 :
debug_enc == 1 ? enc1 :
debug_enc == 2 ? enc2 :
0;
rgb_mixer rgb_mixer (
.clk(clk),
.reset(rst),
.enc0_a(ui_in[0]),
.enc0_b(ui_in[1]),
.enc1_a(ui_in[2]),
.enc1_b(ui_in[3]),
.enc2_a(ui_in[4]),
.enc2_b(ui_in[5]),
.pwm0_out(uo_out[0]),
.pwm1_out(uo_out[1]),
.pwm2_out(uo_out[2]),
// debug
.enc0(enc0),
.enc1(enc1),
.enc2(enc2)
);
endmodule
`default_nettype none
module rgb_mixer (
input wire clk,
input wire reset,
input wire enc0_a,
input wire enc0_b,
input wire enc1_a,
input wire enc1_b,
input wire enc2_a,
input wire enc2_b,
output wire pwm0_out,
output wire pwm1_out,
output wire pwm2_out,
output wire [7:0] enc0,
output wire [7:0] enc1,
output wire [7:0] enc2
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
`default_nettype none
module debounce #(
parameter HIST_LEN = 8
)(
input wire clk,
input wire reset,
input wire button,
output reg debounced
);
localparam on_value = 2 ** HIST_LEN - 1;
reg [HIST_LEN-1:0] button_hist;
always @(posedge clk) begin
if(reset) begin
button_hist <= 0;
debounced <= 1'b0;
end else begin
button_hist <= {button_hist[HIST_LEN-2:0], button};
if(button_hist == on_value)
debounced <= 1'b1;
else if(button_hist == {HIST_LEN{1'b0}})
debounced <= 1'b0;
end
end
endmodule
`default_nettype none
module pwm #(
parameter WIDTH = 8,
parameter INVERT = 0
) (
input wire clk,
input wire reset,
output reg out,
input wire [WIDTH-1:0] level
);
reg [WIDTH-1:0] count;
wire pwm_on = count < level;
always @(posedge clk) begin
if(reset)
count <= 1'b0;
else
count <= count + 1'b1;
end
always @(posedge clk) begin
if(reset)
out <= 0;
else
out <= INVERT == 1'b0 ? pwm_on : ! pwm_on;
end
endmodule
`default_nettype none
module encoder #(
parameter WIDTH = 8,
parameter INCREMENT = 1'b1
)(
input clk,
input reset,
input a,
input b,
output reg [WIDTH-1:0] value
);
reg old_a;
reg old_b;
always @(posedge clk) begin
if(reset) begin
old_a <= 0;
old_b <= 0;
value <= 0;
end else begin
// last values
old_a <= a;
old_b <= b;
// state machine
case ({a,old_a,b,old_b})
4'b1000: value <= value + INCREMENT;
4'b0111: value <= value + INCREMENT;
4'b0010: value <= value - INCREMENT;
4'b1101: value <= value - INCREMENT;
default: value <= value;
endcase
end
end
endmodule
|
module rgb_mixer (
input wire clk,
input wire reset,
input wire enc0_a,
input wire enc0_b,
input wire enc1_a,
input wire enc1_b,
input wire enc2_a,
input wire enc2_b,
output wire pwm0_out,
output wire pwm1_out,
output wire pwm2_out,
output wire [7:0] enc0,
output wire [7:0] enc1,
output wire [7:0] enc2
);
wire enc0_a_db, enc0_b_db;
wire enc1_a_db, enc1_b_db;
wire enc2_a_db, enc2_b_db;
// debouncers, 2 for each encoder
debounce #(.HIST_LEN(8)) debounce0_a(.clk(clk), .reset(reset), .button(enc0_a), .debounced(enc0_a_db));
debounce #(.HIST_LEN(8)) debounce0_b(.clk(clk), .reset(reset), .button(enc0_b), .debounced(enc0_b_db));
debounce #(.HIST_LEN(8)) debounce1_a(.clk(clk), .reset(reset), .button(enc1_a), .debounced(enc1_a_db));
debounce #(.HIST_LEN(8)) debounce1_b(.clk(clk), .reset(reset), .button(enc1_b), .debounced(enc1_b_db));
debounce #(.HIST_LEN(8)) debounce2_a(.clk(clk), .reset(reset), .button(enc2_a), .debounced(enc2_a_db));
debounce #(.HIST_LEN(8)) debounce2_b(.clk(clk), .reset(reset), .button(enc2_b), .debounced(enc2_b_db));
// encoders
encoder #(.WIDTH(8)) encoder0(.clk(clk), .reset(reset), .a(enc0_a_db), .b(enc0_b_db), .value(enc0));
encoder #(.WIDTH(8)) encoder1(.clk(clk), .reset(reset), .a(enc1_a_db), .b(enc1_b_db), .value(enc1));
encoder #(.WIDTH(8)) encoder2(.clk(clk), .reset(reset), .a(enc2_a_db), .b(enc2_b_db), .value(enc2));
// pwm modules
pwm #(.WIDTH(8)) pwm0(.clk(clk), .reset(reset), .out(pwm0_out), .level(enc0));
pwm #(.WIDTH(8)) pwm1(.clk(clk), .reset(reset), .out(pwm1_out), .level(enc1));
pwm #(.WIDTH(8)) pwm2(.clk(clk), .reset(reset), .out(pwm2_out), .level(enc2));
endmodule
|
tt06-finale_0076
|
tt06-finale
|
mattvenn-tt06-rgb-mixer
|
task_tt_um_mattvenn_rgb_mixer
|
tt_um_mattvenn_rgb_mixer
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_mattvenn_rgb_mixer (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
`default_nettype none
module rgb_mixer (
input wire clk,
input wire reset,
input wire enc0_a,
input wire enc0_b,
input wire enc1_a,
input wire enc1_b,
input wire enc2_a,
input wire enc2_b,
output wire pwm0_out,
output wire pwm1_out,
output wire pwm2_out,
output wire [7:0] enc0,
output wire [7:0] enc1,
output wire [7:0] enc2
);
wire enc0_a_db, enc0_b_db;
wire enc1_a_db, enc1_b_db;
wire enc2_a_db, enc2_b_db;
// debouncers, 2 for each encoder
debounce #(.HIST_LEN(8)) debounce0_a(.clk(clk), .reset(reset), .button(enc0_a), .debounced(enc0_a_db));
debounce #(.HIST_LEN(8)) debounce0_b(.clk(clk), .reset(reset), .button(enc0_b), .debounced(enc0_b_db));
debounce #(.HIST_LEN(8)) debounce1_a(.clk(clk), .reset(reset), .button(enc1_a), .debounced(enc1_a_db));
debounce #(.HIST_LEN(8)) debounce1_b(.clk(clk), .reset(reset), .button(enc1_b), .debounced(enc1_b_db));
debounce #(.HIST_LEN(8)) debounce2_a(.clk(clk), .reset(reset), .button(enc2_a), .debounced(enc2_a_db));
debounce #(.HIST_LEN(8)) debounce2_b(.clk(clk), .reset(reset), .button(enc2_b), .debounced(enc2_b_db));
// encoders
encoder #(.WIDTH(8)) encoder0(.clk(clk), .reset(reset), .a(enc0_a_db), .b(enc0_b_db), .value(enc0));
encoder #(.WIDTH(8)) encoder1(.clk(clk), .reset(reset), .a(enc1_a_db), .b(enc1_b_db), .value(enc1));
encoder #(.WIDTH(8)) encoder2(.clk(clk), .reset(reset), .a(enc2_a_db), .b(enc2_b_db), .value(enc2));
// pwm modules
pwm #(.WIDTH(8)) pwm0(.clk(clk), .reset(reset), .out(pwm0_out), .level(enc0));
pwm #(.WIDTH(8)) pwm1(.clk(clk), .reset(reset), .out(pwm1_out), .level(enc1));
pwm #(.WIDTH(8)) pwm2(.clk(clk), .reset(reset), .out(pwm2_out), .level(enc2));
endmodule
`default_nettype none
module debounce #(
parameter HIST_LEN = 8
)(
input wire clk,
input wire reset,
input wire button,
output reg debounced
);
localparam on_value = 2 ** HIST_LEN - 1;
reg [HIST_LEN-1:0] button_hist;
always @(posedge clk) begin
if(reset) begin
button_hist <= 0;
debounced <= 1'b0;
end else begin
button_hist <= {button_hist[HIST_LEN-2:0], button};
if(button_hist == on_value)
debounced <= 1'b1;
else if(button_hist == {HIST_LEN{1'b0}})
debounced <= 1'b0;
end
end
endmodule
`default_nettype none
module pwm #(
parameter WIDTH = 8,
parameter INVERT = 0
) (
input wire clk,
input wire reset,
output reg out,
input wire [WIDTH-1:0] level
);
reg [WIDTH-1:0] count;
wire pwm_on = count < level;
always @(posedge clk) begin
if(reset)
count <= 1'b0;
else
count <= count + 1'b1;
end
always @(posedge clk) begin
if(reset)
out <= 0;
else
out <= INVERT == 1'b0 ? pwm_on : ! pwm_on;
end
endmodule
`default_nettype none
module encoder #(
parameter WIDTH = 8,
parameter INCREMENT = 1'b1
)(
input clk,
input reset,
input a,
input b,
output reg [WIDTH-1:0] value
);
reg old_a;
reg old_b;
always @(posedge clk) begin
if(reset) begin
old_a <= 0;
old_b <= 0;
value <= 0;
end else begin
// last values
old_a <= a;
old_b <= b;
// state machine
case ({a,old_a,b,old_b})
4'b1000: value <= value + INCREMENT;
4'b0111: value <= value + INCREMENT;
4'b0010: value <= value - INCREMENT;
4'b1101: value <= value - INCREMENT;
default: value <= value;
endcase
end
end
endmodule
|
module tt_um_mattvenn_rgb_mixer (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
wire rst = ! rst_n;
assign uio_oe = 8'b1111_1111;
assign uo_out[7:3] = 5'b0_0000;
wire [7:0] enc0, enc1, enc2;
wire [1:0] debug_enc = ui_in[7:6];
assign uio_out = debug_enc == 0 ? enc0 :
debug_enc == 1 ? enc1 :
debug_enc == 2 ? enc2 :
0;
rgb_mixer rgb_mixer (
.clk(clk),
.reset(rst),
.enc0_a(ui_in[0]),
.enc0_b(ui_in[1]),
.enc1_a(ui_in[2]),
.enc1_b(ui_in[3]),
.enc2_a(ui_in[4]),
.enc2_b(ui_in[5]),
.pwm0_out(uo_out[0]),
.pwm1_out(uo_out[1]),
.pwm2_out(uo_out[2]),
// debug
.enc0(enc0),
.enc1(enc1),
.enc2(enc2)
);
endmodule
|
tt06-finale_0077
|
tt06-finale
|
matztron-tt06-PAL
|
task_tt_um_MATTHIAS_M_PAL_TOP_WRAPPER
|
tt_um_MATTHIAS_M_PAL_TOP_WRAPPER
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_MATTHIAS_M_PAL_TOP_WRAPPER (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module PAL #(
parameter N = 8, // Number of Inputs
parameter P = 8, // Number of intermediate stages
parameter M = 8 // Number of outputs
)(
input clk,
input res_n,
input en,
input cfg,
input [N-1:0] INPUT_VARS,
output [M-1:0] OUTPUT_VALS
);
parameter SR_LEN = $signed((2*N * P) + P*M);
// Configuration chain
wire [SR_LEN-1:0] FF_CHAIN;
// ---
// FF_CHAIN
//
// <MSB> [ OR | ... | OR | OR | AND | ... | AND | AND | AND-INV | ... | AND-INV | AND-INV ] <LSB> NO THIS IS WRONG! The inverted inputs are interleaved!
//
// When bit at INV is 1 then it is inverted!
// ---
// Indices for configuration chain
parameter FF_CHAIN_OR_BASE_INDEX = $signed(2 * (N*P)); // the fully poopulated crossbar between N and P needs to be considered; *2 because of inverted & non-inverted inputs
wire [FF_CHAIN_OR_BASE_INDEX-1:0] FF_CHAIN_AND;
wire [SR_LEN-FF_CHAIN_OR_BASE_INDEX-1:0] FF_CHAIN_OR;
assign FF_CHAIN_AND = FF_CHAIN[FF_CHAIN_OR_BASE_INDEX-1:0];
assign FF_CHAIN_OR = FF_CHAIN[SR_LEN-1:FF_CHAIN_OR_BASE_INDEX];
// Shift register (stores the configuration)
sr #(
.LEN(SR_LEN)
) sr (
.clk(clk),
.res_n(res_n),
.en(en),
.cfg(cfg),
.ff_chain(FF_CHAIN)
);
// NOT gates
// redo this!
wire [2*N-1:0] INPUT_VARS_N;
wire [P-1:0] INTERM_VARS;
//
//wire [P-1:0] and_cols[2*N-1:0];
//wire [M-1:0] or_rows[P-1:0];
wire [2*N*P-1:0] and_results;
wire [P*M-1:0] or_results;
wire test_lol;
assign test_lol = clk;
// Iterators (running variables)
genvar i;
genvar p;
genvar n;
genvar m;
// ---
// n=0: 0&1
// n=1: 2&3
// n=2: 4&5
// n=3: 6&7
for (n = 0; n < N; n = n + 1) begin
assign INPUT_VARS_N[2*n] = INPUT_VARS[n]; // even: keep
assign INPUT_VARS_N[2*n+1] = ~INPUT_VARS[n]; // odd: invert
end
// ---
// AND matrix
generate
for (p = 0; p < P; p = p + 1) begin : AND_GEN_LOOP_OUTER
for (n = 0; n < $signed(2*N); n = n + 1 ) begin : AND_GEN_LOOP_INNER
//assign INTERM_VARS[p] = INTERM_VARS[p] ^ (FF_CHAIN[FF_CHAIN_AND_BASE_INDEX + p + n*P] ^ INPUT_VARS[n]);
//assign and_cols[p][n] = INPUT_VARS[n] ^ FF_CHAIN[$signed(FF_CHAIN_AND_BASE_INDEX + p + n*P)];
crosspoint #(.OP("and")) cp (.data_in(INPUT_VARS_N[n]), .cfg_in(FF_CHAIN_AND[$signed(p + n*P)]), .data_out(and_results[$signed(p + n*P)]));
end
// Assign intermediate variables
//assign INTERM_VARS[p] = &and_cols[p]; // AND reduction
reduce_and #(
.LEN(2*N*P),
.STRIDE(P),
.COL_INDEX(p)
) reduce_and_I (
.data_in(and_results), // we are only allowed to take
.reduced_out(INTERM_VARS[p])
);
end
endgenerate
// ---
// OR matrix
generate
for (m = 0; m < M; m = m + 1) begin : OR_GEN_LOOP_OUTER
for (p = 0; p < P; p = p + 1) begin : OR_GEN_LOOP_INNER
//assign OUTPUT_VALS[m] = OUTPUT_VALS[m] | (FF_CHAIN[FF_CHAIN_OR_BASE_INDEX + p + m*P] ^ INTERM_VARS[p]);
//assign or_rows[m][p] = INTERM_VARS[p] ^ FF_CHAIN[$signed(FF_CHAIN_OR_BASE_INDEX + p + m*P)];
crosspoint #(.OP("or")) cp (.data_in(INTERM_VARS[p]), .cfg_in(FF_CHAIN_OR[$signed(p + m*P)]), .data_out(or_results[$signed(p + m*P)]));
end
// Assign to outputs
//assign OUTPUT_VALS[m] = |or_rows[m]; // OR reduction
reduce_or #(
.NUM_INTERM_STAGES(P),
.ROW_INDEX(m),
.LEN(P*M)
) reduce_or_I (
.data_in(or_results),
.reduced_out(OUTPUT_VALS[m])
);
end
endgenerate
// ---
endmodule
module stride #(
//parameter OPERATION = "and", // either put "and" or "or"
parameter LEN = 8,
parameter STRIDE = 2,
parameter START_OFFSET = 0
) (
input [LEN-1:0] in,
output [$signed(LEN/STRIDE)-1:0] strided_out
);
// Idea:
// 0 1 2 3 4 5 6 7
// ^ ^ ^ ^
// | | | |
//
// 0. | [0] 1
// 1. | [2] 3
// 2. | [4] 5
// 3. | [6] 7
genvar i;
genvar stride_index;
generate
for (i = START_OFFSET; i < LEN; i = i + STRIDE) begin : REDUCE_LOOP
assign strided_out[$signed(i/STRIDE)] = in[i];
end
endgenerate
endmodule
module crosspoint #(
parameter OP = "and"
)
(
input data_in,
input cfg_in,
output data_out
);
if (OP == "and") begin
// the neutral element of an AND is the 1 - hence generate 1s at undesired positions.
// we want a 1 when the cfg is 0. We want the value of data_in when the cfg is 1
assign data_out = (cfg_in == 1'b1) ? data_in : 1'b1;
end else if (OP == "or") begin
// the neutral element of the OR is the 0 - hence generate 0s at undesired positions.
// we want a 0 when the cfg is 0. We want the value of data in when the cfg is 1
assign data_out = (cfg_in == 1'b1) ? data_in : 1'b0;
end else begin
//Unspecified... this should not happen
end
endmodule
module reduce_and #(
parameter STRIDE = 2,
parameter LEN = 4,
parameter COL_INDEX = 0
) (
input [LEN-1:0] data_in,
output reduced_out
);
wire [LEN/STRIDE-1:0] data_stride;
//Stride instance
stride #(
.LEN(LEN),
.STRIDE(STRIDE),
.START_OFFSET(COL_INDEX)
) stride_I (
.in(data_in),
.strided_out(data_stride)
);
// TODO: With current implementation this does not work...
// We also need a mask of the bitstream to first remove all positions that are not 1!
// SW has to make sure that there is never both the input and its inverted set to true -> then whole term will be 0!!!
// Col. 1 0 1 1 0 0 1 0
// Bits. 0 1 1 0 0 1 0 1
// ---------------------
// AND 0 0 1 0 0 0 0 0 <- then use this one for reduction!
assign reduced_out = &data_stride; //
endmodule
module reduce_or #(
parameter NUM_INTERM_STAGES = 4,
parameter ROW_INDEX = 0,
parameter LEN = 4
) (
input [LEN-1:0] data_in,
output reduced_out
);
// Reduce operation
//assign reduced_out = |data_stride;
assign reduced_out = |data_in[ROW_INDEX*NUM_INTERM_STAGES+(NUM_INTERM_STAGES-1):ROW_INDEX*NUM_INTERM_STAGES];
endmodule
module sr #(
parameter LEN=8
)(
input clk,
input cfg,
input res_n,
input en,
output [LEN-1:0] ff_chain
);
reg [LEN-1:0] internal_ff_chain;
// Shift left whenever a posedge occurs
always @(posedge clk) begin
if (~res_n) begin
internal_ff_chain <= {(LEN){1'b0}}; // when reset set all bits to 0
end else begin
internal_ff_chain <= internal_ff_chain << 1;
internal_ff_chain[0] <= cfg;
end
end
// only apply configuration to the pal fabric once the enable signal is asserted!
assign ff_chain = en ? internal_ff_chain : {(LEN){1'b0}};
endmodule
|
module tt_um_MATTHIAS_M_PAL_TOP_WRAPPER (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// PAL size parameters
parameter NUM_INPUTS = 8;
parameter NUM_INTERMEDIATE_STAGES = 11;
parameter NUM_OUTPUTS = 5;
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// All output pins must be assigned. If not used, assign to 0.
assign uio_out = 0;
// IO pin configuration
assign uio_oe = 8'b0000_0000; // all IOs are inputs (the LSB is used to shift in Config data)
assign uo_out[7:NUM_OUTPUTS] = {(8-NUM_OUTPUTS){1'b0}}; // tie unused outputs to 0
// Pin assignment
// Clock: uio_in[2]
// Reset: res_n
// Enable: uio_in[1]
// Config bit: uio_in[0]
// Input vars: ui_in[7:0]
// Output vars: uo_out[3:0]
// clk is unused!
// PAL instance
PAL #(
.N(NUM_INPUTS), // Number of Inputs
.M(NUM_OUTPUTS), // NUmber of outputs
.P(NUM_INTERMEDIATE_STAGES) // Number of intermediate stages
) pal_I (
.clk(uio_in[2]), // do clock gating with ena signal?
.res_n(rst_n),
.en(ena & uio_in[1]), // if the enable signal is asserted the configuration is applied to the PAL fabric (also the design must be selected with the tto_en)
.cfg(uio_in[0]),
.INPUT_VARS(ui_in[NUM_INPUTS-1:0]),
.OUTPUT_VALS(uo_out[NUM_OUTPUTS-1:0])
);
endmodule
|
tt06-finale_0078
|
tt06-finale
|
mitsece-tt06-verilog-mitssdd
|
task_co_processor
|
tt_um_mitssdd
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_mitssdd (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
// assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in
// assign ui_in[7:2]=6'b000000;
assign uo_out[7:6]=2'b0;
// assign uio_in = 0;
assign uio_out = 0;
assign uio_oe = 0;
co_processor co_processor (
.clk(clk),
.reset(rst_n),
.r0(ui_in),
.check(uio_in[1:0]),
.Q(uo_out[0])
);
fault_pro fault_pro (
.clk(clk),
.reset(rst_n),
.r0(ui_in),
.check(uio_in[1:0]),
.out(uo_out[3:1]),
.out1(uo_out[5:4])
);
endmodule
module co_processor (
input [7:0] r0, // 8-bit input
input [1:0] check, // sensor checking
input reset,
input clk, // clock input
output reg Q // output Q
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module fault_pro(
input [7:0] r0,
input [1:0] check,
input reset,
input clk,
output reg [2:0] out,
output reg [1:0] out1
);
reg [9:0] proc;
reg [2:0] counter1 = 3'b0;
reg [2:0] counter2 = 3'b0;
reg [2:0] counter3 = 3'b0;
reg [2:0] counter4 = 3'b0;
reg maincount = 1'b0;
reg fin = 1'b0;
reg [9:0] diff1=10'b0;
reg [9:0] diff2=10'b0;
reg [9:0] diff3=10'b0;
reg [9:0] diff4=10'b0;
//data storing registers
reg [9:0] r1=10'b0;
reg [9:0] r2=10'b0;
reg [9:0] r3=10'b0;
reg [9:0] r4=10'b0;
//1st 4 set mean values
reg [9:0] m1=10'b0;
reg [9:0] m2=10'b0;
reg [9:0] m3=10'b0;
reg [9:0] m4=10'b0;
//2nd 4 set mean values
reg [9:0] w1=10'b0;
reg [9:0] w2=10'b0;
reg [9:0] w3=10'b0;
reg [9:0] w4=10'b0;
always @(posedge clk or posedge reset) begin
if (reset) begin
r1 <= 10'b0;
r2 <= 10'b0;
r3 <= 10'b0;
r4 <= 10'b0;
counter1 <= 3'b0;
counter2 <= 3'b0;
counter3 <= 3'b0;
counter4 <= 3'b0;
maincount <= 1'b0;
fin <= 1'b0;
out <= 3'b0;
out1 <= 2'b0;
end else begin
case (check)
2'b00: begin
proc = r1;
counter1 <= counter1 + 1;
end
2'b01: begin
proc = r2;
counter2 <= counter2 + 1;
end
2'b10: begin
proc = r3;
counter3 <= counter3 + 1;
end
2'b11: begin
proc = r4;
counter4 <= counter4 + 1;
end
endcase
case (check)
2'b00: r1 <= proc + r0;
2'b01: r2 <= proc + r0;
2'b10: r3 <= proc + r0;
2'b11: r4 <= proc + r0;
endcase
if (counter1 == 4) begin //checking whether sum of 4 data was calculated
m1 <= r1/4;
//calculating the mean of the 4 datas
end
if (counter2 == 4) begin
m2 <= r2/4;
end
if (counter3 == 4) begin
m2 <= r3/4;
end
if (counter4 == 4) begin
m4 <= r4/4;
end
if (counter1 == 4 && counter2 == 4 && counter3 == 4 && counter4 == 4 && !maincount) begin
maincount <= 1'b1;
r1 <= 10'b0;
r2 <= 10'b0;
r3 <= 10'b0;
r4 <= 10'b0;
counter1 <= 3'b0;
counter2 <= 3'b0;
counter3 <= 3'b0;
counter4 <= 3'b0;
fin <= 1'b1;
end
// calculating mean of next 4 set datas
if (fin) begin
case (check)
2'b00: begin
proc = r1;
counter1 <= counter1 + 1;
end
2'b01: begin
proc = r2;
counter2 <= counter2 + 1;
end
2'b10: begin
proc = r3;
counter3 <= counter3 + 1;
end
2'b11: begin
proc = r4;
counter4 <= counter4 + 1;
end
endcase
case (check)
2'b00: r1 <= proc + r0;
2'b01: r2 <= proc + r0;
2'b10: r3 <= proc + r0;
2'b11: r4 <= proc + r0;
endcase
if (counter1 == 4) begin
w1 <= r1/4;
end
if (counter2 == 4) begin
w2 <= r2/4;
end
if (counter3 == 4) begin
w3 <= r3/4;
end
if (counter4 == 4) begin
w4 <= r4/4;
end
end
diff1 = (w1 > m1) ? (w1 - m1) : (m1 - w1);
diff2 = (w2 > m2) ? (w2 - m2) : (m2 - w2);
diff3 = (w3 > m3) ? (w3 - m3) : (m3 - w3);
diff4 = (w4 > m4) ? (w4 - m4) : (m4 - w4);
if(diff1 >= 100) begin
out <= 3'b100;
out1 <= 2'b00;
end
else if(diff1 >= 50) begin
out <= 3'b011;
out1 <= 2'b00;
end
else if(diff1 >= 25) begin
out <= 3'b010;
out1 <= 2'b00;
end
else if(diff1 >= 10) begin
out <= 3'b001;
out1 <= 2'b00;
end
if(diff2 >= 100) begin
out <= 3'b100;
out1 <= 2'b01;
end
else if(diff2 >= 50) begin
out <= 3'b011;
out1 <= 2'b01;
end
else if(diff2 >= 25) begin
out <= 3'b010;
out1 <= 2'b01;
end
else if(diff2 >= 10) begin
out <= 3'b001;
out1 <= 2'b01;
end
if(diff3 >= 100) begin
out <= 3'b100;
out1 <= 2'b10;
end
else if(diff3 >= 50) begin
out <= 3'b011;
out1 <= 2'b10;
end
else if(diff3 >= 25) begin
out <= 3'b010;
out1 <= 2'b10;
end
else if(diff3 >= 10) begin
out <= 3'b001;
out1 <= 2'b10;
end
if(diff4 >= 100) begin
out <= 3'b100;
out1 <= 2'b11;
end
else if(diff4 >= 50) begin
out <= 3'b011;
out1 <= 2'b11;
end
else if(diff4 >= 25) begin
out <= 3'b010;
out1 <= 2'b11;
end
else if(diff4 >= 10) begin
out <= 3'b001;
out1 <= 2'b11;
end
end
end
endmodule
|
module co_processor (
input [7:0] r0, // 8-bit input
input [1:0] check, // sensor checking
input reset,
input clk, // clock input
output reg Q // output Q
);
reg [7:0] proc; // processing register
reg [7:0] r1= 8'b0;
reg [7:0] r2= 8'b0;
reg [7:0] r3= 8'b0;
reg [7:0] r4= 8'b0;
reg [7:0] res;
always @(posedge clk or posedge reset) begin
if (reset) begin
r1 <= 8'b0;
r2 <= 8'b0;
r3 <= 8'b0;
r4 <= 8'b0;
Q <= 1'b0;
end else begin
case (check)
2'b00: proc = r1;
2'b01: proc = r2;
2'b10: proc = r3;
2'b11: proc = r4;
endcase
if (proc == r0) begin
Q <= 1'b0;
end else begin
if (proc > r0) begin
res = proc - r0;
end else begin
res = r0 - proc;
end
if (res > 8'b00000010) begin
case (check)
2'b00: r1 <= r0;
2'b01: r2 <= r0;
2'b10: r3 <= r0;
2'b11: r4 <= r0;
endcase
Q <= 1'b1;
end else begin
Q <= 1'b0;
end
end
end
end
endmodule
|
tt06-finale_0079
|
tt06-finale
|
mitsece-tt06-verilog-mitssdd
|
task_fault_pro
|
tt_um_mitssdd
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_mitssdd (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
// assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in
// assign ui_in[7:2]=6'b000000;
assign uo_out[7:6]=2'b0;
// assign uio_in = 0;
assign uio_out = 0;
assign uio_oe = 0;
co_processor co_processor (
.clk(clk),
.reset(rst_n),
.r0(ui_in),
.check(uio_in[1:0]),
.Q(uo_out[0])
);
fault_pro fault_pro (
.clk(clk),
.reset(rst_n),
.r0(ui_in),
.check(uio_in[1:0]),
.out(uo_out[3:1]),
.out1(uo_out[5:4])
);
endmodule
module co_processor (
input [7:0] r0, // 8-bit input
input [1:0] check, // sensor checking
input reset,
input clk, // clock input
output reg Q // output Q
);
reg [7:0] proc; // processing register
reg [7:0] r1= 8'b0;
reg [7:0] r2= 8'b0;
reg [7:0] r3= 8'b0;
reg [7:0] r4= 8'b0;
reg [7:0] res;
always @(posedge clk or posedge reset) begin
if (reset) begin
r1 <= 8'b0;
r2 <= 8'b0;
r3 <= 8'b0;
r4 <= 8'b0;
Q <= 1'b0;
end else begin
case (check)
2'b00: proc = r1;
2'b01: proc = r2;
2'b10: proc = r3;
2'b11: proc = r4;
endcase
if (proc == r0) begin
Q <= 1'b0;
end else begin
if (proc > r0) begin
res = proc - r0;
end else begin
res = r0 - proc;
end
if (res > 8'b00000010) begin
case (check)
2'b00: r1 <= r0;
2'b01: r2 <= r0;
2'b10: r3 <= r0;
2'b11: r4 <= r0;
endcase
Q <= 1'b1;
end else begin
Q <= 1'b0;
end
end
end
end
endmodule
module fault_pro(
input [7:0] r0,
input [1:0] check,
input reset,
input clk,
output reg [2:0] out,
output reg [1:0] out1
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
|
module fault_pro(
input [7:0] r0,
input [1:0] check,
input reset,
input clk,
output reg [2:0] out,
output reg [1:0] out1
);
reg [9:0] proc;
reg [2:0] counter1 = 3'b0;
reg [2:0] counter2 = 3'b0;
reg [2:0] counter3 = 3'b0;
reg [2:0] counter4 = 3'b0;
reg maincount = 1'b0;
reg fin = 1'b0;
reg [9:0] diff1=10'b0;
reg [9:0] diff2=10'b0;
reg [9:0] diff3=10'b0;
reg [9:0] diff4=10'b0;
//data storing registers
reg [9:0] r1=10'b0;
reg [9:0] r2=10'b0;
reg [9:0] r3=10'b0;
reg [9:0] r4=10'b0;
//1st 4 set mean values
reg [9:0] m1=10'b0;
reg [9:0] m2=10'b0;
reg [9:0] m3=10'b0;
reg [9:0] m4=10'b0;
//2nd 4 set mean values
reg [9:0] w1=10'b0;
reg [9:0] w2=10'b0;
reg [9:0] w3=10'b0;
reg [9:0] w4=10'b0;
always @(posedge clk or posedge reset) begin
if (reset) begin
r1 <= 10'b0;
r2 <= 10'b0;
r3 <= 10'b0;
r4 <= 10'b0;
counter1 <= 3'b0;
counter2 <= 3'b0;
counter3 <= 3'b0;
counter4 <= 3'b0;
maincount <= 1'b0;
fin <= 1'b0;
out <= 3'b0;
out1 <= 2'b0;
end else begin
case (check)
2'b00: begin
proc = r1;
counter1 <= counter1 + 1;
end
2'b01: begin
proc = r2;
counter2 <= counter2 + 1;
end
2'b10: begin
proc = r3;
counter3 <= counter3 + 1;
end
2'b11: begin
proc = r4;
counter4 <= counter4 + 1;
end
endcase
case (check)
2'b00: r1 <= proc + r0;
2'b01: r2 <= proc + r0;
2'b10: r3 <= proc + r0;
2'b11: r4 <= proc + r0;
endcase
if (counter1 == 4) begin //checking whether sum of 4 data was calculated
m1 <= r1/4;
//calculating the mean of the 4 datas
end
if (counter2 == 4) begin
m2 <= r2/4;
end
if (counter3 == 4) begin
m2 <= r3/4;
end
if (counter4 == 4) begin
m4 <= r4/4;
end
if (counter1 == 4 && counter2 == 4 && counter3 == 4 && counter4 == 4 && !maincount) begin
maincount <= 1'b1;
r1 <= 10'b0;
r2 <= 10'b0;
r3 <= 10'b0;
r4 <= 10'b0;
counter1 <= 3'b0;
counter2 <= 3'b0;
counter3 <= 3'b0;
counter4 <= 3'b0;
fin <= 1'b1;
end
// calculating mean of next 4 set datas
if (fin) begin
case (check)
2'b00: begin
proc = r1;
counter1 <= counter1 + 1;
end
2'b01: begin
proc = r2;
counter2 <= counter2 + 1;
end
2'b10: begin
proc = r3;
counter3 <= counter3 + 1;
end
2'b11: begin
proc = r4;
counter4 <= counter4 + 1;
end
endcase
case (check)
2'b00: r1 <= proc + r0;
2'b01: r2 <= proc + r0;
2'b10: r3 <= proc + r0;
2'b11: r4 <= proc + r0;
endcase
if (counter1 == 4) begin
w1 <= r1/4;
end
if (counter2 == 4) begin
w2 <= r2/4;
end
if (counter3 == 4) begin
w3 <= r3/4;
end
if (counter4 == 4) begin
w4 <= r4/4;
end
end
diff1 = (w1 > m1) ? (w1 - m1) : (m1 - w1);
diff2 = (w2 > m2) ? (w2 - m2) : (m2 - w2);
diff3 = (w3 > m3) ? (w3 - m3) : (m3 - w3);
diff4 = (w4 > m4) ? (w4 - m4) : (m4 - w4);
if(diff1 >= 100) begin
out <= 3'b100;
out1 <= 2'b00;
end
else if(diff1 >= 50) begin
out <= 3'b011;
out1 <= 2'b00;
end
else if(diff1 >= 25) begin
out <= 3'b010;
out1 <= 2'b00;
end
else if(diff1 >= 10) begin
out <= 3'b001;
out1 <= 2'b00;
end
if(diff2 >= 100) begin
out <= 3'b100;
out1 <= 2'b01;
end
else if(diff2 >= 50) begin
out <= 3'b011;
out1 <= 2'b01;
end
else if(diff2 >= 25) begin
out <= 3'b010;
out1 <= 2'b01;
end
else if(diff2 >= 10) begin
out <= 3'b001;
out1 <= 2'b01;
end
if(diff3 >= 100) begin
out <= 3'b100;
out1 <= 2'b10;
end
else if(diff3 >= 50) begin
out <= 3'b011;
out1 <= 2'b10;
end
else if(diff3 >= 25) begin
out <= 3'b010;
out1 <= 2'b10;
end
else if(diff3 >= 10) begin
out <= 3'b001;
out1 <= 2'b10;
end
if(diff4 >= 100) begin
out <= 3'b100;
out1 <= 2'b11;
end
else if(diff4 >= 50) begin
out <= 3'b011;
out1 <= 2'b11;
end
else if(diff4 >= 25) begin
out <= 3'b010;
out1 <= 2'b11;
end
else if(diff4 >= 10) begin
out <= 3'b001;
out1 <= 2'b11;
end
end
end
endmodule
|
tt06-finale_0080
|
tt06-finale
|
mitsece-tt06-verilog-mitssdd
|
task_tt_um_mitssdd
|
tt_um_mitssdd
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_mitssdd (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module co_processor (
input [7:0] r0, // 8-bit input
input [1:0] check, // sensor checking
input reset,
input clk, // clock input
output reg Q // output Q
);
reg [7:0] proc; // processing register
reg [7:0] r1= 8'b0;
reg [7:0] r2= 8'b0;
reg [7:0] r3= 8'b0;
reg [7:0] r4= 8'b0;
reg [7:0] res;
always @(posedge clk or posedge reset) begin
if (reset) begin
r1 <= 8'b0;
r2 <= 8'b0;
r3 <= 8'b0;
r4 <= 8'b0;
Q <= 1'b0;
end else begin
case (check)
2'b00: proc = r1;
2'b01: proc = r2;
2'b10: proc = r3;
2'b11: proc = r4;
endcase
if (proc == r0) begin
Q <= 1'b0;
end else begin
if (proc > r0) begin
res = proc - r0;
end else begin
res = r0 - proc;
end
if (res > 8'b00000010) begin
case (check)
2'b00: r1 <= r0;
2'b01: r2 <= r0;
2'b10: r3 <= r0;
2'b11: r4 <= r0;
endcase
Q <= 1'b1;
end else begin
Q <= 1'b0;
end
end
end
end
endmodule
module fault_pro(
input [7:0] r0,
input [1:0] check,
input reset,
input clk,
output reg [2:0] out,
output reg [1:0] out1
);
reg [9:0] proc;
reg [2:0] counter1 = 3'b0;
reg [2:0] counter2 = 3'b0;
reg [2:0] counter3 = 3'b0;
reg [2:0] counter4 = 3'b0;
reg maincount = 1'b0;
reg fin = 1'b0;
reg [9:0] diff1=10'b0;
reg [9:0] diff2=10'b0;
reg [9:0] diff3=10'b0;
reg [9:0] diff4=10'b0;
//data storing registers
reg [9:0] r1=10'b0;
reg [9:0] r2=10'b0;
reg [9:0] r3=10'b0;
reg [9:0] r4=10'b0;
//1st 4 set mean values
reg [9:0] m1=10'b0;
reg [9:0] m2=10'b0;
reg [9:0] m3=10'b0;
reg [9:0] m4=10'b0;
//2nd 4 set mean values
reg [9:0] w1=10'b0;
reg [9:0] w2=10'b0;
reg [9:0] w3=10'b0;
reg [9:0] w4=10'b0;
always @(posedge clk or posedge reset) begin
if (reset) begin
r1 <= 10'b0;
r2 <= 10'b0;
r3 <= 10'b0;
r4 <= 10'b0;
counter1 <= 3'b0;
counter2 <= 3'b0;
counter3 <= 3'b0;
counter4 <= 3'b0;
maincount <= 1'b0;
fin <= 1'b0;
out <= 3'b0;
out1 <= 2'b0;
end else begin
case (check)
2'b00: begin
proc = r1;
counter1 <= counter1 + 1;
end
2'b01: begin
proc = r2;
counter2 <= counter2 + 1;
end
2'b10: begin
proc = r3;
counter3 <= counter3 + 1;
end
2'b11: begin
proc = r4;
counter4 <= counter4 + 1;
end
endcase
case (check)
2'b00: r1 <= proc + r0;
2'b01: r2 <= proc + r0;
2'b10: r3 <= proc + r0;
2'b11: r4 <= proc + r0;
endcase
if (counter1 == 4) begin //checking whether sum of 4 data was calculated
m1 <= r1/4;
//calculating the mean of the 4 datas
end
if (counter2 == 4) begin
m2 <= r2/4;
end
if (counter3 == 4) begin
m2 <= r3/4;
end
if (counter4 == 4) begin
m4 <= r4/4;
end
if (counter1 == 4 && counter2 == 4 && counter3 == 4 && counter4 == 4 && !maincount) begin
maincount <= 1'b1;
r1 <= 10'b0;
r2 <= 10'b0;
r3 <= 10'b0;
r4 <= 10'b0;
counter1 <= 3'b0;
counter2 <= 3'b0;
counter3 <= 3'b0;
counter4 <= 3'b0;
fin <= 1'b1;
end
// calculating mean of next 4 set datas
if (fin) begin
case (check)
2'b00: begin
proc = r1;
counter1 <= counter1 + 1;
end
2'b01: begin
proc = r2;
counter2 <= counter2 + 1;
end
2'b10: begin
proc = r3;
counter3 <= counter3 + 1;
end
2'b11: begin
proc = r4;
counter4 <= counter4 + 1;
end
endcase
case (check)
2'b00: r1 <= proc + r0;
2'b01: r2 <= proc + r0;
2'b10: r3 <= proc + r0;
2'b11: r4 <= proc + r0;
endcase
if (counter1 == 4) begin
w1 <= r1/4;
end
if (counter2 == 4) begin
w2 <= r2/4;
end
if (counter3 == 4) begin
w3 <= r3/4;
end
if (counter4 == 4) begin
w4 <= r4/4;
end
end
diff1 = (w1 > m1) ? (w1 - m1) : (m1 - w1);
diff2 = (w2 > m2) ? (w2 - m2) : (m2 - w2);
diff3 = (w3 > m3) ? (w3 - m3) : (m3 - w3);
diff4 = (w4 > m4) ? (w4 - m4) : (m4 - w4);
if(diff1 >= 100) begin
out <= 3'b100;
out1 <= 2'b00;
end
else if(diff1 >= 50) begin
out <= 3'b011;
out1 <= 2'b00;
end
else if(diff1 >= 25) begin
out <= 3'b010;
out1 <= 2'b00;
end
else if(diff1 >= 10) begin
out <= 3'b001;
out1 <= 2'b00;
end
if(diff2 >= 100) begin
out <= 3'b100;
out1 <= 2'b01;
end
else if(diff2 >= 50) begin
out <= 3'b011;
out1 <= 2'b01;
end
else if(diff2 >= 25) begin
out <= 3'b010;
out1 <= 2'b01;
end
else if(diff2 >= 10) begin
out <= 3'b001;
out1 <= 2'b01;
end
if(diff3 >= 100) begin
out <= 3'b100;
out1 <= 2'b10;
end
else if(diff3 >= 50) begin
out <= 3'b011;
out1 <= 2'b10;
end
else if(diff3 >= 25) begin
out <= 3'b010;
out1 <= 2'b10;
end
else if(diff3 >= 10) begin
out <= 3'b001;
out1 <= 2'b10;
end
if(diff4 >= 100) begin
out <= 3'b100;
out1 <= 2'b11;
end
else if(diff4 >= 50) begin
out <= 3'b011;
out1 <= 2'b11;
end
else if(diff4 >= 25) begin
out <= 3'b010;
out1 <= 2'b11;
end
else if(diff4 >= 10) begin
out <= 3'b001;
out1 <= 2'b11;
end
end
end
endmodule
|
module tt_um_mitssdd (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
// assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in
// assign ui_in[7:2]=6'b000000;
assign uo_out[7:6]=2'b0;
// assign uio_in = 0;
assign uio_out = 0;
assign uio_oe = 0;
co_processor co_processor (
.clk(clk),
.reset(rst_n),
.r0(ui_in),
.check(uio_in[1:0]),
.Q(uo_out[0])
);
fault_pro fault_pro (
.clk(clk),
.reset(rst_n),
.r0(ui_in),
.check(uio_in[1:0]),
.out(uo_out[3:1]),
.out1(uo_out[5:4])
);
endmodule
|
tt06-finale_0081
|
tt06-finale
|
noritsuna-tt06-tt_um_i4004
|
task_alu
|
tt_um_noritsuna_i4004
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module tt_um_noritsuna_i4004 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena,
input wire clk,
input wire rst_n
);
wire sysclk;
wire clk1_pad;
wire clk2_pad;
wire poc_pad;
wire test_pad;
wire [3:0] data_in_pad;
wire [3:0] data_out_pad;
wire cmrom_pad;
wire cmram0_pad;
wire cmram1_pad;
wire cmram2_pad;
wire cmram3_pad;
wire sync_pad;
//input:
assign sysclk = clk;
assign data_in_pad = ui_in[3:0];
assign clk1_pad = ui_in[4];
assign clk2_pad = ui_in[5];
assign poc_pad = ui_in[6];
assign test_pad = ui_in[7];
//output:
assign cmrom_pad = uo_out[0];
assign cmram0_pad = uo_out[1];
assign cmram1_pad = uo_out[2];
assign cmram2_pad = uo_out[3];
assign cmram3_pad = uo_out[4];
assign sync_pad = uo_out[5];
assign uio_oe[3:0] = 1;
assign data_out_pad = uio_out[3:0];
// All output pins must be assigned. If not used, assign to 0.
assign uo_out[6] = 0;
assign uo_out[7] = 0;
assign uio_out[7:4] = 0;
assign uio_oe[7:4] = 0;
// Common BiDir data bus
wire [3:0] data;
// Timing and I/O Board Outputs
wire clk1;
wire clk2;
wire a12;
wire a22;
wire a32;
wire m12;
wire m22;
wire x12;
wire x22;
wire x32;
wire gate;
wire poc; // Clean POC_PAD
wire n0432; // Clean TEST_PAD
// Outputs from the Instruction Decode board
wire jcn_isz;
wire jin_fin;
wire jun_jms;
wire cn_n;
wire bbl;
wire jms;
wire sc;
wire dc;
wire sc_m22_clk2;
wire fin_fim_src_jin;
wire inc_isz_add_sub_xch_ld;
wire inc_isz_xch;
wire opa0_n;
wire cma;
wire write_acc_1;
wire write_carry_2;
wire read_acc_3;
wire add_group_4;
wire inc_group_5;
wire sub_group_6;
wire ior;
wire iow;
wire ral;
wire rar;
wire ope_n;
wire daa;
wire dcl;
wire inc_isz;
wire kbp;
wire o_ib;
wire tcs;
wire xch;
wire n0342;
wire x21_clk2;
wire x31_clk2;
wire com_n;
// Outputs from the ALU board
wire acc_0;
wire add_0;
wire cy_1;
wire cmram0;
wire cmram1;
wire cmram2;
wire cmram3;
wire cmrom;
// Instantiate the Timing and I/O board
timing_io tio_board (
.sysclk(sysclk),
.clk1_pad(clk1_pad),
.clk2_pad(clk2_pad),
.poc_pad(poc_pad),
.ior(ior),
.clk1(clk1),
.clk2(clk2),
.a12(a12),
.a22(a22),
.a32(a32),
.m12(m12),
.m22(m22),
.x12(x12),
.x22(x22),
.x32(x32),
.gate(gate),
.poc(poc),
.data(data),
.data_in_pad(data_in_pad),
.data_out_pad(data_out_pad),
.test_pad(test_pad),
.n0432(n0432),
.sync_pad(sync_pad),
.cmrom(cmrom),
.cmrom_pad(cmrom_pad),
.cmram0(cmram0),
.cmram0_pad(cmram0_pad),
.cmram1(cmram1),
.cmram1_pad(cmram1_pad),
.cmram2(cmram2),
.cmram2_pad(cmram2_pad),
.cmram3(cmram3),
.cmram3_pad(cmram3_pad)
);
// Instantiate the Instruction Decode board
instruction_decode id_board (
.sysclk(clk),
.clk1(clk1),
.clk2(clk2),
.a22(a22),
.m12(m12),
.m22(m22),
.x12(x12),
.x22(x22),
.x32(x32),
.poc(poc),
.n0432(n0432),
.data(data),
.jcn_isz(jcn_isz),
.jin_fin(jin_fin),
.jun_jms(jun_jms),
.cn_n(cn_n),
.bbl(bbl),
.jms(jms),
.sc(sc),
.dc(dc),
.sc_m22_clk2(sc_m22_clk2),
.fin_fim_src_jin(fin_fim_src_jin),
.inc_isz_add_sub_xch_ld(inc_isz_add_sub_xch_ld),
.inc_isz_xch(inc_isz_xch),
.opa0_n(opa0_n),
.acc_0(acc_0),
.add_0(add_0),
.cy_1(cy_1),
.cma(cma),
.write_acc_1(write_acc_1),
.write_carry_2(write_carry_2),
.read_acc_3(read_acc_3),
.add_group_4(add_group_4),
.inc_group_5(inc_group_5),
.sub_group_6(sub_group_6),
.ior(ior),
.iow(iow),
.ral(ral),
.rar(rar),
.ope_n(ope_n),
.daa(daa),
.dcl(dcl),
.inc_isz(inc_isz),
.kbp(kbp),
.o_ib(o_ib),
.tcs(tcs),
.xch(xch),
.n0342(n0342),
.x21_clk2(x21_clk2),
.x31_clk2(x31_clk2),
.com_n(com_n)
);
// Instantiate the ALU board
alu alu_board (
.sysclk(clk),
.a12(a12),
.m12(m12),
.x12(x12),
.poc(poc),
.data(data),
.acc_0(acc_0),
.add_0(add_0),
.cy_1(cy_1),
.cma(cma),
.write_acc_1(write_acc_1),
.write_carry_2(write_carry_2),
.read_acc_3(read_acc_3),
.add_group_4(add_group_4),
.inc_group_5(inc_group_5),
.sub_group_6(sub_group_6),
.ior(ior),
.iow(iow),
.ral(ral),
.rar(rar),
.ope_n(ope_n),
.daa(daa),
.dcl(dcl),
.inc_isz(inc_isz),
.kbp(kbp),
.o_ib(o_ib),
.tcs(tcs),
.xch(xch),
.n0342(n0342),
.x21_clk2(x21_clk2),
.x31_clk2(x31_clk2),
.com_n(com_n),
.cmram0(cmram0),
.cmram1(cmram1),
.cmram2(cmram2),
.cmram3(cmram3),
.cmrom(cmrom)
);
// Instantiate the Instruction Pointer board
instruction_pointer ip_board (
.sysclk(clk),
.clk1(clk1),
.clk2(clk2),
.a12(a12),
.a22(a22),
.a32(a32),
.m12(m12),
.m22(m22),
.x12(x12),
.x22(x22),
.x32(x32),
.poc(poc),
.m12_m22_clk1_m11_m12(gate),
.data(data),
.jcn_isz(jcn_isz),
.jin_fin(jin_fin),
.jun_jms(jun_jms),
.cn_n(cn_n),
.bbl(bbl),
.jms(jms),
.sc(sc),
.dc(dc)
);
// Instantiate the Scratchpad board
scratchpad sp_board (
.sysclk(clk),
.clk1(clk1),
.clk2(clk2),
.a12(a12),
.a22(a22),
.a32(a32),
.m12(m12),
.m22(m22),
.x12(x12),
.x22(x22),
.x32(x32),
.poc(poc),
.m12_m22_clk1_m11_m12(gate),
.data(data),
.sc_m22_clk2(sc_m22_clk2),
.fin_fim_src_jin(fin_fim_src_jin),
.inc_isz_add_sub_xch_ld(inc_isz_add_sub_xch_ld),
.inc_isz_xch(inc_isz_xch),
.opa0_n(opa0_n),
.sc(sc),
.dc(dc)
);
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module alu(
input wire sysclk,
// Inputs from the Timing and I/O board
input wire a12,
input wire m12,
input wire x12,
input wire poc,
// Common 4-bit data bus
inout wire [3:0] data,
// Outputs to the Instruction Decode board
output wire acc_0,
output wire add_0,
output reg cy_1,
// Inputs from the Instruction Decode board
input wire cma,
input wire write_acc_1,
input wire write_carry_2,
input wire read_acc_3,
input wire add_group_4,
input wire inc_group_5,
input wire sub_group_6,
input wire ior,
input wire iow,
input wire ral,
input wire rar,
input wire ope_n,
input wire daa,
input wire dcl,
input wire inc_isz,
input wire kbp,
input wire o_ib,
input wire tcs,
input wire xch,
input wire n0342,
input wire x21_clk2,
input wire x31_clk2,
input wire com_n,
// Outputs to external pins
output wire cmram0,
output wire cmram1,
output wire cmram2,
output wire cmram3,
output wire cmrom
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module counter(
input wire sysclk,
input wire step_a,
input wire step_b,
output reg q = 1'b0
);
reg q_n = 1'b1;
always @(posedge sysclk) begin
if (step_a) q <= ~q_n;
if (step_b) q_n <= q;
end
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module instruction_decode(
input wire sysclk, // 50 MHz FPGA clock
// Inputs from the Timing and I/O board
input wire clk1,
input wire clk2,
input wire a22,
input wire m12,
input wire m22,
input wire x12,
input wire x22,
input wire x32,
input wire poc, // Power-On Clear (reset)
input wire n0432, // Conditioned TEST_PAD
// Common 4-bit data bus
inout wire [3:0] data,
// These drive the Instruction Pointer (IP) board
output wire jcn_isz, // JCN+ISZ
output wire jin_fin, // JIN+FIN
output wire jun_jms, // JUN+JMS
output wire cn_n, // ~CN
output wire bbl, // BBL
output wire jms, // JMS
// Outputs to both the IP and SP boards
output wire sc, // SC (Single Cycle)
output wire dc, // DC (Double Cycle, ~SC)
// Outputs to the Scratch Pad (SP) board
output wire sc_m22_clk2, // SC&M22&CLK2
output wire fin_fim_src_jin, // FIN+FIM+SRC+JIN
output wire inc_isz_add_sub_xch_ld, // INC+ISZ+ADD+SUB+XCH+LD
output wire inc_isz_xch, // INC+ISZ+XCH
output wire opa0_n, // ~OPA.0
// Inputs from the ALU board (condition bits)
input wire acc_0, // ACC_0
input wire add_0, // ADD_0
input wire cy_1, // CY_1
// Outputs to the Arithmetic Logic Unit (ALU) board
output wire cma,
output wire write_acc_1,
output wire write_carry_2,
output wire read_acc_3,
output wire add_group_4,
output wire inc_group_5,
output wire sub_group_6,
output wire ior,
output wire iow,
output wire ral,
output wire rar,
output wire ope_n,
output wire daa,
output wire dcl,
output wire inc_isz,
output wire kbp,
output wire o_ib,
output wire tcs,
output wire xch,
output wire n0342,
output wire x21_clk2,
output wire x31_clk2,
output wire com_n
);
wire sc_m12_clk2 = sc & m12 & clk2;
assign sc_m22_clk2 = sc & m22 & clk2;
// Latch the first 4 bits of the opcode
reg [3:0] opr = 4'b0000;
always @(posedge sysclk) begin
if (sc_m12_clk2)
opr <= data;
end
// Latch the second 4 bits of the opcode
reg [3:0] opa = 4'b0000;
always @(posedge sysclk) begin
if (sc_m22_clk2)
opa <= data;
end
assign opa0_n = ~opa[0];
// Full OPR Decoding
wire nop = (opr == 4'b0000);
wire jcn = (opr == 4'b0001);
wire fim_src = (opr == 4'b0010);
assign jin_fin = (opr == 4'b0011);
wire jun = (opr == 4'b0100);
assign jms = (opr == 4'b0101);
wire inc = (opr == 4'b0110);
wire isz = (opr == 4'b0111);
wire add = (opr == 4'b1000);
wire sub = (opr == 4'b1001);
wire ld = (opr == 4'b1010);
assign xch = (opr == 4'b1011);
assign bbl = (opr == 4'b1100);
wire ldm = (opr == 4'b1101);
wire io = (opr == 4'b1110);
wire ope = (opr == 4'b1111);
assign ope_n = ~ope;
assign jcn_isz = jcn | isz;
assign jun_jms = jun | jms;
wire ldm_bbl = ldm | bbl;
assign inc_isz = (inc | isz) & sc;
assign inc_isz_xch = inc | isz | xch;
assign inc_isz_add_sub_xch_ld = inc | isz | add | sub | xch | ld;
assign fin_fim_src_jin = fim_src | jin_fin;
// OPE: OPA Decoding
assign o_ib = ope & (opa[3] == 1'b0);
wire clb = ope & (opa == 4'b0000);
wire clc = ope & (opa == 4'b0001);
wire iac = ope & (opa == 4'b0010);
wire cmc = ope & (opa == 4'b0011);
assign cma = ope & (opa == 4'b0100);
assign ral = ope & (opa == 4'b0101);
assign rar = ope & (opa == 4'b0110);
wire tcc = ope & (opa == 4'b0111);
wire dac = ope & (opa == 4'b1000);
assign tcs = ope & (opa == 4'b1001);
wire stc = ope & (opa == 4'b1010);
assign daa = ope & (opa == 4'b1011);
assign kbp = ope & (opa == 4'b1100);
assign dcl = ope & (opa == 4'b1101);
// IO: OPA Decoding
assign iow = io & (opa[3] == 1'b0);
assign ior = io & (opa[3] == 1'b1);
wire adm = io & (opa == 4'b1011);
wire sbm = io & (opa == 4'b1000);
wire fin_fim = fin_fim_src_jin & ~opa[0];
wire src = fim_src & opa[0];
assign write_acc_1 = ~(kbp | tcs | daa | xch | poc | cma | tcc | dac | iac |
clb | ior | ld | sub | add | ldm_bbl);
assign write_carry_2 = ~(tcs | poc | tcc | stc | cmc | dac | iac |
clc | clb | sbm | adm | sub | add);
assign read_acc_3 = ~(daa | rar | ral | dac | iac | sbm | adm | sub | add);
assign add_group_4 = ~(tcs | tcc | adm | add);
assign inc_group_5 = ~(inc_isz | stc | iac);
assign sub_group_6 = ~(cmc | sbm | sub | m12);
// The Condition Flip-Flop
reg n0397;
wire n0486 = ~((opa[2] & acc_0) | (opa[1] & cy_1) | (opa[0] & n0432));
wire n0419 = ~((add_0 & ~isz) & (~jcn | ((~n0486 | opa[3]) & (n0486 | ~opa[3]))));
wire n0413 = ~((sc & n0419 & x32) | (~x32 | n0397));
reg n0405;
always @(posedge sysclk) begin
if (clk2)
n0405 <= n0413;
if (clk1)
n0397 <= ~n0405;
end
assign cn_n = ~n0397;
// The Single-Cycle Flip-Flop
reg n0343;
wire n0368 = ~((sc & (fin_fim | jcn_isz | jun_jms) & x32) | (n0343 & ~x32));
reg n0362;
always @(posedge sysclk) begin
if (clk2)
n0362 <= n0368;
if (clk1)
n0343 <= ~n0362;
end
assign sc = ~n0343;
assign dc = ~sc;
// Generate ~(X21&~CLK2)
reg n0360;
always @(posedge sysclk) begin
if (clk2)
n0360 <= ~x12;
end
wire n0337 = ~(n0360 | clk2);
assign x21_clk2 = ~n0337;
// Generate ~(X31&~CLK2)
reg n0380;
always @(posedge sysclk) begin
if (clk2)
n0380 <= ~x22;
end
wire n0375 = ~(n0380 | clk2);
assign x31_clk2 = ~n0375;
// Generate ~COM
wire n0329 = io;
reg n0414, n0797;
always @(posedge sysclk) begin
if (clk2)
n0414 <= a22;
else
n0797 <= n0414;
end
reg n0433, n0801;
always @(posedge sysclk) begin
if (clk2)
n0433 <= m12;
else
n0801 <= n0433;
end
reg n0425, n0805;
always @(posedge sysclk) begin
if (clk2)
n0425 <= x12;
else
n0805 <= n0425;
end
wire n0782 = ~((n0801 & n0329) | (src & n0805) | n0797);
assign com_n = n0782;
// Generate N0342
wire n0332 = ~(((n0329 | poc) & x22 & clk2) | (~(n0329 | poc) & n0337 & clk1));
assign n0342 = n0332;
// Output OPA onto the data bus
wire opa_ib = (ldm_bbl | jun_jms) & ~x21_clk2;
assign data = opa_ib ? opa : 4'bzzzz;
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module instruction_pointer (
input wire sysclk, // 50 MHz FPGA clock
// Inputs from the Timing and I/O board
input wire clk1,
input wire clk2,
input wire a12,
input wire a22,
input wire a32,
input wire m12,
input wire m22,
input wire x12,
input wire x22,
input wire x32,
input wire poc, // Power-On Clear (reset)
input wire m12_m22_clk1_m11_m12, // M12+M22+CLK1~(M11+M12)
// Common 4-bit data bus
inout wire [3:0] data,
// Inputs from the Instruction Decode board
input wire jcn_isz, // JCN+ISZ
input wire jin_fin, // JIN+FIN
input wire jun_jms, // JUN+JMS
input wire cn_n, // ~CN
input wire bbl, // BBL
input wire jms, // JMS
input wire sc, // SC (Single Cycle)
input wire dc // DC (Double Cycle, ~SC)
);
reg [11:0] dram_array [0:3];
reg [11:0] dram_temp;
wire [3:0] din_n;
wire inh = (jin_fin & sc) | ((jun_jms | (jcn_isz & ~cn_n)) & dc);
// Row Counter stuff
wire [1:0] addr_ptr; // Effective Address counter
wire addr_ptr_step; // CLK2(JMS&DC&M22+BBL(M22+X12+X22))
assign addr_ptr_step = ~(~clk2 | ~(((m22 | x12 | x22) & bbl) |
(m22 & dc & jms)));
counter addr_ptr_0 (
.sysclk(sysclk),
.step_a(clk1),
.step_b(addr_ptr_step),
.q(addr_ptr[0])
);
counter addr_ptr_1 (
.sysclk(sysclk),
.step_a( addr_ptr[0]),
.step_b(~addr_ptr[0]),
.q(addr_ptr[1])
);
// Refresh counter stuff
wire [1:0] addr_rfsh; // Row Refresh counter
wire addr_rfsh_step; // (~INH)&X32&CLK2
assign addr_rfsh_step = ~inh & x32 & clk2;
counter addr_rfsh_0 (
.sysclk(sysclk),
.step_a(clk1),
.step_b(addr_rfsh_step),
.q(addr_rfsh[0])
);
counter addr_rfsh_1 (
.sysclk(sysclk),
.step_a( addr_rfsh[0]),
.step_b(~addr_rfsh[0]),
.q(addr_rfsh[1])
);
// Row selection mux
reg [1:0] row; // {N0409, N0420}
always @(posedge sysclk) begin
if (x12)
row <= addr_rfsh;
if (x32)
row <= addr_ptr;
end
// Row Precharge/Read/Write stuff
wire precharge; // (~INH)(X11+X31)CLK1
wire row_read; // (~POC)CLK2(X12+X32)~INH
wire row_write; // ((~SC)(JIN+FIN))CLK1(M11+X21~INH)
reg n0517;
always @(posedge sysclk) begin
if (clk2)
n0517 <= ~(m22 | x22);
end
assign precharge = ~(n0517 | inh | ~clk1);
assign row_read = ~poc & clk2 & (x12 | x32) & ~inh;
reg n0438;
always @(posedge sysclk) begin
if (clk2)
n0438 <= ~((x12 & ~inh) | a32);
end
assign row_write = ~(n0438 | (jin_fin & ~sc) | ~clk1);
// Column Read selection stuff
reg n0416;
always @(posedge sysclk) begin
if (clk2)
n0416 <= ~x32;
end
wire radb0 = ~(n0416 | clk2);
reg n0384;
always @(posedge sysclk) begin
if (clk2)
n0384 <= ~a12;
end
wire radb1 = ~(n0384 | clk2);
reg n0374;
always @(posedge sysclk) begin
if (clk2)
n0374 <= ~a22;
end
wire radb2 = ~(n0374 | clk2);
// Column Write selection stuff
wire n0322 = ~(sc | cn_n);
wire wadb0 = ~(~clk2 | ~(a12 | (sc & jin_fin & x32) |
(((jcn_isz & n0322) | (jun_jms & ~sc)) & m22)));
wire wadb1 = ~(~clk2 | ~(a22 | (sc & jin_fin & x22) |
(((jcn_isz & n0322) | (jun_jms & ~sc)) & m12)));
wire wadb2 = ~(~clk2 | ~(a32 | (jun_jms & ~sc & x22)));
// Manage the row data buffer
always @(posedge sysclk) begin
if (precharge)
dram_temp <= 12'b0;
if (row_read)
dram_temp <= dram_array[row];
if (wadb0)
dram_temp[ 3:0] <= ~din_n;
if (wadb1)
dram_temp[ 7:4] <= ~din_n;
if (wadb2)
dram_temp[11:8] <= ~din_n;
end
// Handle row writes
always @(posedge sysclk) begin
if (row_write)
dram_array[row] <= dram_temp;
end
// Manage the data output mux
reg [3:0] dout;
always @* begin
(* PARALLEL_CASE *)
case (1'b1)
radb0: dout = dram_temp[ 3:0];
radb1: dout = dram_temp[ 7:4];
radb2: dout = dram_temp[11:8];
default: dout = 4'bzzzz;
endcase
end
assign data = dout;
// Data In mux and incrementer
reg [3:0] incr_in;
always @(posedge sysclk) begin
if (m12_m22_clk1_m11_m12)
incr_in <= data;
end
reg carry_out, carry_in;
wire [4:0] incr_out = (a12 | ((a22 | a32) & carry_in)) ?
(incr_in + 4'b0001) : {1'b0, incr_in};
always @(posedge sysclk) begin
if (clk2)
carry_out <= incr_out[4];
if (clk1)
carry_in <= carry_out;
end
assign din_n = ~incr_out[3:0];
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module scratchpad (
input wire sysclk, // 50 MHz FPGA clock
// Inputs from the Timing and I/O board
input wire clk1,
input wire clk2,
input wire a12,
input wire a22,
input wire a32,
input wire m12,
input wire m22,
input wire x12,
input wire x22,
input wire x32,
input wire poc, // Power-On Clear (reset)
input wire m12_m22_clk1_m11_m12, // M12+M22+CLK1~(M11+M12)
// Common 4-bit data bus
inout wire [3:0] data,
// Inputs from the Instruction Decode board
input wire sc_m22_clk2, // SC&M22&CLK2
input wire fin_fim_src_jin, // FIN+FIM+SRC+JIN
input wire inc_isz_add_sub_xch_ld, // INC+ISZ+ADD+SUB+XCH+LD
input wire inc_isz_xch, // INC+ISZ+XCH
input wire opa0_n, // ~OPA.0
input wire sc, // SC (Single Cycle)
input wire dc // DC (Double Cycle, ~SC)
);
reg [7:0] dram_array [0:7];
reg [7:0] dram_temp;
reg [3:0] din_n;
// Refresh counter stuff
wire [2:0] reg_rfsh; // Row Refresh counter
wire reg_rfsh_step; // SC&A12&CLK2
assign reg_rfsh_step = sc & a12 & clk2;
counter reg_rfsh_0 (
.sysclk(sysclk),
.step_a(clk1),
.step_b(reg_rfsh_step),
.q(reg_rfsh[0])
);
counter reg_rfsh_1 (
.sysclk(sysclk),
.step_a( reg_rfsh[0]),
.step_b(~reg_rfsh[0]),
.q(reg_rfsh[1])
);
counter reg_rfsh_2 (
.sysclk(sysclk),
.step_a( reg_rfsh[1]),
.step_b(~reg_rfsh[1]),
.q(reg_rfsh[2])
);
// Row selection mux
reg [2:0] row; // {N0646, N0617, N0582}
always @(posedge sysclk) begin
if (sc & a22)
row <= reg_rfsh;
if (sc_m22_clk2)
row <= data[3:1];
end
// Row Precharge/Read/Write stuff
wire precharge; // SC(A22+M22)CLK2
wire row_read; // (~POC)&CLK2&SC(A32+X12)
wire row_write; // CLK2&SC(A12+M12)
assign precharge = sc & (a22 | m22) & clk2;
assign row_read = ~(poc | ~(clk2 & sc & (a32 | x12)));
assign row_write = sc & (a12 | m12) & clk2;
// Column Read selection stuff
reg n0615;
always @(posedge sysclk) begin
if (clk2)
n0615 <= ~(x12 & (fin_fim_src_jin |
(opa0_n & inc_isz_add_sub_xch_ld)));
end
wire rrab0 = ~(dc | n0615 | clk2);
reg n0592;
always @(posedge sysclk) begin
if (clk2)
n0592 <= ~((x22 & fin_fim_src_jin) |
(~opa0_n & x12 & inc_isz_add_sub_xch_ld));
end
wire rrab1 = ~(dc | n0592 | clk2);
// Column Write selection stuff
wire n0564 = opa0_n & fin_fim_src_jin & dc;
wire n0568 = inc_isz_xch & x32 & sc;
wire wrab0 = clk2 & ((m12 & n0564) | ( opa0_n & n0568));
wire wrab1 = clk2 & ((m22 & n0564) | (~opa0_n & n0568));
// Manage the row data buffer
always @(posedge sysclk) begin
if (precharge)
dram_temp <= 8'b0;
if (row_read)
dram_temp <= dram_array[row];
if (wrab0)
dram_temp[ 3:0] <= ~din_n;
if (wrab1)
dram_temp[ 7:4] <= ~din_n;
end
// Handle row writes
always @(posedge sysclk) begin
if (row_write)
dram_array[row] <= dram_temp;
end
// Manage the data output mux
reg [3:0] dout;
always @* begin
(* PARALLEL_CASE *)
case (1'b1)
rrab0: dout = dram_temp[ 3:0];
rrab1: dout = dram_temp[ 7:4];
default: dout = 4'bzzzz;
endcase
end
assign data = dout;
// Data In latch
always @(posedge sysclk) begin
if (m12_m22_clk1_m11_m12)
din_n <= ~data;
end
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module timing_io(
input wire sysclk,
input wire clk1_pad,
input wire clk2_pad,
input wire poc_pad,
input wire ior,
// Timing and I/O Board Outputs
output wire clk1,
output wire clk2,
output wire a12,
output wire a22,
output wire a32,
output wire m12,
output wire m22,
output wire x12,
output wire x22,
output wire x32,
output wire gate,
output reg poc,
// External I/O Pad conditioning
inout wire [3:0] data,
inout wire [3:0] data_in_pad,
output wire [3:0] data_out_pad,
input wire test_pad,
output reg n0432,
output reg sync_pad,
input wire cmrom,
output wire cmrom_pad,
input wire cmram0,
output wire cmram0_pad,
input wire cmram1,
output wire cmram1_pad,
input wire cmram2,
output wire cmram2_pad,
input wire cmram3,
output wire cmram3_pad
);
// Simple pass-throughs
assign clk1 = clk1_pad;
assign clk2 = clk2_pad;
assign cmrom_pad = cmrom;
assign cmram0_pad = cmram0;
assign cmram1_pad = cmram1;
assign cmram2_pad = cmram2;
assign cmram3_pad = cmram3;
// Generate the 8 execution phase indicators
reg [0:7] master = 8'h00;
reg [0:7] slave = 8'h00;
always @(posedge sysclk) begin
if (clk2)
master <= {~|slave[0:6], slave[0:6]};
else
sync_pad <= master[7];
if (clk1)
slave <= master;
end
assign a12 = slave[0];
assign a22 = slave[1];
assign a32 = slave[2];
assign m12 = slave[3];
assign m22 = slave[4];
assign x12 = slave[5];
assign x22 = slave[6];
assign x32 = slave[7];
// Generate the DRAM Input Gate signal
// Properly called M12+M22+CLK1~(M11&M12)
wire n0279 = ~(a32 | m12);
reg n0278;
always @(posedge sysclk) begin
if (clk2)
n0278 <= n0279;
end
wire n0708 = ~((n0278 & clk1) | m12 | m22);
assign gate = ~n0708;
// Generate a clean POC signal
always @(posedge sysclk) begin
if (poc_pad) poc <= 1'b1;
else if (a12) poc <= 1'b0;
else poc <= poc;
end
// Generate a clean ~TEST signal (n0432)
always @(posedge sysclk) begin
n0432 <= ~test_pad;
end
// Manage the Data I/O pads
reg L;
always @(posedge sysclk) begin
if (clk2)
L <= a32 | m12 | (x12 & (ior | poc));
end
wire n0702 = ~clk2;
reg n0685;
reg n0699;
reg n0707;
always @(posedge sysclk) begin
if (clk1) begin
n0685 <= ~L;
n0707 <= L;
end
if (n0702)
n0699 <= ~L;
end
wire n0700 = n0707 | (L & n0702) | poc;
wire n0659 = (clk2 & n0685) | (clk1 & L);
wire n0676 = clk1 | n0685 | n0699;
// Incoming data from the external pads
reg [3:0] data_in;
always @* begin
if (n0659) data_in = 4'b1111;
else if (n0676) data_in = 4'bzzzz;
else if (poc) data_in = 4'b0000;
else data_in = data_in_pad;
end
assign data = data_in;
// Outgoing data to the external pads
reg [3:0] data_out;
always @(posedge sysclk) begin
if (n0702)
data_out <= data;
end
assign data_out_pad = poc ? 4'b0000 : (n0700 ? 4'bzzzz : data_out);
assign data_in_pad = poc ? 4'b0000 : (n0700 ? 4'bzzzz : data_out);
endmodule
|
module alu(
input wire sysclk,
// Inputs from the Timing and I/O board
input wire a12,
input wire m12,
input wire x12,
input wire poc,
// Common 4-bit data bus
inout wire [3:0] data,
// Outputs to the Instruction Decode board
output wire acc_0,
output wire add_0,
output reg cy_1,
// Inputs from the Instruction Decode board
input wire cma,
input wire write_acc_1,
input wire write_carry_2,
input wire read_acc_3,
input wire add_group_4,
input wire inc_group_5,
input wire sub_group_6,
input wire ior,
input wire iow,
input wire ral,
input wire rar,
input wire ope_n,
input wire daa,
input wire dcl,
input wire inc_isz,
input wire kbp,
input wire o_ib,
input wire tcs,
input wire xch,
input wire n0342,
input wire x21_clk2,
input wire x31_clk2,
input wire com_n,
// Outputs to external pins
output wire cmram0,
output wire cmram1,
output wire cmram2,
output wire cmram3,
output wire cmrom
);
reg [3:0] acc;
reg cy;
// Decode logic
wire n0854 = ~(~x12);
wire n0351 = ~(x21_clk2 | ~dcl);
wire n0415 = ~(x21_clk2 | ope_n);
wire add_ib = ~(x31_clk2 | ~inc_isz);
wire cy_ib = ~(x31_clk2 | ~iow);
wire acb_ib = ~((x31_clk2 | ~xch) & (x21_clk2 | ~iow));
wire n0477 = ~((~x31_clk2 & ~ior) | (a12 & ior));
wire adc_cy = ~(write_carry_2 | n0477);
wire add_acc = ~(write_acc_1 | n0477);
wire adsr = ~(x31_clk2 | ~rar);
wire adsl = ~(x31_clk2 | ~ral);
wire acc_adac = ~(~cma | n0342);
wire acc_ada = ~(read_acc_3 | n0342);
wire cy_ada = ~(add_group_4 | n0342);
wire cy_adac = ~(sub_group_6 | n0342);
// Latch the incoming data bus
reg [3:0] tmp; // It's the name used in simulator!
always @(posedge sysclk) begin
if (~n0342)
tmp <= data;
if (m12)
tmp <= 4'b1111;
end
// Invert some of the incoming data
reg n0893, n0891, n0889, n0887; // D3, D2, D1, D0
always @(posedge sysclk) begin
if (sub_group_6) begin
n0887 <= tmp[0];
n0889 <= ~tmp[1];
n0891 <= tmp[2];
n0893 <= ~tmp[3];
end
if (~(sub_group_6 | m12)) begin
n0887 <= ~tmp[0];
n0889 <= tmp[1];
n0891 <= ~tmp[2];
n0893 <= tmp[3];
end
end
// Feedback from Accumulator
reg n0873, n0872, n0871, n0870;
always @(posedge sysclk) begin
if (m12)
{n0873, n0872, n0871, n0870} <= 4'b1010;
if (acc_ada)
{n0873, n0872, n0871, n0870} <= acc;
if (acc_adac)
{n0873, n0872, n0871, n0870} <= ~acc;
end
// Carry generator
wire n0546 = ~(inc_group_5 | n0342);
reg n0550;
always @(posedge sysclk) begin
if (m12) n0550 <= 1'b0;
if (n0546) n0550 <= 1'b1;
if (cy_adac) n0550 <= ~cy;
if (cy_ada) n0550 <= cy;
end
wire n0911 = ~(n0550 ? (n0887 | n0870) : (n0887 & n0870));
wire n0553 = n0911;
wire n0912 = ~(n0553 ? (n0889 | n0871) : (n0889 & n0871));
wire n0556 = n0912;
wire n0913 = ~(n0556 ? (n0891 | n0872) : (n0891 & n0872));
wire n0559 = n0913;
wire n0914 = ~(n0559 ? (n0893 | n0873) : (n0893 & n0873));
wire n0861 = n0914;
// Adder
wire n0877 = ~((n0893 & n0559 & n0873) | (n0861 & (n0893 | n0873 | n0559)));
wire n0878 = ~((n0877 & n0550 & n0870) | (n0553 & (n0887 | n0870 | n0550)));
wire n0875 = ~((n0889 & n0553 & n0871) | (n0556 & (n0889 | n0871 | n0553)));
wire n0879 = ~((n0891 & n0556 & n0872) | (n0559 & (n0891 | n0872 | n0556)));
wire n0846 = ~n0878;
wire n0847 = n0875;
wire n0848 = ~n0879;
wire n0514 = n0877;
// Shifter / Accumulator and Carry
reg [3:0] acc_out; // {n0356, n0348, n0347, n0346}
wire n0803 = ~((acc_out[3] & (acc_out[2] | acc_out[1])) | cy_1);
wire n0403 = ~(~daa | n0803);
wire [3:0] acc_in = {n0514, n0848, n0847, n0846};
always @(posedge sysclk) begin
if (adsr)
{acc, cy} <= {cy_1, acc_in};
if (add_acc)
acc <= acc_in;
if (adsl)
{cy, acc} <= {acc_in, cy_1};
if (adc_cy)
cy <= n0861;
if (n0403 & n0415)
cy <= 1'b1;
// Dynamic refresh would occur during M12
end
// Accumulator output latch
always @(posedge sysclk) begin
if (n0854) begin
cy_1 <= cy;
acc_out <= acc;
end
end
assign acc_0 = ~|acc_out;
assign add_0 = ~|acc_in;
// Keyboard Process logic
wire n0378 = ~((daa & n0803) | o_ib);
wire n0345 = kbp & (acc_out == 4'b1000);
wire n0354 = kbp & (acc_out == 4'b0100);
wire n0363 = kbp & (acc_out == 4'b0010);
wire n0370 = kbp & (acc_out == 4'b0001);
wire n0377 = (kbp & (acc_out == 4'b0000)) | ~n0378;
wire n0358 = ~(n0345 | n0354 | n0363 | n0370 | n0377 | n0403);
wire n0366 = ~( n0354 | n0363 | n0370 | n0377 | tcs );
wire n0359 = ~(n0345 | n0370 | n0377 | tcs );
wire n0357 = ~(n0345 | n0363 | n0377 | n0403);
// Data output mux
reg [3:0] dout;
always @(*) begin
dout = 4'bzzzz;
if (acb_ib)
dout = acc_out;
if (add_ib)
dout = acc_in;
if (cy_ib)
dout = {3'bxxx, cy_1};
if (n0415)
dout = {n0358, n0366, n0359, n0357};
end
assign data = dout;
// Generate CMROM / CMRAMn
// This may get moved to the Timing & I/O board
// Inputs: {n0355, n0364, n0371}, n0351, poc, com_n
wire n0355 = ~acc_out[2];
wire n0364 = ~acc_out[1];
wire n0371 = ~acc_out[0];
reg n0749, n0750, n0751;
always @(posedge sysclk) begin
if (poc) begin
n0749 <= 1'b1;
n0750 <= 1'b1;
n0751 <= 1'b1;
end
else begin
if (n0351) begin
n0749 <= n0355;
n0750 <= n0364;
n0751 <= n0371;
end
end
end
assign cmram3 = ~(com_n | n0749);
assign cmram2 = ~(com_n | n0750);
assign cmram1 = ~(com_n | n0751);
assign cmram0 = ~(com_n | ~n0749 | ~n0750 | ~n0751);
assign cmrom = ~(com_n | poc);
endmodule
|
tt06-finale_0082
|
tt06-finale
|
noritsuna-tt06-tt_um_i4004
|
task_counter
|
tt_um_noritsuna_i4004
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module tt_um_noritsuna_i4004 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena,
input wire clk,
input wire rst_n
);
wire sysclk;
wire clk1_pad;
wire clk2_pad;
wire poc_pad;
wire test_pad;
wire [3:0] data_in_pad;
wire [3:0] data_out_pad;
wire cmrom_pad;
wire cmram0_pad;
wire cmram1_pad;
wire cmram2_pad;
wire cmram3_pad;
wire sync_pad;
//input:
assign sysclk = clk;
assign data_in_pad = ui_in[3:0];
assign clk1_pad = ui_in[4];
assign clk2_pad = ui_in[5];
assign poc_pad = ui_in[6];
assign test_pad = ui_in[7];
//output:
assign cmrom_pad = uo_out[0];
assign cmram0_pad = uo_out[1];
assign cmram1_pad = uo_out[2];
assign cmram2_pad = uo_out[3];
assign cmram3_pad = uo_out[4];
assign sync_pad = uo_out[5];
assign uio_oe[3:0] = 1;
assign data_out_pad = uio_out[3:0];
// All output pins must be assigned. If not used, assign to 0.
assign uo_out[6] = 0;
assign uo_out[7] = 0;
assign uio_out[7:4] = 0;
assign uio_oe[7:4] = 0;
// Common BiDir data bus
wire [3:0] data;
// Timing and I/O Board Outputs
wire clk1;
wire clk2;
wire a12;
wire a22;
wire a32;
wire m12;
wire m22;
wire x12;
wire x22;
wire x32;
wire gate;
wire poc; // Clean POC_PAD
wire n0432; // Clean TEST_PAD
// Outputs from the Instruction Decode board
wire jcn_isz;
wire jin_fin;
wire jun_jms;
wire cn_n;
wire bbl;
wire jms;
wire sc;
wire dc;
wire sc_m22_clk2;
wire fin_fim_src_jin;
wire inc_isz_add_sub_xch_ld;
wire inc_isz_xch;
wire opa0_n;
wire cma;
wire write_acc_1;
wire write_carry_2;
wire read_acc_3;
wire add_group_4;
wire inc_group_5;
wire sub_group_6;
wire ior;
wire iow;
wire ral;
wire rar;
wire ope_n;
wire daa;
wire dcl;
wire inc_isz;
wire kbp;
wire o_ib;
wire tcs;
wire xch;
wire n0342;
wire x21_clk2;
wire x31_clk2;
wire com_n;
// Outputs from the ALU board
wire acc_0;
wire add_0;
wire cy_1;
wire cmram0;
wire cmram1;
wire cmram2;
wire cmram3;
wire cmrom;
// Instantiate the Timing and I/O board
timing_io tio_board (
.sysclk(sysclk),
.clk1_pad(clk1_pad),
.clk2_pad(clk2_pad),
.poc_pad(poc_pad),
.ior(ior),
.clk1(clk1),
.clk2(clk2),
.a12(a12),
.a22(a22),
.a32(a32),
.m12(m12),
.m22(m22),
.x12(x12),
.x22(x22),
.x32(x32),
.gate(gate),
.poc(poc),
.data(data),
.data_in_pad(data_in_pad),
.data_out_pad(data_out_pad),
.test_pad(test_pad),
.n0432(n0432),
.sync_pad(sync_pad),
.cmrom(cmrom),
.cmrom_pad(cmrom_pad),
.cmram0(cmram0),
.cmram0_pad(cmram0_pad),
.cmram1(cmram1),
.cmram1_pad(cmram1_pad),
.cmram2(cmram2),
.cmram2_pad(cmram2_pad),
.cmram3(cmram3),
.cmram3_pad(cmram3_pad)
);
// Instantiate the Instruction Decode board
instruction_decode id_board (
.sysclk(clk),
.clk1(clk1),
.clk2(clk2),
.a22(a22),
.m12(m12),
.m22(m22),
.x12(x12),
.x22(x22),
.x32(x32),
.poc(poc),
.n0432(n0432),
.data(data),
.jcn_isz(jcn_isz),
.jin_fin(jin_fin),
.jun_jms(jun_jms),
.cn_n(cn_n),
.bbl(bbl),
.jms(jms),
.sc(sc),
.dc(dc),
.sc_m22_clk2(sc_m22_clk2),
.fin_fim_src_jin(fin_fim_src_jin),
.inc_isz_add_sub_xch_ld(inc_isz_add_sub_xch_ld),
.inc_isz_xch(inc_isz_xch),
.opa0_n(opa0_n),
.acc_0(acc_0),
.add_0(add_0),
.cy_1(cy_1),
.cma(cma),
.write_acc_1(write_acc_1),
.write_carry_2(write_carry_2),
.read_acc_3(read_acc_3),
.add_group_4(add_group_4),
.inc_group_5(inc_group_5),
.sub_group_6(sub_group_6),
.ior(ior),
.iow(iow),
.ral(ral),
.rar(rar),
.ope_n(ope_n),
.daa(daa),
.dcl(dcl),
.inc_isz(inc_isz),
.kbp(kbp),
.o_ib(o_ib),
.tcs(tcs),
.xch(xch),
.n0342(n0342),
.x21_clk2(x21_clk2),
.x31_clk2(x31_clk2),
.com_n(com_n)
);
// Instantiate the ALU board
alu alu_board (
.sysclk(clk),
.a12(a12),
.m12(m12),
.x12(x12),
.poc(poc),
.data(data),
.acc_0(acc_0),
.add_0(add_0),
.cy_1(cy_1),
.cma(cma),
.write_acc_1(write_acc_1),
.write_carry_2(write_carry_2),
.read_acc_3(read_acc_3),
.add_group_4(add_group_4),
.inc_group_5(inc_group_5),
.sub_group_6(sub_group_6),
.ior(ior),
.iow(iow),
.ral(ral),
.rar(rar),
.ope_n(ope_n),
.daa(daa),
.dcl(dcl),
.inc_isz(inc_isz),
.kbp(kbp),
.o_ib(o_ib),
.tcs(tcs),
.xch(xch),
.n0342(n0342),
.x21_clk2(x21_clk2),
.x31_clk2(x31_clk2),
.com_n(com_n),
.cmram0(cmram0),
.cmram1(cmram1),
.cmram2(cmram2),
.cmram3(cmram3),
.cmrom(cmrom)
);
// Instantiate the Instruction Pointer board
instruction_pointer ip_board (
.sysclk(clk),
.clk1(clk1),
.clk2(clk2),
.a12(a12),
.a22(a22),
.a32(a32),
.m12(m12),
.m22(m22),
.x12(x12),
.x22(x22),
.x32(x32),
.poc(poc),
.m12_m22_clk1_m11_m12(gate),
.data(data),
.jcn_isz(jcn_isz),
.jin_fin(jin_fin),
.jun_jms(jun_jms),
.cn_n(cn_n),
.bbl(bbl),
.jms(jms),
.sc(sc),
.dc(dc)
);
// Instantiate the Scratchpad board
scratchpad sp_board (
.sysclk(clk),
.clk1(clk1),
.clk2(clk2),
.a12(a12),
.a22(a22),
.a32(a32),
.m12(m12),
.m22(m22),
.x12(x12),
.x22(x22),
.x32(x32),
.poc(poc),
.m12_m22_clk1_m11_m12(gate),
.data(data),
.sc_m22_clk2(sc_m22_clk2),
.fin_fim_src_jin(fin_fim_src_jin),
.inc_isz_add_sub_xch_ld(inc_isz_add_sub_xch_ld),
.inc_isz_xch(inc_isz_xch),
.opa0_n(opa0_n),
.sc(sc),
.dc(dc)
);
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module alu(
input wire sysclk,
// Inputs from the Timing and I/O board
input wire a12,
input wire m12,
input wire x12,
input wire poc,
// Common 4-bit data bus
inout wire [3:0] data,
// Outputs to the Instruction Decode board
output wire acc_0,
output wire add_0,
output reg cy_1,
// Inputs from the Instruction Decode board
input wire cma,
input wire write_acc_1,
input wire write_carry_2,
input wire read_acc_3,
input wire add_group_4,
input wire inc_group_5,
input wire sub_group_6,
input wire ior,
input wire iow,
input wire ral,
input wire rar,
input wire ope_n,
input wire daa,
input wire dcl,
input wire inc_isz,
input wire kbp,
input wire o_ib,
input wire tcs,
input wire xch,
input wire n0342,
input wire x21_clk2,
input wire x31_clk2,
input wire com_n,
// Outputs to external pins
output wire cmram0,
output wire cmram1,
output wire cmram2,
output wire cmram3,
output wire cmrom
);
reg [3:0] acc;
reg cy;
// Decode logic
wire n0854 = ~(~x12);
wire n0351 = ~(x21_clk2 | ~dcl);
wire n0415 = ~(x21_clk2 | ope_n);
wire add_ib = ~(x31_clk2 | ~inc_isz);
wire cy_ib = ~(x31_clk2 | ~iow);
wire acb_ib = ~((x31_clk2 | ~xch) & (x21_clk2 | ~iow));
wire n0477 = ~((~x31_clk2 & ~ior) | (a12 & ior));
wire adc_cy = ~(write_carry_2 | n0477);
wire add_acc = ~(write_acc_1 | n0477);
wire adsr = ~(x31_clk2 | ~rar);
wire adsl = ~(x31_clk2 | ~ral);
wire acc_adac = ~(~cma | n0342);
wire acc_ada = ~(read_acc_3 | n0342);
wire cy_ada = ~(add_group_4 | n0342);
wire cy_adac = ~(sub_group_6 | n0342);
// Latch the incoming data bus
reg [3:0] tmp; // It's the name used in simulator!
always @(posedge sysclk) begin
if (~n0342)
tmp <= data;
if (m12)
tmp <= 4'b1111;
end
// Invert some of the incoming data
reg n0893, n0891, n0889, n0887; // D3, D2, D1, D0
always @(posedge sysclk) begin
if (sub_group_6) begin
n0887 <= tmp[0];
n0889 <= ~tmp[1];
n0891 <= tmp[2];
n0893 <= ~tmp[3];
end
if (~(sub_group_6 | m12)) begin
n0887 <= ~tmp[0];
n0889 <= tmp[1];
n0891 <= ~tmp[2];
n0893 <= tmp[3];
end
end
// Feedback from Accumulator
reg n0873, n0872, n0871, n0870;
always @(posedge sysclk) begin
if (m12)
{n0873, n0872, n0871, n0870} <= 4'b1010;
if (acc_ada)
{n0873, n0872, n0871, n0870} <= acc;
if (acc_adac)
{n0873, n0872, n0871, n0870} <= ~acc;
end
// Carry generator
wire n0546 = ~(inc_group_5 | n0342);
reg n0550;
always @(posedge sysclk) begin
if (m12) n0550 <= 1'b0;
if (n0546) n0550 <= 1'b1;
if (cy_adac) n0550 <= ~cy;
if (cy_ada) n0550 <= cy;
end
wire n0911 = ~(n0550 ? (n0887 | n0870) : (n0887 & n0870));
wire n0553 = n0911;
wire n0912 = ~(n0553 ? (n0889 | n0871) : (n0889 & n0871));
wire n0556 = n0912;
wire n0913 = ~(n0556 ? (n0891 | n0872) : (n0891 & n0872));
wire n0559 = n0913;
wire n0914 = ~(n0559 ? (n0893 | n0873) : (n0893 & n0873));
wire n0861 = n0914;
// Adder
wire n0877 = ~((n0893 & n0559 & n0873) | (n0861 & (n0893 | n0873 | n0559)));
wire n0878 = ~((n0877 & n0550 & n0870) | (n0553 & (n0887 | n0870 | n0550)));
wire n0875 = ~((n0889 & n0553 & n0871) | (n0556 & (n0889 | n0871 | n0553)));
wire n0879 = ~((n0891 & n0556 & n0872) | (n0559 & (n0891 | n0872 | n0556)));
wire n0846 = ~n0878;
wire n0847 = n0875;
wire n0848 = ~n0879;
wire n0514 = n0877;
// Shifter / Accumulator and Carry
reg [3:0] acc_out; // {n0356, n0348, n0347, n0346}
wire n0803 = ~((acc_out[3] & (acc_out[2] | acc_out[1])) | cy_1);
wire n0403 = ~(~daa | n0803);
wire [3:0] acc_in = {n0514, n0848, n0847, n0846};
always @(posedge sysclk) begin
if (adsr)
{acc, cy} <= {cy_1, acc_in};
if (add_acc)
acc <= acc_in;
if (adsl)
{cy, acc} <= {acc_in, cy_1};
if (adc_cy)
cy <= n0861;
if (n0403 & n0415)
cy <= 1'b1;
// Dynamic refresh would occur during M12
end
// Accumulator output latch
always @(posedge sysclk) begin
if (n0854) begin
cy_1 <= cy;
acc_out <= acc;
end
end
assign acc_0 = ~|acc_out;
assign add_0 = ~|acc_in;
// Keyboard Process logic
wire n0378 = ~((daa & n0803) | o_ib);
wire n0345 = kbp & (acc_out == 4'b1000);
wire n0354 = kbp & (acc_out == 4'b0100);
wire n0363 = kbp & (acc_out == 4'b0010);
wire n0370 = kbp & (acc_out == 4'b0001);
wire n0377 = (kbp & (acc_out == 4'b0000)) | ~n0378;
wire n0358 = ~(n0345 | n0354 | n0363 | n0370 | n0377 | n0403);
wire n0366 = ~( n0354 | n0363 | n0370 | n0377 | tcs );
wire n0359 = ~(n0345 | n0370 | n0377 | tcs );
wire n0357 = ~(n0345 | n0363 | n0377 | n0403);
// Data output mux
reg [3:0] dout;
always @(*) begin
dout = 4'bzzzz;
if (acb_ib)
dout = acc_out;
if (add_ib)
dout = acc_in;
if (cy_ib)
dout = {3'bxxx, cy_1};
if (n0415)
dout = {n0358, n0366, n0359, n0357};
end
assign data = dout;
// Generate CMROM / CMRAMn
// This may get moved to the Timing & I/O board
// Inputs: {n0355, n0364, n0371}, n0351, poc, com_n
wire n0355 = ~acc_out[2];
wire n0364 = ~acc_out[1];
wire n0371 = ~acc_out[0];
reg n0749, n0750, n0751;
always @(posedge sysclk) begin
if (poc) begin
n0749 <= 1'b1;
n0750 <= 1'b1;
n0751 <= 1'b1;
end
else begin
if (n0351) begin
n0749 <= n0355;
n0750 <= n0364;
n0751 <= n0371;
end
end
end
assign cmram3 = ~(com_n | n0749);
assign cmram2 = ~(com_n | n0750);
assign cmram1 = ~(com_n | n0751);
assign cmram0 = ~(com_n | ~n0749 | ~n0750 | ~n0751);
assign cmrom = ~(com_n | poc);
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module counter(
input wire sysclk,
input wire step_a,
input wire step_b,
output reg q = 1'b0
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module instruction_decode(
input wire sysclk, // 50 MHz FPGA clock
// Inputs from the Timing and I/O board
input wire clk1,
input wire clk2,
input wire a22,
input wire m12,
input wire m22,
input wire x12,
input wire x22,
input wire x32,
input wire poc, // Power-On Clear (reset)
input wire n0432, // Conditioned TEST_PAD
// Common 4-bit data bus
inout wire [3:0] data,
// These drive the Instruction Pointer (IP) board
output wire jcn_isz, // JCN+ISZ
output wire jin_fin, // JIN+FIN
output wire jun_jms, // JUN+JMS
output wire cn_n, // ~CN
output wire bbl, // BBL
output wire jms, // JMS
// Outputs to both the IP and SP boards
output wire sc, // SC (Single Cycle)
output wire dc, // DC (Double Cycle, ~SC)
// Outputs to the Scratch Pad (SP) board
output wire sc_m22_clk2, // SC&M22&CLK2
output wire fin_fim_src_jin, // FIN+FIM+SRC+JIN
output wire inc_isz_add_sub_xch_ld, // INC+ISZ+ADD+SUB+XCH+LD
output wire inc_isz_xch, // INC+ISZ+XCH
output wire opa0_n, // ~OPA.0
// Inputs from the ALU board (condition bits)
input wire acc_0, // ACC_0
input wire add_0, // ADD_0
input wire cy_1, // CY_1
// Outputs to the Arithmetic Logic Unit (ALU) board
output wire cma,
output wire write_acc_1,
output wire write_carry_2,
output wire read_acc_3,
output wire add_group_4,
output wire inc_group_5,
output wire sub_group_6,
output wire ior,
output wire iow,
output wire ral,
output wire rar,
output wire ope_n,
output wire daa,
output wire dcl,
output wire inc_isz,
output wire kbp,
output wire o_ib,
output wire tcs,
output wire xch,
output wire n0342,
output wire x21_clk2,
output wire x31_clk2,
output wire com_n
);
wire sc_m12_clk2 = sc & m12 & clk2;
assign sc_m22_clk2 = sc & m22 & clk2;
// Latch the first 4 bits of the opcode
reg [3:0] opr = 4'b0000;
always @(posedge sysclk) begin
if (sc_m12_clk2)
opr <= data;
end
// Latch the second 4 bits of the opcode
reg [3:0] opa = 4'b0000;
always @(posedge sysclk) begin
if (sc_m22_clk2)
opa <= data;
end
assign opa0_n = ~opa[0];
// Full OPR Decoding
wire nop = (opr == 4'b0000);
wire jcn = (opr == 4'b0001);
wire fim_src = (opr == 4'b0010);
assign jin_fin = (opr == 4'b0011);
wire jun = (opr == 4'b0100);
assign jms = (opr == 4'b0101);
wire inc = (opr == 4'b0110);
wire isz = (opr == 4'b0111);
wire add = (opr == 4'b1000);
wire sub = (opr == 4'b1001);
wire ld = (opr == 4'b1010);
assign xch = (opr == 4'b1011);
assign bbl = (opr == 4'b1100);
wire ldm = (opr == 4'b1101);
wire io = (opr == 4'b1110);
wire ope = (opr == 4'b1111);
assign ope_n = ~ope;
assign jcn_isz = jcn | isz;
assign jun_jms = jun | jms;
wire ldm_bbl = ldm | bbl;
assign inc_isz = (inc | isz) & sc;
assign inc_isz_xch = inc | isz | xch;
assign inc_isz_add_sub_xch_ld = inc | isz | add | sub | xch | ld;
assign fin_fim_src_jin = fim_src | jin_fin;
// OPE: OPA Decoding
assign o_ib = ope & (opa[3] == 1'b0);
wire clb = ope & (opa == 4'b0000);
wire clc = ope & (opa == 4'b0001);
wire iac = ope & (opa == 4'b0010);
wire cmc = ope & (opa == 4'b0011);
assign cma = ope & (opa == 4'b0100);
assign ral = ope & (opa == 4'b0101);
assign rar = ope & (opa == 4'b0110);
wire tcc = ope & (opa == 4'b0111);
wire dac = ope & (opa == 4'b1000);
assign tcs = ope & (opa == 4'b1001);
wire stc = ope & (opa == 4'b1010);
assign daa = ope & (opa == 4'b1011);
assign kbp = ope & (opa == 4'b1100);
assign dcl = ope & (opa == 4'b1101);
// IO: OPA Decoding
assign iow = io & (opa[3] == 1'b0);
assign ior = io & (opa[3] == 1'b1);
wire adm = io & (opa == 4'b1011);
wire sbm = io & (opa == 4'b1000);
wire fin_fim = fin_fim_src_jin & ~opa[0];
wire src = fim_src & opa[0];
assign write_acc_1 = ~(kbp | tcs | daa | xch | poc | cma | tcc | dac | iac |
clb | ior | ld | sub | add | ldm_bbl);
assign write_carry_2 = ~(tcs | poc | tcc | stc | cmc | dac | iac |
clc | clb | sbm | adm | sub | add);
assign read_acc_3 = ~(daa | rar | ral | dac | iac | sbm | adm | sub | add);
assign add_group_4 = ~(tcs | tcc | adm | add);
assign inc_group_5 = ~(inc_isz | stc | iac);
assign sub_group_6 = ~(cmc | sbm | sub | m12);
// The Condition Flip-Flop
reg n0397;
wire n0486 = ~((opa[2] & acc_0) | (opa[1] & cy_1) | (opa[0] & n0432));
wire n0419 = ~((add_0 & ~isz) & (~jcn | ((~n0486 | opa[3]) & (n0486 | ~opa[3]))));
wire n0413 = ~((sc & n0419 & x32) | (~x32 | n0397));
reg n0405;
always @(posedge sysclk) begin
if (clk2)
n0405 <= n0413;
if (clk1)
n0397 <= ~n0405;
end
assign cn_n = ~n0397;
// The Single-Cycle Flip-Flop
reg n0343;
wire n0368 = ~((sc & (fin_fim | jcn_isz | jun_jms) & x32) | (n0343 & ~x32));
reg n0362;
always @(posedge sysclk) begin
if (clk2)
n0362 <= n0368;
if (clk1)
n0343 <= ~n0362;
end
assign sc = ~n0343;
assign dc = ~sc;
// Generate ~(X21&~CLK2)
reg n0360;
always @(posedge sysclk) begin
if (clk2)
n0360 <= ~x12;
end
wire n0337 = ~(n0360 | clk2);
assign x21_clk2 = ~n0337;
// Generate ~(X31&~CLK2)
reg n0380;
always @(posedge sysclk) begin
if (clk2)
n0380 <= ~x22;
end
wire n0375 = ~(n0380 | clk2);
assign x31_clk2 = ~n0375;
// Generate ~COM
wire n0329 = io;
reg n0414, n0797;
always @(posedge sysclk) begin
if (clk2)
n0414 <= a22;
else
n0797 <= n0414;
end
reg n0433, n0801;
always @(posedge sysclk) begin
if (clk2)
n0433 <= m12;
else
n0801 <= n0433;
end
reg n0425, n0805;
always @(posedge sysclk) begin
if (clk2)
n0425 <= x12;
else
n0805 <= n0425;
end
wire n0782 = ~((n0801 & n0329) | (src & n0805) | n0797);
assign com_n = n0782;
// Generate N0342
wire n0332 = ~(((n0329 | poc) & x22 & clk2) | (~(n0329 | poc) & n0337 & clk1));
assign n0342 = n0332;
// Output OPA onto the data bus
wire opa_ib = (ldm_bbl | jun_jms) & ~x21_clk2;
assign data = opa_ib ? opa : 4'bzzzz;
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module instruction_pointer (
input wire sysclk, // 50 MHz FPGA clock
// Inputs from the Timing and I/O board
input wire clk1,
input wire clk2,
input wire a12,
input wire a22,
input wire a32,
input wire m12,
input wire m22,
input wire x12,
input wire x22,
input wire x32,
input wire poc, // Power-On Clear (reset)
input wire m12_m22_clk1_m11_m12, // M12+M22+CLK1~(M11+M12)
// Common 4-bit data bus
inout wire [3:0] data,
// Inputs from the Instruction Decode board
input wire jcn_isz, // JCN+ISZ
input wire jin_fin, // JIN+FIN
input wire jun_jms, // JUN+JMS
input wire cn_n, // ~CN
input wire bbl, // BBL
input wire jms, // JMS
input wire sc, // SC (Single Cycle)
input wire dc // DC (Double Cycle, ~SC)
);
reg [11:0] dram_array [0:3];
reg [11:0] dram_temp;
wire [3:0] din_n;
wire inh = (jin_fin & sc) | ((jun_jms | (jcn_isz & ~cn_n)) & dc);
// Row Counter stuff
wire [1:0] addr_ptr; // Effective Address counter
wire addr_ptr_step; // CLK2(JMS&DC&M22+BBL(M22+X12+X22))
assign addr_ptr_step = ~(~clk2 | ~(((m22 | x12 | x22) & bbl) |
(m22 & dc & jms)));
counter addr_ptr_0 (
.sysclk(sysclk),
.step_a(clk1),
.step_b(addr_ptr_step),
.q(addr_ptr[0])
);
counter addr_ptr_1 (
.sysclk(sysclk),
.step_a( addr_ptr[0]),
.step_b(~addr_ptr[0]),
.q(addr_ptr[1])
);
// Refresh counter stuff
wire [1:0] addr_rfsh; // Row Refresh counter
wire addr_rfsh_step; // (~INH)&X32&CLK2
assign addr_rfsh_step = ~inh & x32 & clk2;
counter addr_rfsh_0 (
.sysclk(sysclk),
.step_a(clk1),
.step_b(addr_rfsh_step),
.q(addr_rfsh[0])
);
counter addr_rfsh_1 (
.sysclk(sysclk),
.step_a( addr_rfsh[0]),
.step_b(~addr_rfsh[0]),
.q(addr_rfsh[1])
);
// Row selection mux
reg [1:0] row; // {N0409, N0420}
always @(posedge sysclk) begin
if (x12)
row <= addr_rfsh;
if (x32)
row <= addr_ptr;
end
// Row Precharge/Read/Write stuff
wire precharge; // (~INH)(X11+X31)CLK1
wire row_read; // (~POC)CLK2(X12+X32)~INH
wire row_write; // ((~SC)(JIN+FIN))CLK1(M11+X21~INH)
reg n0517;
always @(posedge sysclk) begin
if (clk2)
n0517 <= ~(m22 | x22);
end
assign precharge = ~(n0517 | inh | ~clk1);
assign row_read = ~poc & clk2 & (x12 | x32) & ~inh;
reg n0438;
always @(posedge sysclk) begin
if (clk2)
n0438 <= ~((x12 & ~inh) | a32);
end
assign row_write = ~(n0438 | (jin_fin & ~sc) | ~clk1);
// Column Read selection stuff
reg n0416;
always @(posedge sysclk) begin
if (clk2)
n0416 <= ~x32;
end
wire radb0 = ~(n0416 | clk2);
reg n0384;
always @(posedge sysclk) begin
if (clk2)
n0384 <= ~a12;
end
wire radb1 = ~(n0384 | clk2);
reg n0374;
always @(posedge sysclk) begin
if (clk2)
n0374 <= ~a22;
end
wire radb2 = ~(n0374 | clk2);
// Column Write selection stuff
wire n0322 = ~(sc | cn_n);
wire wadb0 = ~(~clk2 | ~(a12 | (sc & jin_fin & x32) |
(((jcn_isz & n0322) | (jun_jms & ~sc)) & m22)));
wire wadb1 = ~(~clk2 | ~(a22 | (sc & jin_fin & x22) |
(((jcn_isz & n0322) | (jun_jms & ~sc)) & m12)));
wire wadb2 = ~(~clk2 | ~(a32 | (jun_jms & ~sc & x22)));
// Manage the row data buffer
always @(posedge sysclk) begin
if (precharge)
dram_temp <= 12'b0;
if (row_read)
dram_temp <= dram_array[row];
if (wadb0)
dram_temp[ 3:0] <= ~din_n;
if (wadb1)
dram_temp[ 7:4] <= ~din_n;
if (wadb2)
dram_temp[11:8] <= ~din_n;
end
// Handle row writes
always @(posedge sysclk) begin
if (row_write)
dram_array[row] <= dram_temp;
end
// Manage the data output mux
reg [3:0] dout;
always @* begin
(* PARALLEL_CASE *)
case (1'b1)
radb0: dout = dram_temp[ 3:0];
radb1: dout = dram_temp[ 7:4];
radb2: dout = dram_temp[11:8];
default: dout = 4'bzzzz;
endcase
end
assign data = dout;
// Data In mux and incrementer
reg [3:0] incr_in;
always @(posedge sysclk) begin
if (m12_m22_clk1_m11_m12)
incr_in <= data;
end
reg carry_out, carry_in;
wire [4:0] incr_out = (a12 | ((a22 | a32) & carry_in)) ?
(incr_in + 4'b0001) : {1'b0, incr_in};
always @(posedge sysclk) begin
if (clk2)
carry_out <= incr_out[4];
if (clk1)
carry_in <= carry_out;
end
assign din_n = ~incr_out[3:0];
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module scratchpad (
input wire sysclk, // 50 MHz FPGA clock
// Inputs from the Timing and I/O board
input wire clk1,
input wire clk2,
input wire a12,
input wire a22,
input wire a32,
input wire m12,
input wire m22,
input wire x12,
input wire x22,
input wire x32,
input wire poc, // Power-On Clear (reset)
input wire m12_m22_clk1_m11_m12, // M12+M22+CLK1~(M11+M12)
// Common 4-bit data bus
inout wire [3:0] data,
// Inputs from the Instruction Decode board
input wire sc_m22_clk2, // SC&M22&CLK2
input wire fin_fim_src_jin, // FIN+FIM+SRC+JIN
input wire inc_isz_add_sub_xch_ld, // INC+ISZ+ADD+SUB+XCH+LD
input wire inc_isz_xch, // INC+ISZ+XCH
input wire opa0_n, // ~OPA.0
input wire sc, // SC (Single Cycle)
input wire dc // DC (Double Cycle, ~SC)
);
reg [7:0] dram_array [0:7];
reg [7:0] dram_temp;
reg [3:0] din_n;
// Refresh counter stuff
wire [2:0] reg_rfsh; // Row Refresh counter
wire reg_rfsh_step; // SC&A12&CLK2
assign reg_rfsh_step = sc & a12 & clk2;
counter reg_rfsh_0 (
.sysclk(sysclk),
.step_a(clk1),
.step_b(reg_rfsh_step),
.q(reg_rfsh[0])
);
counter reg_rfsh_1 (
.sysclk(sysclk),
.step_a( reg_rfsh[0]),
.step_b(~reg_rfsh[0]),
.q(reg_rfsh[1])
);
counter reg_rfsh_2 (
.sysclk(sysclk),
.step_a( reg_rfsh[1]),
.step_b(~reg_rfsh[1]),
.q(reg_rfsh[2])
);
// Row selection mux
reg [2:0] row; // {N0646, N0617, N0582}
always @(posedge sysclk) begin
if (sc & a22)
row <= reg_rfsh;
if (sc_m22_clk2)
row <= data[3:1];
end
// Row Precharge/Read/Write stuff
wire precharge; // SC(A22+M22)CLK2
wire row_read; // (~POC)&CLK2&SC(A32+X12)
wire row_write; // CLK2&SC(A12+M12)
assign precharge = sc & (a22 | m22) & clk2;
assign row_read = ~(poc | ~(clk2 & sc & (a32 | x12)));
assign row_write = sc & (a12 | m12) & clk2;
// Column Read selection stuff
reg n0615;
always @(posedge sysclk) begin
if (clk2)
n0615 <= ~(x12 & (fin_fim_src_jin |
(opa0_n & inc_isz_add_sub_xch_ld)));
end
wire rrab0 = ~(dc | n0615 | clk2);
reg n0592;
always @(posedge sysclk) begin
if (clk2)
n0592 <= ~((x22 & fin_fim_src_jin) |
(~opa0_n & x12 & inc_isz_add_sub_xch_ld));
end
wire rrab1 = ~(dc | n0592 | clk2);
// Column Write selection stuff
wire n0564 = opa0_n & fin_fim_src_jin & dc;
wire n0568 = inc_isz_xch & x32 & sc;
wire wrab0 = clk2 & ((m12 & n0564) | ( opa0_n & n0568));
wire wrab1 = clk2 & ((m22 & n0564) | (~opa0_n & n0568));
// Manage the row data buffer
always @(posedge sysclk) begin
if (precharge)
dram_temp <= 8'b0;
if (row_read)
dram_temp <= dram_array[row];
if (wrab0)
dram_temp[ 3:0] <= ~din_n;
if (wrab1)
dram_temp[ 7:4] <= ~din_n;
end
// Handle row writes
always @(posedge sysclk) begin
if (row_write)
dram_array[row] <= dram_temp;
end
// Manage the data output mux
reg [3:0] dout;
always @* begin
(* PARALLEL_CASE *)
case (1'b1)
rrab0: dout = dram_temp[ 3:0];
rrab1: dout = dram_temp[ 7:4];
default: dout = 4'bzzzz;
endcase
end
assign data = dout;
// Data In latch
always @(posedge sysclk) begin
if (m12_m22_clk1_m11_m12)
din_n <= ~data;
end
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module timing_io(
input wire sysclk,
input wire clk1_pad,
input wire clk2_pad,
input wire poc_pad,
input wire ior,
// Timing and I/O Board Outputs
output wire clk1,
output wire clk2,
output wire a12,
output wire a22,
output wire a32,
output wire m12,
output wire m22,
output wire x12,
output wire x22,
output wire x32,
output wire gate,
output reg poc,
// External I/O Pad conditioning
inout wire [3:0] data,
inout wire [3:0] data_in_pad,
output wire [3:0] data_out_pad,
input wire test_pad,
output reg n0432,
output reg sync_pad,
input wire cmrom,
output wire cmrom_pad,
input wire cmram0,
output wire cmram0_pad,
input wire cmram1,
output wire cmram1_pad,
input wire cmram2,
output wire cmram2_pad,
input wire cmram3,
output wire cmram3_pad
);
// Simple pass-throughs
assign clk1 = clk1_pad;
assign clk2 = clk2_pad;
assign cmrom_pad = cmrom;
assign cmram0_pad = cmram0;
assign cmram1_pad = cmram1;
assign cmram2_pad = cmram2;
assign cmram3_pad = cmram3;
// Generate the 8 execution phase indicators
reg [0:7] master = 8'h00;
reg [0:7] slave = 8'h00;
always @(posedge sysclk) begin
if (clk2)
master <= {~|slave[0:6], slave[0:6]};
else
sync_pad <= master[7];
if (clk1)
slave <= master;
end
assign a12 = slave[0];
assign a22 = slave[1];
assign a32 = slave[2];
assign m12 = slave[3];
assign m22 = slave[4];
assign x12 = slave[5];
assign x22 = slave[6];
assign x32 = slave[7];
// Generate the DRAM Input Gate signal
// Properly called M12+M22+CLK1~(M11&M12)
wire n0279 = ~(a32 | m12);
reg n0278;
always @(posedge sysclk) begin
if (clk2)
n0278 <= n0279;
end
wire n0708 = ~((n0278 & clk1) | m12 | m22);
assign gate = ~n0708;
// Generate a clean POC signal
always @(posedge sysclk) begin
if (poc_pad) poc <= 1'b1;
else if (a12) poc <= 1'b0;
else poc <= poc;
end
// Generate a clean ~TEST signal (n0432)
always @(posedge sysclk) begin
n0432 <= ~test_pad;
end
// Manage the Data I/O pads
reg L;
always @(posedge sysclk) begin
if (clk2)
L <= a32 | m12 | (x12 & (ior | poc));
end
wire n0702 = ~clk2;
reg n0685;
reg n0699;
reg n0707;
always @(posedge sysclk) begin
if (clk1) begin
n0685 <= ~L;
n0707 <= L;
end
if (n0702)
n0699 <= ~L;
end
wire n0700 = n0707 | (L & n0702) | poc;
wire n0659 = (clk2 & n0685) | (clk1 & L);
wire n0676 = clk1 | n0685 | n0699;
// Incoming data from the external pads
reg [3:0] data_in;
always @* begin
if (n0659) data_in = 4'b1111;
else if (n0676) data_in = 4'bzzzz;
else if (poc) data_in = 4'b0000;
else data_in = data_in_pad;
end
assign data = data_in;
// Outgoing data to the external pads
reg [3:0] data_out;
always @(posedge sysclk) begin
if (n0702)
data_out <= data;
end
assign data_out_pad = poc ? 4'b0000 : (n0700 ? 4'bzzzz : data_out);
assign data_in_pad = poc ? 4'b0000 : (n0700 ? 4'bzzzz : data_out);
endmodule
|
module counter(
input wire sysclk,
input wire step_a,
input wire step_b,
output reg q = 1'b0
);
reg q_n = 1'b1;
always @(posedge sysclk) begin
if (step_a) q <= ~q_n;
if (step_b) q_n <= q;
end
endmodule
|
tt06-finale_0083
|
tt06-finale
|
noritsuna-tt06-tt_um_i4004
|
task_instruction_decode
|
tt_um_noritsuna_i4004
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
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`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module tt_um_noritsuna_i4004 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena,
input wire clk,
input wire rst_n
);
wire sysclk;
wire clk1_pad;
wire clk2_pad;
wire poc_pad;
wire test_pad;
wire [3:0] data_in_pad;
wire [3:0] data_out_pad;
wire cmrom_pad;
wire cmram0_pad;
wire cmram1_pad;
wire cmram2_pad;
wire cmram3_pad;
wire sync_pad;
//input:
assign sysclk = clk;
assign data_in_pad = ui_in[3:0];
assign clk1_pad = ui_in[4];
assign clk2_pad = ui_in[5];
assign poc_pad = ui_in[6];
assign test_pad = ui_in[7];
//output:
assign cmrom_pad = uo_out[0];
assign cmram0_pad = uo_out[1];
assign cmram1_pad = uo_out[2];
assign cmram2_pad = uo_out[3];
assign cmram3_pad = uo_out[4];
assign sync_pad = uo_out[5];
assign uio_oe[3:0] = 1;
assign data_out_pad = uio_out[3:0];
// All output pins must be assigned. If not used, assign to 0.
assign uo_out[6] = 0;
assign uo_out[7] = 0;
assign uio_out[7:4] = 0;
assign uio_oe[7:4] = 0;
// Common BiDir data bus
wire [3:0] data;
// Timing and I/O Board Outputs
wire clk1;
wire clk2;
wire a12;
wire a22;
wire a32;
wire m12;
wire m22;
wire x12;
wire x22;
wire x32;
wire gate;
wire poc; // Clean POC_PAD
wire n0432; // Clean TEST_PAD
// Outputs from the Instruction Decode board
wire jcn_isz;
wire jin_fin;
wire jun_jms;
wire cn_n;
wire bbl;
wire jms;
wire sc;
wire dc;
wire sc_m22_clk2;
wire fin_fim_src_jin;
wire inc_isz_add_sub_xch_ld;
wire inc_isz_xch;
wire opa0_n;
wire cma;
wire write_acc_1;
wire write_carry_2;
wire read_acc_3;
wire add_group_4;
wire inc_group_5;
wire sub_group_6;
wire ior;
wire iow;
wire ral;
wire rar;
wire ope_n;
wire daa;
wire dcl;
wire inc_isz;
wire kbp;
wire o_ib;
wire tcs;
wire xch;
wire n0342;
wire x21_clk2;
wire x31_clk2;
wire com_n;
// Outputs from the ALU board
wire acc_0;
wire add_0;
wire cy_1;
wire cmram0;
wire cmram1;
wire cmram2;
wire cmram3;
wire cmrom;
// Instantiate the Timing and I/O board
timing_io tio_board (
.sysclk(sysclk),
.clk1_pad(clk1_pad),
.clk2_pad(clk2_pad),
.poc_pad(poc_pad),
.ior(ior),
.clk1(clk1),
.clk2(clk2),
.a12(a12),
.a22(a22),
.a32(a32),
.m12(m12),
.m22(m22),
.x12(x12),
.x22(x22),
.x32(x32),
.gate(gate),
.poc(poc),
.data(data),
.data_in_pad(data_in_pad),
.data_out_pad(data_out_pad),
.test_pad(test_pad),
.n0432(n0432),
.sync_pad(sync_pad),
.cmrom(cmrom),
.cmrom_pad(cmrom_pad),
.cmram0(cmram0),
.cmram0_pad(cmram0_pad),
.cmram1(cmram1),
.cmram1_pad(cmram1_pad),
.cmram2(cmram2),
.cmram2_pad(cmram2_pad),
.cmram3(cmram3),
.cmram3_pad(cmram3_pad)
);
// Instantiate the Instruction Decode board
instruction_decode id_board (
.sysclk(clk),
.clk1(clk1),
.clk2(clk2),
.a22(a22),
.m12(m12),
.m22(m22),
.x12(x12),
.x22(x22),
.x32(x32),
.poc(poc),
.n0432(n0432),
.data(data),
.jcn_isz(jcn_isz),
.jin_fin(jin_fin),
.jun_jms(jun_jms),
.cn_n(cn_n),
.bbl(bbl),
.jms(jms),
.sc(sc),
.dc(dc),
.sc_m22_clk2(sc_m22_clk2),
.fin_fim_src_jin(fin_fim_src_jin),
.inc_isz_add_sub_xch_ld(inc_isz_add_sub_xch_ld),
.inc_isz_xch(inc_isz_xch),
.opa0_n(opa0_n),
.acc_0(acc_0),
.add_0(add_0),
.cy_1(cy_1),
.cma(cma),
.write_acc_1(write_acc_1),
.write_carry_2(write_carry_2),
.read_acc_3(read_acc_3),
.add_group_4(add_group_4),
.inc_group_5(inc_group_5),
.sub_group_6(sub_group_6),
.ior(ior),
.iow(iow),
.ral(ral),
.rar(rar),
.ope_n(ope_n),
.daa(daa),
.dcl(dcl),
.inc_isz(inc_isz),
.kbp(kbp),
.o_ib(o_ib),
.tcs(tcs),
.xch(xch),
.n0342(n0342),
.x21_clk2(x21_clk2),
.x31_clk2(x31_clk2),
.com_n(com_n)
);
// Instantiate the ALU board
alu alu_board (
.sysclk(clk),
.a12(a12),
.m12(m12),
.x12(x12),
.poc(poc),
.data(data),
.acc_0(acc_0),
.add_0(add_0),
.cy_1(cy_1),
.cma(cma),
.write_acc_1(write_acc_1),
.write_carry_2(write_carry_2),
.read_acc_3(read_acc_3),
.add_group_4(add_group_4),
.inc_group_5(inc_group_5),
.sub_group_6(sub_group_6),
.ior(ior),
.iow(iow),
.ral(ral),
.rar(rar),
.ope_n(ope_n),
.daa(daa),
.dcl(dcl),
.inc_isz(inc_isz),
.kbp(kbp),
.o_ib(o_ib),
.tcs(tcs),
.xch(xch),
.n0342(n0342),
.x21_clk2(x21_clk2),
.x31_clk2(x31_clk2),
.com_n(com_n),
.cmram0(cmram0),
.cmram1(cmram1),
.cmram2(cmram2),
.cmram3(cmram3),
.cmrom(cmrom)
);
// Instantiate the Instruction Pointer board
instruction_pointer ip_board (
.sysclk(clk),
.clk1(clk1),
.clk2(clk2),
.a12(a12),
.a22(a22),
.a32(a32),
.m12(m12),
.m22(m22),
.x12(x12),
.x22(x22),
.x32(x32),
.poc(poc),
.m12_m22_clk1_m11_m12(gate),
.data(data),
.jcn_isz(jcn_isz),
.jin_fin(jin_fin),
.jun_jms(jun_jms),
.cn_n(cn_n),
.bbl(bbl),
.jms(jms),
.sc(sc),
.dc(dc)
);
// Instantiate the Scratchpad board
scratchpad sp_board (
.sysclk(clk),
.clk1(clk1),
.clk2(clk2),
.a12(a12),
.a22(a22),
.a32(a32),
.m12(m12),
.m22(m22),
.x12(x12),
.x22(x22),
.x32(x32),
.poc(poc),
.m12_m22_clk1_m11_m12(gate),
.data(data),
.sc_m22_clk2(sc_m22_clk2),
.fin_fim_src_jin(fin_fim_src_jin),
.inc_isz_add_sub_xch_ld(inc_isz_add_sub_xch_ld),
.inc_isz_xch(inc_isz_xch),
.opa0_n(opa0_n),
.sc(sc),
.dc(dc)
);
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module alu(
input wire sysclk,
// Inputs from the Timing and I/O board
input wire a12,
input wire m12,
input wire x12,
input wire poc,
// Common 4-bit data bus
inout wire [3:0] data,
// Outputs to the Instruction Decode board
output wire acc_0,
output wire add_0,
output reg cy_1,
// Inputs from the Instruction Decode board
input wire cma,
input wire write_acc_1,
input wire write_carry_2,
input wire read_acc_3,
input wire add_group_4,
input wire inc_group_5,
input wire sub_group_6,
input wire ior,
input wire iow,
input wire ral,
input wire rar,
input wire ope_n,
input wire daa,
input wire dcl,
input wire inc_isz,
input wire kbp,
input wire o_ib,
input wire tcs,
input wire xch,
input wire n0342,
input wire x21_clk2,
input wire x31_clk2,
input wire com_n,
// Outputs to external pins
output wire cmram0,
output wire cmram1,
output wire cmram2,
output wire cmram3,
output wire cmrom
);
reg [3:0] acc;
reg cy;
// Decode logic
wire n0854 = ~(~x12);
wire n0351 = ~(x21_clk2 | ~dcl);
wire n0415 = ~(x21_clk2 | ope_n);
wire add_ib = ~(x31_clk2 | ~inc_isz);
wire cy_ib = ~(x31_clk2 | ~iow);
wire acb_ib = ~((x31_clk2 | ~xch) & (x21_clk2 | ~iow));
wire n0477 = ~((~x31_clk2 & ~ior) | (a12 & ior));
wire adc_cy = ~(write_carry_2 | n0477);
wire add_acc = ~(write_acc_1 | n0477);
wire adsr = ~(x31_clk2 | ~rar);
wire adsl = ~(x31_clk2 | ~ral);
wire acc_adac = ~(~cma | n0342);
wire acc_ada = ~(read_acc_3 | n0342);
wire cy_ada = ~(add_group_4 | n0342);
wire cy_adac = ~(sub_group_6 | n0342);
// Latch the incoming data bus
reg [3:0] tmp; // It's the name used in simulator!
always @(posedge sysclk) begin
if (~n0342)
tmp <= data;
if (m12)
tmp <= 4'b1111;
end
// Invert some of the incoming data
reg n0893, n0891, n0889, n0887; // D3, D2, D1, D0
always @(posedge sysclk) begin
if (sub_group_6) begin
n0887 <= tmp[0];
n0889 <= ~tmp[1];
n0891 <= tmp[2];
n0893 <= ~tmp[3];
end
if (~(sub_group_6 | m12)) begin
n0887 <= ~tmp[0];
n0889 <= tmp[1];
n0891 <= ~tmp[2];
n0893 <= tmp[3];
end
end
// Feedback from Accumulator
reg n0873, n0872, n0871, n0870;
always @(posedge sysclk) begin
if (m12)
{n0873, n0872, n0871, n0870} <= 4'b1010;
if (acc_ada)
{n0873, n0872, n0871, n0870} <= acc;
if (acc_adac)
{n0873, n0872, n0871, n0870} <= ~acc;
end
// Carry generator
wire n0546 = ~(inc_group_5 | n0342);
reg n0550;
always @(posedge sysclk) begin
if (m12) n0550 <= 1'b0;
if (n0546) n0550 <= 1'b1;
if (cy_adac) n0550 <= ~cy;
if (cy_ada) n0550 <= cy;
end
wire n0911 = ~(n0550 ? (n0887 | n0870) : (n0887 & n0870));
wire n0553 = n0911;
wire n0912 = ~(n0553 ? (n0889 | n0871) : (n0889 & n0871));
wire n0556 = n0912;
wire n0913 = ~(n0556 ? (n0891 | n0872) : (n0891 & n0872));
wire n0559 = n0913;
wire n0914 = ~(n0559 ? (n0893 | n0873) : (n0893 & n0873));
wire n0861 = n0914;
// Adder
wire n0877 = ~((n0893 & n0559 & n0873) | (n0861 & (n0893 | n0873 | n0559)));
wire n0878 = ~((n0877 & n0550 & n0870) | (n0553 & (n0887 | n0870 | n0550)));
wire n0875 = ~((n0889 & n0553 & n0871) | (n0556 & (n0889 | n0871 | n0553)));
wire n0879 = ~((n0891 & n0556 & n0872) | (n0559 & (n0891 | n0872 | n0556)));
wire n0846 = ~n0878;
wire n0847 = n0875;
wire n0848 = ~n0879;
wire n0514 = n0877;
// Shifter / Accumulator and Carry
reg [3:0] acc_out; // {n0356, n0348, n0347, n0346}
wire n0803 = ~((acc_out[3] & (acc_out[2] | acc_out[1])) | cy_1);
wire n0403 = ~(~daa | n0803);
wire [3:0] acc_in = {n0514, n0848, n0847, n0846};
always @(posedge sysclk) begin
if (adsr)
{acc, cy} <= {cy_1, acc_in};
if (add_acc)
acc <= acc_in;
if (adsl)
{cy, acc} <= {acc_in, cy_1};
if (adc_cy)
cy <= n0861;
if (n0403 & n0415)
cy <= 1'b1;
// Dynamic refresh would occur during M12
end
// Accumulator output latch
always @(posedge sysclk) begin
if (n0854) begin
cy_1 <= cy;
acc_out <= acc;
end
end
assign acc_0 = ~|acc_out;
assign add_0 = ~|acc_in;
// Keyboard Process logic
wire n0378 = ~((daa & n0803) | o_ib);
wire n0345 = kbp & (acc_out == 4'b1000);
wire n0354 = kbp & (acc_out == 4'b0100);
wire n0363 = kbp & (acc_out == 4'b0010);
wire n0370 = kbp & (acc_out == 4'b0001);
wire n0377 = (kbp & (acc_out == 4'b0000)) | ~n0378;
wire n0358 = ~(n0345 | n0354 | n0363 | n0370 | n0377 | n0403);
wire n0366 = ~( n0354 | n0363 | n0370 | n0377 | tcs );
wire n0359 = ~(n0345 | n0370 | n0377 | tcs );
wire n0357 = ~(n0345 | n0363 | n0377 | n0403);
// Data output mux
reg [3:0] dout;
always @(*) begin
dout = 4'bzzzz;
if (acb_ib)
dout = acc_out;
if (add_ib)
dout = acc_in;
if (cy_ib)
dout = {3'bxxx, cy_1};
if (n0415)
dout = {n0358, n0366, n0359, n0357};
end
assign data = dout;
// Generate CMROM / CMRAMn
// This may get moved to the Timing & I/O board
// Inputs: {n0355, n0364, n0371}, n0351, poc, com_n
wire n0355 = ~acc_out[2];
wire n0364 = ~acc_out[1];
wire n0371 = ~acc_out[0];
reg n0749, n0750, n0751;
always @(posedge sysclk) begin
if (poc) begin
n0749 <= 1'b1;
n0750 <= 1'b1;
n0751 <= 1'b1;
end
else begin
if (n0351) begin
n0749 <= n0355;
n0750 <= n0364;
n0751 <= n0371;
end
end
end
assign cmram3 = ~(com_n | n0749);
assign cmram2 = ~(com_n | n0750);
assign cmram1 = ~(com_n | n0751);
assign cmram0 = ~(com_n | ~n0749 | ~n0750 | ~n0751);
assign cmrom = ~(com_n | poc);
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module counter(
input wire sysclk,
input wire step_a,
input wire step_b,
output reg q = 1'b0
);
reg q_n = 1'b1;
always @(posedge sysclk) begin
if (step_a) q <= ~q_n;
if (step_b) q_n <= q;
end
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module instruction_decode(
input wire sysclk, // 50 MHz FPGA clock
// Inputs from the Timing and I/O board
input wire clk1,
input wire clk2,
input wire a22,
input wire m12,
input wire m22,
input wire x12,
input wire x22,
input wire x32,
input wire poc, // Power-On Clear (reset)
input wire n0432, // Conditioned TEST_PAD
// Common 4-bit data bus
inout wire [3:0] data,
// These drive the Instruction Pointer (IP) board
output wire jcn_isz, // JCN+ISZ
output wire jin_fin, // JIN+FIN
output wire jun_jms, // JUN+JMS
output wire cn_n, // ~CN
output wire bbl, // BBL
output wire jms, // JMS
// Outputs to both the IP and SP boards
output wire sc, // SC (Single Cycle)
output wire dc, // DC (Double Cycle, ~SC)
// Outputs to the Scratch Pad (SP) board
output wire sc_m22_clk2, // SC&M22&CLK2
output wire fin_fim_src_jin, // FIN+FIM+SRC+JIN
output wire inc_isz_add_sub_xch_ld, // INC+ISZ+ADD+SUB+XCH+LD
output wire inc_isz_xch, // INC+ISZ+XCH
output wire opa0_n, // ~OPA.0
// Inputs from the ALU board (condition bits)
input wire acc_0, // ACC_0
input wire add_0, // ADD_0
input wire cy_1, // CY_1
// Outputs to the Arithmetic Logic Unit (ALU) board
output wire cma,
output wire write_acc_1,
output wire write_carry_2,
output wire read_acc_3,
output wire add_group_4,
output wire inc_group_5,
output wire sub_group_6,
output wire ior,
output wire iow,
output wire ral,
output wire rar,
output wire ope_n,
output wire daa,
output wire dcl,
output wire inc_isz,
output wire kbp,
output wire o_ib,
output wire tcs,
output wire xch,
output wire n0342,
output wire x21_clk2,
output wire x31_clk2,
output wire com_n
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module instruction_pointer (
input wire sysclk, // 50 MHz FPGA clock
// Inputs from the Timing and I/O board
input wire clk1,
input wire clk2,
input wire a12,
input wire a22,
input wire a32,
input wire m12,
input wire m22,
input wire x12,
input wire x22,
input wire x32,
input wire poc, // Power-On Clear (reset)
input wire m12_m22_clk1_m11_m12, // M12+M22+CLK1~(M11+M12)
// Common 4-bit data bus
inout wire [3:0] data,
// Inputs from the Instruction Decode board
input wire jcn_isz, // JCN+ISZ
input wire jin_fin, // JIN+FIN
input wire jun_jms, // JUN+JMS
input wire cn_n, // ~CN
input wire bbl, // BBL
input wire jms, // JMS
input wire sc, // SC (Single Cycle)
input wire dc // DC (Double Cycle, ~SC)
);
reg [11:0] dram_array [0:3];
reg [11:0] dram_temp;
wire [3:0] din_n;
wire inh = (jin_fin & sc) | ((jun_jms | (jcn_isz & ~cn_n)) & dc);
// Row Counter stuff
wire [1:0] addr_ptr; // Effective Address counter
wire addr_ptr_step; // CLK2(JMS&DC&M22+BBL(M22+X12+X22))
assign addr_ptr_step = ~(~clk2 | ~(((m22 | x12 | x22) & bbl) |
(m22 & dc & jms)));
counter addr_ptr_0 (
.sysclk(sysclk),
.step_a(clk1),
.step_b(addr_ptr_step),
.q(addr_ptr[0])
);
counter addr_ptr_1 (
.sysclk(sysclk),
.step_a( addr_ptr[0]),
.step_b(~addr_ptr[0]),
.q(addr_ptr[1])
);
// Refresh counter stuff
wire [1:0] addr_rfsh; // Row Refresh counter
wire addr_rfsh_step; // (~INH)&X32&CLK2
assign addr_rfsh_step = ~inh & x32 & clk2;
counter addr_rfsh_0 (
.sysclk(sysclk),
.step_a(clk1),
.step_b(addr_rfsh_step),
.q(addr_rfsh[0])
);
counter addr_rfsh_1 (
.sysclk(sysclk),
.step_a( addr_rfsh[0]),
.step_b(~addr_rfsh[0]),
.q(addr_rfsh[1])
);
// Row selection mux
reg [1:0] row; // {N0409, N0420}
always @(posedge sysclk) begin
if (x12)
row <= addr_rfsh;
if (x32)
row <= addr_ptr;
end
// Row Precharge/Read/Write stuff
wire precharge; // (~INH)(X11+X31)CLK1
wire row_read; // (~POC)CLK2(X12+X32)~INH
wire row_write; // ((~SC)(JIN+FIN))CLK1(M11+X21~INH)
reg n0517;
always @(posedge sysclk) begin
if (clk2)
n0517 <= ~(m22 | x22);
end
assign precharge = ~(n0517 | inh | ~clk1);
assign row_read = ~poc & clk2 & (x12 | x32) & ~inh;
reg n0438;
always @(posedge sysclk) begin
if (clk2)
n0438 <= ~((x12 & ~inh) | a32);
end
assign row_write = ~(n0438 | (jin_fin & ~sc) | ~clk1);
// Column Read selection stuff
reg n0416;
always @(posedge sysclk) begin
if (clk2)
n0416 <= ~x32;
end
wire radb0 = ~(n0416 | clk2);
reg n0384;
always @(posedge sysclk) begin
if (clk2)
n0384 <= ~a12;
end
wire radb1 = ~(n0384 | clk2);
reg n0374;
always @(posedge sysclk) begin
if (clk2)
n0374 <= ~a22;
end
wire radb2 = ~(n0374 | clk2);
// Column Write selection stuff
wire n0322 = ~(sc | cn_n);
wire wadb0 = ~(~clk2 | ~(a12 | (sc & jin_fin & x32) |
(((jcn_isz & n0322) | (jun_jms & ~sc)) & m22)));
wire wadb1 = ~(~clk2 | ~(a22 | (sc & jin_fin & x22) |
(((jcn_isz & n0322) | (jun_jms & ~sc)) & m12)));
wire wadb2 = ~(~clk2 | ~(a32 | (jun_jms & ~sc & x22)));
// Manage the row data buffer
always @(posedge sysclk) begin
if (precharge)
dram_temp <= 12'b0;
if (row_read)
dram_temp <= dram_array[row];
if (wadb0)
dram_temp[ 3:0] <= ~din_n;
if (wadb1)
dram_temp[ 7:4] <= ~din_n;
if (wadb2)
dram_temp[11:8] <= ~din_n;
end
// Handle row writes
always @(posedge sysclk) begin
if (row_write)
dram_array[row] <= dram_temp;
end
// Manage the data output mux
reg [3:0] dout;
always @* begin
(* PARALLEL_CASE *)
case (1'b1)
radb0: dout = dram_temp[ 3:0];
radb1: dout = dram_temp[ 7:4];
radb2: dout = dram_temp[11:8];
default: dout = 4'bzzzz;
endcase
end
assign data = dout;
// Data In mux and incrementer
reg [3:0] incr_in;
always @(posedge sysclk) begin
if (m12_m22_clk1_m11_m12)
incr_in <= data;
end
reg carry_out, carry_in;
wire [4:0] incr_out = (a12 | ((a22 | a32) & carry_in)) ?
(incr_in + 4'b0001) : {1'b0, incr_in};
always @(posedge sysclk) begin
if (clk2)
carry_out <= incr_out[4];
if (clk1)
carry_in <= carry_out;
end
assign din_n = ~incr_out[3:0];
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module scratchpad (
input wire sysclk, // 50 MHz FPGA clock
// Inputs from the Timing and I/O board
input wire clk1,
input wire clk2,
input wire a12,
input wire a22,
input wire a32,
input wire m12,
input wire m22,
input wire x12,
input wire x22,
input wire x32,
input wire poc, // Power-On Clear (reset)
input wire m12_m22_clk1_m11_m12, // M12+M22+CLK1~(M11+M12)
// Common 4-bit data bus
inout wire [3:0] data,
// Inputs from the Instruction Decode board
input wire sc_m22_clk2, // SC&M22&CLK2
input wire fin_fim_src_jin, // FIN+FIM+SRC+JIN
input wire inc_isz_add_sub_xch_ld, // INC+ISZ+ADD+SUB+XCH+LD
input wire inc_isz_xch, // INC+ISZ+XCH
input wire opa0_n, // ~OPA.0
input wire sc, // SC (Single Cycle)
input wire dc // DC (Double Cycle, ~SC)
);
reg [7:0] dram_array [0:7];
reg [7:0] dram_temp;
reg [3:0] din_n;
// Refresh counter stuff
wire [2:0] reg_rfsh; // Row Refresh counter
wire reg_rfsh_step; // SC&A12&CLK2
assign reg_rfsh_step = sc & a12 & clk2;
counter reg_rfsh_0 (
.sysclk(sysclk),
.step_a(clk1),
.step_b(reg_rfsh_step),
.q(reg_rfsh[0])
);
counter reg_rfsh_1 (
.sysclk(sysclk),
.step_a( reg_rfsh[0]),
.step_b(~reg_rfsh[0]),
.q(reg_rfsh[1])
);
counter reg_rfsh_2 (
.sysclk(sysclk),
.step_a( reg_rfsh[1]),
.step_b(~reg_rfsh[1]),
.q(reg_rfsh[2])
);
// Row selection mux
reg [2:0] row; // {N0646, N0617, N0582}
always @(posedge sysclk) begin
if (sc & a22)
row <= reg_rfsh;
if (sc_m22_clk2)
row <= data[3:1];
end
// Row Precharge/Read/Write stuff
wire precharge; // SC(A22+M22)CLK2
wire row_read; // (~POC)&CLK2&SC(A32+X12)
wire row_write; // CLK2&SC(A12+M12)
assign precharge = sc & (a22 | m22) & clk2;
assign row_read = ~(poc | ~(clk2 & sc & (a32 | x12)));
assign row_write = sc & (a12 | m12) & clk2;
// Column Read selection stuff
reg n0615;
always @(posedge sysclk) begin
if (clk2)
n0615 <= ~(x12 & (fin_fim_src_jin |
(opa0_n & inc_isz_add_sub_xch_ld)));
end
wire rrab0 = ~(dc | n0615 | clk2);
reg n0592;
always @(posedge sysclk) begin
if (clk2)
n0592 <= ~((x22 & fin_fim_src_jin) |
(~opa0_n & x12 & inc_isz_add_sub_xch_ld));
end
wire rrab1 = ~(dc | n0592 | clk2);
// Column Write selection stuff
wire n0564 = opa0_n & fin_fim_src_jin & dc;
wire n0568 = inc_isz_xch & x32 & sc;
wire wrab0 = clk2 & ((m12 & n0564) | ( opa0_n & n0568));
wire wrab1 = clk2 & ((m22 & n0564) | (~opa0_n & n0568));
// Manage the row data buffer
always @(posedge sysclk) begin
if (precharge)
dram_temp <= 8'b0;
if (row_read)
dram_temp <= dram_array[row];
if (wrab0)
dram_temp[ 3:0] <= ~din_n;
if (wrab1)
dram_temp[ 7:4] <= ~din_n;
end
// Handle row writes
always @(posedge sysclk) begin
if (row_write)
dram_array[row] <= dram_temp;
end
// Manage the data output mux
reg [3:0] dout;
always @* begin
(* PARALLEL_CASE *)
case (1'b1)
rrab0: dout = dram_temp[ 3:0];
rrab1: dout = dram_temp[ 7:4];
default: dout = 4'bzzzz;
endcase
end
assign data = dout;
// Data In latch
always @(posedge sysclk) begin
if (m12_m22_clk1_m11_m12)
din_n <= ~data;
end
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module timing_io(
input wire sysclk,
input wire clk1_pad,
input wire clk2_pad,
input wire poc_pad,
input wire ior,
// Timing and I/O Board Outputs
output wire clk1,
output wire clk2,
output wire a12,
output wire a22,
output wire a32,
output wire m12,
output wire m22,
output wire x12,
output wire x22,
output wire x32,
output wire gate,
output reg poc,
// External I/O Pad conditioning
inout wire [3:0] data,
inout wire [3:0] data_in_pad,
output wire [3:0] data_out_pad,
input wire test_pad,
output reg n0432,
output reg sync_pad,
input wire cmrom,
output wire cmrom_pad,
input wire cmram0,
output wire cmram0_pad,
input wire cmram1,
output wire cmram1_pad,
input wire cmram2,
output wire cmram2_pad,
input wire cmram3,
output wire cmram3_pad
);
// Simple pass-throughs
assign clk1 = clk1_pad;
assign clk2 = clk2_pad;
assign cmrom_pad = cmrom;
assign cmram0_pad = cmram0;
assign cmram1_pad = cmram1;
assign cmram2_pad = cmram2;
assign cmram3_pad = cmram3;
// Generate the 8 execution phase indicators
reg [0:7] master = 8'h00;
reg [0:7] slave = 8'h00;
always @(posedge sysclk) begin
if (clk2)
master <= {~|slave[0:6], slave[0:6]};
else
sync_pad <= master[7];
if (clk1)
slave <= master;
end
assign a12 = slave[0];
assign a22 = slave[1];
assign a32 = slave[2];
assign m12 = slave[3];
assign m22 = slave[4];
assign x12 = slave[5];
assign x22 = slave[6];
assign x32 = slave[7];
// Generate the DRAM Input Gate signal
// Properly called M12+M22+CLK1~(M11&M12)
wire n0279 = ~(a32 | m12);
reg n0278;
always @(posedge sysclk) begin
if (clk2)
n0278 <= n0279;
end
wire n0708 = ~((n0278 & clk1) | m12 | m22);
assign gate = ~n0708;
// Generate a clean POC signal
always @(posedge sysclk) begin
if (poc_pad) poc <= 1'b1;
else if (a12) poc <= 1'b0;
else poc <= poc;
end
// Generate a clean ~TEST signal (n0432)
always @(posedge sysclk) begin
n0432 <= ~test_pad;
end
// Manage the Data I/O pads
reg L;
always @(posedge sysclk) begin
if (clk2)
L <= a32 | m12 | (x12 & (ior | poc));
end
wire n0702 = ~clk2;
reg n0685;
reg n0699;
reg n0707;
always @(posedge sysclk) begin
if (clk1) begin
n0685 <= ~L;
n0707 <= L;
end
if (n0702)
n0699 <= ~L;
end
wire n0700 = n0707 | (L & n0702) | poc;
wire n0659 = (clk2 & n0685) | (clk1 & L);
wire n0676 = clk1 | n0685 | n0699;
// Incoming data from the external pads
reg [3:0] data_in;
always @* begin
if (n0659) data_in = 4'b1111;
else if (n0676) data_in = 4'bzzzz;
else if (poc) data_in = 4'b0000;
else data_in = data_in_pad;
end
assign data = data_in;
// Outgoing data to the external pads
reg [3:0] data_out;
always @(posedge sysclk) begin
if (n0702)
data_out <= data;
end
assign data_out_pad = poc ? 4'b0000 : (n0700 ? 4'bzzzz : data_out);
assign data_in_pad = poc ? 4'b0000 : (n0700 ? 4'bzzzz : data_out);
endmodule
|
module instruction_decode(
input wire sysclk, // 50 MHz FPGA clock
// Inputs from the Timing and I/O board
input wire clk1,
input wire clk2,
input wire a22,
input wire m12,
input wire m22,
input wire x12,
input wire x22,
input wire x32,
input wire poc, // Power-On Clear (reset)
input wire n0432, // Conditioned TEST_PAD
// Common 4-bit data bus
inout wire [3:0] data,
// These drive the Instruction Pointer (IP) board
output wire jcn_isz, // JCN+ISZ
output wire jin_fin, // JIN+FIN
output wire jun_jms, // JUN+JMS
output wire cn_n, // ~CN
output wire bbl, // BBL
output wire jms, // JMS
// Outputs to both the IP and SP boards
output wire sc, // SC (Single Cycle)
output wire dc, // DC (Double Cycle, ~SC)
// Outputs to the Scratch Pad (SP) board
output wire sc_m22_clk2, // SC&M22&CLK2
output wire fin_fim_src_jin, // FIN+FIM+SRC+JIN
output wire inc_isz_add_sub_xch_ld, // INC+ISZ+ADD+SUB+XCH+LD
output wire inc_isz_xch, // INC+ISZ+XCH
output wire opa0_n, // ~OPA.0
// Inputs from the ALU board (condition bits)
input wire acc_0, // ACC_0
input wire add_0, // ADD_0
input wire cy_1, // CY_1
// Outputs to the Arithmetic Logic Unit (ALU) board
output wire cma,
output wire write_acc_1,
output wire write_carry_2,
output wire read_acc_3,
output wire add_group_4,
output wire inc_group_5,
output wire sub_group_6,
output wire ior,
output wire iow,
output wire ral,
output wire rar,
output wire ope_n,
output wire daa,
output wire dcl,
output wire inc_isz,
output wire kbp,
output wire o_ib,
output wire tcs,
output wire xch,
output wire n0342,
output wire x21_clk2,
output wire x31_clk2,
output wire com_n
);
wire sc_m12_clk2 = sc & m12 & clk2;
assign sc_m22_clk2 = sc & m22 & clk2;
// Latch the first 4 bits of the opcode
reg [3:0] opr = 4'b0000;
always @(posedge sysclk) begin
if (sc_m12_clk2)
opr <= data;
end
// Latch the second 4 bits of the opcode
reg [3:0] opa = 4'b0000;
always @(posedge sysclk) begin
if (sc_m22_clk2)
opa <= data;
end
assign opa0_n = ~opa[0];
// Full OPR Decoding
wire nop = (opr == 4'b0000);
wire jcn = (opr == 4'b0001);
wire fim_src = (opr == 4'b0010);
assign jin_fin = (opr == 4'b0011);
wire jun = (opr == 4'b0100);
assign jms = (opr == 4'b0101);
wire inc = (opr == 4'b0110);
wire isz = (opr == 4'b0111);
wire add = (opr == 4'b1000);
wire sub = (opr == 4'b1001);
wire ld = (opr == 4'b1010);
assign xch = (opr == 4'b1011);
assign bbl = (opr == 4'b1100);
wire ldm = (opr == 4'b1101);
wire io = (opr == 4'b1110);
wire ope = (opr == 4'b1111);
assign ope_n = ~ope;
assign jcn_isz = jcn | isz;
assign jun_jms = jun | jms;
wire ldm_bbl = ldm | bbl;
assign inc_isz = (inc | isz) & sc;
assign inc_isz_xch = inc | isz | xch;
assign inc_isz_add_sub_xch_ld = inc | isz | add | sub | xch | ld;
assign fin_fim_src_jin = fim_src | jin_fin;
// OPE: OPA Decoding
assign o_ib = ope & (opa[3] == 1'b0);
wire clb = ope & (opa == 4'b0000);
wire clc = ope & (opa == 4'b0001);
wire iac = ope & (opa == 4'b0010);
wire cmc = ope & (opa == 4'b0011);
assign cma = ope & (opa == 4'b0100);
assign ral = ope & (opa == 4'b0101);
assign rar = ope & (opa == 4'b0110);
wire tcc = ope & (opa == 4'b0111);
wire dac = ope & (opa == 4'b1000);
assign tcs = ope & (opa == 4'b1001);
wire stc = ope & (opa == 4'b1010);
assign daa = ope & (opa == 4'b1011);
assign kbp = ope & (opa == 4'b1100);
assign dcl = ope & (opa == 4'b1101);
// IO: OPA Decoding
assign iow = io & (opa[3] == 1'b0);
assign ior = io & (opa[3] == 1'b1);
wire adm = io & (opa == 4'b1011);
wire sbm = io & (opa == 4'b1000);
wire fin_fim = fin_fim_src_jin & ~opa[0];
wire src = fim_src & opa[0];
assign write_acc_1 = ~(kbp | tcs | daa | xch | poc | cma | tcc | dac | iac |
clb | ior | ld | sub | add | ldm_bbl);
assign write_carry_2 = ~(tcs | poc | tcc | stc | cmc | dac | iac |
clc | clb | sbm | adm | sub | add);
assign read_acc_3 = ~(daa | rar | ral | dac | iac | sbm | adm | sub | add);
assign add_group_4 = ~(tcs | tcc | adm | add);
assign inc_group_5 = ~(inc_isz | stc | iac);
assign sub_group_6 = ~(cmc | sbm | sub | m12);
// The Condition Flip-Flop
reg n0397;
wire n0486 = ~((opa[2] & acc_0) | (opa[1] & cy_1) | (opa[0] & n0432));
wire n0419 = ~((add_0 & ~isz) & (~jcn | ((~n0486 | opa[3]) & (n0486 | ~opa[3]))));
wire n0413 = ~((sc & n0419 & x32) | (~x32 | n0397));
reg n0405;
always @(posedge sysclk) begin
if (clk2)
n0405 <= n0413;
if (clk1)
n0397 <= ~n0405;
end
assign cn_n = ~n0397;
// The Single-Cycle Flip-Flop
reg n0343;
wire n0368 = ~((sc & (fin_fim | jcn_isz | jun_jms) & x32) | (n0343 & ~x32));
reg n0362;
always @(posedge sysclk) begin
if (clk2)
n0362 <= n0368;
if (clk1)
n0343 <= ~n0362;
end
assign sc = ~n0343;
assign dc = ~sc;
// Generate ~(X21&~CLK2)
reg n0360;
always @(posedge sysclk) begin
if (clk2)
n0360 <= ~x12;
end
wire n0337 = ~(n0360 | clk2);
assign x21_clk2 = ~n0337;
// Generate ~(X31&~CLK2)
reg n0380;
always @(posedge sysclk) begin
if (clk2)
n0380 <= ~x22;
end
wire n0375 = ~(n0380 | clk2);
assign x31_clk2 = ~n0375;
// Generate ~COM
wire n0329 = io;
reg n0414, n0797;
always @(posedge sysclk) begin
if (clk2)
n0414 <= a22;
else
n0797 <= n0414;
end
reg n0433, n0801;
always @(posedge sysclk) begin
if (clk2)
n0433 <= m12;
else
n0801 <= n0433;
end
reg n0425, n0805;
always @(posedge sysclk) begin
if (clk2)
n0425 <= x12;
else
n0805 <= n0425;
end
wire n0782 = ~((n0801 & n0329) | (src & n0805) | n0797);
assign com_n = n0782;
// Generate N0342
wire n0332 = ~(((n0329 | poc) & x22 & clk2) | (~(n0329 | poc) & n0337 & clk1));
assign n0342 = n0332;
// Output OPA onto the data bus
wire opa_ib = (ldm_bbl | jun_jms) & ~x21_clk2;
assign data = opa_ib ? opa : 4'bzzzz;
endmodule
|
tt06-finale_0084
|
tt06-finale
|
noritsuna-tt06-tt_um_i4004
|
task_instruction_pointer
|
tt_um_noritsuna_i4004
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module tt_um_noritsuna_i4004 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena,
input wire clk,
input wire rst_n
);
wire sysclk;
wire clk1_pad;
wire clk2_pad;
wire poc_pad;
wire test_pad;
wire [3:0] data_in_pad;
wire [3:0] data_out_pad;
wire cmrom_pad;
wire cmram0_pad;
wire cmram1_pad;
wire cmram2_pad;
wire cmram3_pad;
wire sync_pad;
//input:
assign sysclk = clk;
assign data_in_pad = ui_in[3:0];
assign clk1_pad = ui_in[4];
assign clk2_pad = ui_in[5];
assign poc_pad = ui_in[6];
assign test_pad = ui_in[7];
//output:
assign cmrom_pad = uo_out[0];
assign cmram0_pad = uo_out[1];
assign cmram1_pad = uo_out[2];
assign cmram2_pad = uo_out[3];
assign cmram3_pad = uo_out[4];
assign sync_pad = uo_out[5];
assign uio_oe[3:0] = 1;
assign data_out_pad = uio_out[3:0];
// All output pins must be assigned. If not used, assign to 0.
assign uo_out[6] = 0;
assign uo_out[7] = 0;
assign uio_out[7:4] = 0;
assign uio_oe[7:4] = 0;
// Common BiDir data bus
wire [3:0] data;
// Timing and I/O Board Outputs
wire clk1;
wire clk2;
wire a12;
wire a22;
wire a32;
wire m12;
wire m22;
wire x12;
wire x22;
wire x32;
wire gate;
wire poc; // Clean POC_PAD
wire n0432; // Clean TEST_PAD
// Outputs from the Instruction Decode board
wire jcn_isz;
wire jin_fin;
wire jun_jms;
wire cn_n;
wire bbl;
wire jms;
wire sc;
wire dc;
wire sc_m22_clk2;
wire fin_fim_src_jin;
wire inc_isz_add_sub_xch_ld;
wire inc_isz_xch;
wire opa0_n;
wire cma;
wire write_acc_1;
wire write_carry_2;
wire read_acc_3;
wire add_group_4;
wire inc_group_5;
wire sub_group_6;
wire ior;
wire iow;
wire ral;
wire rar;
wire ope_n;
wire daa;
wire dcl;
wire inc_isz;
wire kbp;
wire o_ib;
wire tcs;
wire xch;
wire n0342;
wire x21_clk2;
wire x31_clk2;
wire com_n;
// Outputs from the ALU board
wire acc_0;
wire add_0;
wire cy_1;
wire cmram0;
wire cmram1;
wire cmram2;
wire cmram3;
wire cmrom;
// Instantiate the Timing and I/O board
timing_io tio_board (
.sysclk(sysclk),
.clk1_pad(clk1_pad),
.clk2_pad(clk2_pad),
.poc_pad(poc_pad),
.ior(ior),
.clk1(clk1),
.clk2(clk2),
.a12(a12),
.a22(a22),
.a32(a32),
.m12(m12),
.m22(m22),
.x12(x12),
.x22(x22),
.x32(x32),
.gate(gate),
.poc(poc),
.data(data),
.data_in_pad(data_in_pad),
.data_out_pad(data_out_pad),
.test_pad(test_pad),
.n0432(n0432),
.sync_pad(sync_pad),
.cmrom(cmrom),
.cmrom_pad(cmrom_pad),
.cmram0(cmram0),
.cmram0_pad(cmram0_pad),
.cmram1(cmram1),
.cmram1_pad(cmram1_pad),
.cmram2(cmram2),
.cmram2_pad(cmram2_pad),
.cmram3(cmram3),
.cmram3_pad(cmram3_pad)
);
// Instantiate the Instruction Decode board
instruction_decode id_board (
.sysclk(clk),
.clk1(clk1),
.clk2(clk2),
.a22(a22),
.m12(m12),
.m22(m22),
.x12(x12),
.x22(x22),
.x32(x32),
.poc(poc),
.n0432(n0432),
.data(data),
.jcn_isz(jcn_isz),
.jin_fin(jin_fin),
.jun_jms(jun_jms),
.cn_n(cn_n),
.bbl(bbl),
.jms(jms),
.sc(sc),
.dc(dc),
.sc_m22_clk2(sc_m22_clk2),
.fin_fim_src_jin(fin_fim_src_jin),
.inc_isz_add_sub_xch_ld(inc_isz_add_sub_xch_ld),
.inc_isz_xch(inc_isz_xch),
.opa0_n(opa0_n),
.acc_0(acc_0),
.add_0(add_0),
.cy_1(cy_1),
.cma(cma),
.write_acc_1(write_acc_1),
.write_carry_2(write_carry_2),
.read_acc_3(read_acc_3),
.add_group_4(add_group_4),
.inc_group_5(inc_group_5),
.sub_group_6(sub_group_6),
.ior(ior),
.iow(iow),
.ral(ral),
.rar(rar),
.ope_n(ope_n),
.daa(daa),
.dcl(dcl),
.inc_isz(inc_isz),
.kbp(kbp),
.o_ib(o_ib),
.tcs(tcs),
.xch(xch),
.n0342(n0342),
.x21_clk2(x21_clk2),
.x31_clk2(x31_clk2),
.com_n(com_n)
);
// Instantiate the ALU board
alu alu_board (
.sysclk(clk),
.a12(a12),
.m12(m12),
.x12(x12),
.poc(poc),
.data(data),
.acc_0(acc_0),
.add_0(add_0),
.cy_1(cy_1),
.cma(cma),
.write_acc_1(write_acc_1),
.write_carry_2(write_carry_2),
.read_acc_3(read_acc_3),
.add_group_4(add_group_4),
.inc_group_5(inc_group_5),
.sub_group_6(sub_group_6),
.ior(ior),
.iow(iow),
.ral(ral),
.rar(rar),
.ope_n(ope_n),
.daa(daa),
.dcl(dcl),
.inc_isz(inc_isz),
.kbp(kbp),
.o_ib(o_ib),
.tcs(tcs),
.xch(xch),
.n0342(n0342),
.x21_clk2(x21_clk2),
.x31_clk2(x31_clk2),
.com_n(com_n),
.cmram0(cmram0),
.cmram1(cmram1),
.cmram2(cmram2),
.cmram3(cmram3),
.cmrom(cmrom)
);
// Instantiate the Instruction Pointer board
instruction_pointer ip_board (
.sysclk(clk),
.clk1(clk1),
.clk2(clk2),
.a12(a12),
.a22(a22),
.a32(a32),
.m12(m12),
.m22(m22),
.x12(x12),
.x22(x22),
.x32(x32),
.poc(poc),
.m12_m22_clk1_m11_m12(gate),
.data(data),
.jcn_isz(jcn_isz),
.jin_fin(jin_fin),
.jun_jms(jun_jms),
.cn_n(cn_n),
.bbl(bbl),
.jms(jms),
.sc(sc),
.dc(dc)
);
// Instantiate the Scratchpad board
scratchpad sp_board (
.sysclk(clk),
.clk1(clk1),
.clk2(clk2),
.a12(a12),
.a22(a22),
.a32(a32),
.m12(m12),
.m22(m22),
.x12(x12),
.x22(x22),
.x32(x32),
.poc(poc),
.m12_m22_clk1_m11_m12(gate),
.data(data),
.sc_m22_clk2(sc_m22_clk2),
.fin_fim_src_jin(fin_fim_src_jin),
.inc_isz_add_sub_xch_ld(inc_isz_add_sub_xch_ld),
.inc_isz_xch(inc_isz_xch),
.opa0_n(opa0_n),
.sc(sc),
.dc(dc)
);
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module alu(
input wire sysclk,
// Inputs from the Timing and I/O board
input wire a12,
input wire m12,
input wire x12,
input wire poc,
// Common 4-bit data bus
inout wire [3:0] data,
// Outputs to the Instruction Decode board
output wire acc_0,
output wire add_0,
output reg cy_1,
// Inputs from the Instruction Decode board
input wire cma,
input wire write_acc_1,
input wire write_carry_2,
input wire read_acc_3,
input wire add_group_4,
input wire inc_group_5,
input wire sub_group_6,
input wire ior,
input wire iow,
input wire ral,
input wire rar,
input wire ope_n,
input wire daa,
input wire dcl,
input wire inc_isz,
input wire kbp,
input wire o_ib,
input wire tcs,
input wire xch,
input wire n0342,
input wire x21_clk2,
input wire x31_clk2,
input wire com_n,
// Outputs to external pins
output wire cmram0,
output wire cmram1,
output wire cmram2,
output wire cmram3,
output wire cmrom
);
reg [3:0] acc;
reg cy;
// Decode logic
wire n0854 = ~(~x12);
wire n0351 = ~(x21_clk2 | ~dcl);
wire n0415 = ~(x21_clk2 | ope_n);
wire add_ib = ~(x31_clk2 | ~inc_isz);
wire cy_ib = ~(x31_clk2 | ~iow);
wire acb_ib = ~((x31_clk2 | ~xch) & (x21_clk2 | ~iow));
wire n0477 = ~((~x31_clk2 & ~ior) | (a12 & ior));
wire adc_cy = ~(write_carry_2 | n0477);
wire add_acc = ~(write_acc_1 | n0477);
wire adsr = ~(x31_clk2 | ~rar);
wire adsl = ~(x31_clk2 | ~ral);
wire acc_adac = ~(~cma | n0342);
wire acc_ada = ~(read_acc_3 | n0342);
wire cy_ada = ~(add_group_4 | n0342);
wire cy_adac = ~(sub_group_6 | n0342);
// Latch the incoming data bus
reg [3:0] tmp; // It's the name used in simulator!
always @(posedge sysclk) begin
if (~n0342)
tmp <= data;
if (m12)
tmp <= 4'b1111;
end
// Invert some of the incoming data
reg n0893, n0891, n0889, n0887; // D3, D2, D1, D0
always @(posedge sysclk) begin
if (sub_group_6) begin
n0887 <= tmp[0];
n0889 <= ~tmp[1];
n0891 <= tmp[2];
n0893 <= ~tmp[3];
end
if (~(sub_group_6 | m12)) begin
n0887 <= ~tmp[0];
n0889 <= tmp[1];
n0891 <= ~tmp[2];
n0893 <= tmp[3];
end
end
// Feedback from Accumulator
reg n0873, n0872, n0871, n0870;
always @(posedge sysclk) begin
if (m12)
{n0873, n0872, n0871, n0870} <= 4'b1010;
if (acc_ada)
{n0873, n0872, n0871, n0870} <= acc;
if (acc_adac)
{n0873, n0872, n0871, n0870} <= ~acc;
end
// Carry generator
wire n0546 = ~(inc_group_5 | n0342);
reg n0550;
always @(posedge sysclk) begin
if (m12) n0550 <= 1'b0;
if (n0546) n0550 <= 1'b1;
if (cy_adac) n0550 <= ~cy;
if (cy_ada) n0550 <= cy;
end
wire n0911 = ~(n0550 ? (n0887 | n0870) : (n0887 & n0870));
wire n0553 = n0911;
wire n0912 = ~(n0553 ? (n0889 | n0871) : (n0889 & n0871));
wire n0556 = n0912;
wire n0913 = ~(n0556 ? (n0891 | n0872) : (n0891 & n0872));
wire n0559 = n0913;
wire n0914 = ~(n0559 ? (n0893 | n0873) : (n0893 & n0873));
wire n0861 = n0914;
// Adder
wire n0877 = ~((n0893 & n0559 & n0873) | (n0861 & (n0893 | n0873 | n0559)));
wire n0878 = ~((n0877 & n0550 & n0870) | (n0553 & (n0887 | n0870 | n0550)));
wire n0875 = ~((n0889 & n0553 & n0871) | (n0556 & (n0889 | n0871 | n0553)));
wire n0879 = ~((n0891 & n0556 & n0872) | (n0559 & (n0891 | n0872 | n0556)));
wire n0846 = ~n0878;
wire n0847 = n0875;
wire n0848 = ~n0879;
wire n0514 = n0877;
// Shifter / Accumulator and Carry
reg [3:0] acc_out; // {n0356, n0348, n0347, n0346}
wire n0803 = ~((acc_out[3] & (acc_out[2] | acc_out[1])) | cy_1);
wire n0403 = ~(~daa | n0803);
wire [3:0] acc_in = {n0514, n0848, n0847, n0846};
always @(posedge sysclk) begin
if (adsr)
{acc, cy} <= {cy_1, acc_in};
if (add_acc)
acc <= acc_in;
if (adsl)
{cy, acc} <= {acc_in, cy_1};
if (adc_cy)
cy <= n0861;
if (n0403 & n0415)
cy <= 1'b1;
// Dynamic refresh would occur during M12
end
// Accumulator output latch
always @(posedge sysclk) begin
if (n0854) begin
cy_1 <= cy;
acc_out <= acc;
end
end
assign acc_0 = ~|acc_out;
assign add_0 = ~|acc_in;
// Keyboard Process logic
wire n0378 = ~((daa & n0803) | o_ib);
wire n0345 = kbp & (acc_out == 4'b1000);
wire n0354 = kbp & (acc_out == 4'b0100);
wire n0363 = kbp & (acc_out == 4'b0010);
wire n0370 = kbp & (acc_out == 4'b0001);
wire n0377 = (kbp & (acc_out == 4'b0000)) | ~n0378;
wire n0358 = ~(n0345 | n0354 | n0363 | n0370 | n0377 | n0403);
wire n0366 = ~( n0354 | n0363 | n0370 | n0377 | tcs );
wire n0359 = ~(n0345 | n0370 | n0377 | tcs );
wire n0357 = ~(n0345 | n0363 | n0377 | n0403);
// Data output mux
reg [3:0] dout;
always @(*) begin
dout = 4'bzzzz;
if (acb_ib)
dout = acc_out;
if (add_ib)
dout = acc_in;
if (cy_ib)
dout = {3'bxxx, cy_1};
if (n0415)
dout = {n0358, n0366, n0359, n0357};
end
assign data = dout;
// Generate CMROM / CMRAMn
// This may get moved to the Timing & I/O board
// Inputs: {n0355, n0364, n0371}, n0351, poc, com_n
wire n0355 = ~acc_out[2];
wire n0364 = ~acc_out[1];
wire n0371 = ~acc_out[0];
reg n0749, n0750, n0751;
always @(posedge sysclk) begin
if (poc) begin
n0749 <= 1'b1;
n0750 <= 1'b1;
n0751 <= 1'b1;
end
else begin
if (n0351) begin
n0749 <= n0355;
n0750 <= n0364;
n0751 <= n0371;
end
end
end
assign cmram3 = ~(com_n | n0749);
assign cmram2 = ~(com_n | n0750);
assign cmram1 = ~(com_n | n0751);
assign cmram0 = ~(com_n | ~n0749 | ~n0750 | ~n0751);
assign cmrom = ~(com_n | poc);
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module counter(
input wire sysclk,
input wire step_a,
input wire step_b,
output reg q = 1'b0
);
reg q_n = 1'b1;
always @(posedge sysclk) begin
if (step_a) q <= ~q_n;
if (step_b) q_n <= q;
end
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module instruction_decode(
input wire sysclk, // 50 MHz FPGA clock
// Inputs from the Timing and I/O board
input wire clk1,
input wire clk2,
input wire a22,
input wire m12,
input wire m22,
input wire x12,
input wire x22,
input wire x32,
input wire poc, // Power-On Clear (reset)
input wire n0432, // Conditioned TEST_PAD
// Common 4-bit data bus
inout wire [3:0] data,
// These drive the Instruction Pointer (IP) board
output wire jcn_isz, // JCN+ISZ
output wire jin_fin, // JIN+FIN
output wire jun_jms, // JUN+JMS
output wire cn_n, // ~CN
output wire bbl, // BBL
output wire jms, // JMS
// Outputs to both the IP and SP boards
output wire sc, // SC (Single Cycle)
output wire dc, // DC (Double Cycle, ~SC)
// Outputs to the Scratch Pad (SP) board
output wire sc_m22_clk2, // SC&M22&CLK2
output wire fin_fim_src_jin, // FIN+FIM+SRC+JIN
output wire inc_isz_add_sub_xch_ld, // INC+ISZ+ADD+SUB+XCH+LD
output wire inc_isz_xch, // INC+ISZ+XCH
output wire opa0_n, // ~OPA.0
// Inputs from the ALU board (condition bits)
input wire acc_0, // ACC_0
input wire add_0, // ADD_0
input wire cy_1, // CY_1
// Outputs to the Arithmetic Logic Unit (ALU) board
output wire cma,
output wire write_acc_1,
output wire write_carry_2,
output wire read_acc_3,
output wire add_group_4,
output wire inc_group_5,
output wire sub_group_6,
output wire ior,
output wire iow,
output wire ral,
output wire rar,
output wire ope_n,
output wire daa,
output wire dcl,
output wire inc_isz,
output wire kbp,
output wire o_ib,
output wire tcs,
output wire xch,
output wire n0342,
output wire x21_clk2,
output wire x31_clk2,
output wire com_n
);
wire sc_m12_clk2 = sc & m12 & clk2;
assign sc_m22_clk2 = sc & m22 & clk2;
// Latch the first 4 bits of the opcode
reg [3:0] opr = 4'b0000;
always @(posedge sysclk) begin
if (sc_m12_clk2)
opr <= data;
end
// Latch the second 4 bits of the opcode
reg [3:0] opa = 4'b0000;
always @(posedge sysclk) begin
if (sc_m22_clk2)
opa <= data;
end
assign opa0_n = ~opa[0];
// Full OPR Decoding
wire nop = (opr == 4'b0000);
wire jcn = (opr == 4'b0001);
wire fim_src = (opr == 4'b0010);
assign jin_fin = (opr == 4'b0011);
wire jun = (opr == 4'b0100);
assign jms = (opr == 4'b0101);
wire inc = (opr == 4'b0110);
wire isz = (opr == 4'b0111);
wire add = (opr == 4'b1000);
wire sub = (opr == 4'b1001);
wire ld = (opr == 4'b1010);
assign xch = (opr == 4'b1011);
assign bbl = (opr == 4'b1100);
wire ldm = (opr == 4'b1101);
wire io = (opr == 4'b1110);
wire ope = (opr == 4'b1111);
assign ope_n = ~ope;
assign jcn_isz = jcn | isz;
assign jun_jms = jun | jms;
wire ldm_bbl = ldm | bbl;
assign inc_isz = (inc | isz) & sc;
assign inc_isz_xch = inc | isz | xch;
assign inc_isz_add_sub_xch_ld = inc | isz | add | sub | xch | ld;
assign fin_fim_src_jin = fim_src | jin_fin;
// OPE: OPA Decoding
assign o_ib = ope & (opa[3] == 1'b0);
wire clb = ope & (opa == 4'b0000);
wire clc = ope & (opa == 4'b0001);
wire iac = ope & (opa == 4'b0010);
wire cmc = ope & (opa == 4'b0011);
assign cma = ope & (opa == 4'b0100);
assign ral = ope & (opa == 4'b0101);
assign rar = ope & (opa == 4'b0110);
wire tcc = ope & (opa == 4'b0111);
wire dac = ope & (opa == 4'b1000);
assign tcs = ope & (opa == 4'b1001);
wire stc = ope & (opa == 4'b1010);
assign daa = ope & (opa == 4'b1011);
assign kbp = ope & (opa == 4'b1100);
assign dcl = ope & (opa == 4'b1101);
// IO: OPA Decoding
assign iow = io & (opa[3] == 1'b0);
assign ior = io & (opa[3] == 1'b1);
wire adm = io & (opa == 4'b1011);
wire sbm = io & (opa == 4'b1000);
wire fin_fim = fin_fim_src_jin & ~opa[0];
wire src = fim_src & opa[0];
assign write_acc_1 = ~(kbp | tcs | daa | xch | poc | cma | tcc | dac | iac |
clb | ior | ld | sub | add | ldm_bbl);
assign write_carry_2 = ~(tcs | poc | tcc | stc | cmc | dac | iac |
clc | clb | sbm | adm | sub | add);
assign read_acc_3 = ~(daa | rar | ral | dac | iac | sbm | adm | sub | add);
assign add_group_4 = ~(tcs | tcc | adm | add);
assign inc_group_5 = ~(inc_isz | stc | iac);
assign sub_group_6 = ~(cmc | sbm | sub | m12);
// The Condition Flip-Flop
reg n0397;
wire n0486 = ~((opa[2] & acc_0) | (opa[1] & cy_1) | (opa[0] & n0432));
wire n0419 = ~((add_0 & ~isz) & (~jcn | ((~n0486 | opa[3]) & (n0486 | ~opa[3]))));
wire n0413 = ~((sc & n0419 & x32) | (~x32 | n0397));
reg n0405;
always @(posedge sysclk) begin
if (clk2)
n0405 <= n0413;
if (clk1)
n0397 <= ~n0405;
end
assign cn_n = ~n0397;
// The Single-Cycle Flip-Flop
reg n0343;
wire n0368 = ~((sc & (fin_fim | jcn_isz | jun_jms) & x32) | (n0343 & ~x32));
reg n0362;
always @(posedge sysclk) begin
if (clk2)
n0362 <= n0368;
if (clk1)
n0343 <= ~n0362;
end
assign sc = ~n0343;
assign dc = ~sc;
// Generate ~(X21&~CLK2)
reg n0360;
always @(posedge sysclk) begin
if (clk2)
n0360 <= ~x12;
end
wire n0337 = ~(n0360 | clk2);
assign x21_clk2 = ~n0337;
// Generate ~(X31&~CLK2)
reg n0380;
always @(posedge sysclk) begin
if (clk2)
n0380 <= ~x22;
end
wire n0375 = ~(n0380 | clk2);
assign x31_clk2 = ~n0375;
// Generate ~COM
wire n0329 = io;
reg n0414, n0797;
always @(posedge sysclk) begin
if (clk2)
n0414 <= a22;
else
n0797 <= n0414;
end
reg n0433, n0801;
always @(posedge sysclk) begin
if (clk2)
n0433 <= m12;
else
n0801 <= n0433;
end
reg n0425, n0805;
always @(posedge sysclk) begin
if (clk2)
n0425 <= x12;
else
n0805 <= n0425;
end
wire n0782 = ~((n0801 & n0329) | (src & n0805) | n0797);
assign com_n = n0782;
// Generate N0342
wire n0332 = ~(((n0329 | poc) & x22 & clk2) | (~(n0329 | poc) & n0337 & clk1));
assign n0342 = n0332;
// Output OPA onto the data bus
wire opa_ib = (ldm_bbl | jun_jms) & ~x21_clk2;
assign data = opa_ib ? opa : 4'bzzzz;
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module instruction_pointer (
input wire sysclk, // 50 MHz FPGA clock
// Inputs from the Timing and I/O board
input wire clk1,
input wire clk2,
input wire a12,
input wire a22,
input wire a32,
input wire m12,
input wire m22,
input wire x12,
input wire x22,
input wire x32,
input wire poc, // Power-On Clear (reset)
input wire m12_m22_clk1_m11_m12, // M12+M22+CLK1~(M11+M12)
// Common 4-bit data bus
inout wire [3:0] data,
// Inputs from the Instruction Decode board
input wire jcn_isz, // JCN+ISZ
input wire jin_fin, // JIN+FIN
input wire jun_jms, // JUN+JMS
input wire cn_n, // ~CN
input wire bbl, // BBL
input wire jms, // JMS
input wire sc, // SC (Single Cycle)
input wire dc // DC (Double Cycle, ~SC)
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module scratchpad (
input wire sysclk, // 50 MHz FPGA clock
// Inputs from the Timing and I/O board
input wire clk1,
input wire clk2,
input wire a12,
input wire a22,
input wire a32,
input wire m12,
input wire m22,
input wire x12,
input wire x22,
input wire x32,
input wire poc, // Power-On Clear (reset)
input wire m12_m22_clk1_m11_m12, // M12+M22+CLK1~(M11+M12)
// Common 4-bit data bus
inout wire [3:0] data,
// Inputs from the Instruction Decode board
input wire sc_m22_clk2, // SC&M22&CLK2
input wire fin_fim_src_jin, // FIN+FIM+SRC+JIN
input wire inc_isz_add_sub_xch_ld, // INC+ISZ+ADD+SUB+XCH+LD
input wire inc_isz_xch, // INC+ISZ+XCH
input wire opa0_n, // ~OPA.0
input wire sc, // SC (Single Cycle)
input wire dc // DC (Double Cycle, ~SC)
);
reg [7:0] dram_array [0:7];
reg [7:0] dram_temp;
reg [3:0] din_n;
// Refresh counter stuff
wire [2:0] reg_rfsh; // Row Refresh counter
wire reg_rfsh_step; // SC&A12&CLK2
assign reg_rfsh_step = sc & a12 & clk2;
counter reg_rfsh_0 (
.sysclk(sysclk),
.step_a(clk1),
.step_b(reg_rfsh_step),
.q(reg_rfsh[0])
);
counter reg_rfsh_1 (
.sysclk(sysclk),
.step_a( reg_rfsh[0]),
.step_b(~reg_rfsh[0]),
.q(reg_rfsh[1])
);
counter reg_rfsh_2 (
.sysclk(sysclk),
.step_a( reg_rfsh[1]),
.step_b(~reg_rfsh[1]),
.q(reg_rfsh[2])
);
// Row selection mux
reg [2:0] row; // {N0646, N0617, N0582}
always @(posedge sysclk) begin
if (sc & a22)
row <= reg_rfsh;
if (sc_m22_clk2)
row <= data[3:1];
end
// Row Precharge/Read/Write stuff
wire precharge; // SC(A22+M22)CLK2
wire row_read; // (~POC)&CLK2&SC(A32+X12)
wire row_write; // CLK2&SC(A12+M12)
assign precharge = sc & (a22 | m22) & clk2;
assign row_read = ~(poc | ~(clk2 & sc & (a32 | x12)));
assign row_write = sc & (a12 | m12) & clk2;
// Column Read selection stuff
reg n0615;
always @(posedge sysclk) begin
if (clk2)
n0615 <= ~(x12 & (fin_fim_src_jin |
(opa0_n & inc_isz_add_sub_xch_ld)));
end
wire rrab0 = ~(dc | n0615 | clk2);
reg n0592;
always @(posedge sysclk) begin
if (clk2)
n0592 <= ~((x22 & fin_fim_src_jin) |
(~opa0_n & x12 & inc_isz_add_sub_xch_ld));
end
wire rrab1 = ~(dc | n0592 | clk2);
// Column Write selection stuff
wire n0564 = opa0_n & fin_fim_src_jin & dc;
wire n0568 = inc_isz_xch & x32 & sc;
wire wrab0 = clk2 & ((m12 & n0564) | ( opa0_n & n0568));
wire wrab1 = clk2 & ((m22 & n0564) | (~opa0_n & n0568));
// Manage the row data buffer
always @(posedge sysclk) begin
if (precharge)
dram_temp <= 8'b0;
if (row_read)
dram_temp <= dram_array[row];
if (wrab0)
dram_temp[ 3:0] <= ~din_n;
if (wrab1)
dram_temp[ 7:4] <= ~din_n;
end
// Handle row writes
always @(posedge sysclk) begin
if (row_write)
dram_array[row] <= dram_temp;
end
// Manage the data output mux
reg [3:0] dout;
always @* begin
(* PARALLEL_CASE *)
case (1'b1)
rrab0: dout = dram_temp[ 3:0];
rrab1: dout = dram_temp[ 7:4];
default: dout = 4'bzzzz;
endcase
end
assign data = dout;
// Data In latch
always @(posedge sysclk) begin
if (m12_m22_clk1_m11_m12)
din_n <= ~data;
end
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module timing_io(
input wire sysclk,
input wire clk1_pad,
input wire clk2_pad,
input wire poc_pad,
input wire ior,
// Timing and I/O Board Outputs
output wire clk1,
output wire clk2,
output wire a12,
output wire a22,
output wire a32,
output wire m12,
output wire m22,
output wire x12,
output wire x22,
output wire x32,
output wire gate,
output reg poc,
// External I/O Pad conditioning
inout wire [3:0] data,
inout wire [3:0] data_in_pad,
output wire [3:0] data_out_pad,
input wire test_pad,
output reg n0432,
output reg sync_pad,
input wire cmrom,
output wire cmrom_pad,
input wire cmram0,
output wire cmram0_pad,
input wire cmram1,
output wire cmram1_pad,
input wire cmram2,
output wire cmram2_pad,
input wire cmram3,
output wire cmram3_pad
);
// Simple pass-throughs
assign clk1 = clk1_pad;
assign clk2 = clk2_pad;
assign cmrom_pad = cmrom;
assign cmram0_pad = cmram0;
assign cmram1_pad = cmram1;
assign cmram2_pad = cmram2;
assign cmram3_pad = cmram3;
// Generate the 8 execution phase indicators
reg [0:7] master = 8'h00;
reg [0:7] slave = 8'h00;
always @(posedge sysclk) begin
if (clk2)
master <= {~|slave[0:6], slave[0:6]};
else
sync_pad <= master[7];
if (clk1)
slave <= master;
end
assign a12 = slave[0];
assign a22 = slave[1];
assign a32 = slave[2];
assign m12 = slave[3];
assign m22 = slave[4];
assign x12 = slave[5];
assign x22 = slave[6];
assign x32 = slave[7];
// Generate the DRAM Input Gate signal
// Properly called M12+M22+CLK1~(M11&M12)
wire n0279 = ~(a32 | m12);
reg n0278;
always @(posedge sysclk) begin
if (clk2)
n0278 <= n0279;
end
wire n0708 = ~((n0278 & clk1) | m12 | m22);
assign gate = ~n0708;
// Generate a clean POC signal
always @(posedge sysclk) begin
if (poc_pad) poc <= 1'b1;
else if (a12) poc <= 1'b0;
else poc <= poc;
end
// Generate a clean ~TEST signal (n0432)
always @(posedge sysclk) begin
n0432 <= ~test_pad;
end
// Manage the Data I/O pads
reg L;
always @(posedge sysclk) begin
if (clk2)
L <= a32 | m12 | (x12 & (ior | poc));
end
wire n0702 = ~clk2;
reg n0685;
reg n0699;
reg n0707;
always @(posedge sysclk) begin
if (clk1) begin
n0685 <= ~L;
n0707 <= L;
end
if (n0702)
n0699 <= ~L;
end
wire n0700 = n0707 | (L & n0702) | poc;
wire n0659 = (clk2 & n0685) | (clk1 & L);
wire n0676 = clk1 | n0685 | n0699;
// Incoming data from the external pads
reg [3:0] data_in;
always @* begin
if (n0659) data_in = 4'b1111;
else if (n0676) data_in = 4'bzzzz;
else if (poc) data_in = 4'b0000;
else data_in = data_in_pad;
end
assign data = data_in;
// Outgoing data to the external pads
reg [3:0] data_out;
always @(posedge sysclk) begin
if (n0702)
data_out <= data;
end
assign data_out_pad = poc ? 4'b0000 : (n0700 ? 4'bzzzz : data_out);
assign data_in_pad = poc ? 4'b0000 : (n0700 ? 4'bzzzz : data_out);
endmodule
|
module instruction_pointer (
input wire sysclk, // 50 MHz FPGA clock
// Inputs from the Timing and I/O board
input wire clk1,
input wire clk2,
input wire a12,
input wire a22,
input wire a32,
input wire m12,
input wire m22,
input wire x12,
input wire x22,
input wire x32,
input wire poc, // Power-On Clear (reset)
input wire m12_m22_clk1_m11_m12, // M12+M22+CLK1~(M11+M12)
// Common 4-bit data bus
inout wire [3:0] data,
// Inputs from the Instruction Decode board
input wire jcn_isz, // JCN+ISZ
input wire jin_fin, // JIN+FIN
input wire jun_jms, // JUN+JMS
input wire cn_n, // ~CN
input wire bbl, // BBL
input wire jms, // JMS
input wire sc, // SC (Single Cycle)
input wire dc // DC (Double Cycle, ~SC)
);
reg [11:0] dram_array [0:3];
reg [11:0] dram_temp;
wire [3:0] din_n;
wire inh = (jin_fin & sc) | ((jun_jms | (jcn_isz & ~cn_n)) & dc);
// Row Counter stuff
wire [1:0] addr_ptr; // Effective Address counter
wire addr_ptr_step; // CLK2(JMS&DC&M22+BBL(M22+X12+X22))
assign addr_ptr_step = ~(~clk2 | ~(((m22 | x12 | x22) & bbl) |
(m22 & dc & jms)));
counter addr_ptr_0 (
.sysclk(sysclk),
.step_a(clk1),
.step_b(addr_ptr_step),
.q(addr_ptr[0])
);
counter addr_ptr_1 (
.sysclk(sysclk),
.step_a( addr_ptr[0]),
.step_b(~addr_ptr[0]),
.q(addr_ptr[1])
);
// Refresh counter stuff
wire [1:0] addr_rfsh; // Row Refresh counter
wire addr_rfsh_step; // (~INH)&X32&CLK2
assign addr_rfsh_step = ~inh & x32 & clk2;
counter addr_rfsh_0 (
.sysclk(sysclk),
.step_a(clk1),
.step_b(addr_rfsh_step),
.q(addr_rfsh[0])
);
counter addr_rfsh_1 (
.sysclk(sysclk),
.step_a( addr_rfsh[0]),
.step_b(~addr_rfsh[0]),
.q(addr_rfsh[1])
);
// Row selection mux
reg [1:0] row; // {N0409, N0420}
always @(posedge sysclk) begin
if (x12)
row <= addr_rfsh;
if (x32)
row <= addr_ptr;
end
// Row Precharge/Read/Write stuff
wire precharge; // (~INH)(X11+X31)CLK1
wire row_read; // (~POC)CLK2(X12+X32)~INH
wire row_write; // ((~SC)(JIN+FIN))CLK1(M11+X21~INH)
reg n0517;
always @(posedge sysclk) begin
if (clk2)
n0517 <= ~(m22 | x22);
end
assign precharge = ~(n0517 | inh | ~clk1);
assign row_read = ~poc & clk2 & (x12 | x32) & ~inh;
reg n0438;
always @(posedge sysclk) begin
if (clk2)
n0438 <= ~((x12 & ~inh) | a32);
end
assign row_write = ~(n0438 | (jin_fin & ~sc) | ~clk1);
// Column Read selection stuff
reg n0416;
always @(posedge sysclk) begin
if (clk2)
n0416 <= ~x32;
end
wire radb0 = ~(n0416 | clk2);
reg n0384;
always @(posedge sysclk) begin
if (clk2)
n0384 <= ~a12;
end
wire radb1 = ~(n0384 | clk2);
reg n0374;
always @(posedge sysclk) begin
if (clk2)
n0374 <= ~a22;
end
wire radb2 = ~(n0374 | clk2);
// Column Write selection stuff
wire n0322 = ~(sc | cn_n);
wire wadb0 = ~(~clk2 | ~(a12 | (sc & jin_fin & x32) |
(((jcn_isz & n0322) | (jun_jms & ~sc)) & m22)));
wire wadb1 = ~(~clk2 | ~(a22 | (sc & jin_fin & x22) |
(((jcn_isz & n0322) | (jun_jms & ~sc)) & m12)));
wire wadb2 = ~(~clk2 | ~(a32 | (jun_jms & ~sc & x22)));
// Manage the row data buffer
always @(posedge sysclk) begin
if (precharge)
dram_temp <= 12'b0;
if (row_read)
dram_temp <= dram_array[row];
if (wadb0)
dram_temp[ 3:0] <= ~din_n;
if (wadb1)
dram_temp[ 7:4] <= ~din_n;
if (wadb2)
dram_temp[11:8] <= ~din_n;
end
// Handle row writes
always @(posedge sysclk) begin
if (row_write)
dram_array[row] <= dram_temp;
end
// Manage the data output mux
reg [3:0] dout;
always @* begin
(* PARALLEL_CASE *)
case (1'b1)
radb0: dout = dram_temp[ 3:0];
radb1: dout = dram_temp[ 7:4];
radb2: dout = dram_temp[11:8];
default: dout = 4'bzzzz;
endcase
end
assign data = dout;
// Data In mux and incrementer
reg [3:0] incr_in;
always @(posedge sysclk) begin
if (m12_m22_clk1_m11_m12)
incr_in <= data;
end
reg carry_out, carry_in;
wire [4:0] incr_out = (a12 | ((a22 | a32) & carry_in)) ?
(incr_in + 4'b0001) : {1'b0, incr_in};
always @(posedge sysclk) begin
if (clk2)
carry_out <= incr_out[4];
if (clk1)
carry_in <= carry_out;
end
assign din_n = ~incr_out[3:0];
endmodule
|
tt06-finale_0085
|
tt06-finale
|
noritsuna-tt06-tt_um_i4004
|
task_scratchpad
|
tt_um_noritsuna_i4004
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module tt_um_noritsuna_i4004 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena,
input wire clk,
input wire rst_n
);
wire sysclk;
wire clk1_pad;
wire clk2_pad;
wire poc_pad;
wire test_pad;
wire [3:0] data_in_pad;
wire [3:0] data_out_pad;
wire cmrom_pad;
wire cmram0_pad;
wire cmram1_pad;
wire cmram2_pad;
wire cmram3_pad;
wire sync_pad;
//input:
assign sysclk = clk;
assign data_in_pad = ui_in[3:0];
assign clk1_pad = ui_in[4];
assign clk2_pad = ui_in[5];
assign poc_pad = ui_in[6];
assign test_pad = ui_in[7];
//output:
assign cmrom_pad = uo_out[0];
assign cmram0_pad = uo_out[1];
assign cmram1_pad = uo_out[2];
assign cmram2_pad = uo_out[3];
assign cmram3_pad = uo_out[4];
assign sync_pad = uo_out[5];
assign uio_oe[3:0] = 1;
assign data_out_pad = uio_out[3:0];
// All output pins must be assigned. If not used, assign to 0.
assign uo_out[6] = 0;
assign uo_out[7] = 0;
assign uio_out[7:4] = 0;
assign uio_oe[7:4] = 0;
// Common BiDir data bus
wire [3:0] data;
// Timing and I/O Board Outputs
wire clk1;
wire clk2;
wire a12;
wire a22;
wire a32;
wire m12;
wire m22;
wire x12;
wire x22;
wire x32;
wire gate;
wire poc; // Clean POC_PAD
wire n0432; // Clean TEST_PAD
// Outputs from the Instruction Decode board
wire jcn_isz;
wire jin_fin;
wire jun_jms;
wire cn_n;
wire bbl;
wire jms;
wire sc;
wire dc;
wire sc_m22_clk2;
wire fin_fim_src_jin;
wire inc_isz_add_sub_xch_ld;
wire inc_isz_xch;
wire opa0_n;
wire cma;
wire write_acc_1;
wire write_carry_2;
wire read_acc_3;
wire add_group_4;
wire inc_group_5;
wire sub_group_6;
wire ior;
wire iow;
wire ral;
wire rar;
wire ope_n;
wire daa;
wire dcl;
wire inc_isz;
wire kbp;
wire o_ib;
wire tcs;
wire xch;
wire n0342;
wire x21_clk2;
wire x31_clk2;
wire com_n;
// Outputs from the ALU board
wire acc_0;
wire add_0;
wire cy_1;
wire cmram0;
wire cmram1;
wire cmram2;
wire cmram3;
wire cmrom;
// Instantiate the Timing and I/O board
timing_io tio_board (
.sysclk(sysclk),
.clk1_pad(clk1_pad),
.clk2_pad(clk2_pad),
.poc_pad(poc_pad),
.ior(ior),
.clk1(clk1),
.clk2(clk2),
.a12(a12),
.a22(a22),
.a32(a32),
.m12(m12),
.m22(m22),
.x12(x12),
.x22(x22),
.x32(x32),
.gate(gate),
.poc(poc),
.data(data),
.data_in_pad(data_in_pad),
.data_out_pad(data_out_pad),
.test_pad(test_pad),
.n0432(n0432),
.sync_pad(sync_pad),
.cmrom(cmrom),
.cmrom_pad(cmrom_pad),
.cmram0(cmram0),
.cmram0_pad(cmram0_pad),
.cmram1(cmram1),
.cmram1_pad(cmram1_pad),
.cmram2(cmram2),
.cmram2_pad(cmram2_pad),
.cmram3(cmram3),
.cmram3_pad(cmram3_pad)
);
// Instantiate the Instruction Decode board
instruction_decode id_board (
.sysclk(clk),
.clk1(clk1),
.clk2(clk2),
.a22(a22),
.m12(m12),
.m22(m22),
.x12(x12),
.x22(x22),
.x32(x32),
.poc(poc),
.n0432(n0432),
.data(data),
.jcn_isz(jcn_isz),
.jin_fin(jin_fin),
.jun_jms(jun_jms),
.cn_n(cn_n),
.bbl(bbl),
.jms(jms),
.sc(sc),
.dc(dc),
.sc_m22_clk2(sc_m22_clk2),
.fin_fim_src_jin(fin_fim_src_jin),
.inc_isz_add_sub_xch_ld(inc_isz_add_sub_xch_ld),
.inc_isz_xch(inc_isz_xch),
.opa0_n(opa0_n),
.acc_0(acc_0),
.add_0(add_0),
.cy_1(cy_1),
.cma(cma),
.write_acc_1(write_acc_1),
.write_carry_2(write_carry_2),
.read_acc_3(read_acc_3),
.add_group_4(add_group_4),
.inc_group_5(inc_group_5),
.sub_group_6(sub_group_6),
.ior(ior),
.iow(iow),
.ral(ral),
.rar(rar),
.ope_n(ope_n),
.daa(daa),
.dcl(dcl),
.inc_isz(inc_isz),
.kbp(kbp),
.o_ib(o_ib),
.tcs(tcs),
.xch(xch),
.n0342(n0342),
.x21_clk2(x21_clk2),
.x31_clk2(x31_clk2),
.com_n(com_n)
);
// Instantiate the ALU board
alu alu_board (
.sysclk(clk),
.a12(a12),
.m12(m12),
.x12(x12),
.poc(poc),
.data(data),
.acc_0(acc_0),
.add_0(add_0),
.cy_1(cy_1),
.cma(cma),
.write_acc_1(write_acc_1),
.write_carry_2(write_carry_2),
.read_acc_3(read_acc_3),
.add_group_4(add_group_4),
.inc_group_5(inc_group_5),
.sub_group_6(sub_group_6),
.ior(ior),
.iow(iow),
.ral(ral),
.rar(rar),
.ope_n(ope_n),
.daa(daa),
.dcl(dcl),
.inc_isz(inc_isz),
.kbp(kbp),
.o_ib(o_ib),
.tcs(tcs),
.xch(xch),
.n0342(n0342),
.x21_clk2(x21_clk2),
.x31_clk2(x31_clk2),
.com_n(com_n),
.cmram0(cmram0),
.cmram1(cmram1),
.cmram2(cmram2),
.cmram3(cmram3),
.cmrom(cmrom)
);
// Instantiate the Instruction Pointer board
instruction_pointer ip_board (
.sysclk(clk),
.clk1(clk1),
.clk2(clk2),
.a12(a12),
.a22(a22),
.a32(a32),
.m12(m12),
.m22(m22),
.x12(x12),
.x22(x22),
.x32(x32),
.poc(poc),
.m12_m22_clk1_m11_m12(gate),
.data(data),
.jcn_isz(jcn_isz),
.jin_fin(jin_fin),
.jun_jms(jun_jms),
.cn_n(cn_n),
.bbl(bbl),
.jms(jms),
.sc(sc),
.dc(dc)
);
// Instantiate the Scratchpad board
scratchpad sp_board (
.sysclk(clk),
.clk1(clk1),
.clk2(clk2),
.a12(a12),
.a22(a22),
.a32(a32),
.m12(m12),
.m22(m22),
.x12(x12),
.x22(x22),
.x32(x32),
.poc(poc),
.m12_m22_clk1_m11_m12(gate),
.data(data),
.sc_m22_clk2(sc_m22_clk2),
.fin_fim_src_jin(fin_fim_src_jin),
.inc_isz_add_sub_xch_ld(inc_isz_add_sub_xch_ld),
.inc_isz_xch(inc_isz_xch),
.opa0_n(opa0_n),
.sc(sc),
.dc(dc)
);
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module alu(
input wire sysclk,
// Inputs from the Timing and I/O board
input wire a12,
input wire m12,
input wire x12,
input wire poc,
// Common 4-bit data bus
inout wire [3:0] data,
// Outputs to the Instruction Decode board
output wire acc_0,
output wire add_0,
output reg cy_1,
// Inputs from the Instruction Decode board
input wire cma,
input wire write_acc_1,
input wire write_carry_2,
input wire read_acc_3,
input wire add_group_4,
input wire inc_group_5,
input wire sub_group_6,
input wire ior,
input wire iow,
input wire ral,
input wire rar,
input wire ope_n,
input wire daa,
input wire dcl,
input wire inc_isz,
input wire kbp,
input wire o_ib,
input wire tcs,
input wire xch,
input wire n0342,
input wire x21_clk2,
input wire x31_clk2,
input wire com_n,
// Outputs to external pins
output wire cmram0,
output wire cmram1,
output wire cmram2,
output wire cmram3,
output wire cmrom
);
reg [3:0] acc;
reg cy;
// Decode logic
wire n0854 = ~(~x12);
wire n0351 = ~(x21_clk2 | ~dcl);
wire n0415 = ~(x21_clk2 | ope_n);
wire add_ib = ~(x31_clk2 | ~inc_isz);
wire cy_ib = ~(x31_clk2 | ~iow);
wire acb_ib = ~((x31_clk2 | ~xch) & (x21_clk2 | ~iow));
wire n0477 = ~((~x31_clk2 & ~ior) | (a12 & ior));
wire adc_cy = ~(write_carry_2 | n0477);
wire add_acc = ~(write_acc_1 | n0477);
wire adsr = ~(x31_clk2 | ~rar);
wire adsl = ~(x31_clk2 | ~ral);
wire acc_adac = ~(~cma | n0342);
wire acc_ada = ~(read_acc_3 | n0342);
wire cy_ada = ~(add_group_4 | n0342);
wire cy_adac = ~(sub_group_6 | n0342);
// Latch the incoming data bus
reg [3:0] tmp; // It's the name used in simulator!
always @(posedge sysclk) begin
if (~n0342)
tmp <= data;
if (m12)
tmp <= 4'b1111;
end
// Invert some of the incoming data
reg n0893, n0891, n0889, n0887; // D3, D2, D1, D0
always @(posedge sysclk) begin
if (sub_group_6) begin
n0887 <= tmp[0];
n0889 <= ~tmp[1];
n0891 <= tmp[2];
n0893 <= ~tmp[3];
end
if (~(sub_group_6 | m12)) begin
n0887 <= ~tmp[0];
n0889 <= tmp[1];
n0891 <= ~tmp[2];
n0893 <= tmp[3];
end
end
// Feedback from Accumulator
reg n0873, n0872, n0871, n0870;
always @(posedge sysclk) begin
if (m12)
{n0873, n0872, n0871, n0870} <= 4'b1010;
if (acc_ada)
{n0873, n0872, n0871, n0870} <= acc;
if (acc_adac)
{n0873, n0872, n0871, n0870} <= ~acc;
end
// Carry generator
wire n0546 = ~(inc_group_5 | n0342);
reg n0550;
always @(posedge sysclk) begin
if (m12) n0550 <= 1'b0;
if (n0546) n0550 <= 1'b1;
if (cy_adac) n0550 <= ~cy;
if (cy_ada) n0550 <= cy;
end
wire n0911 = ~(n0550 ? (n0887 | n0870) : (n0887 & n0870));
wire n0553 = n0911;
wire n0912 = ~(n0553 ? (n0889 | n0871) : (n0889 & n0871));
wire n0556 = n0912;
wire n0913 = ~(n0556 ? (n0891 | n0872) : (n0891 & n0872));
wire n0559 = n0913;
wire n0914 = ~(n0559 ? (n0893 | n0873) : (n0893 & n0873));
wire n0861 = n0914;
// Adder
wire n0877 = ~((n0893 & n0559 & n0873) | (n0861 & (n0893 | n0873 | n0559)));
wire n0878 = ~((n0877 & n0550 & n0870) | (n0553 & (n0887 | n0870 | n0550)));
wire n0875 = ~((n0889 & n0553 & n0871) | (n0556 & (n0889 | n0871 | n0553)));
wire n0879 = ~((n0891 & n0556 & n0872) | (n0559 & (n0891 | n0872 | n0556)));
wire n0846 = ~n0878;
wire n0847 = n0875;
wire n0848 = ~n0879;
wire n0514 = n0877;
// Shifter / Accumulator and Carry
reg [3:0] acc_out; // {n0356, n0348, n0347, n0346}
wire n0803 = ~((acc_out[3] & (acc_out[2] | acc_out[1])) | cy_1);
wire n0403 = ~(~daa | n0803);
wire [3:0] acc_in = {n0514, n0848, n0847, n0846};
always @(posedge sysclk) begin
if (adsr)
{acc, cy} <= {cy_1, acc_in};
if (add_acc)
acc <= acc_in;
if (adsl)
{cy, acc} <= {acc_in, cy_1};
if (adc_cy)
cy <= n0861;
if (n0403 & n0415)
cy <= 1'b1;
// Dynamic refresh would occur during M12
end
// Accumulator output latch
always @(posedge sysclk) begin
if (n0854) begin
cy_1 <= cy;
acc_out <= acc;
end
end
assign acc_0 = ~|acc_out;
assign add_0 = ~|acc_in;
// Keyboard Process logic
wire n0378 = ~((daa & n0803) | o_ib);
wire n0345 = kbp & (acc_out == 4'b1000);
wire n0354 = kbp & (acc_out == 4'b0100);
wire n0363 = kbp & (acc_out == 4'b0010);
wire n0370 = kbp & (acc_out == 4'b0001);
wire n0377 = (kbp & (acc_out == 4'b0000)) | ~n0378;
wire n0358 = ~(n0345 | n0354 | n0363 | n0370 | n0377 | n0403);
wire n0366 = ~( n0354 | n0363 | n0370 | n0377 | tcs );
wire n0359 = ~(n0345 | n0370 | n0377 | tcs );
wire n0357 = ~(n0345 | n0363 | n0377 | n0403);
// Data output mux
reg [3:0] dout;
always @(*) begin
dout = 4'bzzzz;
if (acb_ib)
dout = acc_out;
if (add_ib)
dout = acc_in;
if (cy_ib)
dout = {3'bxxx, cy_1};
if (n0415)
dout = {n0358, n0366, n0359, n0357};
end
assign data = dout;
// Generate CMROM / CMRAMn
// This may get moved to the Timing & I/O board
// Inputs: {n0355, n0364, n0371}, n0351, poc, com_n
wire n0355 = ~acc_out[2];
wire n0364 = ~acc_out[1];
wire n0371 = ~acc_out[0];
reg n0749, n0750, n0751;
always @(posedge sysclk) begin
if (poc) begin
n0749 <= 1'b1;
n0750 <= 1'b1;
n0751 <= 1'b1;
end
else begin
if (n0351) begin
n0749 <= n0355;
n0750 <= n0364;
n0751 <= n0371;
end
end
end
assign cmram3 = ~(com_n | n0749);
assign cmram2 = ~(com_n | n0750);
assign cmram1 = ~(com_n | n0751);
assign cmram0 = ~(com_n | ~n0749 | ~n0750 | ~n0751);
assign cmrom = ~(com_n | poc);
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module counter(
input wire sysclk,
input wire step_a,
input wire step_b,
output reg q = 1'b0
);
reg q_n = 1'b1;
always @(posedge sysclk) begin
if (step_a) q <= ~q_n;
if (step_b) q_n <= q;
end
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module instruction_decode(
input wire sysclk, // 50 MHz FPGA clock
// Inputs from the Timing and I/O board
input wire clk1,
input wire clk2,
input wire a22,
input wire m12,
input wire m22,
input wire x12,
input wire x22,
input wire x32,
input wire poc, // Power-On Clear (reset)
input wire n0432, // Conditioned TEST_PAD
// Common 4-bit data bus
inout wire [3:0] data,
// These drive the Instruction Pointer (IP) board
output wire jcn_isz, // JCN+ISZ
output wire jin_fin, // JIN+FIN
output wire jun_jms, // JUN+JMS
output wire cn_n, // ~CN
output wire bbl, // BBL
output wire jms, // JMS
// Outputs to both the IP and SP boards
output wire sc, // SC (Single Cycle)
output wire dc, // DC (Double Cycle, ~SC)
// Outputs to the Scratch Pad (SP) board
output wire sc_m22_clk2, // SC&M22&CLK2
output wire fin_fim_src_jin, // FIN+FIM+SRC+JIN
output wire inc_isz_add_sub_xch_ld, // INC+ISZ+ADD+SUB+XCH+LD
output wire inc_isz_xch, // INC+ISZ+XCH
output wire opa0_n, // ~OPA.0
// Inputs from the ALU board (condition bits)
input wire acc_0, // ACC_0
input wire add_0, // ADD_0
input wire cy_1, // CY_1
// Outputs to the Arithmetic Logic Unit (ALU) board
output wire cma,
output wire write_acc_1,
output wire write_carry_2,
output wire read_acc_3,
output wire add_group_4,
output wire inc_group_5,
output wire sub_group_6,
output wire ior,
output wire iow,
output wire ral,
output wire rar,
output wire ope_n,
output wire daa,
output wire dcl,
output wire inc_isz,
output wire kbp,
output wire o_ib,
output wire tcs,
output wire xch,
output wire n0342,
output wire x21_clk2,
output wire x31_clk2,
output wire com_n
);
wire sc_m12_clk2 = sc & m12 & clk2;
assign sc_m22_clk2 = sc & m22 & clk2;
// Latch the first 4 bits of the opcode
reg [3:0] opr = 4'b0000;
always @(posedge sysclk) begin
if (sc_m12_clk2)
opr <= data;
end
// Latch the second 4 bits of the opcode
reg [3:0] opa = 4'b0000;
always @(posedge sysclk) begin
if (sc_m22_clk2)
opa <= data;
end
assign opa0_n = ~opa[0];
// Full OPR Decoding
wire nop = (opr == 4'b0000);
wire jcn = (opr == 4'b0001);
wire fim_src = (opr == 4'b0010);
assign jin_fin = (opr == 4'b0011);
wire jun = (opr == 4'b0100);
assign jms = (opr == 4'b0101);
wire inc = (opr == 4'b0110);
wire isz = (opr == 4'b0111);
wire add = (opr == 4'b1000);
wire sub = (opr == 4'b1001);
wire ld = (opr == 4'b1010);
assign xch = (opr == 4'b1011);
assign bbl = (opr == 4'b1100);
wire ldm = (opr == 4'b1101);
wire io = (opr == 4'b1110);
wire ope = (opr == 4'b1111);
assign ope_n = ~ope;
assign jcn_isz = jcn | isz;
assign jun_jms = jun | jms;
wire ldm_bbl = ldm | bbl;
assign inc_isz = (inc | isz) & sc;
assign inc_isz_xch = inc | isz | xch;
assign inc_isz_add_sub_xch_ld = inc | isz | add | sub | xch | ld;
assign fin_fim_src_jin = fim_src | jin_fin;
// OPE: OPA Decoding
assign o_ib = ope & (opa[3] == 1'b0);
wire clb = ope & (opa == 4'b0000);
wire clc = ope & (opa == 4'b0001);
wire iac = ope & (opa == 4'b0010);
wire cmc = ope & (opa == 4'b0011);
assign cma = ope & (opa == 4'b0100);
assign ral = ope & (opa == 4'b0101);
assign rar = ope & (opa == 4'b0110);
wire tcc = ope & (opa == 4'b0111);
wire dac = ope & (opa == 4'b1000);
assign tcs = ope & (opa == 4'b1001);
wire stc = ope & (opa == 4'b1010);
assign daa = ope & (opa == 4'b1011);
assign kbp = ope & (opa == 4'b1100);
assign dcl = ope & (opa == 4'b1101);
// IO: OPA Decoding
assign iow = io & (opa[3] == 1'b0);
assign ior = io & (opa[3] == 1'b1);
wire adm = io & (opa == 4'b1011);
wire sbm = io & (opa == 4'b1000);
wire fin_fim = fin_fim_src_jin & ~opa[0];
wire src = fim_src & opa[0];
assign write_acc_1 = ~(kbp | tcs | daa | xch | poc | cma | tcc | dac | iac |
clb | ior | ld | sub | add | ldm_bbl);
assign write_carry_2 = ~(tcs | poc | tcc | stc | cmc | dac | iac |
clc | clb | sbm | adm | sub | add);
assign read_acc_3 = ~(daa | rar | ral | dac | iac | sbm | adm | sub | add);
assign add_group_4 = ~(tcs | tcc | adm | add);
assign inc_group_5 = ~(inc_isz | stc | iac);
assign sub_group_6 = ~(cmc | sbm | sub | m12);
// The Condition Flip-Flop
reg n0397;
wire n0486 = ~((opa[2] & acc_0) | (opa[1] & cy_1) | (opa[0] & n0432));
wire n0419 = ~((add_0 & ~isz) & (~jcn | ((~n0486 | opa[3]) & (n0486 | ~opa[3]))));
wire n0413 = ~((sc & n0419 & x32) | (~x32 | n0397));
reg n0405;
always @(posedge sysclk) begin
if (clk2)
n0405 <= n0413;
if (clk1)
n0397 <= ~n0405;
end
assign cn_n = ~n0397;
// The Single-Cycle Flip-Flop
reg n0343;
wire n0368 = ~((sc & (fin_fim | jcn_isz | jun_jms) & x32) | (n0343 & ~x32));
reg n0362;
always @(posedge sysclk) begin
if (clk2)
n0362 <= n0368;
if (clk1)
n0343 <= ~n0362;
end
assign sc = ~n0343;
assign dc = ~sc;
// Generate ~(X21&~CLK2)
reg n0360;
always @(posedge sysclk) begin
if (clk2)
n0360 <= ~x12;
end
wire n0337 = ~(n0360 | clk2);
assign x21_clk2 = ~n0337;
// Generate ~(X31&~CLK2)
reg n0380;
always @(posedge sysclk) begin
if (clk2)
n0380 <= ~x22;
end
wire n0375 = ~(n0380 | clk2);
assign x31_clk2 = ~n0375;
// Generate ~COM
wire n0329 = io;
reg n0414, n0797;
always @(posedge sysclk) begin
if (clk2)
n0414 <= a22;
else
n0797 <= n0414;
end
reg n0433, n0801;
always @(posedge sysclk) begin
if (clk2)
n0433 <= m12;
else
n0801 <= n0433;
end
reg n0425, n0805;
always @(posedge sysclk) begin
if (clk2)
n0425 <= x12;
else
n0805 <= n0425;
end
wire n0782 = ~((n0801 & n0329) | (src & n0805) | n0797);
assign com_n = n0782;
// Generate N0342
wire n0332 = ~(((n0329 | poc) & x22 & clk2) | (~(n0329 | poc) & n0337 & clk1));
assign n0342 = n0332;
// Output OPA onto the data bus
wire opa_ib = (ldm_bbl | jun_jms) & ~x21_clk2;
assign data = opa_ib ? opa : 4'bzzzz;
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module instruction_pointer (
input wire sysclk, // 50 MHz FPGA clock
// Inputs from the Timing and I/O board
input wire clk1,
input wire clk2,
input wire a12,
input wire a22,
input wire a32,
input wire m12,
input wire m22,
input wire x12,
input wire x22,
input wire x32,
input wire poc, // Power-On Clear (reset)
input wire m12_m22_clk1_m11_m12, // M12+M22+CLK1~(M11+M12)
// Common 4-bit data bus
inout wire [3:0] data,
// Inputs from the Instruction Decode board
input wire jcn_isz, // JCN+ISZ
input wire jin_fin, // JIN+FIN
input wire jun_jms, // JUN+JMS
input wire cn_n, // ~CN
input wire bbl, // BBL
input wire jms, // JMS
input wire sc, // SC (Single Cycle)
input wire dc // DC (Double Cycle, ~SC)
);
reg [11:0] dram_array [0:3];
reg [11:0] dram_temp;
wire [3:0] din_n;
wire inh = (jin_fin & sc) | ((jun_jms | (jcn_isz & ~cn_n)) & dc);
// Row Counter stuff
wire [1:0] addr_ptr; // Effective Address counter
wire addr_ptr_step; // CLK2(JMS&DC&M22+BBL(M22+X12+X22))
assign addr_ptr_step = ~(~clk2 | ~(((m22 | x12 | x22) & bbl) |
(m22 & dc & jms)));
counter addr_ptr_0 (
.sysclk(sysclk),
.step_a(clk1),
.step_b(addr_ptr_step),
.q(addr_ptr[0])
);
counter addr_ptr_1 (
.sysclk(sysclk),
.step_a( addr_ptr[0]),
.step_b(~addr_ptr[0]),
.q(addr_ptr[1])
);
// Refresh counter stuff
wire [1:0] addr_rfsh; // Row Refresh counter
wire addr_rfsh_step; // (~INH)&X32&CLK2
assign addr_rfsh_step = ~inh & x32 & clk2;
counter addr_rfsh_0 (
.sysclk(sysclk),
.step_a(clk1),
.step_b(addr_rfsh_step),
.q(addr_rfsh[0])
);
counter addr_rfsh_1 (
.sysclk(sysclk),
.step_a( addr_rfsh[0]),
.step_b(~addr_rfsh[0]),
.q(addr_rfsh[1])
);
// Row selection mux
reg [1:0] row; // {N0409, N0420}
always @(posedge sysclk) begin
if (x12)
row <= addr_rfsh;
if (x32)
row <= addr_ptr;
end
// Row Precharge/Read/Write stuff
wire precharge; // (~INH)(X11+X31)CLK1
wire row_read; // (~POC)CLK2(X12+X32)~INH
wire row_write; // ((~SC)(JIN+FIN))CLK1(M11+X21~INH)
reg n0517;
always @(posedge sysclk) begin
if (clk2)
n0517 <= ~(m22 | x22);
end
assign precharge = ~(n0517 | inh | ~clk1);
assign row_read = ~poc & clk2 & (x12 | x32) & ~inh;
reg n0438;
always @(posedge sysclk) begin
if (clk2)
n0438 <= ~((x12 & ~inh) | a32);
end
assign row_write = ~(n0438 | (jin_fin & ~sc) | ~clk1);
// Column Read selection stuff
reg n0416;
always @(posedge sysclk) begin
if (clk2)
n0416 <= ~x32;
end
wire radb0 = ~(n0416 | clk2);
reg n0384;
always @(posedge sysclk) begin
if (clk2)
n0384 <= ~a12;
end
wire radb1 = ~(n0384 | clk2);
reg n0374;
always @(posedge sysclk) begin
if (clk2)
n0374 <= ~a22;
end
wire radb2 = ~(n0374 | clk2);
// Column Write selection stuff
wire n0322 = ~(sc | cn_n);
wire wadb0 = ~(~clk2 | ~(a12 | (sc & jin_fin & x32) |
(((jcn_isz & n0322) | (jun_jms & ~sc)) & m22)));
wire wadb1 = ~(~clk2 | ~(a22 | (sc & jin_fin & x22) |
(((jcn_isz & n0322) | (jun_jms & ~sc)) & m12)));
wire wadb2 = ~(~clk2 | ~(a32 | (jun_jms & ~sc & x22)));
// Manage the row data buffer
always @(posedge sysclk) begin
if (precharge)
dram_temp <= 12'b0;
if (row_read)
dram_temp <= dram_array[row];
if (wadb0)
dram_temp[ 3:0] <= ~din_n;
if (wadb1)
dram_temp[ 7:4] <= ~din_n;
if (wadb2)
dram_temp[11:8] <= ~din_n;
end
// Handle row writes
always @(posedge sysclk) begin
if (row_write)
dram_array[row] <= dram_temp;
end
// Manage the data output mux
reg [3:0] dout;
always @* begin
(* PARALLEL_CASE *)
case (1'b1)
radb0: dout = dram_temp[ 3:0];
radb1: dout = dram_temp[ 7:4];
radb2: dout = dram_temp[11:8];
default: dout = 4'bzzzz;
endcase
end
assign data = dout;
// Data In mux and incrementer
reg [3:0] incr_in;
always @(posedge sysclk) begin
if (m12_m22_clk1_m11_m12)
incr_in <= data;
end
reg carry_out, carry_in;
wire [4:0] incr_out = (a12 | ((a22 | a32) & carry_in)) ?
(incr_in + 4'b0001) : {1'b0, incr_in};
always @(posedge sysclk) begin
if (clk2)
carry_out <= incr_out[4];
if (clk1)
carry_in <= carry_out;
end
assign din_n = ~incr_out[3:0];
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module scratchpad (
input wire sysclk, // 50 MHz FPGA clock
// Inputs from the Timing and I/O board
input wire clk1,
input wire clk2,
input wire a12,
input wire a22,
input wire a32,
input wire m12,
input wire m22,
input wire x12,
input wire x22,
input wire x32,
input wire poc, // Power-On Clear (reset)
input wire m12_m22_clk1_m11_m12, // M12+M22+CLK1~(M11+M12)
// Common 4-bit data bus
inout wire [3:0] data,
// Inputs from the Instruction Decode board
input wire sc_m22_clk2, // SC&M22&CLK2
input wire fin_fim_src_jin, // FIN+FIM+SRC+JIN
input wire inc_isz_add_sub_xch_ld, // INC+ISZ+ADD+SUB+XCH+LD
input wire inc_isz_xch, // INC+ISZ+XCH
input wire opa0_n, // ~OPA.0
input wire sc, // SC (Single Cycle)
input wire dc // DC (Double Cycle, ~SC)
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module timing_io(
input wire sysclk,
input wire clk1_pad,
input wire clk2_pad,
input wire poc_pad,
input wire ior,
// Timing and I/O Board Outputs
output wire clk1,
output wire clk2,
output wire a12,
output wire a22,
output wire a32,
output wire m12,
output wire m22,
output wire x12,
output wire x22,
output wire x32,
output wire gate,
output reg poc,
// External I/O Pad conditioning
inout wire [3:0] data,
inout wire [3:0] data_in_pad,
output wire [3:0] data_out_pad,
input wire test_pad,
output reg n0432,
output reg sync_pad,
input wire cmrom,
output wire cmrom_pad,
input wire cmram0,
output wire cmram0_pad,
input wire cmram1,
output wire cmram1_pad,
input wire cmram2,
output wire cmram2_pad,
input wire cmram3,
output wire cmram3_pad
);
// Simple pass-throughs
assign clk1 = clk1_pad;
assign clk2 = clk2_pad;
assign cmrom_pad = cmrom;
assign cmram0_pad = cmram0;
assign cmram1_pad = cmram1;
assign cmram2_pad = cmram2;
assign cmram3_pad = cmram3;
// Generate the 8 execution phase indicators
reg [0:7] master = 8'h00;
reg [0:7] slave = 8'h00;
always @(posedge sysclk) begin
if (clk2)
master <= {~|slave[0:6], slave[0:6]};
else
sync_pad <= master[7];
if (clk1)
slave <= master;
end
assign a12 = slave[0];
assign a22 = slave[1];
assign a32 = slave[2];
assign m12 = slave[3];
assign m22 = slave[4];
assign x12 = slave[5];
assign x22 = slave[6];
assign x32 = slave[7];
// Generate the DRAM Input Gate signal
// Properly called M12+M22+CLK1~(M11&M12)
wire n0279 = ~(a32 | m12);
reg n0278;
always @(posedge sysclk) begin
if (clk2)
n0278 <= n0279;
end
wire n0708 = ~((n0278 & clk1) | m12 | m22);
assign gate = ~n0708;
// Generate a clean POC signal
always @(posedge sysclk) begin
if (poc_pad) poc <= 1'b1;
else if (a12) poc <= 1'b0;
else poc <= poc;
end
// Generate a clean ~TEST signal (n0432)
always @(posedge sysclk) begin
n0432 <= ~test_pad;
end
// Manage the Data I/O pads
reg L;
always @(posedge sysclk) begin
if (clk2)
L <= a32 | m12 | (x12 & (ior | poc));
end
wire n0702 = ~clk2;
reg n0685;
reg n0699;
reg n0707;
always @(posedge sysclk) begin
if (clk1) begin
n0685 <= ~L;
n0707 <= L;
end
if (n0702)
n0699 <= ~L;
end
wire n0700 = n0707 | (L & n0702) | poc;
wire n0659 = (clk2 & n0685) | (clk1 & L);
wire n0676 = clk1 | n0685 | n0699;
// Incoming data from the external pads
reg [3:0] data_in;
always @* begin
if (n0659) data_in = 4'b1111;
else if (n0676) data_in = 4'bzzzz;
else if (poc) data_in = 4'b0000;
else data_in = data_in_pad;
end
assign data = data_in;
// Outgoing data to the external pads
reg [3:0] data_out;
always @(posedge sysclk) begin
if (n0702)
data_out <= data;
end
assign data_out_pad = poc ? 4'b0000 : (n0700 ? 4'bzzzz : data_out);
assign data_in_pad = poc ? 4'b0000 : (n0700 ? 4'bzzzz : data_out);
endmodule
|
module scratchpad (
input wire sysclk, // 50 MHz FPGA clock
// Inputs from the Timing and I/O board
input wire clk1,
input wire clk2,
input wire a12,
input wire a22,
input wire a32,
input wire m12,
input wire m22,
input wire x12,
input wire x22,
input wire x32,
input wire poc, // Power-On Clear (reset)
input wire m12_m22_clk1_m11_m12, // M12+M22+CLK1~(M11+M12)
// Common 4-bit data bus
inout wire [3:0] data,
// Inputs from the Instruction Decode board
input wire sc_m22_clk2, // SC&M22&CLK2
input wire fin_fim_src_jin, // FIN+FIM+SRC+JIN
input wire inc_isz_add_sub_xch_ld, // INC+ISZ+ADD+SUB+XCH+LD
input wire inc_isz_xch, // INC+ISZ+XCH
input wire opa0_n, // ~OPA.0
input wire sc, // SC (Single Cycle)
input wire dc // DC (Double Cycle, ~SC)
);
reg [7:0] dram_array [0:7];
reg [7:0] dram_temp;
reg [3:0] din_n;
// Refresh counter stuff
wire [2:0] reg_rfsh; // Row Refresh counter
wire reg_rfsh_step; // SC&A12&CLK2
assign reg_rfsh_step = sc & a12 & clk2;
counter reg_rfsh_0 (
.sysclk(sysclk),
.step_a(clk1),
.step_b(reg_rfsh_step),
.q(reg_rfsh[0])
);
counter reg_rfsh_1 (
.sysclk(sysclk),
.step_a( reg_rfsh[0]),
.step_b(~reg_rfsh[0]),
.q(reg_rfsh[1])
);
counter reg_rfsh_2 (
.sysclk(sysclk),
.step_a( reg_rfsh[1]),
.step_b(~reg_rfsh[1]),
.q(reg_rfsh[2])
);
// Row selection mux
reg [2:0] row; // {N0646, N0617, N0582}
always @(posedge sysclk) begin
if (sc & a22)
row <= reg_rfsh;
if (sc_m22_clk2)
row <= data[3:1];
end
// Row Precharge/Read/Write stuff
wire precharge; // SC(A22+M22)CLK2
wire row_read; // (~POC)&CLK2&SC(A32+X12)
wire row_write; // CLK2&SC(A12+M12)
assign precharge = sc & (a22 | m22) & clk2;
assign row_read = ~(poc | ~(clk2 & sc & (a32 | x12)));
assign row_write = sc & (a12 | m12) & clk2;
// Column Read selection stuff
reg n0615;
always @(posedge sysclk) begin
if (clk2)
n0615 <= ~(x12 & (fin_fim_src_jin |
(opa0_n & inc_isz_add_sub_xch_ld)));
end
wire rrab0 = ~(dc | n0615 | clk2);
reg n0592;
always @(posedge sysclk) begin
if (clk2)
n0592 <= ~((x22 & fin_fim_src_jin) |
(~opa0_n & x12 & inc_isz_add_sub_xch_ld));
end
wire rrab1 = ~(dc | n0592 | clk2);
// Column Write selection stuff
wire n0564 = opa0_n & fin_fim_src_jin & dc;
wire n0568 = inc_isz_xch & x32 & sc;
wire wrab0 = clk2 & ((m12 & n0564) | ( opa0_n & n0568));
wire wrab1 = clk2 & ((m22 & n0564) | (~opa0_n & n0568));
// Manage the row data buffer
always @(posedge sysclk) begin
if (precharge)
dram_temp <= 8'b0;
if (row_read)
dram_temp <= dram_array[row];
if (wrab0)
dram_temp[ 3:0] <= ~din_n;
if (wrab1)
dram_temp[ 7:4] <= ~din_n;
end
// Handle row writes
always @(posedge sysclk) begin
if (row_write)
dram_array[row] <= dram_temp;
end
// Manage the data output mux
reg [3:0] dout;
always @* begin
(* PARALLEL_CASE *)
case (1'b1)
rrab0: dout = dram_temp[ 3:0];
rrab1: dout = dram_temp[ 7:4];
default: dout = 4'bzzzz;
endcase
end
assign data = dout;
// Data In latch
always @(posedge sysclk) begin
if (m12_m22_clk1_m11_m12)
din_n <= ~data;
end
endmodule
|
tt06-finale_0086
|
tt06-finale
|
noritsuna-tt06-tt_um_i4004
|
task_timing_io
|
tt_um_noritsuna_i4004
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module tt_um_noritsuna_i4004 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena,
input wire clk,
input wire rst_n
);
wire sysclk;
wire clk1_pad;
wire clk2_pad;
wire poc_pad;
wire test_pad;
wire [3:0] data_in_pad;
wire [3:0] data_out_pad;
wire cmrom_pad;
wire cmram0_pad;
wire cmram1_pad;
wire cmram2_pad;
wire cmram3_pad;
wire sync_pad;
//input:
assign sysclk = clk;
assign data_in_pad = ui_in[3:0];
assign clk1_pad = ui_in[4];
assign clk2_pad = ui_in[5];
assign poc_pad = ui_in[6];
assign test_pad = ui_in[7];
//output:
assign cmrom_pad = uo_out[0];
assign cmram0_pad = uo_out[1];
assign cmram1_pad = uo_out[2];
assign cmram2_pad = uo_out[3];
assign cmram3_pad = uo_out[4];
assign sync_pad = uo_out[5];
assign uio_oe[3:0] = 1;
assign data_out_pad = uio_out[3:0];
// All output pins must be assigned. If not used, assign to 0.
assign uo_out[6] = 0;
assign uo_out[7] = 0;
assign uio_out[7:4] = 0;
assign uio_oe[7:4] = 0;
// Common BiDir data bus
wire [3:0] data;
// Timing and I/O Board Outputs
wire clk1;
wire clk2;
wire a12;
wire a22;
wire a32;
wire m12;
wire m22;
wire x12;
wire x22;
wire x32;
wire gate;
wire poc; // Clean POC_PAD
wire n0432; // Clean TEST_PAD
// Outputs from the Instruction Decode board
wire jcn_isz;
wire jin_fin;
wire jun_jms;
wire cn_n;
wire bbl;
wire jms;
wire sc;
wire dc;
wire sc_m22_clk2;
wire fin_fim_src_jin;
wire inc_isz_add_sub_xch_ld;
wire inc_isz_xch;
wire opa0_n;
wire cma;
wire write_acc_1;
wire write_carry_2;
wire read_acc_3;
wire add_group_4;
wire inc_group_5;
wire sub_group_6;
wire ior;
wire iow;
wire ral;
wire rar;
wire ope_n;
wire daa;
wire dcl;
wire inc_isz;
wire kbp;
wire o_ib;
wire tcs;
wire xch;
wire n0342;
wire x21_clk2;
wire x31_clk2;
wire com_n;
// Outputs from the ALU board
wire acc_0;
wire add_0;
wire cy_1;
wire cmram0;
wire cmram1;
wire cmram2;
wire cmram3;
wire cmrom;
// Instantiate the Timing and I/O board
timing_io tio_board (
.sysclk(sysclk),
.clk1_pad(clk1_pad),
.clk2_pad(clk2_pad),
.poc_pad(poc_pad),
.ior(ior),
.clk1(clk1),
.clk2(clk2),
.a12(a12),
.a22(a22),
.a32(a32),
.m12(m12),
.m22(m22),
.x12(x12),
.x22(x22),
.x32(x32),
.gate(gate),
.poc(poc),
.data(data),
.data_in_pad(data_in_pad),
.data_out_pad(data_out_pad),
.test_pad(test_pad),
.n0432(n0432),
.sync_pad(sync_pad),
.cmrom(cmrom),
.cmrom_pad(cmrom_pad),
.cmram0(cmram0),
.cmram0_pad(cmram0_pad),
.cmram1(cmram1),
.cmram1_pad(cmram1_pad),
.cmram2(cmram2),
.cmram2_pad(cmram2_pad),
.cmram3(cmram3),
.cmram3_pad(cmram3_pad)
);
// Instantiate the Instruction Decode board
instruction_decode id_board (
.sysclk(clk),
.clk1(clk1),
.clk2(clk2),
.a22(a22),
.m12(m12),
.m22(m22),
.x12(x12),
.x22(x22),
.x32(x32),
.poc(poc),
.n0432(n0432),
.data(data),
.jcn_isz(jcn_isz),
.jin_fin(jin_fin),
.jun_jms(jun_jms),
.cn_n(cn_n),
.bbl(bbl),
.jms(jms),
.sc(sc),
.dc(dc),
.sc_m22_clk2(sc_m22_clk2),
.fin_fim_src_jin(fin_fim_src_jin),
.inc_isz_add_sub_xch_ld(inc_isz_add_sub_xch_ld),
.inc_isz_xch(inc_isz_xch),
.opa0_n(opa0_n),
.acc_0(acc_0),
.add_0(add_0),
.cy_1(cy_1),
.cma(cma),
.write_acc_1(write_acc_1),
.write_carry_2(write_carry_2),
.read_acc_3(read_acc_3),
.add_group_4(add_group_4),
.inc_group_5(inc_group_5),
.sub_group_6(sub_group_6),
.ior(ior),
.iow(iow),
.ral(ral),
.rar(rar),
.ope_n(ope_n),
.daa(daa),
.dcl(dcl),
.inc_isz(inc_isz),
.kbp(kbp),
.o_ib(o_ib),
.tcs(tcs),
.xch(xch),
.n0342(n0342),
.x21_clk2(x21_clk2),
.x31_clk2(x31_clk2),
.com_n(com_n)
);
// Instantiate the ALU board
alu alu_board (
.sysclk(clk),
.a12(a12),
.m12(m12),
.x12(x12),
.poc(poc),
.data(data),
.acc_0(acc_0),
.add_0(add_0),
.cy_1(cy_1),
.cma(cma),
.write_acc_1(write_acc_1),
.write_carry_2(write_carry_2),
.read_acc_3(read_acc_3),
.add_group_4(add_group_4),
.inc_group_5(inc_group_5),
.sub_group_6(sub_group_6),
.ior(ior),
.iow(iow),
.ral(ral),
.rar(rar),
.ope_n(ope_n),
.daa(daa),
.dcl(dcl),
.inc_isz(inc_isz),
.kbp(kbp),
.o_ib(o_ib),
.tcs(tcs),
.xch(xch),
.n0342(n0342),
.x21_clk2(x21_clk2),
.x31_clk2(x31_clk2),
.com_n(com_n),
.cmram0(cmram0),
.cmram1(cmram1),
.cmram2(cmram2),
.cmram3(cmram3),
.cmrom(cmrom)
);
// Instantiate the Instruction Pointer board
instruction_pointer ip_board (
.sysclk(clk),
.clk1(clk1),
.clk2(clk2),
.a12(a12),
.a22(a22),
.a32(a32),
.m12(m12),
.m22(m22),
.x12(x12),
.x22(x22),
.x32(x32),
.poc(poc),
.m12_m22_clk1_m11_m12(gate),
.data(data),
.jcn_isz(jcn_isz),
.jin_fin(jin_fin),
.jun_jms(jun_jms),
.cn_n(cn_n),
.bbl(bbl),
.jms(jms),
.sc(sc),
.dc(dc)
);
// Instantiate the Scratchpad board
scratchpad sp_board (
.sysclk(clk),
.clk1(clk1),
.clk2(clk2),
.a12(a12),
.a22(a22),
.a32(a32),
.m12(m12),
.m22(m22),
.x12(x12),
.x22(x22),
.x32(x32),
.poc(poc),
.m12_m22_clk1_m11_m12(gate),
.data(data),
.sc_m22_clk2(sc_m22_clk2),
.fin_fim_src_jin(fin_fim_src_jin),
.inc_isz_add_sub_xch_ld(inc_isz_add_sub_xch_ld),
.inc_isz_xch(inc_isz_xch),
.opa0_n(opa0_n),
.sc(sc),
.dc(dc)
);
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module alu(
input wire sysclk,
// Inputs from the Timing and I/O board
input wire a12,
input wire m12,
input wire x12,
input wire poc,
// Common 4-bit data bus
inout wire [3:0] data,
// Outputs to the Instruction Decode board
output wire acc_0,
output wire add_0,
output reg cy_1,
// Inputs from the Instruction Decode board
input wire cma,
input wire write_acc_1,
input wire write_carry_2,
input wire read_acc_3,
input wire add_group_4,
input wire inc_group_5,
input wire sub_group_6,
input wire ior,
input wire iow,
input wire ral,
input wire rar,
input wire ope_n,
input wire daa,
input wire dcl,
input wire inc_isz,
input wire kbp,
input wire o_ib,
input wire tcs,
input wire xch,
input wire n0342,
input wire x21_clk2,
input wire x31_clk2,
input wire com_n,
// Outputs to external pins
output wire cmram0,
output wire cmram1,
output wire cmram2,
output wire cmram3,
output wire cmrom
);
reg [3:0] acc;
reg cy;
// Decode logic
wire n0854 = ~(~x12);
wire n0351 = ~(x21_clk2 | ~dcl);
wire n0415 = ~(x21_clk2 | ope_n);
wire add_ib = ~(x31_clk2 | ~inc_isz);
wire cy_ib = ~(x31_clk2 | ~iow);
wire acb_ib = ~((x31_clk2 | ~xch) & (x21_clk2 | ~iow));
wire n0477 = ~((~x31_clk2 & ~ior) | (a12 & ior));
wire adc_cy = ~(write_carry_2 | n0477);
wire add_acc = ~(write_acc_1 | n0477);
wire adsr = ~(x31_clk2 | ~rar);
wire adsl = ~(x31_clk2 | ~ral);
wire acc_adac = ~(~cma | n0342);
wire acc_ada = ~(read_acc_3 | n0342);
wire cy_ada = ~(add_group_4 | n0342);
wire cy_adac = ~(sub_group_6 | n0342);
// Latch the incoming data bus
reg [3:0] tmp; // It's the name used in simulator!
always @(posedge sysclk) begin
if (~n0342)
tmp <= data;
if (m12)
tmp <= 4'b1111;
end
// Invert some of the incoming data
reg n0893, n0891, n0889, n0887; // D3, D2, D1, D0
always @(posedge sysclk) begin
if (sub_group_6) begin
n0887 <= tmp[0];
n0889 <= ~tmp[1];
n0891 <= tmp[2];
n0893 <= ~tmp[3];
end
if (~(sub_group_6 | m12)) begin
n0887 <= ~tmp[0];
n0889 <= tmp[1];
n0891 <= ~tmp[2];
n0893 <= tmp[3];
end
end
// Feedback from Accumulator
reg n0873, n0872, n0871, n0870;
always @(posedge sysclk) begin
if (m12)
{n0873, n0872, n0871, n0870} <= 4'b1010;
if (acc_ada)
{n0873, n0872, n0871, n0870} <= acc;
if (acc_adac)
{n0873, n0872, n0871, n0870} <= ~acc;
end
// Carry generator
wire n0546 = ~(inc_group_5 | n0342);
reg n0550;
always @(posedge sysclk) begin
if (m12) n0550 <= 1'b0;
if (n0546) n0550 <= 1'b1;
if (cy_adac) n0550 <= ~cy;
if (cy_ada) n0550 <= cy;
end
wire n0911 = ~(n0550 ? (n0887 | n0870) : (n0887 & n0870));
wire n0553 = n0911;
wire n0912 = ~(n0553 ? (n0889 | n0871) : (n0889 & n0871));
wire n0556 = n0912;
wire n0913 = ~(n0556 ? (n0891 | n0872) : (n0891 & n0872));
wire n0559 = n0913;
wire n0914 = ~(n0559 ? (n0893 | n0873) : (n0893 & n0873));
wire n0861 = n0914;
// Adder
wire n0877 = ~((n0893 & n0559 & n0873) | (n0861 & (n0893 | n0873 | n0559)));
wire n0878 = ~((n0877 & n0550 & n0870) | (n0553 & (n0887 | n0870 | n0550)));
wire n0875 = ~((n0889 & n0553 & n0871) | (n0556 & (n0889 | n0871 | n0553)));
wire n0879 = ~((n0891 & n0556 & n0872) | (n0559 & (n0891 | n0872 | n0556)));
wire n0846 = ~n0878;
wire n0847 = n0875;
wire n0848 = ~n0879;
wire n0514 = n0877;
// Shifter / Accumulator and Carry
reg [3:0] acc_out; // {n0356, n0348, n0347, n0346}
wire n0803 = ~((acc_out[3] & (acc_out[2] | acc_out[1])) | cy_1);
wire n0403 = ~(~daa | n0803);
wire [3:0] acc_in = {n0514, n0848, n0847, n0846};
always @(posedge sysclk) begin
if (adsr)
{acc, cy} <= {cy_1, acc_in};
if (add_acc)
acc <= acc_in;
if (adsl)
{cy, acc} <= {acc_in, cy_1};
if (adc_cy)
cy <= n0861;
if (n0403 & n0415)
cy <= 1'b1;
// Dynamic refresh would occur during M12
end
// Accumulator output latch
always @(posedge sysclk) begin
if (n0854) begin
cy_1 <= cy;
acc_out <= acc;
end
end
assign acc_0 = ~|acc_out;
assign add_0 = ~|acc_in;
// Keyboard Process logic
wire n0378 = ~((daa & n0803) | o_ib);
wire n0345 = kbp & (acc_out == 4'b1000);
wire n0354 = kbp & (acc_out == 4'b0100);
wire n0363 = kbp & (acc_out == 4'b0010);
wire n0370 = kbp & (acc_out == 4'b0001);
wire n0377 = (kbp & (acc_out == 4'b0000)) | ~n0378;
wire n0358 = ~(n0345 | n0354 | n0363 | n0370 | n0377 | n0403);
wire n0366 = ~( n0354 | n0363 | n0370 | n0377 | tcs );
wire n0359 = ~(n0345 | n0370 | n0377 | tcs );
wire n0357 = ~(n0345 | n0363 | n0377 | n0403);
// Data output mux
reg [3:0] dout;
always @(*) begin
dout = 4'bzzzz;
if (acb_ib)
dout = acc_out;
if (add_ib)
dout = acc_in;
if (cy_ib)
dout = {3'bxxx, cy_1};
if (n0415)
dout = {n0358, n0366, n0359, n0357};
end
assign data = dout;
// Generate CMROM / CMRAMn
// This may get moved to the Timing & I/O board
// Inputs: {n0355, n0364, n0371}, n0351, poc, com_n
wire n0355 = ~acc_out[2];
wire n0364 = ~acc_out[1];
wire n0371 = ~acc_out[0];
reg n0749, n0750, n0751;
always @(posedge sysclk) begin
if (poc) begin
n0749 <= 1'b1;
n0750 <= 1'b1;
n0751 <= 1'b1;
end
else begin
if (n0351) begin
n0749 <= n0355;
n0750 <= n0364;
n0751 <= n0371;
end
end
end
assign cmram3 = ~(com_n | n0749);
assign cmram2 = ~(com_n | n0750);
assign cmram1 = ~(com_n | n0751);
assign cmram0 = ~(com_n | ~n0749 | ~n0750 | ~n0751);
assign cmrom = ~(com_n | poc);
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module counter(
input wire sysclk,
input wire step_a,
input wire step_b,
output reg q = 1'b0
);
reg q_n = 1'b1;
always @(posedge sysclk) begin
if (step_a) q <= ~q_n;
if (step_b) q_n <= q;
end
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module instruction_decode(
input wire sysclk, // 50 MHz FPGA clock
// Inputs from the Timing and I/O board
input wire clk1,
input wire clk2,
input wire a22,
input wire m12,
input wire m22,
input wire x12,
input wire x22,
input wire x32,
input wire poc, // Power-On Clear (reset)
input wire n0432, // Conditioned TEST_PAD
// Common 4-bit data bus
inout wire [3:0] data,
// These drive the Instruction Pointer (IP) board
output wire jcn_isz, // JCN+ISZ
output wire jin_fin, // JIN+FIN
output wire jun_jms, // JUN+JMS
output wire cn_n, // ~CN
output wire bbl, // BBL
output wire jms, // JMS
// Outputs to both the IP and SP boards
output wire sc, // SC (Single Cycle)
output wire dc, // DC (Double Cycle, ~SC)
// Outputs to the Scratch Pad (SP) board
output wire sc_m22_clk2, // SC&M22&CLK2
output wire fin_fim_src_jin, // FIN+FIM+SRC+JIN
output wire inc_isz_add_sub_xch_ld, // INC+ISZ+ADD+SUB+XCH+LD
output wire inc_isz_xch, // INC+ISZ+XCH
output wire opa0_n, // ~OPA.0
// Inputs from the ALU board (condition bits)
input wire acc_0, // ACC_0
input wire add_0, // ADD_0
input wire cy_1, // CY_1
// Outputs to the Arithmetic Logic Unit (ALU) board
output wire cma,
output wire write_acc_1,
output wire write_carry_2,
output wire read_acc_3,
output wire add_group_4,
output wire inc_group_5,
output wire sub_group_6,
output wire ior,
output wire iow,
output wire ral,
output wire rar,
output wire ope_n,
output wire daa,
output wire dcl,
output wire inc_isz,
output wire kbp,
output wire o_ib,
output wire tcs,
output wire xch,
output wire n0342,
output wire x21_clk2,
output wire x31_clk2,
output wire com_n
);
wire sc_m12_clk2 = sc & m12 & clk2;
assign sc_m22_clk2 = sc & m22 & clk2;
// Latch the first 4 bits of the opcode
reg [3:0] opr = 4'b0000;
always @(posedge sysclk) begin
if (sc_m12_clk2)
opr <= data;
end
// Latch the second 4 bits of the opcode
reg [3:0] opa = 4'b0000;
always @(posedge sysclk) begin
if (sc_m22_clk2)
opa <= data;
end
assign opa0_n = ~opa[0];
// Full OPR Decoding
wire nop = (opr == 4'b0000);
wire jcn = (opr == 4'b0001);
wire fim_src = (opr == 4'b0010);
assign jin_fin = (opr == 4'b0011);
wire jun = (opr == 4'b0100);
assign jms = (opr == 4'b0101);
wire inc = (opr == 4'b0110);
wire isz = (opr == 4'b0111);
wire add = (opr == 4'b1000);
wire sub = (opr == 4'b1001);
wire ld = (opr == 4'b1010);
assign xch = (opr == 4'b1011);
assign bbl = (opr == 4'b1100);
wire ldm = (opr == 4'b1101);
wire io = (opr == 4'b1110);
wire ope = (opr == 4'b1111);
assign ope_n = ~ope;
assign jcn_isz = jcn | isz;
assign jun_jms = jun | jms;
wire ldm_bbl = ldm | bbl;
assign inc_isz = (inc | isz) & sc;
assign inc_isz_xch = inc | isz | xch;
assign inc_isz_add_sub_xch_ld = inc | isz | add | sub | xch | ld;
assign fin_fim_src_jin = fim_src | jin_fin;
// OPE: OPA Decoding
assign o_ib = ope & (opa[3] == 1'b0);
wire clb = ope & (opa == 4'b0000);
wire clc = ope & (opa == 4'b0001);
wire iac = ope & (opa == 4'b0010);
wire cmc = ope & (opa == 4'b0011);
assign cma = ope & (opa == 4'b0100);
assign ral = ope & (opa == 4'b0101);
assign rar = ope & (opa == 4'b0110);
wire tcc = ope & (opa == 4'b0111);
wire dac = ope & (opa == 4'b1000);
assign tcs = ope & (opa == 4'b1001);
wire stc = ope & (opa == 4'b1010);
assign daa = ope & (opa == 4'b1011);
assign kbp = ope & (opa == 4'b1100);
assign dcl = ope & (opa == 4'b1101);
// IO: OPA Decoding
assign iow = io & (opa[3] == 1'b0);
assign ior = io & (opa[3] == 1'b1);
wire adm = io & (opa == 4'b1011);
wire sbm = io & (opa == 4'b1000);
wire fin_fim = fin_fim_src_jin & ~opa[0];
wire src = fim_src & opa[0];
assign write_acc_1 = ~(kbp | tcs | daa | xch | poc | cma | tcc | dac | iac |
clb | ior | ld | sub | add | ldm_bbl);
assign write_carry_2 = ~(tcs | poc | tcc | stc | cmc | dac | iac |
clc | clb | sbm | adm | sub | add);
assign read_acc_3 = ~(daa | rar | ral | dac | iac | sbm | adm | sub | add);
assign add_group_4 = ~(tcs | tcc | adm | add);
assign inc_group_5 = ~(inc_isz | stc | iac);
assign sub_group_6 = ~(cmc | sbm | sub | m12);
// The Condition Flip-Flop
reg n0397;
wire n0486 = ~((opa[2] & acc_0) | (opa[1] & cy_1) | (opa[0] & n0432));
wire n0419 = ~((add_0 & ~isz) & (~jcn | ((~n0486 | opa[3]) & (n0486 | ~opa[3]))));
wire n0413 = ~((sc & n0419 & x32) | (~x32 | n0397));
reg n0405;
always @(posedge sysclk) begin
if (clk2)
n0405 <= n0413;
if (clk1)
n0397 <= ~n0405;
end
assign cn_n = ~n0397;
// The Single-Cycle Flip-Flop
reg n0343;
wire n0368 = ~((sc & (fin_fim | jcn_isz | jun_jms) & x32) | (n0343 & ~x32));
reg n0362;
always @(posedge sysclk) begin
if (clk2)
n0362 <= n0368;
if (clk1)
n0343 <= ~n0362;
end
assign sc = ~n0343;
assign dc = ~sc;
// Generate ~(X21&~CLK2)
reg n0360;
always @(posedge sysclk) begin
if (clk2)
n0360 <= ~x12;
end
wire n0337 = ~(n0360 | clk2);
assign x21_clk2 = ~n0337;
// Generate ~(X31&~CLK2)
reg n0380;
always @(posedge sysclk) begin
if (clk2)
n0380 <= ~x22;
end
wire n0375 = ~(n0380 | clk2);
assign x31_clk2 = ~n0375;
// Generate ~COM
wire n0329 = io;
reg n0414, n0797;
always @(posedge sysclk) begin
if (clk2)
n0414 <= a22;
else
n0797 <= n0414;
end
reg n0433, n0801;
always @(posedge sysclk) begin
if (clk2)
n0433 <= m12;
else
n0801 <= n0433;
end
reg n0425, n0805;
always @(posedge sysclk) begin
if (clk2)
n0425 <= x12;
else
n0805 <= n0425;
end
wire n0782 = ~((n0801 & n0329) | (src & n0805) | n0797);
assign com_n = n0782;
// Generate N0342
wire n0332 = ~(((n0329 | poc) & x22 & clk2) | (~(n0329 | poc) & n0337 & clk1));
assign n0342 = n0332;
// Output OPA onto the data bus
wire opa_ib = (ldm_bbl | jun_jms) & ~x21_clk2;
assign data = opa_ib ? opa : 4'bzzzz;
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module instruction_pointer (
input wire sysclk, // 50 MHz FPGA clock
// Inputs from the Timing and I/O board
input wire clk1,
input wire clk2,
input wire a12,
input wire a22,
input wire a32,
input wire m12,
input wire m22,
input wire x12,
input wire x22,
input wire x32,
input wire poc, // Power-On Clear (reset)
input wire m12_m22_clk1_m11_m12, // M12+M22+CLK1~(M11+M12)
// Common 4-bit data bus
inout wire [3:0] data,
// Inputs from the Instruction Decode board
input wire jcn_isz, // JCN+ISZ
input wire jin_fin, // JIN+FIN
input wire jun_jms, // JUN+JMS
input wire cn_n, // ~CN
input wire bbl, // BBL
input wire jms, // JMS
input wire sc, // SC (Single Cycle)
input wire dc // DC (Double Cycle, ~SC)
);
reg [11:0] dram_array [0:3];
reg [11:0] dram_temp;
wire [3:0] din_n;
wire inh = (jin_fin & sc) | ((jun_jms | (jcn_isz & ~cn_n)) & dc);
// Row Counter stuff
wire [1:0] addr_ptr; // Effective Address counter
wire addr_ptr_step; // CLK2(JMS&DC&M22+BBL(M22+X12+X22))
assign addr_ptr_step = ~(~clk2 | ~(((m22 | x12 | x22) & bbl) |
(m22 & dc & jms)));
counter addr_ptr_0 (
.sysclk(sysclk),
.step_a(clk1),
.step_b(addr_ptr_step),
.q(addr_ptr[0])
);
counter addr_ptr_1 (
.sysclk(sysclk),
.step_a( addr_ptr[0]),
.step_b(~addr_ptr[0]),
.q(addr_ptr[1])
);
// Refresh counter stuff
wire [1:0] addr_rfsh; // Row Refresh counter
wire addr_rfsh_step; // (~INH)&X32&CLK2
assign addr_rfsh_step = ~inh & x32 & clk2;
counter addr_rfsh_0 (
.sysclk(sysclk),
.step_a(clk1),
.step_b(addr_rfsh_step),
.q(addr_rfsh[0])
);
counter addr_rfsh_1 (
.sysclk(sysclk),
.step_a( addr_rfsh[0]),
.step_b(~addr_rfsh[0]),
.q(addr_rfsh[1])
);
// Row selection mux
reg [1:0] row; // {N0409, N0420}
always @(posedge sysclk) begin
if (x12)
row <= addr_rfsh;
if (x32)
row <= addr_ptr;
end
// Row Precharge/Read/Write stuff
wire precharge; // (~INH)(X11+X31)CLK1
wire row_read; // (~POC)CLK2(X12+X32)~INH
wire row_write; // ((~SC)(JIN+FIN))CLK1(M11+X21~INH)
reg n0517;
always @(posedge sysclk) begin
if (clk2)
n0517 <= ~(m22 | x22);
end
assign precharge = ~(n0517 | inh | ~clk1);
assign row_read = ~poc & clk2 & (x12 | x32) & ~inh;
reg n0438;
always @(posedge sysclk) begin
if (clk2)
n0438 <= ~((x12 & ~inh) | a32);
end
assign row_write = ~(n0438 | (jin_fin & ~sc) | ~clk1);
// Column Read selection stuff
reg n0416;
always @(posedge sysclk) begin
if (clk2)
n0416 <= ~x32;
end
wire radb0 = ~(n0416 | clk2);
reg n0384;
always @(posedge sysclk) begin
if (clk2)
n0384 <= ~a12;
end
wire radb1 = ~(n0384 | clk2);
reg n0374;
always @(posedge sysclk) begin
if (clk2)
n0374 <= ~a22;
end
wire radb2 = ~(n0374 | clk2);
// Column Write selection stuff
wire n0322 = ~(sc | cn_n);
wire wadb0 = ~(~clk2 | ~(a12 | (sc & jin_fin & x32) |
(((jcn_isz & n0322) | (jun_jms & ~sc)) & m22)));
wire wadb1 = ~(~clk2 | ~(a22 | (sc & jin_fin & x22) |
(((jcn_isz & n0322) | (jun_jms & ~sc)) & m12)));
wire wadb2 = ~(~clk2 | ~(a32 | (jun_jms & ~sc & x22)));
// Manage the row data buffer
always @(posedge sysclk) begin
if (precharge)
dram_temp <= 12'b0;
if (row_read)
dram_temp <= dram_array[row];
if (wadb0)
dram_temp[ 3:0] <= ~din_n;
if (wadb1)
dram_temp[ 7:4] <= ~din_n;
if (wadb2)
dram_temp[11:8] <= ~din_n;
end
// Handle row writes
always @(posedge sysclk) begin
if (row_write)
dram_array[row] <= dram_temp;
end
// Manage the data output mux
reg [3:0] dout;
always @* begin
(* PARALLEL_CASE *)
case (1'b1)
radb0: dout = dram_temp[ 3:0];
radb1: dout = dram_temp[ 7:4];
radb2: dout = dram_temp[11:8];
default: dout = 4'bzzzz;
endcase
end
assign data = dout;
// Data In mux and incrementer
reg [3:0] incr_in;
always @(posedge sysclk) begin
if (m12_m22_clk1_m11_m12)
incr_in <= data;
end
reg carry_out, carry_in;
wire [4:0] incr_out = (a12 | ((a22 | a32) & carry_in)) ?
(incr_in + 4'b0001) : {1'b0, incr_in};
always @(posedge sysclk) begin
if (clk2)
carry_out <= incr_out[4];
if (clk1)
carry_in <= carry_out;
end
assign din_n = ~incr_out[3:0];
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module scratchpad (
input wire sysclk, // 50 MHz FPGA clock
// Inputs from the Timing and I/O board
input wire clk1,
input wire clk2,
input wire a12,
input wire a22,
input wire a32,
input wire m12,
input wire m22,
input wire x12,
input wire x22,
input wire x32,
input wire poc, // Power-On Clear (reset)
input wire m12_m22_clk1_m11_m12, // M12+M22+CLK1~(M11+M12)
// Common 4-bit data bus
inout wire [3:0] data,
// Inputs from the Instruction Decode board
input wire sc_m22_clk2, // SC&M22&CLK2
input wire fin_fim_src_jin, // FIN+FIM+SRC+JIN
input wire inc_isz_add_sub_xch_ld, // INC+ISZ+ADD+SUB+XCH+LD
input wire inc_isz_xch, // INC+ISZ+XCH
input wire opa0_n, // ~OPA.0
input wire sc, // SC (Single Cycle)
input wire dc // DC (Double Cycle, ~SC)
);
reg [7:0] dram_array [0:7];
reg [7:0] dram_temp;
reg [3:0] din_n;
// Refresh counter stuff
wire [2:0] reg_rfsh; // Row Refresh counter
wire reg_rfsh_step; // SC&A12&CLK2
assign reg_rfsh_step = sc & a12 & clk2;
counter reg_rfsh_0 (
.sysclk(sysclk),
.step_a(clk1),
.step_b(reg_rfsh_step),
.q(reg_rfsh[0])
);
counter reg_rfsh_1 (
.sysclk(sysclk),
.step_a( reg_rfsh[0]),
.step_b(~reg_rfsh[0]),
.q(reg_rfsh[1])
);
counter reg_rfsh_2 (
.sysclk(sysclk),
.step_a( reg_rfsh[1]),
.step_b(~reg_rfsh[1]),
.q(reg_rfsh[2])
);
// Row selection mux
reg [2:0] row; // {N0646, N0617, N0582}
always @(posedge sysclk) begin
if (sc & a22)
row <= reg_rfsh;
if (sc_m22_clk2)
row <= data[3:1];
end
// Row Precharge/Read/Write stuff
wire precharge; // SC(A22+M22)CLK2
wire row_read; // (~POC)&CLK2&SC(A32+X12)
wire row_write; // CLK2&SC(A12+M12)
assign precharge = sc & (a22 | m22) & clk2;
assign row_read = ~(poc | ~(clk2 & sc & (a32 | x12)));
assign row_write = sc & (a12 | m12) & clk2;
// Column Read selection stuff
reg n0615;
always @(posedge sysclk) begin
if (clk2)
n0615 <= ~(x12 & (fin_fim_src_jin |
(opa0_n & inc_isz_add_sub_xch_ld)));
end
wire rrab0 = ~(dc | n0615 | clk2);
reg n0592;
always @(posedge sysclk) begin
if (clk2)
n0592 <= ~((x22 & fin_fim_src_jin) |
(~opa0_n & x12 & inc_isz_add_sub_xch_ld));
end
wire rrab1 = ~(dc | n0592 | clk2);
// Column Write selection stuff
wire n0564 = opa0_n & fin_fim_src_jin & dc;
wire n0568 = inc_isz_xch & x32 & sc;
wire wrab0 = clk2 & ((m12 & n0564) | ( opa0_n & n0568));
wire wrab1 = clk2 & ((m22 & n0564) | (~opa0_n & n0568));
// Manage the row data buffer
always @(posedge sysclk) begin
if (precharge)
dram_temp <= 8'b0;
if (row_read)
dram_temp <= dram_array[row];
if (wrab0)
dram_temp[ 3:0] <= ~din_n;
if (wrab1)
dram_temp[ 7:4] <= ~din_n;
end
// Handle row writes
always @(posedge sysclk) begin
if (row_write)
dram_array[row] <= dram_temp;
end
// Manage the data output mux
reg [3:0] dout;
always @* begin
(* PARALLEL_CASE *)
case (1'b1)
rrab0: dout = dram_temp[ 3:0];
rrab1: dout = dram_temp[ 7:4];
default: dout = 4'bzzzz;
endcase
end
assign data = dout;
// Data In latch
always @(posedge sysclk) begin
if (m12_m22_clk1_m11_m12)
din_n <= ~data;
end
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module timing_io(
input wire sysclk,
input wire clk1_pad,
input wire clk2_pad,
input wire poc_pad,
input wire ior,
// Timing and I/O Board Outputs
output wire clk1,
output wire clk2,
output wire a12,
output wire a22,
output wire a32,
output wire m12,
output wire m22,
output wire x12,
output wire x22,
output wire x32,
output wire gate,
output reg poc,
// External I/O Pad conditioning
inout wire [3:0] data,
inout wire [3:0] data_in_pad,
output wire [3:0] data_out_pad,
input wire test_pad,
output reg n0432,
output reg sync_pad,
input wire cmrom,
output wire cmrom_pad,
input wire cmram0,
output wire cmram0_pad,
input wire cmram1,
output wire cmram1_pad,
input wire cmram2,
output wire cmram2_pad,
input wire cmram3,
output wire cmram3_pad
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
|
module timing_io(
input wire sysclk,
input wire clk1_pad,
input wire clk2_pad,
input wire poc_pad,
input wire ior,
// Timing and I/O Board Outputs
output wire clk1,
output wire clk2,
output wire a12,
output wire a22,
output wire a32,
output wire m12,
output wire m22,
output wire x12,
output wire x22,
output wire x32,
output wire gate,
output reg poc,
// External I/O Pad conditioning
inout wire [3:0] data,
inout wire [3:0] data_in_pad,
output wire [3:0] data_out_pad,
input wire test_pad,
output reg n0432,
output reg sync_pad,
input wire cmrom,
output wire cmrom_pad,
input wire cmram0,
output wire cmram0_pad,
input wire cmram1,
output wire cmram1_pad,
input wire cmram2,
output wire cmram2_pad,
input wire cmram3,
output wire cmram3_pad
);
// Simple pass-throughs
assign clk1 = clk1_pad;
assign clk2 = clk2_pad;
assign cmrom_pad = cmrom;
assign cmram0_pad = cmram0;
assign cmram1_pad = cmram1;
assign cmram2_pad = cmram2;
assign cmram3_pad = cmram3;
// Generate the 8 execution phase indicators
reg [0:7] master = 8'h00;
reg [0:7] slave = 8'h00;
always @(posedge sysclk) begin
if (clk2)
master <= {~|slave[0:6], slave[0:6]};
else
sync_pad <= master[7];
if (clk1)
slave <= master;
end
assign a12 = slave[0];
assign a22 = slave[1];
assign a32 = slave[2];
assign m12 = slave[3];
assign m22 = slave[4];
assign x12 = slave[5];
assign x22 = slave[6];
assign x32 = slave[7];
// Generate the DRAM Input Gate signal
// Properly called M12+M22+CLK1~(M11&M12)
wire n0279 = ~(a32 | m12);
reg n0278;
always @(posedge sysclk) begin
if (clk2)
n0278 <= n0279;
end
wire n0708 = ~((n0278 & clk1) | m12 | m22);
assign gate = ~n0708;
// Generate a clean POC signal
always @(posedge sysclk) begin
if (poc_pad) poc <= 1'b1;
else if (a12) poc <= 1'b0;
else poc <= poc;
end
// Generate a clean ~TEST signal (n0432)
always @(posedge sysclk) begin
n0432 <= ~test_pad;
end
// Manage the Data I/O pads
reg L;
always @(posedge sysclk) begin
if (clk2)
L <= a32 | m12 | (x12 & (ior | poc));
end
wire n0702 = ~clk2;
reg n0685;
reg n0699;
reg n0707;
always @(posedge sysclk) begin
if (clk1) begin
n0685 <= ~L;
n0707 <= L;
end
if (n0702)
n0699 <= ~L;
end
wire n0700 = n0707 | (L & n0702) | poc;
wire n0659 = (clk2 & n0685) | (clk1 & L);
wire n0676 = clk1 | n0685 | n0699;
// Incoming data from the external pads
reg [3:0] data_in;
always @* begin
if (n0659) data_in = 4'b1111;
else if (n0676) data_in = 4'bzzzz;
else if (poc) data_in = 4'b0000;
else data_in = data_in_pad;
end
assign data = data_in;
// Outgoing data to the external pads
reg [3:0] data_out;
always @(posedge sysclk) begin
if (n0702)
data_out <= data;
end
assign data_out_pad = poc ? 4'b0000 : (n0700 ? 4'bzzzz : data_out);
assign data_in_pad = poc ? 4'b0000 : (n0700 ? 4'bzzzz : data_out);
endmodule
|
tt06-finale_0087
|
tt06-finale
|
noritsuna-tt06-tt_um_i4004
|
task_tt_um_noritsuna_i4004
|
tt_um_noritsuna_i4004
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module tt_um_noritsuna_i4004 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena,
input wire clk,
input wire rst_n
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module alu(
input wire sysclk,
// Inputs from the Timing and I/O board
input wire a12,
input wire m12,
input wire x12,
input wire poc,
// Common 4-bit data bus
inout wire [3:0] data,
// Outputs to the Instruction Decode board
output wire acc_0,
output wire add_0,
output reg cy_1,
// Inputs from the Instruction Decode board
input wire cma,
input wire write_acc_1,
input wire write_carry_2,
input wire read_acc_3,
input wire add_group_4,
input wire inc_group_5,
input wire sub_group_6,
input wire ior,
input wire iow,
input wire ral,
input wire rar,
input wire ope_n,
input wire daa,
input wire dcl,
input wire inc_isz,
input wire kbp,
input wire o_ib,
input wire tcs,
input wire xch,
input wire n0342,
input wire x21_clk2,
input wire x31_clk2,
input wire com_n,
// Outputs to external pins
output wire cmram0,
output wire cmram1,
output wire cmram2,
output wire cmram3,
output wire cmrom
);
reg [3:0] acc;
reg cy;
// Decode logic
wire n0854 = ~(~x12);
wire n0351 = ~(x21_clk2 | ~dcl);
wire n0415 = ~(x21_clk2 | ope_n);
wire add_ib = ~(x31_clk2 | ~inc_isz);
wire cy_ib = ~(x31_clk2 | ~iow);
wire acb_ib = ~((x31_clk2 | ~xch) & (x21_clk2 | ~iow));
wire n0477 = ~((~x31_clk2 & ~ior) | (a12 & ior));
wire adc_cy = ~(write_carry_2 | n0477);
wire add_acc = ~(write_acc_1 | n0477);
wire adsr = ~(x31_clk2 | ~rar);
wire adsl = ~(x31_clk2 | ~ral);
wire acc_adac = ~(~cma | n0342);
wire acc_ada = ~(read_acc_3 | n0342);
wire cy_ada = ~(add_group_4 | n0342);
wire cy_adac = ~(sub_group_6 | n0342);
// Latch the incoming data bus
reg [3:0] tmp; // It's the name used in simulator!
always @(posedge sysclk) begin
if (~n0342)
tmp <= data;
if (m12)
tmp <= 4'b1111;
end
// Invert some of the incoming data
reg n0893, n0891, n0889, n0887; // D3, D2, D1, D0
always @(posedge sysclk) begin
if (sub_group_6) begin
n0887 <= tmp[0];
n0889 <= ~tmp[1];
n0891 <= tmp[2];
n0893 <= ~tmp[3];
end
if (~(sub_group_6 | m12)) begin
n0887 <= ~tmp[0];
n0889 <= tmp[1];
n0891 <= ~tmp[2];
n0893 <= tmp[3];
end
end
// Feedback from Accumulator
reg n0873, n0872, n0871, n0870;
always @(posedge sysclk) begin
if (m12)
{n0873, n0872, n0871, n0870} <= 4'b1010;
if (acc_ada)
{n0873, n0872, n0871, n0870} <= acc;
if (acc_adac)
{n0873, n0872, n0871, n0870} <= ~acc;
end
// Carry generator
wire n0546 = ~(inc_group_5 | n0342);
reg n0550;
always @(posedge sysclk) begin
if (m12) n0550 <= 1'b0;
if (n0546) n0550 <= 1'b1;
if (cy_adac) n0550 <= ~cy;
if (cy_ada) n0550 <= cy;
end
wire n0911 = ~(n0550 ? (n0887 | n0870) : (n0887 & n0870));
wire n0553 = n0911;
wire n0912 = ~(n0553 ? (n0889 | n0871) : (n0889 & n0871));
wire n0556 = n0912;
wire n0913 = ~(n0556 ? (n0891 | n0872) : (n0891 & n0872));
wire n0559 = n0913;
wire n0914 = ~(n0559 ? (n0893 | n0873) : (n0893 & n0873));
wire n0861 = n0914;
// Adder
wire n0877 = ~((n0893 & n0559 & n0873) | (n0861 & (n0893 | n0873 | n0559)));
wire n0878 = ~((n0877 & n0550 & n0870) | (n0553 & (n0887 | n0870 | n0550)));
wire n0875 = ~((n0889 & n0553 & n0871) | (n0556 & (n0889 | n0871 | n0553)));
wire n0879 = ~((n0891 & n0556 & n0872) | (n0559 & (n0891 | n0872 | n0556)));
wire n0846 = ~n0878;
wire n0847 = n0875;
wire n0848 = ~n0879;
wire n0514 = n0877;
// Shifter / Accumulator and Carry
reg [3:0] acc_out; // {n0356, n0348, n0347, n0346}
wire n0803 = ~((acc_out[3] & (acc_out[2] | acc_out[1])) | cy_1);
wire n0403 = ~(~daa | n0803);
wire [3:0] acc_in = {n0514, n0848, n0847, n0846};
always @(posedge sysclk) begin
if (adsr)
{acc, cy} <= {cy_1, acc_in};
if (add_acc)
acc <= acc_in;
if (adsl)
{cy, acc} <= {acc_in, cy_1};
if (adc_cy)
cy <= n0861;
if (n0403 & n0415)
cy <= 1'b1;
// Dynamic refresh would occur during M12
end
// Accumulator output latch
always @(posedge sysclk) begin
if (n0854) begin
cy_1 <= cy;
acc_out <= acc;
end
end
assign acc_0 = ~|acc_out;
assign add_0 = ~|acc_in;
// Keyboard Process logic
wire n0378 = ~((daa & n0803) | o_ib);
wire n0345 = kbp & (acc_out == 4'b1000);
wire n0354 = kbp & (acc_out == 4'b0100);
wire n0363 = kbp & (acc_out == 4'b0010);
wire n0370 = kbp & (acc_out == 4'b0001);
wire n0377 = (kbp & (acc_out == 4'b0000)) | ~n0378;
wire n0358 = ~(n0345 | n0354 | n0363 | n0370 | n0377 | n0403);
wire n0366 = ~( n0354 | n0363 | n0370 | n0377 | tcs );
wire n0359 = ~(n0345 | n0370 | n0377 | tcs );
wire n0357 = ~(n0345 | n0363 | n0377 | n0403);
// Data output mux
reg [3:0] dout;
always @(*) begin
dout = 4'bzzzz;
if (acb_ib)
dout = acc_out;
if (add_ib)
dout = acc_in;
if (cy_ib)
dout = {3'bxxx, cy_1};
if (n0415)
dout = {n0358, n0366, n0359, n0357};
end
assign data = dout;
// Generate CMROM / CMRAMn
// This may get moved to the Timing & I/O board
// Inputs: {n0355, n0364, n0371}, n0351, poc, com_n
wire n0355 = ~acc_out[2];
wire n0364 = ~acc_out[1];
wire n0371 = ~acc_out[0];
reg n0749, n0750, n0751;
always @(posedge sysclk) begin
if (poc) begin
n0749 <= 1'b1;
n0750 <= 1'b1;
n0751 <= 1'b1;
end
else begin
if (n0351) begin
n0749 <= n0355;
n0750 <= n0364;
n0751 <= n0371;
end
end
end
assign cmram3 = ~(com_n | n0749);
assign cmram2 = ~(com_n | n0750);
assign cmram1 = ~(com_n | n0751);
assign cmram0 = ~(com_n | ~n0749 | ~n0750 | ~n0751);
assign cmrom = ~(com_n | poc);
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module counter(
input wire sysclk,
input wire step_a,
input wire step_b,
output reg q = 1'b0
);
reg q_n = 1'b1;
always @(posedge sysclk) begin
if (step_a) q <= ~q_n;
if (step_b) q_n <= q;
end
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module instruction_decode(
input wire sysclk, // 50 MHz FPGA clock
// Inputs from the Timing and I/O board
input wire clk1,
input wire clk2,
input wire a22,
input wire m12,
input wire m22,
input wire x12,
input wire x22,
input wire x32,
input wire poc, // Power-On Clear (reset)
input wire n0432, // Conditioned TEST_PAD
// Common 4-bit data bus
inout wire [3:0] data,
// These drive the Instruction Pointer (IP) board
output wire jcn_isz, // JCN+ISZ
output wire jin_fin, // JIN+FIN
output wire jun_jms, // JUN+JMS
output wire cn_n, // ~CN
output wire bbl, // BBL
output wire jms, // JMS
// Outputs to both the IP and SP boards
output wire sc, // SC (Single Cycle)
output wire dc, // DC (Double Cycle, ~SC)
// Outputs to the Scratch Pad (SP) board
output wire sc_m22_clk2, // SC&M22&CLK2
output wire fin_fim_src_jin, // FIN+FIM+SRC+JIN
output wire inc_isz_add_sub_xch_ld, // INC+ISZ+ADD+SUB+XCH+LD
output wire inc_isz_xch, // INC+ISZ+XCH
output wire opa0_n, // ~OPA.0
// Inputs from the ALU board (condition bits)
input wire acc_0, // ACC_0
input wire add_0, // ADD_0
input wire cy_1, // CY_1
// Outputs to the Arithmetic Logic Unit (ALU) board
output wire cma,
output wire write_acc_1,
output wire write_carry_2,
output wire read_acc_3,
output wire add_group_4,
output wire inc_group_5,
output wire sub_group_6,
output wire ior,
output wire iow,
output wire ral,
output wire rar,
output wire ope_n,
output wire daa,
output wire dcl,
output wire inc_isz,
output wire kbp,
output wire o_ib,
output wire tcs,
output wire xch,
output wire n0342,
output wire x21_clk2,
output wire x31_clk2,
output wire com_n
);
wire sc_m12_clk2 = sc & m12 & clk2;
assign sc_m22_clk2 = sc & m22 & clk2;
// Latch the first 4 bits of the opcode
reg [3:0] opr = 4'b0000;
always @(posedge sysclk) begin
if (sc_m12_clk2)
opr <= data;
end
// Latch the second 4 bits of the opcode
reg [3:0] opa = 4'b0000;
always @(posedge sysclk) begin
if (sc_m22_clk2)
opa <= data;
end
assign opa0_n = ~opa[0];
// Full OPR Decoding
wire nop = (opr == 4'b0000);
wire jcn = (opr == 4'b0001);
wire fim_src = (opr == 4'b0010);
assign jin_fin = (opr == 4'b0011);
wire jun = (opr == 4'b0100);
assign jms = (opr == 4'b0101);
wire inc = (opr == 4'b0110);
wire isz = (opr == 4'b0111);
wire add = (opr == 4'b1000);
wire sub = (opr == 4'b1001);
wire ld = (opr == 4'b1010);
assign xch = (opr == 4'b1011);
assign bbl = (opr == 4'b1100);
wire ldm = (opr == 4'b1101);
wire io = (opr == 4'b1110);
wire ope = (opr == 4'b1111);
assign ope_n = ~ope;
assign jcn_isz = jcn | isz;
assign jun_jms = jun | jms;
wire ldm_bbl = ldm | bbl;
assign inc_isz = (inc | isz) & sc;
assign inc_isz_xch = inc | isz | xch;
assign inc_isz_add_sub_xch_ld = inc | isz | add | sub | xch | ld;
assign fin_fim_src_jin = fim_src | jin_fin;
// OPE: OPA Decoding
assign o_ib = ope & (opa[3] == 1'b0);
wire clb = ope & (opa == 4'b0000);
wire clc = ope & (opa == 4'b0001);
wire iac = ope & (opa == 4'b0010);
wire cmc = ope & (opa == 4'b0011);
assign cma = ope & (opa == 4'b0100);
assign ral = ope & (opa == 4'b0101);
assign rar = ope & (opa == 4'b0110);
wire tcc = ope & (opa == 4'b0111);
wire dac = ope & (opa == 4'b1000);
assign tcs = ope & (opa == 4'b1001);
wire stc = ope & (opa == 4'b1010);
assign daa = ope & (opa == 4'b1011);
assign kbp = ope & (opa == 4'b1100);
assign dcl = ope & (opa == 4'b1101);
// IO: OPA Decoding
assign iow = io & (opa[3] == 1'b0);
assign ior = io & (opa[3] == 1'b1);
wire adm = io & (opa == 4'b1011);
wire sbm = io & (opa == 4'b1000);
wire fin_fim = fin_fim_src_jin & ~opa[0];
wire src = fim_src & opa[0];
assign write_acc_1 = ~(kbp | tcs | daa | xch | poc | cma | tcc | dac | iac |
clb | ior | ld | sub | add | ldm_bbl);
assign write_carry_2 = ~(tcs | poc | tcc | stc | cmc | dac | iac |
clc | clb | sbm | adm | sub | add);
assign read_acc_3 = ~(daa | rar | ral | dac | iac | sbm | adm | sub | add);
assign add_group_4 = ~(tcs | tcc | adm | add);
assign inc_group_5 = ~(inc_isz | stc | iac);
assign sub_group_6 = ~(cmc | sbm | sub | m12);
// The Condition Flip-Flop
reg n0397;
wire n0486 = ~((opa[2] & acc_0) | (opa[1] & cy_1) | (opa[0] & n0432));
wire n0419 = ~((add_0 & ~isz) & (~jcn | ((~n0486 | opa[3]) & (n0486 | ~opa[3]))));
wire n0413 = ~((sc & n0419 & x32) | (~x32 | n0397));
reg n0405;
always @(posedge sysclk) begin
if (clk2)
n0405 <= n0413;
if (clk1)
n0397 <= ~n0405;
end
assign cn_n = ~n0397;
// The Single-Cycle Flip-Flop
reg n0343;
wire n0368 = ~((sc & (fin_fim | jcn_isz | jun_jms) & x32) | (n0343 & ~x32));
reg n0362;
always @(posedge sysclk) begin
if (clk2)
n0362 <= n0368;
if (clk1)
n0343 <= ~n0362;
end
assign sc = ~n0343;
assign dc = ~sc;
// Generate ~(X21&~CLK2)
reg n0360;
always @(posedge sysclk) begin
if (clk2)
n0360 <= ~x12;
end
wire n0337 = ~(n0360 | clk2);
assign x21_clk2 = ~n0337;
// Generate ~(X31&~CLK2)
reg n0380;
always @(posedge sysclk) begin
if (clk2)
n0380 <= ~x22;
end
wire n0375 = ~(n0380 | clk2);
assign x31_clk2 = ~n0375;
// Generate ~COM
wire n0329 = io;
reg n0414, n0797;
always @(posedge sysclk) begin
if (clk2)
n0414 <= a22;
else
n0797 <= n0414;
end
reg n0433, n0801;
always @(posedge sysclk) begin
if (clk2)
n0433 <= m12;
else
n0801 <= n0433;
end
reg n0425, n0805;
always @(posedge sysclk) begin
if (clk2)
n0425 <= x12;
else
n0805 <= n0425;
end
wire n0782 = ~((n0801 & n0329) | (src & n0805) | n0797);
assign com_n = n0782;
// Generate N0342
wire n0332 = ~(((n0329 | poc) & x22 & clk2) | (~(n0329 | poc) & n0337 & clk1));
assign n0342 = n0332;
// Output OPA onto the data bus
wire opa_ib = (ldm_bbl | jun_jms) & ~x21_clk2;
assign data = opa_ib ? opa : 4'bzzzz;
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module instruction_pointer (
input wire sysclk, // 50 MHz FPGA clock
// Inputs from the Timing and I/O board
input wire clk1,
input wire clk2,
input wire a12,
input wire a22,
input wire a32,
input wire m12,
input wire m22,
input wire x12,
input wire x22,
input wire x32,
input wire poc, // Power-On Clear (reset)
input wire m12_m22_clk1_m11_m12, // M12+M22+CLK1~(M11+M12)
// Common 4-bit data bus
inout wire [3:0] data,
// Inputs from the Instruction Decode board
input wire jcn_isz, // JCN+ISZ
input wire jin_fin, // JIN+FIN
input wire jun_jms, // JUN+JMS
input wire cn_n, // ~CN
input wire bbl, // BBL
input wire jms, // JMS
input wire sc, // SC (Single Cycle)
input wire dc // DC (Double Cycle, ~SC)
);
reg [11:0] dram_array [0:3];
reg [11:0] dram_temp;
wire [3:0] din_n;
wire inh = (jin_fin & sc) | ((jun_jms | (jcn_isz & ~cn_n)) & dc);
// Row Counter stuff
wire [1:0] addr_ptr; // Effective Address counter
wire addr_ptr_step; // CLK2(JMS&DC&M22+BBL(M22+X12+X22))
assign addr_ptr_step = ~(~clk2 | ~(((m22 | x12 | x22) & bbl) |
(m22 & dc & jms)));
counter addr_ptr_0 (
.sysclk(sysclk),
.step_a(clk1),
.step_b(addr_ptr_step),
.q(addr_ptr[0])
);
counter addr_ptr_1 (
.sysclk(sysclk),
.step_a( addr_ptr[0]),
.step_b(~addr_ptr[0]),
.q(addr_ptr[1])
);
// Refresh counter stuff
wire [1:0] addr_rfsh; // Row Refresh counter
wire addr_rfsh_step; // (~INH)&X32&CLK2
assign addr_rfsh_step = ~inh & x32 & clk2;
counter addr_rfsh_0 (
.sysclk(sysclk),
.step_a(clk1),
.step_b(addr_rfsh_step),
.q(addr_rfsh[0])
);
counter addr_rfsh_1 (
.sysclk(sysclk),
.step_a( addr_rfsh[0]),
.step_b(~addr_rfsh[0]),
.q(addr_rfsh[1])
);
// Row selection mux
reg [1:0] row; // {N0409, N0420}
always @(posedge sysclk) begin
if (x12)
row <= addr_rfsh;
if (x32)
row <= addr_ptr;
end
// Row Precharge/Read/Write stuff
wire precharge; // (~INH)(X11+X31)CLK1
wire row_read; // (~POC)CLK2(X12+X32)~INH
wire row_write; // ((~SC)(JIN+FIN))CLK1(M11+X21~INH)
reg n0517;
always @(posedge sysclk) begin
if (clk2)
n0517 <= ~(m22 | x22);
end
assign precharge = ~(n0517 | inh | ~clk1);
assign row_read = ~poc & clk2 & (x12 | x32) & ~inh;
reg n0438;
always @(posedge sysclk) begin
if (clk2)
n0438 <= ~((x12 & ~inh) | a32);
end
assign row_write = ~(n0438 | (jin_fin & ~sc) | ~clk1);
// Column Read selection stuff
reg n0416;
always @(posedge sysclk) begin
if (clk2)
n0416 <= ~x32;
end
wire radb0 = ~(n0416 | clk2);
reg n0384;
always @(posedge sysclk) begin
if (clk2)
n0384 <= ~a12;
end
wire radb1 = ~(n0384 | clk2);
reg n0374;
always @(posedge sysclk) begin
if (clk2)
n0374 <= ~a22;
end
wire radb2 = ~(n0374 | clk2);
// Column Write selection stuff
wire n0322 = ~(sc | cn_n);
wire wadb0 = ~(~clk2 | ~(a12 | (sc & jin_fin & x32) |
(((jcn_isz & n0322) | (jun_jms & ~sc)) & m22)));
wire wadb1 = ~(~clk2 | ~(a22 | (sc & jin_fin & x22) |
(((jcn_isz & n0322) | (jun_jms & ~sc)) & m12)));
wire wadb2 = ~(~clk2 | ~(a32 | (jun_jms & ~sc & x22)));
// Manage the row data buffer
always @(posedge sysclk) begin
if (precharge)
dram_temp <= 12'b0;
if (row_read)
dram_temp <= dram_array[row];
if (wadb0)
dram_temp[ 3:0] <= ~din_n;
if (wadb1)
dram_temp[ 7:4] <= ~din_n;
if (wadb2)
dram_temp[11:8] <= ~din_n;
end
// Handle row writes
always @(posedge sysclk) begin
if (row_write)
dram_array[row] <= dram_temp;
end
// Manage the data output mux
reg [3:0] dout;
always @* begin
(* PARALLEL_CASE *)
case (1'b1)
radb0: dout = dram_temp[ 3:0];
radb1: dout = dram_temp[ 7:4];
radb2: dout = dram_temp[11:8];
default: dout = 4'bzzzz;
endcase
end
assign data = dout;
// Data In mux and incrementer
reg [3:0] incr_in;
always @(posedge sysclk) begin
if (m12_m22_clk1_m11_m12)
incr_in <= data;
end
reg carry_out, carry_in;
wire [4:0] incr_out = (a12 | ((a22 | a32) & carry_in)) ?
(incr_in + 4'b0001) : {1'b0, incr_in};
always @(posedge sysclk) begin
if (clk2)
carry_out <= incr_out[4];
if (clk1)
carry_in <= carry_out;
end
assign din_n = ~incr_out[3:0];
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module scratchpad (
input wire sysclk, // 50 MHz FPGA clock
// Inputs from the Timing and I/O board
input wire clk1,
input wire clk2,
input wire a12,
input wire a22,
input wire a32,
input wire m12,
input wire m22,
input wire x12,
input wire x22,
input wire x32,
input wire poc, // Power-On Clear (reset)
input wire m12_m22_clk1_m11_m12, // M12+M22+CLK1~(M11+M12)
// Common 4-bit data bus
inout wire [3:0] data,
// Inputs from the Instruction Decode board
input wire sc_m22_clk2, // SC&M22&CLK2
input wire fin_fim_src_jin, // FIN+FIM+SRC+JIN
input wire inc_isz_add_sub_xch_ld, // INC+ISZ+ADD+SUB+XCH+LD
input wire inc_isz_xch, // INC+ISZ+XCH
input wire opa0_n, // ~OPA.0
input wire sc, // SC (Single Cycle)
input wire dc // DC (Double Cycle, ~SC)
);
reg [7:0] dram_array [0:7];
reg [7:0] dram_temp;
reg [3:0] din_n;
// Refresh counter stuff
wire [2:0] reg_rfsh; // Row Refresh counter
wire reg_rfsh_step; // SC&A12&CLK2
assign reg_rfsh_step = sc & a12 & clk2;
counter reg_rfsh_0 (
.sysclk(sysclk),
.step_a(clk1),
.step_b(reg_rfsh_step),
.q(reg_rfsh[0])
);
counter reg_rfsh_1 (
.sysclk(sysclk),
.step_a( reg_rfsh[0]),
.step_b(~reg_rfsh[0]),
.q(reg_rfsh[1])
);
counter reg_rfsh_2 (
.sysclk(sysclk),
.step_a( reg_rfsh[1]),
.step_b(~reg_rfsh[1]),
.q(reg_rfsh[2])
);
// Row selection mux
reg [2:0] row; // {N0646, N0617, N0582}
always @(posedge sysclk) begin
if (sc & a22)
row <= reg_rfsh;
if (sc_m22_clk2)
row <= data[3:1];
end
// Row Precharge/Read/Write stuff
wire precharge; // SC(A22+M22)CLK2
wire row_read; // (~POC)&CLK2&SC(A32+X12)
wire row_write; // CLK2&SC(A12+M12)
assign precharge = sc & (a22 | m22) & clk2;
assign row_read = ~(poc | ~(clk2 & sc & (a32 | x12)));
assign row_write = sc & (a12 | m12) & clk2;
// Column Read selection stuff
reg n0615;
always @(posedge sysclk) begin
if (clk2)
n0615 <= ~(x12 & (fin_fim_src_jin |
(opa0_n & inc_isz_add_sub_xch_ld)));
end
wire rrab0 = ~(dc | n0615 | clk2);
reg n0592;
always @(posedge sysclk) begin
if (clk2)
n0592 <= ~((x22 & fin_fim_src_jin) |
(~opa0_n & x12 & inc_isz_add_sub_xch_ld));
end
wire rrab1 = ~(dc | n0592 | clk2);
// Column Write selection stuff
wire n0564 = opa0_n & fin_fim_src_jin & dc;
wire n0568 = inc_isz_xch & x32 & sc;
wire wrab0 = clk2 & ((m12 & n0564) | ( opa0_n & n0568));
wire wrab1 = clk2 & ((m22 & n0564) | (~opa0_n & n0568));
// Manage the row data buffer
always @(posedge sysclk) begin
if (precharge)
dram_temp <= 8'b0;
if (row_read)
dram_temp <= dram_array[row];
if (wrab0)
dram_temp[ 3:0] <= ~din_n;
if (wrab1)
dram_temp[ 7:4] <= ~din_n;
end
// Handle row writes
always @(posedge sysclk) begin
if (row_write)
dram_array[row] <= dram_temp;
end
// Manage the data output mux
reg [3:0] dout;
always @* begin
(* PARALLEL_CASE *)
case (1'b1)
rrab0: dout = dram_temp[ 3:0];
rrab1: dout = dram_temp[ 7:4];
default: dout = 4'bzzzz;
endcase
end
assign data = dout;
// Data In latch
always @(posedge sysclk) begin
if (m12_m22_clk1_m11_m12)
din_n <= ~data;
end
endmodule
`define default_netname none
`default_nettype none
////////////////////////////////////////////////////////////////////////
//
// 4004 Counter sub-module
//
// This file is part of the MCS-4 project hosted at OpenCores:
// http://www.opencores.org/cores/mcs-4/
//
// Copyright 2012 by Reece Pollack <rrpollack@opencores.org>
//
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// are NOT "public domain" and are protected by copyright.
//
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// details of this license.
//
////////////////////////////////////////////////////////////////////////
module timing_io(
input wire sysclk,
input wire clk1_pad,
input wire clk2_pad,
input wire poc_pad,
input wire ior,
// Timing and I/O Board Outputs
output wire clk1,
output wire clk2,
output wire a12,
output wire a22,
output wire a32,
output wire m12,
output wire m22,
output wire x12,
output wire x22,
output wire x32,
output wire gate,
output reg poc,
// External I/O Pad conditioning
inout wire [3:0] data,
inout wire [3:0] data_in_pad,
output wire [3:0] data_out_pad,
input wire test_pad,
output reg n0432,
output reg sync_pad,
input wire cmrom,
output wire cmrom_pad,
input wire cmram0,
output wire cmram0_pad,
input wire cmram1,
output wire cmram1_pad,
input wire cmram2,
output wire cmram2_pad,
input wire cmram3,
output wire cmram3_pad
);
// Simple pass-throughs
assign clk1 = clk1_pad;
assign clk2 = clk2_pad;
assign cmrom_pad = cmrom;
assign cmram0_pad = cmram0;
assign cmram1_pad = cmram1;
assign cmram2_pad = cmram2;
assign cmram3_pad = cmram3;
// Generate the 8 execution phase indicators
reg [0:7] master = 8'h00;
reg [0:7] slave = 8'h00;
always @(posedge sysclk) begin
if (clk2)
master <= {~|slave[0:6], slave[0:6]};
else
sync_pad <= master[7];
if (clk1)
slave <= master;
end
assign a12 = slave[0];
assign a22 = slave[1];
assign a32 = slave[2];
assign m12 = slave[3];
assign m22 = slave[4];
assign x12 = slave[5];
assign x22 = slave[6];
assign x32 = slave[7];
// Generate the DRAM Input Gate signal
// Properly called M12+M22+CLK1~(M11&M12)
wire n0279 = ~(a32 | m12);
reg n0278;
always @(posedge sysclk) begin
if (clk2)
n0278 <= n0279;
end
wire n0708 = ~((n0278 & clk1) | m12 | m22);
assign gate = ~n0708;
// Generate a clean POC signal
always @(posedge sysclk) begin
if (poc_pad) poc <= 1'b1;
else if (a12) poc <= 1'b0;
else poc <= poc;
end
// Generate a clean ~TEST signal (n0432)
always @(posedge sysclk) begin
n0432 <= ~test_pad;
end
// Manage the Data I/O pads
reg L;
always @(posedge sysclk) begin
if (clk2)
L <= a32 | m12 | (x12 & (ior | poc));
end
wire n0702 = ~clk2;
reg n0685;
reg n0699;
reg n0707;
always @(posedge sysclk) begin
if (clk1) begin
n0685 <= ~L;
n0707 <= L;
end
if (n0702)
n0699 <= ~L;
end
wire n0700 = n0707 | (L & n0702) | poc;
wire n0659 = (clk2 & n0685) | (clk1 & L);
wire n0676 = clk1 | n0685 | n0699;
// Incoming data from the external pads
reg [3:0] data_in;
always @* begin
if (n0659) data_in = 4'b1111;
else if (n0676) data_in = 4'bzzzz;
else if (poc) data_in = 4'b0000;
else data_in = data_in_pad;
end
assign data = data_in;
// Outgoing data to the external pads
reg [3:0] data_out;
always @(posedge sysclk) begin
if (n0702)
data_out <= data;
end
assign data_out_pad = poc ? 4'b0000 : (n0700 ? 4'bzzzz : data_out);
assign data_in_pad = poc ? 4'b0000 : (n0700 ? 4'bzzzz : data_out);
endmodule
|
module tt_um_noritsuna_i4004 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena,
input wire clk,
input wire rst_n
);
wire sysclk;
wire clk1_pad;
wire clk2_pad;
wire poc_pad;
wire test_pad;
wire [3:0] data_in_pad;
wire [3:0] data_out_pad;
wire cmrom_pad;
wire cmram0_pad;
wire cmram1_pad;
wire cmram2_pad;
wire cmram3_pad;
wire sync_pad;
//input:
assign sysclk = clk;
assign data_in_pad = ui_in[3:0];
assign clk1_pad = ui_in[4];
assign clk2_pad = ui_in[5];
assign poc_pad = ui_in[6];
assign test_pad = ui_in[7];
//output:
assign cmrom_pad = uo_out[0];
assign cmram0_pad = uo_out[1];
assign cmram1_pad = uo_out[2];
assign cmram2_pad = uo_out[3];
assign cmram3_pad = uo_out[4];
assign sync_pad = uo_out[5];
assign uio_oe[3:0] = 1;
assign data_out_pad = uio_out[3:0];
// All output pins must be assigned. If not used, assign to 0.
assign uo_out[6] = 0;
assign uo_out[7] = 0;
assign uio_out[7:4] = 0;
assign uio_oe[7:4] = 0;
// Common BiDir data bus
wire [3:0] data;
// Timing and I/O Board Outputs
wire clk1;
wire clk2;
wire a12;
wire a22;
wire a32;
wire m12;
wire m22;
wire x12;
wire x22;
wire x32;
wire gate;
wire poc; // Clean POC_PAD
wire n0432; // Clean TEST_PAD
// Outputs from the Instruction Decode board
wire jcn_isz;
wire jin_fin;
wire jun_jms;
wire cn_n;
wire bbl;
wire jms;
wire sc;
wire dc;
wire sc_m22_clk2;
wire fin_fim_src_jin;
wire inc_isz_add_sub_xch_ld;
wire inc_isz_xch;
wire opa0_n;
wire cma;
wire write_acc_1;
wire write_carry_2;
wire read_acc_3;
wire add_group_4;
wire inc_group_5;
wire sub_group_6;
wire ior;
wire iow;
wire ral;
wire rar;
wire ope_n;
wire daa;
wire dcl;
wire inc_isz;
wire kbp;
wire o_ib;
wire tcs;
wire xch;
wire n0342;
wire x21_clk2;
wire x31_clk2;
wire com_n;
// Outputs from the ALU board
wire acc_0;
wire add_0;
wire cy_1;
wire cmram0;
wire cmram1;
wire cmram2;
wire cmram3;
wire cmrom;
// Instantiate the Timing and I/O board
timing_io tio_board (
.sysclk(sysclk),
.clk1_pad(clk1_pad),
.clk2_pad(clk2_pad),
.poc_pad(poc_pad),
.ior(ior),
.clk1(clk1),
.clk2(clk2),
.a12(a12),
.a22(a22),
.a32(a32),
.m12(m12),
.m22(m22),
.x12(x12),
.x22(x22),
.x32(x32),
.gate(gate),
.poc(poc),
.data(data),
.data_in_pad(data_in_pad),
.data_out_pad(data_out_pad),
.test_pad(test_pad),
.n0432(n0432),
.sync_pad(sync_pad),
.cmrom(cmrom),
.cmrom_pad(cmrom_pad),
.cmram0(cmram0),
.cmram0_pad(cmram0_pad),
.cmram1(cmram1),
.cmram1_pad(cmram1_pad),
.cmram2(cmram2),
.cmram2_pad(cmram2_pad),
.cmram3(cmram3),
.cmram3_pad(cmram3_pad)
);
// Instantiate the Instruction Decode board
instruction_decode id_board (
.sysclk(clk),
.clk1(clk1),
.clk2(clk2),
.a22(a22),
.m12(m12),
.m22(m22),
.x12(x12),
.x22(x22),
.x32(x32),
.poc(poc),
.n0432(n0432),
.data(data),
.jcn_isz(jcn_isz),
.jin_fin(jin_fin),
.jun_jms(jun_jms),
.cn_n(cn_n),
.bbl(bbl),
.jms(jms),
.sc(sc),
.dc(dc),
.sc_m22_clk2(sc_m22_clk2),
.fin_fim_src_jin(fin_fim_src_jin),
.inc_isz_add_sub_xch_ld(inc_isz_add_sub_xch_ld),
.inc_isz_xch(inc_isz_xch),
.opa0_n(opa0_n),
.acc_0(acc_0),
.add_0(add_0),
.cy_1(cy_1),
.cma(cma),
.write_acc_1(write_acc_1),
.write_carry_2(write_carry_2),
.read_acc_3(read_acc_3),
.add_group_4(add_group_4),
.inc_group_5(inc_group_5),
.sub_group_6(sub_group_6),
.ior(ior),
.iow(iow),
.ral(ral),
.rar(rar),
.ope_n(ope_n),
.daa(daa),
.dcl(dcl),
.inc_isz(inc_isz),
.kbp(kbp),
.o_ib(o_ib),
.tcs(tcs),
.xch(xch),
.n0342(n0342),
.x21_clk2(x21_clk2),
.x31_clk2(x31_clk2),
.com_n(com_n)
);
// Instantiate the ALU board
alu alu_board (
.sysclk(clk),
.a12(a12),
.m12(m12),
.x12(x12),
.poc(poc),
.data(data),
.acc_0(acc_0),
.add_0(add_0),
.cy_1(cy_1),
.cma(cma),
.write_acc_1(write_acc_1),
.write_carry_2(write_carry_2),
.read_acc_3(read_acc_3),
.add_group_4(add_group_4),
.inc_group_5(inc_group_5),
.sub_group_6(sub_group_6),
.ior(ior),
.iow(iow),
.ral(ral),
.rar(rar),
.ope_n(ope_n),
.daa(daa),
.dcl(dcl),
.inc_isz(inc_isz),
.kbp(kbp),
.o_ib(o_ib),
.tcs(tcs),
.xch(xch),
.n0342(n0342),
.x21_clk2(x21_clk2),
.x31_clk2(x31_clk2),
.com_n(com_n),
.cmram0(cmram0),
.cmram1(cmram1),
.cmram2(cmram2),
.cmram3(cmram3),
.cmrom(cmrom)
);
// Instantiate the Instruction Pointer board
instruction_pointer ip_board (
.sysclk(clk),
.clk1(clk1),
.clk2(clk2),
.a12(a12),
.a22(a22),
.a32(a32),
.m12(m12),
.m22(m22),
.x12(x12),
.x22(x22),
.x32(x32),
.poc(poc),
.m12_m22_clk1_m11_m12(gate),
.data(data),
.jcn_isz(jcn_isz),
.jin_fin(jin_fin),
.jun_jms(jun_jms),
.cn_n(cn_n),
.bbl(bbl),
.jms(jms),
.sc(sc),
.dc(dc)
);
// Instantiate the Scratchpad board
scratchpad sp_board (
.sysclk(clk),
.clk1(clk1),
.clk2(clk2),
.a12(a12),
.a22(a22),
.a32(a32),
.m12(m12),
.m22(m22),
.x12(x12),
.x22(x22),
.x32(x32),
.poc(poc),
.m12_m22_clk1_m11_m12(gate),
.data(data),
.sc_m22_clk2(sc_m22_clk2),
.fin_fim_src_jin(fin_fim_src_jin),
.inc_isz_add_sub_xch_ld(inc_isz_add_sub_xch_ld),
.inc_isz_xch(inc_isz_xch),
.opa0_n(opa0_n),
.sc(sc),
.dc(dc)
);
endmodule
|
tt06-finale_0088
|
tt06-finale
|
pcky-tt06-wokwi
|
task_number_init
|
tt_um_pckys_game
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_pckys_game (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
assign uio_out = 0;
assign uio_oe = 0;
assign DI = ui_in;
assign uo_out = DO;
reg [7:0] DI,DO;
reg rst;
assign rst = !rst_n;
reg [7:0] counter;
reg [7:0] number;
reg [11:0] counter2;
reg [2:0] counter3;
reg [7:0] pattern0;
reg [7:0] pattern1;
reg [7:0] pattern2;
reg start = 0;
assign DO = (start)?
((rst)?pattern1:
(DI>number)?8'b01000001:
(DI==number)?pattern2:
(DI<number)?8'b01001000:
0):pattern0;
always @(posedge clk )
begin
if (rst) begin
start <= 1;
number <= counter;
end
end
number_init n_init_inst (clk, rst, counter);
timer t_inst (clk, counter2, counter3);
assign pattern0 =
(counter3 == 0) ? 8'b11010000 :
(counter3 == 1) ? 8'b11010000 :
(counter3 == 2) ? 8'b11010000 :
(counter3 == 3) ? 8'b01010000 :
(counter3 == 4) ? 8'b01010000 :
8'b01010000 ;
assign pattern1 =
(counter3 == 0) ? 8'b10100000 :
(counter3 == 1) ? 8'b00010000 :
(counter3 == 2) ? 8'b00001000 :
(counter3 == 3) ? 8'b10000100 :
(counter3 == 4) ? 8'b00000010 :
8'b00000001 ;
assign pattern2 =
(counter3 == 0) ? 8'b01000000 :
(counter3 == 1) ? 8'b01000000 :
(counter3 == 2) ? 8'b01000000 :
(counter3 == 3) ? 8'b01001001 :
(counter3 == 4) ? 8'b01001001 :
8'b01001001 ;
endmodule
module number_init(
input clk,
input rst,
output [7:0] out
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module timer(input clk, output reg [11:0] counter = 12'h0 + 12'd512, output reg [2:0] counter2 = 0);
reg flag1 = 0;
always @(posedge clk) begin
counter <= counter + 1'b1;
if (counter[9]) begin
if(counter2 == 6)
counter2 <= 0;
if(flag1) begin
flag1 <= 0;
if(counter2 == 6)
counter2 <= 0;
else
counter2 <= counter2 + 1;
end
end else begin
flag1 <= 1;
end
end
endmodule
|
module number_init(
input clk,
input rst,
output [7:0] out
);
reg [7:0] counter;
assign out = counter;
always @(posedge clk )
begin
counter <= 0;
if (rst) begin
counter <= counter + 1;
end else begin
end
end
endmodule
|
tt06-finale_0089
|
tt06-finale
|
pcky-tt06-wokwi
|
task_timer
|
tt_um_pckys_game
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_pckys_game (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
assign uio_out = 0;
assign uio_oe = 0;
assign DI = ui_in;
assign uo_out = DO;
reg [7:0] DI,DO;
reg rst;
assign rst = !rst_n;
reg [7:0] counter;
reg [7:0] number;
reg [11:0] counter2;
reg [2:0] counter3;
reg [7:0] pattern0;
reg [7:0] pattern1;
reg [7:0] pattern2;
reg start = 0;
assign DO = (start)?
((rst)?pattern1:
(DI>number)?8'b01000001:
(DI==number)?pattern2:
(DI<number)?8'b01001000:
0):pattern0;
always @(posedge clk )
begin
if (rst) begin
start <= 1;
number <= counter;
end
end
number_init n_init_inst (clk, rst, counter);
timer t_inst (clk, counter2, counter3);
assign pattern0 =
(counter3 == 0) ? 8'b11010000 :
(counter3 == 1) ? 8'b11010000 :
(counter3 == 2) ? 8'b11010000 :
(counter3 == 3) ? 8'b01010000 :
(counter3 == 4) ? 8'b01010000 :
8'b01010000 ;
assign pattern1 =
(counter3 == 0) ? 8'b10100000 :
(counter3 == 1) ? 8'b00010000 :
(counter3 == 2) ? 8'b00001000 :
(counter3 == 3) ? 8'b10000100 :
(counter3 == 4) ? 8'b00000010 :
8'b00000001 ;
assign pattern2 =
(counter3 == 0) ? 8'b01000000 :
(counter3 == 1) ? 8'b01000000 :
(counter3 == 2) ? 8'b01000000 :
(counter3 == 3) ? 8'b01001001 :
(counter3 == 4) ? 8'b01001001 :
8'b01001001 ;
endmodule
module number_init(
input clk,
input rst,
output [7:0] out
);
reg [7:0] counter;
assign out = counter;
always @(posedge clk )
begin
counter <= 0;
if (rst) begin
counter <= counter + 1;
end else begin
end
end
endmodule
module timer(input clk, output reg [11:0] counter = 12'h0 + 12'd512, output reg [2:0] counter2 = 0);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
|
module timer(input clk, output reg [11:0] counter = 12'h0 + 12'd512, output reg [2:0] counter2 = 0);
reg flag1 = 0;
always @(posedge clk) begin
counter <= counter + 1'b1;
if (counter[9]) begin
if(counter2 == 6)
counter2 <= 0;
if(flag1) begin
flag1 <= 0;
if(counter2 == 6)
counter2 <= 0;
else
counter2 <= counter2 + 1;
end
end else begin
flag1 <= 1;
end
end
endmodule
|
tt06-finale_0090
|
tt06-finale
|
pcky-tt06-wokwi
|
task_tt_um_pckys_game
|
tt_um_pckys_game
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
module tt_um_pckys_game (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module number_init(
input clk,
input rst,
output [7:0] out
);
reg [7:0] counter;
assign out = counter;
always @(posedge clk )
begin
counter <= 0;
if (rst) begin
counter <= counter + 1;
end else begin
end
end
endmodule
module timer(input clk, output reg [11:0] counter = 12'h0 + 12'd512, output reg [2:0] counter2 = 0);
reg flag1 = 0;
always @(posedge clk) begin
counter <= counter + 1'b1;
if (counter[9]) begin
if(counter2 == 6)
counter2 <= 0;
if(flag1) begin
flag1 <= 0;
if(counter2 == 6)
counter2 <= 0;
else
counter2 <= counter2 + 1;
end
end else begin
flag1 <= 1;
end
end
endmodule
|
module tt_um_pckys_game (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// All output pins must be assigned. If not used, assign to 0.
assign uio_out = 0;
assign uio_oe = 0;
assign DI = ui_in;
assign uo_out = DO;
reg [7:0] DI,DO;
reg rst;
assign rst = !rst_n;
reg [7:0] counter;
reg [7:0] number;
reg [11:0] counter2;
reg [2:0] counter3;
reg [7:0] pattern0;
reg [7:0] pattern1;
reg [7:0] pattern2;
reg start = 0;
assign DO = (start)?
((rst)?pattern1:
(DI>number)?8'b01000001:
(DI==number)?pattern2:
(DI<number)?8'b01001000:
0):pattern0;
always @(posedge clk )
begin
if (rst) begin
start <= 1;
number <= counter;
end
end
number_init n_init_inst (clk, rst, counter);
timer t_inst (clk, counter2, counter3);
assign pattern0 =
(counter3 == 0) ? 8'b11010000 :
(counter3 == 1) ? 8'b11010000 :
(counter3 == 2) ? 8'b11010000 :
(counter3 == 3) ? 8'b01010000 :
(counter3 == 4) ? 8'b01010000 :
8'b01010000 ;
assign pattern1 =
(counter3 == 0) ? 8'b10100000 :
(counter3 == 1) ? 8'b00010000 :
(counter3 == 2) ? 8'b00001000 :
(counter3 == 3) ? 8'b10000100 :
(counter3 == 4) ? 8'b00000010 :
8'b00000001 ;
assign pattern2 =
(counter3 == 0) ? 8'b01000000 :
(counter3 == 1) ? 8'b01000000 :
(counter3 == 2) ? 8'b01000000 :
(counter3 == 3) ? 8'b01001001 :
(counter3 == 4) ? 8'b01001001 :
8'b01001001 ;
endmodule
|
tt06-finale_0091
|
tt06-finale
|
pyamnihc-tt06_um_ks_pyamnihc
|
task_prbs15
|
tt_um_ks_pyamnihc
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
`default_nettype none
module tt_um_ks_pyamnihc (
input wire [7:0] ui_in, // Dedicated inputs - connected to the input switches
output wire [7:0] uo_out, // Dedicated outputs - connected to the 7 segment display
input wire [7:0] uio_in, // IOs: Bidirectional Input path
output wire [7:0] uio_out, // IOs: Bidirectional Output path
output wire [7:0] uio_oe, // IOs: Bidirectional Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// SPI param.
localparam SPI_INST_WIDTH = 1;
localparam SPI_ADDR_WIDTH = 7;
localparam SPI_DATA_WIDTH = 8;
localparam SPI_NUM_CONFIG_REG = 8;
localparam SPI_NUM_STATUS_REG = 2;
// I2S param.
localparam I2S_AUDIO_DW = 8;
// KS param.
localparam KS_MAX_LENGTH = 32;
localparam KS_DATA_WIDTH = 8;
localparam KS_PRBS_WIDTH = 2;
localparam KS_EXTN_BITS = 4;
localparam KS_FRAC_BITS = 4;
// clock dividers
reg [3:0] clk_rise_counter;
wire clk_r16;
always @(posedge clk) begin
if (!rst_n) clk_rise_counter <= 'b0;
else clk_rise_counter <= clk_rise_counter + 1;
end
assign clk_r16 = clk_rise_counter[3];
// SPI register map
wire sck_i;
assign sck_i = uio_in[0];
wire sdi_i;
assign sdi_i = uio_in[1];
wire sdo_o;
assign uio_out[2] = sdo_o;
wire cs_ni;
assign cs_ni = uio_in[3];
// i2s tx
wire i2s_sck_o;
assign uio_out[4] = i2s_sck_o;
wire i2s_ws_o;
assign uio_out[5] = i2s_ws_o;
wire i2s_sd_o;
assign uio_out[6] = i2s_sd_o;
assign uio_out[0] = 1'b0;
assign uio_out[1] = 1'b0;
assign uio_out[3] = 1'b0;
assign uio_oe = 8'b1111_0100;
assign uo_out[0] = rst_n;
assign uo_out[1] = rst_n_prbs_15;
assign uo_out[2] = rst_n_prbs_7;
assign uo_out[3] = rst_n_ks_string;
assign uo_out[4] = freeze_prbs_7;
assign uo_out[5] = freeze_prbs_15;
assign uo_out[6] = i2s_noise_sel;
assign uo_out[7] = pluck;
// prbs tx
assign uio_out[7] = prbs_15;
// register map, packed to unpacked
wire [SPI_DATA_WIDTH*SPI_NUM_CONFIG_REG-1:0] config_bus_o;
wire [SPI_DATA_WIDTH*SPI_NUM_STATUS_REG-1:0] status_bus_i;
wire [SPI_DATA_WIDTH-1:0] config_arr [SPI_NUM_CONFIG_REG-1:0];
genvar i;
generate
for (i = 0; i < SPI_NUM_CONFIG_REG; i = i + 1) begin
assign config_arr[i] = config_bus_o[SPI_DATA_WIDTH*(i+1)-1:SPI_DATA_WIDTH*i];
end
endgenerate
wire [SPI_DATA_WIDTH-1:0] status_arr [SPI_NUM_CONFIG_REG-1:0];
generate
for (i = 0; i < SPI_NUM_STATUS_REG; i = i + 1) begin
assign status_bus_i[SPI_DATA_WIDTH*(i+1)-1:SPI_DATA_WIDTH*i] = status_arr[i];
end
endgenerate
assign status_arr[0] = 8'hC0;
assign status_arr[1] = 8'h01;
// SPI peripheral
wire [SPI_ADDR_WIDTH-1:0] spi_addr;
wire [SPI_DATA_WIDTH-1:0] spi_write_data, spi_read_data;
wire spi_write_en, spi_read_en;
spi_slave_mem_interface #(.INST_WIDTH(SPI_INST_WIDTH),
.ADDR_WIDTH(SPI_ADDR_WIDTH),
.DATA_WIDTH(SPI_DATA_WIDTH)
) spi_slave_mem_interface_0 (
.sck_i(sck_i),
.sdi_i(sdi_i),
.sdo_o(sdo_o),
.cs_ni(cs_ni && rst_n),
.addr_o(spi_addr),
.write_data_o(spi_write_data),
.write_en_o(spi_write_en),
.read_data_i(spi_read_data),
.read_en_o(spi_read_en)
);
// Register map
register_map #( .ADDR_WIDTH(SPI_ADDR_WIDTH),
.DATA_WIDTH(SPI_DATA_WIDTH),
.NUM_CONFIG_REG(SPI_NUM_CONFIG_REG),
.NUM_STATUS_REG(SPI_NUM_STATUS_REG)
) register_map_0 (
.clk_i(clk),
.rst_ni(rst_n),
.addr_i(spi_addr),
.write_data_i(spi_write_data),
.write_en_i(spi_write_en),
.read_data_o(spi_read_data),
.read_en_i(spi_read_en),
.config_bus_o(config_bus_o),
.status_bus_i(status_bus_i)
);
// prbs15
wire rst_n_prbs_15;
assign rst_n_prbs_15 = ~config_arr[0][0] && ~ui_in[0];
wire [14:0] lfsr_init_15;
assign lfsr_init_15 = {~config_arr[2][6:0], ~config_arr[1][7:0]};
wire load_prbs_15;
assign load_prbs_15 = config_arr[2][7] || ui_in[1];
wire freeze_prbs_15;
assign freeze_prbs_15 = config_arr[0][4] || ui_in[2];
wire prbs_15;
wire [14:0] prbs_frame_15;
prbs15 prbs15_0 (
.clk_i(clk_r16),
.rst_ni(rst_n && rst_n_prbs_15),
.lfsr_init_i(lfsr_init_15),
.load_prbs_i(load_prbs_15),
.freeze_i(freeze_prbs_15),
.prbs_o(prbs_15),
.prbs_frame_o(prbs_frame_15)
);
// prbs7
wire rst_n_prbs_7;
assign rst_n_prbs_7 = ~config_arr[0][1] && ~ui_in[0];
wire [6:0] lfsr_init_7;
assign lfsr_init_7 = config_arr[3][6:0];
wire load_prbs_7;
assign load_prbs_7 = config_arr[3][7] || ui_in[1];
wire freeze_prbs_7;
assign freeze_prbs_7 = config_arr[0][5] || ui_in[3];
wire prbs_7;
wire [6:0] prbs_frame_7;
prbs7 prbs7_0 (
.clk_i(clk_r16),
.rst_ni(rst_n && rst_n_prbs_7),
.lfsr_init_i(lfsr_init_7),
.load_prbs_i(load_prbs_7),
.freeze_i(freeze_prbs_7),
.prbs_o(prbs_7),
.prbs_frame_o(prbs_frame_7)
);
// i2s sample select
wire i2s_noise_sel = config_arr[0][7] || ui_in[4];
wire [I2S_AUDIO_DW-1:0] l_data, r_data;
assign l_data = i2s_noise_sel ? prbs_frame_15[I2S_AUDIO_DW-1:0] : ks_sample;
assign r_data = i2s_noise_sel ? {1'b0, prbs_frame_7} : ks_sample;
reg [I2S_AUDIO_DW-1:0] l_data_reg, r_data_reg;
wire l_load_en, r_load_en;
always @(negedge i2s_sck_o) begin
if (l_load_en == 1) l_data_reg <= l_data;
else l_data_reg <= l_data_reg;
if (r_load_en == 1) r_data_reg <= r_data;
else r_data_reg <= r_data_reg;
end
// i2s tx
assign i2s_sck_o = ~clk;
assign i2s_ws_o = clk_r16;
i2s_tx #(
.AUDIO_DW(I2S_AUDIO_DW)
) i2s_tx_0 (
.sck_i(i2s_sck_o),
.ws_i(i2s_ws_o),
.sd_o(i2s_sd_o),
.l_data_i(l_data_reg),
.r_data_i(r_data_reg),
.l_load_en_o(l_load_en),
.r_load_en_o(r_load_en)
);
// ks string
wire ks_clk;
assign ks_clk = clk_r16;
wire rst_n_ks_string;
assign rst_n_ks_string = ~config_arr[0][2] && ~ui_in[5];
wire ks_freeze;
assign ks_freeze = config_arr[0][7];
wire pluck;
assign pluck = config_arr[4][0] || ui_in[6];
wire round_en;
assign round_en = config_arr[4][1];
wire toggle_pattern_prbs_n;
assign toggle_pattern_prbs_n = config_arr[4][2];
wire drum_string_n;
assign drum_string_n = config_arr[4][3];
wire fine_tune_en;
assign fine_tune_en = config_arr[4][4];
wire dynamics_en;
assign dynamics_en = config_arr[4][5];
wire [KS_DATA_WIDTH-1:0] fine_tune_C;
assign fine_tune_C = config_arr[5];
wire [KS_DATA_WIDTH-1:0] dynamics_R;
assign dynamics_R = config_arr[6];
wire clip_noise;
assign clip_noise = config_arr[4][6];
wire [KS_PRBS_WIDTH-1:0] prbs_data;
assign prbs_data = {prbs_15, prbs_7};
wire [KS_DATA_WIDTH-1:0] ks_period;
assign ks_period = ~config_arr[7];
wire [KS_DATA_WIDTH-1:0] ks_sample;
ks_string #(
.MAX_LENGTH(KS_MAX_LENGTH),
.DATA_WIDTH(KS_DATA_WIDTH),
.PRBS_WIDTH(KS_PRBS_WIDTH),
.EXTN_BITS(KS_EXTN_BITS),
.FRAC_BITS(KS_FRAC_BITS)
) ks_string_0 (
.clk_i(ks_clk),
.rst_ni(rst_n && rst_n_ks_string),
.freeze_i(ks_freeze),
.pluck_i(pluck),
.round_en_i(round_en),
.toggle_pattern_prbs_ni(toggle_pattern_prbs_n),
.drum_string_ni(drum_string_n),
.fine_tune_en_i(fine_tune_en),
.fine_tune_C_i(fine_tune_C),
.dynamics_en_i(dynamics_en),
.dynamics_R_i(dynamics_R),
.clip_noise_i(clip_noise),
.prbs_data_i(prbs_data),
.period_i(ks_period),
.ks_sample_o(ks_sample)
);
endmodule
module spi_slave_mem_interface #(
parameter INST_WIDTH = 1,
parameter ADDR_WIDTH = 7,
parameter DATA_WIDTH = 8
) (
input sck_i,
input sdi_i,
output sdo_o,
input cs_ni,
output [ADDR_WIDTH-1:0] addr_o,
output [DATA_WIDTH-1:0] write_data_o,
output write_en_o,
input [DATA_WIDTH-1:0] read_data_i,
output read_en_o
);
// CPOL: 0, CPHA: 0
localparam SPI_FRAME_WIDTH = INST_WIDTH + ADDR_WIDTH + DATA_WIDTH;
localparam BIT_COUNT_WIDTH = $clog2(SPI_FRAME_WIDTH) + 1;
// shift register buffer
reg [SPI_FRAME_WIDTH-1:0] pico_reg;
always @(posedge sck_i or posedge cs_ni) begin
if (cs_ni) pico_reg <= 'b0;
else pico_reg <= {pico_reg[SPI_FRAME_WIDTH-2:0], sdi_i};
end
// keeps track of current bit position
reg [BIT_COUNT_WIDTH-1:0] bit_count;
always @(posedge sck_i or posedge cs_ni) begin
if (cs_ni) begin
bit_count <= 'b0;
end else if ((read_flag || write_flag) &&
(bit_count == (SPI_FRAME_WIDTH))) begin
bit_count <= INST_WIDTH+ADDR_WIDTH+1;
end else begin
bit_count <= bit_count + 1'b1;
end
end
// instruction decode
reg read_flag, write_flag;
always @(posedge sck_i or posedge cs_ni) begin
if (cs_ni) begin
read_flag <= 'b0;
write_flag <= 'b0;
end else if (bit_count < INST_WIDTH) begin
read_flag <= sdi_i;
write_flag <= !sdi_i;
end
end
// address decode and latch
reg [ADDR_WIDTH-1:0] addr_reg;
always @(posedge sck_i or posedge cs_ni) begin
if (cs_ni) begin
addr_reg <= 'b0;
end else if (bit_count == (INST_WIDTH + ADDR_WIDTH - 1)) begin
addr_reg <= {pico_reg[ADDR_WIDTH-2:0], sdi_i};
end else if (bit_count == (SPI_FRAME_WIDTH)) begin
addr_reg <= addr_reg + 1'b1;
end
end
assign addr_o = addr_reg;
// write data latch
reg [DATA_WIDTH-1:0] write_data;
always @(posedge sck_i or posedge cs_ni) begin
if (cs_ni) begin
write_data <= 'b0;
end else if ((write_flag == 1'b1)
&& (bit_count == (SPI_FRAME_WIDTH - 1))) begin
write_data <= {pico_reg[DATA_WIDTH-2:0], sdi_i};
end
end
// write enable strobe
reg write_en;
always @(posedge sck_i or posedge cs_ni) begin
if (cs_ni) begin
write_en <= 'b0;
end else if ((write_flag == 1'b1)
&& (bit_count == (SPI_FRAME_WIDTH - 1))) begin
write_en <= 1'b1;
end else begin
write_en <= 1'b0;
end
end
assign write_data_o = write_data;
assign write_en_o = write_en;
// read enable strobe
reg read_en;
always @(posedge sck_i or posedge cs_ni) begin
if (cs_ni) begin
read_en <= 'b0;
end else if ((read_flag == 1'b1)
&& ((bit_count == (INST_WIDTH + ADDR_WIDTH - 1)
|| bit_count == (SPI_FRAME_WIDTH)))) begin
read_en <= 1'b1;
end else begin
read_en <= 1'b0;
end
end
assign read_en_o = read_en;
// shift out read data
reg sdo_reg;
always @(negedge sck_i or posedge cs_ni) begin
if (cs_ni) begin
sdo_reg <= 'b0;
end else if ((read_flag == 1'b1)
&& (bit_count > (INST_WIDTH + ADDR_WIDTH - 1))
&& (bit_count < SPI_FRAME_WIDTH)) begin
sdo_reg <= read_data_i[(SPI_FRAME_WIDTH - 1) - bit_count];
end else begin
sdo_reg <= 1'b0;
end
end
assign sdo_o = sdo_reg;
endmodule
module register_map #(
parameter ADDR_WIDTH = 7,
parameter DATA_WIDTH = 8,
parameter NUM_CONFIG_REG = 12,
parameter NUM_STATUS_REG = 4
) (
input clk_i,
input rst_ni,
input [ADDR_WIDTH-1:0] addr_i,
input [DATA_WIDTH-1:0] write_data_i,
input write_en_i,
output [DATA_WIDTH-1:0] read_data_o,
input read_en_i,
output [DATA_WIDTH*NUM_CONFIG_REG-1:0] config_bus_o,
input [DATA_WIDTH*NUM_STATUS_REG-1:0] status_bus_i
);
// packed to unpacked conversion
reg [DATA_WIDTH-1:0] register_map_mem [NUM_CONFIG_REG-1:0];
genvar i;
generate
for (i = 0; i < NUM_CONFIG_REG; i = i + 1) begin
assign config_bus_o[DATA_WIDTH*(i+1)-1: DATA_WIDTH*i] = register_map_mem[i];
end
endgenerate
wire [DATA_WIDTH*(NUM_CONFIG_REG+NUM_STATUS_REG)-1:0] csr_read_bus;
assign csr_read_bus = {status_bus_i, config_bus_o};
wire [DATA_WIDTH-1:0] csr_read_arr [NUM_CONFIG_REG+NUM_STATUS_REG-1:0];
generate
for (i = 0; i < (NUM_CONFIG_REG + NUM_STATUS_REG); i = i + 1) begin
assign csr_read_arr[i] = csr_read_bus[DATA_WIDTH*(i+1)-1:DATA_WIDTH*i];
end
endgenerate
// synchronize to clk_i domain
// write_data should be stable when write_en is asserted
reg [3:0] write_en_shift_reg;
always @(posedge clk_i) begin
if (!rst_ni) begin
write_en_shift_reg <= 'b0;
end else begin
write_en_shift_reg <= {write_en_shift_reg[2:0], write_en_i};
end
end
wire write_en_rise_pulse;
assign write_en_rise_pulse = !write_en_shift_reg[3] && write_en_shift_reg[2];
reg [DATA_WIDTH-1:0] read_data_1, read_data_2;
always @(posedge clk_i) begin
if (!rst_ni) begin
read_data_1 <= 'b0;
read_data_2 <= 'b0;
end else if (read_en_i == 1) begin
if (addr_i < (NUM_CONFIG_REG + NUM_STATUS_REG)) begin
read_data_1 <= csr_read_arr[addr_i];
read_data_2 <= read_data_1;
end
else begin
read_data_2 <= 8'hff;
end
end
end
assign read_data_o = read_data_2;
// attempt to non-zero init. can't make it work with skywater-pdk
always @(posedge clk_i) begin
if (!rst_ni) begin
register_map_mem[0] <= 'b0;
end else if ((addr_i == 0) && (addr_i < NUM_CONFIG_REG)) begin
if (write_en_rise_pulse == 1) register_map_mem[0] <= write_data_i;
end
end
generate
for (i = 1; i < NUM_CONFIG_REG; i = i + 1) begin
always @(posedge clk_i) begin
if (!rst_ni) begin
register_map_mem[i] <= 'b0;
end else if ((addr_i == i) && (addr_i < NUM_CONFIG_REG)) begin
if (write_en_rise_pulse == 1) register_map_mem[i] <= write_data_i;
end
end
end
endgenerate
endmodule
module prbs15 (
input clk_i,
input rst_ni,
input [14:0] lfsr_init_i,
input load_prbs_i,
input freeze_i,
output prbs_o,
output [14:0] prbs_frame_o
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module prbs7 (
input clk_i,
input rst_ni,
input [6:0] lfsr_init_i,
input load_prbs_i,
input freeze_i,
output prbs_o,
output [6:0] prbs_frame_o
);
// referenced from, https://en.wikipedia.org/wiki/Pseudorandom_binary_sequence
// PRBS7 = x^7 + x^6 + 1
reg [6:0] lfsr_reg;
always @(posedge clk_i) begin
if (!rst_ni) begin
lfsr_reg <= 'b0;
end else if (load_prbs_i == 1) begin
lfsr_reg <= lfsr_init_i;
end else if (freeze_i == 1) begin
lfsr_reg <= lfsr_reg;
end else begin
lfsr_reg <= {lfsr_reg[5:0], lfsr_reg[6] ^ lfsr_reg[5]};
end
end
assign prbs_o = lfsr_reg[6];
assign prbs_frame_o = lfsr_reg;
endmodule
module i2s_tx #(
parameter AUDIO_DW = 8
) (
input sck_i,
input ws_i,
output sd_o,
input [AUDIO_DW-1:0] l_data_i,
input [AUDIO_DW-1:0] r_data_i,
output l_load_en_o,
output r_load_en_o
);
// referenced from, i2s spec. at https://www.nxp.com/docs/en/user-manual/UM11732.pdf
reg wsd[1:0];
always @(posedge sck_i) begin
wsd[0] <= ws_i;
wsd[1] <= wsd[0];
end
assign l_load_en_o = wsd[1] & !wsd[0];
assign r_load_en_o = !wsd[1] & wsd[0];
wire wsp;
assign wsp = wsd[0] ^ wsd[1];
reg [AUDIO_DW-1:0] sd_shift_reg;
wire [AUDIO_DW-1:0] l_data, r_data;
assign l_data = !wsd[0] ? l_data_i : {AUDIO_DW{1'b0}};
assign r_data = wsd[0] ? r_data_i : {AUDIO_DW{1'b0}};
always @(negedge sck_i) begin
if (wsp == 1) sd_shift_reg <= l_data | r_data;
else sd_shift_reg <= {sd_shift_reg[AUDIO_DW-2:0], 1'b0};
end
assign sd_o = sd_shift_reg[AUDIO_DW-1];
endmodule
module ks_string #(
parameter MAX_LENGTH = 256,
parameter DATA_WIDTH = 8,
parameter PRBS_WIDTH = 2,
parameter EXTN_BITS = 4,
parameter FRAC_BITS = 4
) (
input clk_i,
input rst_ni,
input freeze_i,
input round_en_i,
input pluck_i,
input toggle_pattern_prbs_ni,
input drum_string_ni,
input fine_tune_en_i,
input signed [DATA_WIDTH-1:0] fine_tune_C_i,
input dynamics_en_i,
input [DATA_WIDTH-1:0] dynamics_R_i,
input clip_noise_i,
input [PRBS_WIDTH-1:0] prbs_data_i,
input [DATA_WIDTH-1:0] period_i,
output [DATA_WIDTH-1:0] ks_sample_o
);
// referenced from, papers at https://doi.org/10.2307/3680062
// https://doi.org/10.2307/3680063
localparam EXTENDED_WIDTH = DATA_WIDTH+EXTN_BITS;
wire [DATA_WIDTH-1:0] clamped_period = period_i < MAX_LENGTH ? period_i : MAX_LENGTH;
wire [DATA_WIDTH-1:0] period_idx;
assign period_idx = clamped_period - 8'h01;
// pluck sync and detect
reg [3:0] pluck_shift_reg;
always @(posedge clk_i) begin
if (!rst_ni) begin
pluck_shift_reg <= 'b0;
end else begin
pluck_shift_reg <= {pluck_shift_reg[2:0], pluck_i};
end
end
wire pluck_rise_pulse;
assign pluck_rise_pulse = !pluck_shift_reg[3] && pluck_shift_reg[2];
// noise burst capture
reg signed [EXTENDED_WIDTH+FRAC_BITS-1:0] noise_reg;
reg [$clog2(MAX_LENGTH)-1:0] prbs_burst_counter;
reg prbs_burst_en;
reg [DATA_WIDTH-1:0] noise_sample_reg;
always @(posedge clk_i) begin
if (!rst_ni) noise_sample_reg <= 'b0;
else noise_sample_reg <= {noise_sample_reg[DATA_WIDTH-2:0], ^prbs_data_i};
end
// peak-peak clipped noise
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] clip_noise_sample;
assign clip_noise_sample = (^prbs_data_i) ? ({{(EXTN_BITS+1){1'b0}}, {((DATA_WIDTH+FRAC_BITS)-1){1'b1}}})
: ({{(EXTN_BITS+1){1'b1}}, {((DATA_WIDTH+FRAC_BITS)-1){1'b0}}});
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] noise_sample;
assign noise_sample = clip_noise_i ? clip_noise_sample : {{EXTN_BITS{noise_sample_reg[DATA_WIDTH-1]}}, noise_sample_reg, {FRAC_BITS{1'b0}}};
// noise dynamics filter
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] yd_0;
assign yd_0 = noise_sample_dyn;
reg signed [EXTENDED_WIDTH+FRAC_BITS-1:0] yd_1;
always @(posedge clk_i) begin
if (!rst_ni) yd_1 <= 'b0;
else yd_1 <= yd_0;
end
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] R_diff, noise_sample_dyn;
wire signed [DATA_WIDTH+EXTENDED_WIDTH+FRAC_BITS-1:0] scaled_R_diff;
assign R_diff = yd_1 - noise_sample;
assign scaled_R_diff = (dynamics_R_i * R_diff) >>> DATA_WIDTH;
assign noise_sample_dyn = noise_sample + scaled_R_diff;
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] noise_sample_w;
assign noise_sample_w = dynamics_en_i ? noise_sample_dyn : noise_sample;
reg toggle_bit;
always @(posedge clk_i) begin
if (!rst_ni) toggle_bit <= 'b0;
else toggle_bit <= ~toggle_bit;
end
wire [EXTENDED_WIDTH+FRAC_BITS-1:0] toggle_clamp;
assign toggle_clamp = {{EXTN_BITS{toggle_bit}}, {toggle_bit, {DATA_WIDTH-1{~toggle_bit}}}, {FRAC_BITS{~toggle_bit}}};
wire [EXTENDED_WIDTH+FRAC_BITS-1:0] noise_mux_sample;
assign noise_mux_sample = toggle_pattern_prbs_ni ? toggle_clamp : noise_sample_w;
always @(posedge clk_i) begin
if (!rst_ni) begin
prbs_burst_counter <= 'b0;
noise_reg <= 'b0;
prbs_burst_en <= 'b0;
end else begin
if (pluck_rise_pulse == 1'b1) begin
prbs_burst_counter <= 'b0;
noise_reg <= noise_mux_sample;
prbs_burst_en <= 'b1;
end else if (prbs_burst_en == 1'b1) begin
if (prbs_burst_counter < clamped_period) begin
prbs_burst_counter <= prbs_burst_counter + 1;
noise_reg <= noise_mux_sample;
prbs_burst_en <= 1'b1;
end else begin
prbs_burst_counter <= 'b0;
noise_reg <= 'b0;
prbs_burst_en <= 1'b0;
end
end else begin
prbs_burst_counter <= 'b0;
noise_reg <= 'b0;
prbs_burst_en <= 'b0;
end
end
end
// filter taps
wire signed [DATA_WIDTH-1:0] x_p;
assign x_p = string_reg[period_idx];
wire signed [DATA_WIDTH-1:0] x_p_1;
assign x_p_1 = delay_reg;
// Strong filter
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] strong_string_avg;
assign strong_string_avg = (((x_p <<< FRAC_BITS) + (x_p_1 <<< FRAC_BITS)) >>> 1);
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] strong_drum_avg;
assign strong_drum_avg = prbs_data_i[0] ? strong_string_avg : -strong_string_avg;
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] strong_filter_w;
assign strong_filter_w = drum_string_ni ? strong_drum_avg : strong_string_avg;
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] ks_sample_w;
assign ks_sample_w = noise_reg + strong_filter_w + (round_en_i ? (1 << (FRAC_BITS-1)) : 0);
reg signed [EXTENDED_WIDTH+FRAC_BITS-1:0] strong_filter_1;
always @(posedge clk_i) begin
if (!rst_ni) strong_filter_1 <= 'b0;
else strong_filter_1 <= strong_filter_w;
end
// Fine Tune
reg signed [EXTENDED_WIDTH+FRAC_BITS-1:0] y_1;
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] y_0, C_diff;
wire signed [DATA_WIDTH+EXTENDED_WIDTH+FRAC_BITS-1:0] scaled_C_diff;
assign C_diff = strong_filter_w - y_1;
assign scaled_C_diff = ((fine_tune_C_i * C_diff) >>> (DATA_WIDTH-1));
assign y_0 = strong_filter_1 + scaled_C_diff;
always @(posedge clk_i) begin
if (!rst_ni) y_1 <= 'b0;
else y_1 <= y_0;
end
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] ks_sample_ft_w;
assign ks_sample_ft_w = noise_reg + y_0 + (round_en_i ? (1 << (FRAC_BITS-1)) : 0);
wire [EXTENDED_WIDTH+FRAC_BITS-1:0] ks_loop_sample_w;
assign ks_loop_sample_w = fine_tune_en_i ? ks_sample_ft_w : ks_sample_w;
// overflow detect
wire ks_sign_bit;
assign ks_sign_bit = ks_loop_sample_w[EXTENDED_WIDTH+FRAC_BITS-1];
wire ks_data_msb;
assign ks_data_msb = ks_loop_sample_w[DATA_WIDTH+FRAC_BITS-1];
wire ks_ovf;
assign ks_ovf = ks_sign_bit ^ ks_data_msb;
wire [EXTENDED_WIDTH+FRAC_BITS-1:0] ks_clamped_val;
assign ks_clamped_val = {{EXTN_BITS{ks_sign_bit}}, {ks_sign_bit, {DATA_WIDTH-1{ks_data_msb}}}, {FRAC_BITS{ks_data_msb}}};
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] ks_loop_clamped_w;
assign ks_loop_clamped_w = ks_ovf ? ks_clamped_val : ks_loop_sample_w;
wire [DATA_WIDTH-1:0] ks_loop_sample_o;
assign ks_loop_sample_o = ks_loop_clamped_w[DATA_WIDTH+FRAC_BITS-1:FRAC_BITS];
assign ks_sample_o = ks_loop_sample_o;
// wavetable
reg [DATA_WIDTH-1:0] string_reg [MAX_LENGTH-1:0];
// reg [MAX_LENGTH-1:0] [DATA_WIDTH-1:0] string_reg;
always @(posedge clk_i) begin
if (!rst_ni) begin
string_reg[0] <= 'b0;
end else if (freeze_i) begin
string_reg[0] <= string_reg[0];
end else begin
string_reg[0] <= ks_loop_sample_o;
end
end
genvar i;
generate
for (i = 1; i < MAX_LENGTH; i = i + 1) begin
always @(posedge clk_i) begin
if (!rst_ni) begin
string_reg[i] <= 'b0;
end else if (freeze_i) begin
string_reg[i] <= string_reg[i];
end else begin
string_reg[i] <= string_reg[i-1];
end
end
end
endgenerate
reg [DATA_WIDTH-1:0] delay_reg;
always @(posedge clk_i) begin
if (!rst_ni) begin
delay_reg <= 'b0;
end else begin
delay_reg <= string_reg[period_idx];
end
end
endmodule
|
module prbs15 (
input clk_i,
input rst_ni,
input [14:0] lfsr_init_i,
input load_prbs_i,
input freeze_i,
output prbs_o,
output [14:0] prbs_frame_o
);
// referenced from, https://en.wikipedia.org/wiki/Pseudorandom_binary_sequence
// PRBS15 = x^15 + x^14 + 1
reg [14:0] lfsr_reg;
always @(posedge clk_i) begin
if (!rst_ni) begin
lfsr_reg <= 'b0;
end else if (load_prbs_i == 1) begin
lfsr_reg <= lfsr_init_i;
end else if (freeze_i == 1) begin
lfsr_reg <= lfsr_reg;
end else begin
lfsr_reg <= {lfsr_reg[13:0], lfsr_reg[14] ^ lfsr_reg[13]};
end
end
assign prbs_o = lfsr_reg[14];
assign prbs_frame_o = lfsr_reg;
endmodule
|
tt06-finale_0092
|
tt06-finale
|
pyamnihc-tt06_um_ks_pyamnihc
|
task_prbs7
|
tt_um_ks_pyamnihc
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
`default_nettype none
module tt_um_ks_pyamnihc (
input wire [7:0] ui_in, // Dedicated inputs - connected to the input switches
output wire [7:0] uo_out, // Dedicated outputs - connected to the 7 segment display
input wire [7:0] uio_in, // IOs: Bidirectional Input path
output wire [7:0] uio_out, // IOs: Bidirectional Output path
output wire [7:0] uio_oe, // IOs: Bidirectional Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// SPI param.
localparam SPI_INST_WIDTH = 1;
localparam SPI_ADDR_WIDTH = 7;
localparam SPI_DATA_WIDTH = 8;
localparam SPI_NUM_CONFIG_REG = 8;
localparam SPI_NUM_STATUS_REG = 2;
// I2S param.
localparam I2S_AUDIO_DW = 8;
// KS param.
localparam KS_MAX_LENGTH = 32;
localparam KS_DATA_WIDTH = 8;
localparam KS_PRBS_WIDTH = 2;
localparam KS_EXTN_BITS = 4;
localparam KS_FRAC_BITS = 4;
// clock dividers
reg [3:0] clk_rise_counter;
wire clk_r16;
always @(posedge clk) begin
if (!rst_n) clk_rise_counter <= 'b0;
else clk_rise_counter <= clk_rise_counter + 1;
end
assign clk_r16 = clk_rise_counter[3];
// SPI register map
wire sck_i;
assign sck_i = uio_in[0];
wire sdi_i;
assign sdi_i = uio_in[1];
wire sdo_o;
assign uio_out[2] = sdo_o;
wire cs_ni;
assign cs_ni = uio_in[3];
// i2s tx
wire i2s_sck_o;
assign uio_out[4] = i2s_sck_o;
wire i2s_ws_o;
assign uio_out[5] = i2s_ws_o;
wire i2s_sd_o;
assign uio_out[6] = i2s_sd_o;
assign uio_out[0] = 1'b0;
assign uio_out[1] = 1'b0;
assign uio_out[3] = 1'b0;
assign uio_oe = 8'b1111_0100;
assign uo_out[0] = rst_n;
assign uo_out[1] = rst_n_prbs_15;
assign uo_out[2] = rst_n_prbs_7;
assign uo_out[3] = rst_n_ks_string;
assign uo_out[4] = freeze_prbs_7;
assign uo_out[5] = freeze_prbs_15;
assign uo_out[6] = i2s_noise_sel;
assign uo_out[7] = pluck;
// prbs tx
assign uio_out[7] = prbs_15;
// register map, packed to unpacked
wire [SPI_DATA_WIDTH*SPI_NUM_CONFIG_REG-1:0] config_bus_o;
wire [SPI_DATA_WIDTH*SPI_NUM_STATUS_REG-1:0] status_bus_i;
wire [SPI_DATA_WIDTH-1:0] config_arr [SPI_NUM_CONFIG_REG-1:0];
genvar i;
generate
for (i = 0; i < SPI_NUM_CONFIG_REG; i = i + 1) begin
assign config_arr[i] = config_bus_o[SPI_DATA_WIDTH*(i+1)-1:SPI_DATA_WIDTH*i];
end
endgenerate
wire [SPI_DATA_WIDTH-1:0] status_arr [SPI_NUM_CONFIG_REG-1:0];
generate
for (i = 0; i < SPI_NUM_STATUS_REG; i = i + 1) begin
assign status_bus_i[SPI_DATA_WIDTH*(i+1)-1:SPI_DATA_WIDTH*i] = status_arr[i];
end
endgenerate
assign status_arr[0] = 8'hC0;
assign status_arr[1] = 8'h01;
// SPI peripheral
wire [SPI_ADDR_WIDTH-1:0] spi_addr;
wire [SPI_DATA_WIDTH-1:0] spi_write_data, spi_read_data;
wire spi_write_en, spi_read_en;
spi_slave_mem_interface #(.INST_WIDTH(SPI_INST_WIDTH),
.ADDR_WIDTH(SPI_ADDR_WIDTH),
.DATA_WIDTH(SPI_DATA_WIDTH)
) spi_slave_mem_interface_0 (
.sck_i(sck_i),
.sdi_i(sdi_i),
.sdo_o(sdo_o),
.cs_ni(cs_ni && rst_n),
.addr_o(spi_addr),
.write_data_o(spi_write_data),
.write_en_o(spi_write_en),
.read_data_i(spi_read_data),
.read_en_o(spi_read_en)
);
// Register map
register_map #( .ADDR_WIDTH(SPI_ADDR_WIDTH),
.DATA_WIDTH(SPI_DATA_WIDTH),
.NUM_CONFIG_REG(SPI_NUM_CONFIG_REG),
.NUM_STATUS_REG(SPI_NUM_STATUS_REG)
) register_map_0 (
.clk_i(clk),
.rst_ni(rst_n),
.addr_i(spi_addr),
.write_data_i(spi_write_data),
.write_en_i(spi_write_en),
.read_data_o(spi_read_data),
.read_en_i(spi_read_en),
.config_bus_o(config_bus_o),
.status_bus_i(status_bus_i)
);
// prbs15
wire rst_n_prbs_15;
assign rst_n_prbs_15 = ~config_arr[0][0] && ~ui_in[0];
wire [14:0] lfsr_init_15;
assign lfsr_init_15 = {~config_arr[2][6:0], ~config_arr[1][7:0]};
wire load_prbs_15;
assign load_prbs_15 = config_arr[2][7] || ui_in[1];
wire freeze_prbs_15;
assign freeze_prbs_15 = config_arr[0][4] || ui_in[2];
wire prbs_15;
wire [14:0] prbs_frame_15;
prbs15 prbs15_0 (
.clk_i(clk_r16),
.rst_ni(rst_n && rst_n_prbs_15),
.lfsr_init_i(lfsr_init_15),
.load_prbs_i(load_prbs_15),
.freeze_i(freeze_prbs_15),
.prbs_o(prbs_15),
.prbs_frame_o(prbs_frame_15)
);
// prbs7
wire rst_n_prbs_7;
assign rst_n_prbs_7 = ~config_arr[0][1] && ~ui_in[0];
wire [6:0] lfsr_init_7;
assign lfsr_init_7 = config_arr[3][6:0];
wire load_prbs_7;
assign load_prbs_7 = config_arr[3][7] || ui_in[1];
wire freeze_prbs_7;
assign freeze_prbs_7 = config_arr[0][5] || ui_in[3];
wire prbs_7;
wire [6:0] prbs_frame_7;
prbs7 prbs7_0 (
.clk_i(clk_r16),
.rst_ni(rst_n && rst_n_prbs_7),
.lfsr_init_i(lfsr_init_7),
.load_prbs_i(load_prbs_7),
.freeze_i(freeze_prbs_7),
.prbs_o(prbs_7),
.prbs_frame_o(prbs_frame_7)
);
// i2s sample select
wire i2s_noise_sel = config_arr[0][7] || ui_in[4];
wire [I2S_AUDIO_DW-1:0] l_data, r_data;
assign l_data = i2s_noise_sel ? prbs_frame_15[I2S_AUDIO_DW-1:0] : ks_sample;
assign r_data = i2s_noise_sel ? {1'b0, prbs_frame_7} : ks_sample;
reg [I2S_AUDIO_DW-1:0] l_data_reg, r_data_reg;
wire l_load_en, r_load_en;
always @(negedge i2s_sck_o) begin
if (l_load_en == 1) l_data_reg <= l_data;
else l_data_reg <= l_data_reg;
if (r_load_en == 1) r_data_reg <= r_data;
else r_data_reg <= r_data_reg;
end
// i2s tx
assign i2s_sck_o = ~clk;
assign i2s_ws_o = clk_r16;
i2s_tx #(
.AUDIO_DW(I2S_AUDIO_DW)
) i2s_tx_0 (
.sck_i(i2s_sck_o),
.ws_i(i2s_ws_o),
.sd_o(i2s_sd_o),
.l_data_i(l_data_reg),
.r_data_i(r_data_reg),
.l_load_en_o(l_load_en),
.r_load_en_o(r_load_en)
);
// ks string
wire ks_clk;
assign ks_clk = clk_r16;
wire rst_n_ks_string;
assign rst_n_ks_string = ~config_arr[0][2] && ~ui_in[5];
wire ks_freeze;
assign ks_freeze = config_arr[0][7];
wire pluck;
assign pluck = config_arr[4][0] || ui_in[6];
wire round_en;
assign round_en = config_arr[4][1];
wire toggle_pattern_prbs_n;
assign toggle_pattern_prbs_n = config_arr[4][2];
wire drum_string_n;
assign drum_string_n = config_arr[4][3];
wire fine_tune_en;
assign fine_tune_en = config_arr[4][4];
wire dynamics_en;
assign dynamics_en = config_arr[4][5];
wire [KS_DATA_WIDTH-1:0] fine_tune_C;
assign fine_tune_C = config_arr[5];
wire [KS_DATA_WIDTH-1:0] dynamics_R;
assign dynamics_R = config_arr[6];
wire clip_noise;
assign clip_noise = config_arr[4][6];
wire [KS_PRBS_WIDTH-1:0] prbs_data;
assign prbs_data = {prbs_15, prbs_7};
wire [KS_DATA_WIDTH-1:0] ks_period;
assign ks_period = ~config_arr[7];
wire [KS_DATA_WIDTH-1:0] ks_sample;
ks_string #(
.MAX_LENGTH(KS_MAX_LENGTH),
.DATA_WIDTH(KS_DATA_WIDTH),
.PRBS_WIDTH(KS_PRBS_WIDTH),
.EXTN_BITS(KS_EXTN_BITS),
.FRAC_BITS(KS_FRAC_BITS)
) ks_string_0 (
.clk_i(ks_clk),
.rst_ni(rst_n && rst_n_ks_string),
.freeze_i(ks_freeze),
.pluck_i(pluck),
.round_en_i(round_en),
.toggle_pattern_prbs_ni(toggle_pattern_prbs_n),
.drum_string_ni(drum_string_n),
.fine_tune_en_i(fine_tune_en),
.fine_tune_C_i(fine_tune_C),
.dynamics_en_i(dynamics_en),
.dynamics_R_i(dynamics_R),
.clip_noise_i(clip_noise),
.prbs_data_i(prbs_data),
.period_i(ks_period),
.ks_sample_o(ks_sample)
);
endmodule
module spi_slave_mem_interface #(
parameter INST_WIDTH = 1,
parameter ADDR_WIDTH = 7,
parameter DATA_WIDTH = 8
) (
input sck_i,
input sdi_i,
output sdo_o,
input cs_ni,
output [ADDR_WIDTH-1:0] addr_o,
output [DATA_WIDTH-1:0] write_data_o,
output write_en_o,
input [DATA_WIDTH-1:0] read_data_i,
output read_en_o
);
// CPOL: 0, CPHA: 0
localparam SPI_FRAME_WIDTH = INST_WIDTH + ADDR_WIDTH + DATA_WIDTH;
localparam BIT_COUNT_WIDTH = $clog2(SPI_FRAME_WIDTH) + 1;
// shift register buffer
reg [SPI_FRAME_WIDTH-1:0] pico_reg;
always @(posedge sck_i or posedge cs_ni) begin
if (cs_ni) pico_reg <= 'b0;
else pico_reg <= {pico_reg[SPI_FRAME_WIDTH-2:0], sdi_i};
end
// keeps track of current bit position
reg [BIT_COUNT_WIDTH-1:0] bit_count;
always @(posedge sck_i or posedge cs_ni) begin
if (cs_ni) begin
bit_count <= 'b0;
end else if ((read_flag || write_flag) &&
(bit_count == (SPI_FRAME_WIDTH))) begin
bit_count <= INST_WIDTH+ADDR_WIDTH+1;
end else begin
bit_count <= bit_count + 1'b1;
end
end
// instruction decode
reg read_flag, write_flag;
always @(posedge sck_i or posedge cs_ni) begin
if (cs_ni) begin
read_flag <= 'b0;
write_flag <= 'b0;
end else if (bit_count < INST_WIDTH) begin
read_flag <= sdi_i;
write_flag <= !sdi_i;
end
end
// address decode and latch
reg [ADDR_WIDTH-1:0] addr_reg;
always @(posedge sck_i or posedge cs_ni) begin
if (cs_ni) begin
addr_reg <= 'b0;
end else if (bit_count == (INST_WIDTH + ADDR_WIDTH - 1)) begin
addr_reg <= {pico_reg[ADDR_WIDTH-2:0], sdi_i};
end else if (bit_count == (SPI_FRAME_WIDTH)) begin
addr_reg <= addr_reg + 1'b1;
end
end
assign addr_o = addr_reg;
// write data latch
reg [DATA_WIDTH-1:0] write_data;
always @(posedge sck_i or posedge cs_ni) begin
if (cs_ni) begin
write_data <= 'b0;
end else if ((write_flag == 1'b1)
&& (bit_count == (SPI_FRAME_WIDTH - 1))) begin
write_data <= {pico_reg[DATA_WIDTH-2:0], sdi_i};
end
end
// write enable strobe
reg write_en;
always @(posedge sck_i or posedge cs_ni) begin
if (cs_ni) begin
write_en <= 'b0;
end else if ((write_flag == 1'b1)
&& (bit_count == (SPI_FRAME_WIDTH - 1))) begin
write_en <= 1'b1;
end else begin
write_en <= 1'b0;
end
end
assign write_data_o = write_data;
assign write_en_o = write_en;
// read enable strobe
reg read_en;
always @(posedge sck_i or posedge cs_ni) begin
if (cs_ni) begin
read_en <= 'b0;
end else if ((read_flag == 1'b1)
&& ((bit_count == (INST_WIDTH + ADDR_WIDTH - 1)
|| bit_count == (SPI_FRAME_WIDTH)))) begin
read_en <= 1'b1;
end else begin
read_en <= 1'b0;
end
end
assign read_en_o = read_en;
// shift out read data
reg sdo_reg;
always @(negedge sck_i or posedge cs_ni) begin
if (cs_ni) begin
sdo_reg <= 'b0;
end else if ((read_flag == 1'b1)
&& (bit_count > (INST_WIDTH + ADDR_WIDTH - 1))
&& (bit_count < SPI_FRAME_WIDTH)) begin
sdo_reg <= read_data_i[(SPI_FRAME_WIDTH - 1) - bit_count];
end else begin
sdo_reg <= 1'b0;
end
end
assign sdo_o = sdo_reg;
endmodule
module register_map #(
parameter ADDR_WIDTH = 7,
parameter DATA_WIDTH = 8,
parameter NUM_CONFIG_REG = 12,
parameter NUM_STATUS_REG = 4
) (
input clk_i,
input rst_ni,
input [ADDR_WIDTH-1:0] addr_i,
input [DATA_WIDTH-1:0] write_data_i,
input write_en_i,
output [DATA_WIDTH-1:0] read_data_o,
input read_en_i,
output [DATA_WIDTH*NUM_CONFIG_REG-1:0] config_bus_o,
input [DATA_WIDTH*NUM_STATUS_REG-1:0] status_bus_i
);
// packed to unpacked conversion
reg [DATA_WIDTH-1:0] register_map_mem [NUM_CONFIG_REG-1:0];
genvar i;
generate
for (i = 0; i < NUM_CONFIG_REG; i = i + 1) begin
assign config_bus_o[DATA_WIDTH*(i+1)-1: DATA_WIDTH*i] = register_map_mem[i];
end
endgenerate
wire [DATA_WIDTH*(NUM_CONFIG_REG+NUM_STATUS_REG)-1:0] csr_read_bus;
assign csr_read_bus = {status_bus_i, config_bus_o};
wire [DATA_WIDTH-1:0] csr_read_arr [NUM_CONFIG_REG+NUM_STATUS_REG-1:0];
generate
for (i = 0; i < (NUM_CONFIG_REG + NUM_STATUS_REG); i = i + 1) begin
assign csr_read_arr[i] = csr_read_bus[DATA_WIDTH*(i+1)-1:DATA_WIDTH*i];
end
endgenerate
// synchronize to clk_i domain
// write_data should be stable when write_en is asserted
reg [3:0] write_en_shift_reg;
always @(posedge clk_i) begin
if (!rst_ni) begin
write_en_shift_reg <= 'b0;
end else begin
write_en_shift_reg <= {write_en_shift_reg[2:0], write_en_i};
end
end
wire write_en_rise_pulse;
assign write_en_rise_pulse = !write_en_shift_reg[3] && write_en_shift_reg[2];
reg [DATA_WIDTH-1:0] read_data_1, read_data_2;
always @(posedge clk_i) begin
if (!rst_ni) begin
read_data_1 <= 'b0;
read_data_2 <= 'b0;
end else if (read_en_i == 1) begin
if (addr_i < (NUM_CONFIG_REG + NUM_STATUS_REG)) begin
read_data_1 <= csr_read_arr[addr_i];
read_data_2 <= read_data_1;
end
else begin
read_data_2 <= 8'hff;
end
end
end
assign read_data_o = read_data_2;
// attempt to non-zero init. can't make it work with skywater-pdk
always @(posedge clk_i) begin
if (!rst_ni) begin
register_map_mem[0] <= 'b0;
end else if ((addr_i == 0) && (addr_i < NUM_CONFIG_REG)) begin
if (write_en_rise_pulse == 1) register_map_mem[0] <= write_data_i;
end
end
generate
for (i = 1; i < NUM_CONFIG_REG; i = i + 1) begin
always @(posedge clk_i) begin
if (!rst_ni) begin
register_map_mem[i] <= 'b0;
end else if ((addr_i == i) && (addr_i < NUM_CONFIG_REG)) begin
if (write_en_rise_pulse == 1) register_map_mem[i] <= write_data_i;
end
end
end
endgenerate
endmodule
module prbs15 (
input clk_i,
input rst_ni,
input [14:0] lfsr_init_i,
input load_prbs_i,
input freeze_i,
output prbs_o,
output [14:0] prbs_frame_o
);
// referenced from, https://en.wikipedia.org/wiki/Pseudorandom_binary_sequence
// PRBS15 = x^15 + x^14 + 1
reg [14:0] lfsr_reg;
always @(posedge clk_i) begin
if (!rst_ni) begin
lfsr_reg <= 'b0;
end else if (load_prbs_i == 1) begin
lfsr_reg <= lfsr_init_i;
end else if (freeze_i == 1) begin
lfsr_reg <= lfsr_reg;
end else begin
lfsr_reg <= {lfsr_reg[13:0], lfsr_reg[14] ^ lfsr_reg[13]};
end
end
assign prbs_o = lfsr_reg[14];
assign prbs_frame_o = lfsr_reg;
endmodule
module prbs7 (
input clk_i,
input rst_ni,
input [6:0] lfsr_init_i,
input load_prbs_i,
input freeze_i,
output prbs_o,
output [6:0] prbs_frame_o
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module i2s_tx #(
parameter AUDIO_DW = 8
) (
input sck_i,
input ws_i,
output sd_o,
input [AUDIO_DW-1:0] l_data_i,
input [AUDIO_DW-1:0] r_data_i,
output l_load_en_o,
output r_load_en_o
);
// referenced from, i2s spec. at https://www.nxp.com/docs/en/user-manual/UM11732.pdf
reg wsd[1:0];
always @(posedge sck_i) begin
wsd[0] <= ws_i;
wsd[1] <= wsd[0];
end
assign l_load_en_o = wsd[1] & !wsd[0];
assign r_load_en_o = !wsd[1] & wsd[0];
wire wsp;
assign wsp = wsd[0] ^ wsd[1];
reg [AUDIO_DW-1:0] sd_shift_reg;
wire [AUDIO_DW-1:0] l_data, r_data;
assign l_data = !wsd[0] ? l_data_i : {AUDIO_DW{1'b0}};
assign r_data = wsd[0] ? r_data_i : {AUDIO_DW{1'b0}};
always @(negedge sck_i) begin
if (wsp == 1) sd_shift_reg <= l_data | r_data;
else sd_shift_reg <= {sd_shift_reg[AUDIO_DW-2:0], 1'b0};
end
assign sd_o = sd_shift_reg[AUDIO_DW-1];
endmodule
module ks_string #(
parameter MAX_LENGTH = 256,
parameter DATA_WIDTH = 8,
parameter PRBS_WIDTH = 2,
parameter EXTN_BITS = 4,
parameter FRAC_BITS = 4
) (
input clk_i,
input rst_ni,
input freeze_i,
input round_en_i,
input pluck_i,
input toggle_pattern_prbs_ni,
input drum_string_ni,
input fine_tune_en_i,
input signed [DATA_WIDTH-1:0] fine_tune_C_i,
input dynamics_en_i,
input [DATA_WIDTH-1:0] dynamics_R_i,
input clip_noise_i,
input [PRBS_WIDTH-1:0] prbs_data_i,
input [DATA_WIDTH-1:0] period_i,
output [DATA_WIDTH-1:0] ks_sample_o
);
// referenced from, papers at https://doi.org/10.2307/3680062
// https://doi.org/10.2307/3680063
localparam EXTENDED_WIDTH = DATA_WIDTH+EXTN_BITS;
wire [DATA_WIDTH-1:0] clamped_period = period_i < MAX_LENGTH ? period_i : MAX_LENGTH;
wire [DATA_WIDTH-1:0] period_idx;
assign period_idx = clamped_period - 8'h01;
// pluck sync and detect
reg [3:0] pluck_shift_reg;
always @(posedge clk_i) begin
if (!rst_ni) begin
pluck_shift_reg <= 'b0;
end else begin
pluck_shift_reg <= {pluck_shift_reg[2:0], pluck_i};
end
end
wire pluck_rise_pulse;
assign pluck_rise_pulse = !pluck_shift_reg[3] && pluck_shift_reg[2];
// noise burst capture
reg signed [EXTENDED_WIDTH+FRAC_BITS-1:0] noise_reg;
reg [$clog2(MAX_LENGTH)-1:0] prbs_burst_counter;
reg prbs_burst_en;
reg [DATA_WIDTH-1:0] noise_sample_reg;
always @(posedge clk_i) begin
if (!rst_ni) noise_sample_reg <= 'b0;
else noise_sample_reg <= {noise_sample_reg[DATA_WIDTH-2:0], ^prbs_data_i};
end
// peak-peak clipped noise
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] clip_noise_sample;
assign clip_noise_sample = (^prbs_data_i) ? ({{(EXTN_BITS+1){1'b0}}, {((DATA_WIDTH+FRAC_BITS)-1){1'b1}}})
: ({{(EXTN_BITS+1){1'b1}}, {((DATA_WIDTH+FRAC_BITS)-1){1'b0}}});
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] noise_sample;
assign noise_sample = clip_noise_i ? clip_noise_sample : {{EXTN_BITS{noise_sample_reg[DATA_WIDTH-1]}}, noise_sample_reg, {FRAC_BITS{1'b0}}};
// noise dynamics filter
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] yd_0;
assign yd_0 = noise_sample_dyn;
reg signed [EXTENDED_WIDTH+FRAC_BITS-1:0] yd_1;
always @(posedge clk_i) begin
if (!rst_ni) yd_1 <= 'b0;
else yd_1 <= yd_0;
end
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] R_diff, noise_sample_dyn;
wire signed [DATA_WIDTH+EXTENDED_WIDTH+FRAC_BITS-1:0] scaled_R_diff;
assign R_diff = yd_1 - noise_sample;
assign scaled_R_diff = (dynamics_R_i * R_diff) >>> DATA_WIDTH;
assign noise_sample_dyn = noise_sample + scaled_R_diff;
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] noise_sample_w;
assign noise_sample_w = dynamics_en_i ? noise_sample_dyn : noise_sample;
reg toggle_bit;
always @(posedge clk_i) begin
if (!rst_ni) toggle_bit <= 'b0;
else toggle_bit <= ~toggle_bit;
end
wire [EXTENDED_WIDTH+FRAC_BITS-1:0] toggle_clamp;
assign toggle_clamp = {{EXTN_BITS{toggle_bit}}, {toggle_bit, {DATA_WIDTH-1{~toggle_bit}}}, {FRAC_BITS{~toggle_bit}}};
wire [EXTENDED_WIDTH+FRAC_BITS-1:0] noise_mux_sample;
assign noise_mux_sample = toggle_pattern_prbs_ni ? toggle_clamp : noise_sample_w;
always @(posedge clk_i) begin
if (!rst_ni) begin
prbs_burst_counter <= 'b0;
noise_reg <= 'b0;
prbs_burst_en <= 'b0;
end else begin
if (pluck_rise_pulse == 1'b1) begin
prbs_burst_counter <= 'b0;
noise_reg <= noise_mux_sample;
prbs_burst_en <= 'b1;
end else if (prbs_burst_en == 1'b1) begin
if (prbs_burst_counter < clamped_period) begin
prbs_burst_counter <= prbs_burst_counter + 1;
noise_reg <= noise_mux_sample;
prbs_burst_en <= 1'b1;
end else begin
prbs_burst_counter <= 'b0;
noise_reg <= 'b0;
prbs_burst_en <= 1'b0;
end
end else begin
prbs_burst_counter <= 'b0;
noise_reg <= 'b0;
prbs_burst_en <= 'b0;
end
end
end
// filter taps
wire signed [DATA_WIDTH-1:0] x_p;
assign x_p = string_reg[period_idx];
wire signed [DATA_WIDTH-1:0] x_p_1;
assign x_p_1 = delay_reg;
// Strong filter
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] strong_string_avg;
assign strong_string_avg = (((x_p <<< FRAC_BITS) + (x_p_1 <<< FRAC_BITS)) >>> 1);
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] strong_drum_avg;
assign strong_drum_avg = prbs_data_i[0] ? strong_string_avg : -strong_string_avg;
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] strong_filter_w;
assign strong_filter_w = drum_string_ni ? strong_drum_avg : strong_string_avg;
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] ks_sample_w;
assign ks_sample_w = noise_reg + strong_filter_w + (round_en_i ? (1 << (FRAC_BITS-1)) : 0);
reg signed [EXTENDED_WIDTH+FRAC_BITS-1:0] strong_filter_1;
always @(posedge clk_i) begin
if (!rst_ni) strong_filter_1 <= 'b0;
else strong_filter_1 <= strong_filter_w;
end
// Fine Tune
reg signed [EXTENDED_WIDTH+FRAC_BITS-1:0] y_1;
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] y_0, C_diff;
wire signed [DATA_WIDTH+EXTENDED_WIDTH+FRAC_BITS-1:0] scaled_C_diff;
assign C_diff = strong_filter_w - y_1;
assign scaled_C_diff = ((fine_tune_C_i * C_diff) >>> (DATA_WIDTH-1));
assign y_0 = strong_filter_1 + scaled_C_diff;
always @(posedge clk_i) begin
if (!rst_ni) y_1 <= 'b0;
else y_1 <= y_0;
end
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] ks_sample_ft_w;
assign ks_sample_ft_w = noise_reg + y_0 + (round_en_i ? (1 << (FRAC_BITS-1)) : 0);
wire [EXTENDED_WIDTH+FRAC_BITS-1:0] ks_loop_sample_w;
assign ks_loop_sample_w = fine_tune_en_i ? ks_sample_ft_w : ks_sample_w;
// overflow detect
wire ks_sign_bit;
assign ks_sign_bit = ks_loop_sample_w[EXTENDED_WIDTH+FRAC_BITS-1];
wire ks_data_msb;
assign ks_data_msb = ks_loop_sample_w[DATA_WIDTH+FRAC_BITS-1];
wire ks_ovf;
assign ks_ovf = ks_sign_bit ^ ks_data_msb;
wire [EXTENDED_WIDTH+FRAC_BITS-1:0] ks_clamped_val;
assign ks_clamped_val = {{EXTN_BITS{ks_sign_bit}}, {ks_sign_bit, {DATA_WIDTH-1{ks_data_msb}}}, {FRAC_BITS{ks_data_msb}}};
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] ks_loop_clamped_w;
assign ks_loop_clamped_w = ks_ovf ? ks_clamped_val : ks_loop_sample_w;
wire [DATA_WIDTH-1:0] ks_loop_sample_o;
assign ks_loop_sample_o = ks_loop_clamped_w[DATA_WIDTH+FRAC_BITS-1:FRAC_BITS];
assign ks_sample_o = ks_loop_sample_o;
// wavetable
reg [DATA_WIDTH-1:0] string_reg [MAX_LENGTH-1:0];
// reg [MAX_LENGTH-1:0] [DATA_WIDTH-1:0] string_reg;
always @(posedge clk_i) begin
if (!rst_ni) begin
string_reg[0] <= 'b0;
end else if (freeze_i) begin
string_reg[0] <= string_reg[0];
end else begin
string_reg[0] <= ks_loop_sample_o;
end
end
genvar i;
generate
for (i = 1; i < MAX_LENGTH; i = i + 1) begin
always @(posedge clk_i) begin
if (!rst_ni) begin
string_reg[i] <= 'b0;
end else if (freeze_i) begin
string_reg[i] <= string_reg[i];
end else begin
string_reg[i] <= string_reg[i-1];
end
end
end
endgenerate
reg [DATA_WIDTH-1:0] delay_reg;
always @(posedge clk_i) begin
if (!rst_ni) begin
delay_reg <= 'b0;
end else begin
delay_reg <= string_reg[period_idx];
end
end
endmodule
|
module prbs7 (
input clk_i,
input rst_ni,
input [6:0] lfsr_init_i,
input load_prbs_i,
input freeze_i,
output prbs_o,
output [6:0] prbs_frame_o
);
// referenced from, https://en.wikipedia.org/wiki/Pseudorandom_binary_sequence
// PRBS7 = x^7 + x^6 + 1
reg [6:0] lfsr_reg;
always @(posedge clk_i) begin
if (!rst_ni) begin
lfsr_reg <= 'b0;
end else if (load_prbs_i == 1) begin
lfsr_reg <= lfsr_init_i;
end else if (freeze_i == 1) begin
lfsr_reg <= lfsr_reg;
end else begin
lfsr_reg <= {lfsr_reg[5:0], lfsr_reg[6] ^ lfsr_reg[5]};
end
end
assign prbs_o = lfsr_reg[6];
assign prbs_frame_o = lfsr_reg;
endmodule
|
tt06-finale_0093
|
tt06-finale
|
pyamnihc-tt06_um_ks_pyamnihc
|
task_tt_um_ks_pyamnihc
|
tt_um_ks_pyamnihc
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
`default_nettype none
module tt_um_ks_pyamnihc (
input wire [7:0] ui_in, // Dedicated inputs - connected to the input switches
output wire [7:0] uo_out, // Dedicated outputs - connected to the 7 segment display
input wire [7:0] uio_in, // IOs: Bidirectional Input path
output wire [7:0] uio_out, // IOs: Bidirectional Output path
output wire [7:0] uio_oe, // IOs: Bidirectional Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module spi_slave_mem_interface #(
parameter INST_WIDTH = 1,
parameter ADDR_WIDTH = 7,
parameter DATA_WIDTH = 8
) (
input sck_i,
input sdi_i,
output sdo_o,
input cs_ni,
output [ADDR_WIDTH-1:0] addr_o,
output [DATA_WIDTH-1:0] write_data_o,
output write_en_o,
input [DATA_WIDTH-1:0] read_data_i,
output read_en_o
);
// CPOL: 0, CPHA: 0
localparam SPI_FRAME_WIDTH = INST_WIDTH + ADDR_WIDTH + DATA_WIDTH;
localparam BIT_COUNT_WIDTH = $clog2(SPI_FRAME_WIDTH) + 1;
// shift register buffer
reg [SPI_FRAME_WIDTH-1:0] pico_reg;
always @(posedge sck_i or posedge cs_ni) begin
if (cs_ni) pico_reg <= 'b0;
else pico_reg <= {pico_reg[SPI_FRAME_WIDTH-2:0], sdi_i};
end
// keeps track of current bit position
reg [BIT_COUNT_WIDTH-1:0] bit_count;
always @(posedge sck_i or posedge cs_ni) begin
if (cs_ni) begin
bit_count <= 'b0;
end else if ((read_flag || write_flag) &&
(bit_count == (SPI_FRAME_WIDTH))) begin
bit_count <= INST_WIDTH+ADDR_WIDTH+1;
end else begin
bit_count <= bit_count + 1'b1;
end
end
// instruction decode
reg read_flag, write_flag;
always @(posedge sck_i or posedge cs_ni) begin
if (cs_ni) begin
read_flag <= 'b0;
write_flag <= 'b0;
end else if (bit_count < INST_WIDTH) begin
read_flag <= sdi_i;
write_flag <= !sdi_i;
end
end
// address decode and latch
reg [ADDR_WIDTH-1:0] addr_reg;
always @(posedge sck_i or posedge cs_ni) begin
if (cs_ni) begin
addr_reg <= 'b0;
end else if (bit_count == (INST_WIDTH + ADDR_WIDTH - 1)) begin
addr_reg <= {pico_reg[ADDR_WIDTH-2:0], sdi_i};
end else if (bit_count == (SPI_FRAME_WIDTH)) begin
addr_reg <= addr_reg + 1'b1;
end
end
assign addr_o = addr_reg;
// write data latch
reg [DATA_WIDTH-1:0] write_data;
always @(posedge sck_i or posedge cs_ni) begin
if (cs_ni) begin
write_data <= 'b0;
end else if ((write_flag == 1'b1)
&& (bit_count == (SPI_FRAME_WIDTH - 1))) begin
write_data <= {pico_reg[DATA_WIDTH-2:0], sdi_i};
end
end
// write enable strobe
reg write_en;
always @(posedge sck_i or posedge cs_ni) begin
if (cs_ni) begin
write_en <= 'b0;
end else if ((write_flag == 1'b1)
&& (bit_count == (SPI_FRAME_WIDTH - 1))) begin
write_en <= 1'b1;
end else begin
write_en <= 1'b0;
end
end
assign write_data_o = write_data;
assign write_en_o = write_en;
// read enable strobe
reg read_en;
always @(posedge sck_i or posedge cs_ni) begin
if (cs_ni) begin
read_en <= 'b0;
end else if ((read_flag == 1'b1)
&& ((bit_count == (INST_WIDTH + ADDR_WIDTH - 1)
|| bit_count == (SPI_FRAME_WIDTH)))) begin
read_en <= 1'b1;
end else begin
read_en <= 1'b0;
end
end
assign read_en_o = read_en;
// shift out read data
reg sdo_reg;
always @(negedge sck_i or posedge cs_ni) begin
if (cs_ni) begin
sdo_reg <= 'b0;
end else if ((read_flag == 1'b1)
&& (bit_count > (INST_WIDTH + ADDR_WIDTH - 1))
&& (bit_count < SPI_FRAME_WIDTH)) begin
sdo_reg <= read_data_i[(SPI_FRAME_WIDTH - 1) - bit_count];
end else begin
sdo_reg <= 1'b0;
end
end
assign sdo_o = sdo_reg;
endmodule
module register_map #(
parameter ADDR_WIDTH = 7,
parameter DATA_WIDTH = 8,
parameter NUM_CONFIG_REG = 12,
parameter NUM_STATUS_REG = 4
) (
input clk_i,
input rst_ni,
input [ADDR_WIDTH-1:0] addr_i,
input [DATA_WIDTH-1:0] write_data_i,
input write_en_i,
output [DATA_WIDTH-1:0] read_data_o,
input read_en_i,
output [DATA_WIDTH*NUM_CONFIG_REG-1:0] config_bus_o,
input [DATA_WIDTH*NUM_STATUS_REG-1:0] status_bus_i
);
// packed to unpacked conversion
reg [DATA_WIDTH-1:0] register_map_mem [NUM_CONFIG_REG-1:0];
genvar i;
generate
for (i = 0; i < NUM_CONFIG_REG; i = i + 1) begin
assign config_bus_o[DATA_WIDTH*(i+1)-1: DATA_WIDTH*i] = register_map_mem[i];
end
endgenerate
wire [DATA_WIDTH*(NUM_CONFIG_REG+NUM_STATUS_REG)-1:0] csr_read_bus;
assign csr_read_bus = {status_bus_i, config_bus_o};
wire [DATA_WIDTH-1:0] csr_read_arr [NUM_CONFIG_REG+NUM_STATUS_REG-1:0];
generate
for (i = 0; i < (NUM_CONFIG_REG + NUM_STATUS_REG); i = i + 1) begin
assign csr_read_arr[i] = csr_read_bus[DATA_WIDTH*(i+1)-1:DATA_WIDTH*i];
end
endgenerate
// synchronize to clk_i domain
// write_data should be stable when write_en is asserted
reg [3:0] write_en_shift_reg;
always @(posedge clk_i) begin
if (!rst_ni) begin
write_en_shift_reg <= 'b0;
end else begin
write_en_shift_reg <= {write_en_shift_reg[2:0], write_en_i};
end
end
wire write_en_rise_pulse;
assign write_en_rise_pulse = !write_en_shift_reg[3] && write_en_shift_reg[2];
reg [DATA_WIDTH-1:0] read_data_1, read_data_2;
always @(posedge clk_i) begin
if (!rst_ni) begin
read_data_1 <= 'b0;
read_data_2 <= 'b0;
end else if (read_en_i == 1) begin
if (addr_i < (NUM_CONFIG_REG + NUM_STATUS_REG)) begin
read_data_1 <= csr_read_arr[addr_i];
read_data_2 <= read_data_1;
end
else begin
read_data_2 <= 8'hff;
end
end
end
assign read_data_o = read_data_2;
// attempt to non-zero init. can't make it work with skywater-pdk
always @(posedge clk_i) begin
if (!rst_ni) begin
register_map_mem[0] <= 'b0;
end else if ((addr_i == 0) && (addr_i < NUM_CONFIG_REG)) begin
if (write_en_rise_pulse == 1) register_map_mem[0] <= write_data_i;
end
end
generate
for (i = 1; i < NUM_CONFIG_REG; i = i + 1) begin
always @(posedge clk_i) begin
if (!rst_ni) begin
register_map_mem[i] <= 'b0;
end else if ((addr_i == i) && (addr_i < NUM_CONFIG_REG)) begin
if (write_en_rise_pulse == 1) register_map_mem[i] <= write_data_i;
end
end
end
endgenerate
endmodule
module prbs15 (
input clk_i,
input rst_ni,
input [14:0] lfsr_init_i,
input load_prbs_i,
input freeze_i,
output prbs_o,
output [14:0] prbs_frame_o
);
// referenced from, https://en.wikipedia.org/wiki/Pseudorandom_binary_sequence
// PRBS15 = x^15 + x^14 + 1
reg [14:0] lfsr_reg;
always @(posedge clk_i) begin
if (!rst_ni) begin
lfsr_reg <= 'b0;
end else if (load_prbs_i == 1) begin
lfsr_reg <= lfsr_init_i;
end else if (freeze_i == 1) begin
lfsr_reg <= lfsr_reg;
end else begin
lfsr_reg <= {lfsr_reg[13:0], lfsr_reg[14] ^ lfsr_reg[13]};
end
end
assign prbs_o = lfsr_reg[14];
assign prbs_frame_o = lfsr_reg;
endmodule
module prbs7 (
input clk_i,
input rst_ni,
input [6:0] lfsr_init_i,
input load_prbs_i,
input freeze_i,
output prbs_o,
output [6:0] prbs_frame_o
);
// referenced from, https://en.wikipedia.org/wiki/Pseudorandom_binary_sequence
// PRBS7 = x^7 + x^6 + 1
reg [6:0] lfsr_reg;
always @(posedge clk_i) begin
if (!rst_ni) begin
lfsr_reg <= 'b0;
end else if (load_prbs_i == 1) begin
lfsr_reg <= lfsr_init_i;
end else if (freeze_i == 1) begin
lfsr_reg <= lfsr_reg;
end else begin
lfsr_reg <= {lfsr_reg[5:0], lfsr_reg[6] ^ lfsr_reg[5]};
end
end
assign prbs_o = lfsr_reg[6];
assign prbs_frame_o = lfsr_reg;
endmodule
module i2s_tx #(
parameter AUDIO_DW = 8
) (
input sck_i,
input ws_i,
output sd_o,
input [AUDIO_DW-1:0] l_data_i,
input [AUDIO_DW-1:0] r_data_i,
output l_load_en_o,
output r_load_en_o
);
// referenced from, i2s spec. at https://www.nxp.com/docs/en/user-manual/UM11732.pdf
reg wsd[1:0];
always @(posedge sck_i) begin
wsd[0] <= ws_i;
wsd[1] <= wsd[0];
end
assign l_load_en_o = wsd[1] & !wsd[0];
assign r_load_en_o = !wsd[1] & wsd[0];
wire wsp;
assign wsp = wsd[0] ^ wsd[1];
reg [AUDIO_DW-1:0] sd_shift_reg;
wire [AUDIO_DW-1:0] l_data, r_data;
assign l_data = !wsd[0] ? l_data_i : {AUDIO_DW{1'b0}};
assign r_data = wsd[0] ? r_data_i : {AUDIO_DW{1'b0}};
always @(negedge sck_i) begin
if (wsp == 1) sd_shift_reg <= l_data | r_data;
else sd_shift_reg <= {sd_shift_reg[AUDIO_DW-2:0], 1'b0};
end
assign sd_o = sd_shift_reg[AUDIO_DW-1];
endmodule
module ks_string #(
parameter MAX_LENGTH = 256,
parameter DATA_WIDTH = 8,
parameter PRBS_WIDTH = 2,
parameter EXTN_BITS = 4,
parameter FRAC_BITS = 4
) (
input clk_i,
input rst_ni,
input freeze_i,
input round_en_i,
input pluck_i,
input toggle_pattern_prbs_ni,
input drum_string_ni,
input fine_tune_en_i,
input signed [DATA_WIDTH-1:0] fine_tune_C_i,
input dynamics_en_i,
input [DATA_WIDTH-1:0] dynamics_R_i,
input clip_noise_i,
input [PRBS_WIDTH-1:0] prbs_data_i,
input [DATA_WIDTH-1:0] period_i,
output [DATA_WIDTH-1:0] ks_sample_o
);
// referenced from, papers at https://doi.org/10.2307/3680062
// https://doi.org/10.2307/3680063
localparam EXTENDED_WIDTH = DATA_WIDTH+EXTN_BITS;
wire [DATA_WIDTH-1:0] clamped_period = period_i < MAX_LENGTH ? period_i : MAX_LENGTH;
wire [DATA_WIDTH-1:0] period_idx;
assign period_idx = clamped_period - 8'h01;
// pluck sync and detect
reg [3:0] pluck_shift_reg;
always @(posedge clk_i) begin
if (!rst_ni) begin
pluck_shift_reg <= 'b0;
end else begin
pluck_shift_reg <= {pluck_shift_reg[2:0], pluck_i};
end
end
wire pluck_rise_pulse;
assign pluck_rise_pulse = !pluck_shift_reg[3] && pluck_shift_reg[2];
// noise burst capture
reg signed [EXTENDED_WIDTH+FRAC_BITS-1:0] noise_reg;
reg [$clog2(MAX_LENGTH)-1:0] prbs_burst_counter;
reg prbs_burst_en;
reg [DATA_WIDTH-1:0] noise_sample_reg;
always @(posedge clk_i) begin
if (!rst_ni) noise_sample_reg <= 'b0;
else noise_sample_reg <= {noise_sample_reg[DATA_WIDTH-2:0], ^prbs_data_i};
end
// peak-peak clipped noise
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] clip_noise_sample;
assign clip_noise_sample = (^prbs_data_i) ? ({{(EXTN_BITS+1){1'b0}}, {((DATA_WIDTH+FRAC_BITS)-1){1'b1}}})
: ({{(EXTN_BITS+1){1'b1}}, {((DATA_WIDTH+FRAC_BITS)-1){1'b0}}});
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] noise_sample;
assign noise_sample = clip_noise_i ? clip_noise_sample : {{EXTN_BITS{noise_sample_reg[DATA_WIDTH-1]}}, noise_sample_reg, {FRAC_BITS{1'b0}}};
// noise dynamics filter
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] yd_0;
assign yd_0 = noise_sample_dyn;
reg signed [EXTENDED_WIDTH+FRAC_BITS-1:0] yd_1;
always @(posedge clk_i) begin
if (!rst_ni) yd_1 <= 'b0;
else yd_1 <= yd_0;
end
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] R_diff, noise_sample_dyn;
wire signed [DATA_WIDTH+EXTENDED_WIDTH+FRAC_BITS-1:0] scaled_R_diff;
assign R_diff = yd_1 - noise_sample;
assign scaled_R_diff = (dynamics_R_i * R_diff) >>> DATA_WIDTH;
assign noise_sample_dyn = noise_sample + scaled_R_diff;
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] noise_sample_w;
assign noise_sample_w = dynamics_en_i ? noise_sample_dyn : noise_sample;
reg toggle_bit;
always @(posedge clk_i) begin
if (!rst_ni) toggle_bit <= 'b0;
else toggle_bit <= ~toggle_bit;
end
wire [EXTENDED_WIDTH+FRAC_BITS-1:0] toggle_clamp;
assign toggle_clamp = {{EXTN_BITS{toggle_bit}}, {toggle_bit, {DATA_WIDTH-1{~toggle_bit}}}, {FRAC_BITS{~toggle_bit}}};
wire [EXTENDED_WIDTH+FRAC_BITS-1:0] noise_mux_sample;
assign noise_mux_sample = toggle_pattern_prbs_ni ? toggle_clamp : noise_sample_w;
always @(posedge clk_i) begin
if (!rst_ni) begin
prbs_burst_counter <= 'b0;
noise_reg <= 'b0;
prbs_burst_en <= 'b0;
end else begin
if (pluck_rise_pulse == 1'b1) begin
prbs_burst_counter <= 'b0;
noise_reg <= noise_mux_sample;
prbs_burst_en <= 'b1;
end else if (prbs_burst_en == 1'b1) begin
if (prbs_burst_counter < clamped_period) begin
prbs_burst_counter <= prbs_burst_counter + 1;
noise_reg <= noise_mux_sample;
prbs_burst_en <= 1'b1;
end else begin
prbs_burst_counter <= 'b0;
noise_reg <= 'b0;
prbs_burst_en <= 1'b0;
end
end else begin
prbs_burst_counter <= 'b0;
noise_reg <= 'b0;
prbs_burst_en <= 'b0;
end
end
end
// filter taps
wire signed [DATA_WIDTH-1:0] x_p;
assign x_p = string_reg[period_idx];
wire signed [DATA_WIDTH-1:0] x_p_1;
assign x_p_1 = delay_reg;
// Strong filter
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] strong_string_avg;
assign strong_string_avg = (((x_p <<< FRAC_BITS) + (x_p_1 <<< FRAC_BITS)) >>> 1);
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] strong_drum_avg;
assign strong_drum_avg = prbs_data_i[0] ? strong_string_avg : -strong_string_avg;
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] strong_filter_w;
assign strong_filter_w = drum_string_ni ? strong_drum_avg : strong_string_avg;
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] ks_sample_w;
assign ks_sample_w = noise_reg + strong_filter_w + (round_en_i ? (1 << (FRAC_BITS-1)) : 0);
reg signed [EXTENDED_WIDTH+FRAC_BITS-1:0] strong_filter_1;
always @(posedge clk_i) begin
if (!rst_ni) strong_filter_1 <= 'b0;
else strong_filter_1 <= strong_filter_w;
end
// Fine Tune
reg signed [EXTENDED_WIDTH+FRAC_BITS-1:0] y_1;
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] y_0, C_diff;
wire signed [DATA_WIDTH+EXTENDED_WIDTH+FRAC_BITS-1:0] scaled_C_diff;
assign C_diff = strong_filter_w - y_1;
assign scaled_C_diff = ((fine_tune_C_i * C_diff) >>> (DATA_WIDTH-1));
assign y_0 = strong_filter_1 + scaled_C_diff;
always @(posedge clk_i) begin
if (!rst_ni) y_1 <= 'b0;
else y_1 <= y_0;
end
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] ks_sample_ft_w;
assign ks_sample_ft_w = noise_reg + y_0 + (round_en_i ? (1 << (FRAC_BITS-1)) : 0);
wire [EXTENDED_WIDTH+FRAC_BITS-1:0] ks_loop_sample_w;
assign ks_loop_sample_w = fine_tune_en_i ? ks_sample_ft_w : ks_sample_w;
// overflow detect
wire ks_sign_bit;
assign ks_sign_bit = ks_loop_sample_w[EXTENDED_WIDTH+FRAC_BITS-1];
wire ks_data_msb;
assign ks_data_msb = ks_loop_sample_w[DATA_WIDTH+FRAC_BITS-1];
wire ks_ovf;
assign ks_ovf = ks_sign_bit ^ ks_data_msb;
wire [EXTENDED_WIDTH+FRAC_BITS-1:0] ks_clamped_val;
assign ks_clamped_val = {{EXTN_BITS{ks_sign_bit}}, {ks_sign_bit, {DATA_WIDTH-1{ks_data_msb}}}, {FRAC_BITS{ks_data_msb}}};
wire signed [EXTENDED_WIDTH+FRAC_BITS-1:0] ks_loop_clamped_w;
assign ks_loop_clamped_w = ks_ovf ? ks_clamped_val : ks_loop_sample_w;
wire [DATA_WIDTH-1:0] ks_loop_sample_o;
assign ks_loop_sample_o = ks_loop_clamped_w[DATA_WIDTH+FRAC_BITS-1:FRAC_BITS];
assign ks_sample_o = ks_loop_sample_o;
// wavetable
reg [DATA_WIDTH-1:0] string_reg [MAX_LENGTH-1:0];
// reg [MAX_LENGTH-1:0] [DATA_WIDTH-1:0] string_reg;
always @(posedge clk_i) begin
if (!rst_ni) begin
string_reg[0] <= 'b0;
end else if (freeze_i) begin
string_reg[0] <= string_reg[0];
end else begin
string_reg[0] <= ks_loop_sample_o;
end
end
genvar i;
generate
for (i = 1; i < MAX_LENGTH; i = i + 1) begin
always @(posedge clk_i) begin
if (!rst_ni) begin
string_reg[i] <= 'b0;
end else if (freeze_i) begin
string_reg[i] <= string_reg[i];
end else begin
string_reg[i] <= string_reg[i-1];
end
end
end
endgenerate
reg [DATA_WIDTH-1:0] delay_reg;
always @(posedge clk_i) begin
if (!rst_ni) begin
delay_reg <= 'b0;
end else begin
delay_reg <= string_reg[period_idx];
end
end
endmodule
|
module tt_um_ks_pyamnihc (
input wire [7:0] ui_in, // Dedicated inputs - connected to the input switches
output wire [7:0] uo_out, // Dedicated outputs - connected to the 7 segment display
input wire [7:0] uio_in, // IOs: Bidirectional Input path
output wire [7:0] uio_out, // IOs: Bidirectional Output path
output wire [7:0] uio_oe, // IOs: Bidirectional Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// SPI param.
localparam SPI_INST_WIDTH = 1;
localparam SPI_ADDR_WIDTH = 7;
localparam SPI_DATA_WIDTH = 8;
localparam SPI_NUM_CONFIG_REG = 8;
localparam SPI_NUM_STATUS_REG = 2;
// I2S param.
localparam I2S_AUDIO_DW = 8;
// KS param.
localparam KS_MAX_LENGTH = 32;
localparam KS_DATA_WIDTH = 8;
localparam KS_PRBS_WIDTH = 2;
localparam KS_EXTN_BITS = 4;
localparam KS_FRAC_BITS = 4;
// clock dividers
reg [3:0] clk_rise_counter;
wire clk_r16;
always @(posedge clk) begin
if (!rst_n) clk_rise_counter <= 'b0;
else clk_rise_counter <= clk_rise_counter + 1;
end
assign clk_r16 = clk_rise_counter[3];
// SPI register map
wire sck_i;
assign sck_i = uio_in[0];
wire sdi_i;
assign sdi_i = uio_in[1];
wire sdo_o;
assign uio_out[2] = sdo_o;
wire cs_ni;
assign cs_ni = uio_in[3];
// i2s tx
wire i2s_sck_o;
assign uio_out[4] = i2s_sck_o;
wire i2s_ws_o;
assign uio_out[5] = i2s_ws_o;
wire i2s_sd_o;
assign uio_out[6] = i2s_sd_o;
assign uio_out[0] = 1'b0;
assign uio_out[1] = 1'b0;
assign uio_out[3] = 1'b0;
assign uio_oe = 8'b1111_0100;
assign uo_out[0] = rst_n;
assign uo_out[1] = rst_n_prbs_15;
assign uo_out[2] = rst_n_prbs_7;
assign uo_out[3] = rst_n_ks_string;
assign uo_out[4] = freeze_prbs_7;
assign uo_out[5] = freeze_prbs_15;
assign uo_out[6] = i2s_noise_sel;
assign uo_out[7] = pluck;
// prbs tx
assign uio_out[7] = prbs_15;
// register map, packed to unpacked
wire [SPI_DATA_WIDTH*SPI_NUM_CONFIG_REG-1:0] config_bus_o;
wire [SPI_DATA_WIDTH*SPI_NUM_STATUS_REG-1:0] status_bus_i;
wire [SPI_DATA_WIDTH-1:0] config_arr [SPI_NUM_CONFIG_REG-1:0];
genvar i;
generate
for (i = 0; i < SPI_NUM_CONFIG_REG; i = i + 1) begin
assign config_arr[i] = config_bus_o[SPI_DATA_WIDTH*(i+1)-1:SPI_DATA_WIDTH*i];
end
endgenerate
wire [SPI_DATA_WIDTH-1:0] status_arr [SPI_NUM_CONFIG_REG-1:0];
generate
for (i = 0; i < SPI_NUM_STATUS_REG; i = i + 1) begin
assign status_bus_i[SPI_DATA_WIDTH*(i+1)-1:SPI_DATA_WIDTH*i] = status_arr[i];
end
endgenerate
assign status_arr[0] = 8'hC0;
assign status_arr[1] = 8'h01;
// SPI peripheral
wire [SPI_ADDR_WIDTH-1:0] spi_addr;
wire [SPI_DATA_WIDTH-1:0] spi_write_data, spi_read_data;
wire spi_write_en, spi_read_en;
spi_slave_mem_interface #(.INST_WIDTH(SPI_INST_WIDTH),
.ADDR_WIDTH(SPI_ADDR_WIDTH),
.DATA_WIDTH(SPI_DATA_WIDTH)
) spi_slave_mem_interface_0 (
.sck_i(sck_i),
.sdi_i(sdi_i),
.sdo_o(sdo_o),
.cs_ni(cs_ni && rst_n),
.addr_o(spi_addr),
.write_data_o(spi_write_data),
.write_en_o(spi_write_en),
.read_data_i(spi_read_data),
.read_en_o(spi_read_en)
);
// Register map
register_map #( .ADDR_WIDTH(SPI_ADDR_WIDTH),
.DATA_WIDTH(SPI_DATA_WIDTH),
.NUM_CONFIG_REG(SPI_NUM_CONFIG_REG),
.NUM_STATUS_REG(SPI_NUM_STATUS_REG)
) register_map_0 (
.clk_i(clk),
.rst_ni(rst_n),
.addr_i(spi_addr),
.write_data_i(spi_write_data),
.write_en_i(spi_write_en),
.read_data_o(spi_read_data),
.read_en_i(spi_read_en),
.config_bus_o(config_bus_o),
.status_bus_i(status_bus_i)
);
// prbs15
wire rst_n_prbs_15;
assign rst_n_prbs_15 = ~config_arr[0][0] && ~ui_in[0];
wire [14:0] lfsr_init_15;
assign lfsr_init_15 = {~config_arr[2][6:0], ~config_arr[1][7:0]};
wire load_prbs_15;
assign load_prbs_15 = config_arr[2][7] || ui_in[1];
wire freeze_prbs_15;
assign freeze_prbs_15 = config_arr[0][4] || ui_in[2];
wire prbs_15;
wire [14:0] prbs_frame_15;
prbs15 prbs15_0 (
.clk_i(clk_r16),
.rst_ni(rst_n && rst_n_prbs_15),
.lfsr_init_i(lfsr_init_15),
.load_prbs_i(load_prbs_15),
.freeze_i(freeze_prbs_15),
.prbs_o(prbs_15),
.prbs_frame_o(prbs_frame_15)
);
// prbs7
wire rst_n_prbs_7;
assign rst_n_prbs_7 = ~config_arr[0][1] && ~ui_in[0];
wire [6:0] lfsr_init_7;
assign lfsr_init_7 = config_arr[3][6:0];
wire load_prbs_7;
assign load_prbs_7 = config_arr[3][7] || ui_in[1];
wire freeze_prbs_7;
assign freeze_prbs_7 = config_arr[0][5] || ui_in[3];
wire prbs_7;
wire [6:0] prbs_frame_7;
prbs7 prbs7_0 (
.clk_i(clk_r16),
.rst_ni(rst_n && rst_n_prbs_7),
.lfsr_init_i(lfsr_init_7),
.load_prbs_i(load_prbs_7),
.freeze_i(freeze_prbs_7),
.prbs_o(prbs_7),
.prbs_frame_o(prbs_frame_7)
);
// i2s sample select
wire i2s_noise_sel = config_arr[0][7] || ui_in[4];
wire [I2S_AUDIO_DW-1:0] l_data, r_data;
assign l_data = i2s_noise_sel ? prbs_frame_15[I2S_AUDIO_DW-1:0] : ks_sample;
assign r_data = i2s_noise_sel ? {1'b0, prbs_frame_7} : ks_sample;
reg [I2S_AUDIO_DW-1:0] l_data_reg, r_data_reg;
wire l_load_en, r_load_en;
always @(negedge i2s_sck_o) begin
if (l_load_en == 1) l_data_reg <= l_data;
else l_data_reg <= l_data_reg;
if (r_load_en == 1) r_data_reg <= r_data;
else r_data_reg <= r_data_reg;
end
// i2s tx
assign i2s_sck_o = ~clk;
assign i2s_ws_o = clk_r16;
i2s_tx #(
.AUDIO_DW(I2S_AUDIO_DW)
) i2s_tx_0 (
.sck_i(i2s_sck_o),
.ws_i(i2s_ws_o),
.sd_o(i2s_sd_o),
.l_data_i(l_data_reg),
.r_data_i(r_data_reg),
.l_load_en_o(l_load_en),
.r_load_en_o(r_load_en)
);
// ks string
wire ks_clk;
assign ks_clk = clk_r16;
wire rst_n_ks_string;
assign rst_n_ks_string = ~config_arr[0][2] && ~ui_in[5];
wire ks_freeze;
assign ks_freeze = config_arr[0][7];
wire pluck;
assign pluck = config_arr[4][0] || ui_in[6];
wire round_en;
assign round_en = config_arr[4][1];
wire toggle_pattern_prbs_n;
assign toggle_pattern_prbs_n = config_arr[4][2];
wire drum_string_n;
assign drum_string_n = config_arr[4][3];
wire fine_tune_en;
assign fine_tune_en = config_arr[4][4];
wire dynamics_en;
assign dynamics_en = config_arr[4][5];
wire [KS_DATA_WIDTH-1:0] fine_tune_C;
assign fine_tune_C = config_arr[5];
wire [KS_DATA_WIDTH-1:0] dynamics_R;
assign dynamics_R = config_arr[6];
wire clip_noise;
assign clip_noise = config_arr[4][6];
wire [KS_PRBS_WIDTH-1:0] prbs_data;
assign prbs_data = {prbs_15, prbs_7};
wire [KS_DATA_WIDTH-1:0] ks_period;
assign ks_period = ~config_arr[7];
wire [KS_DATA_WIDTH-1:0] ks_sample;
ks_string #(
.MAX_LENGTH(KS_MAX_LENGTH),
.DATA_WIDTH(KS_DATA_WIDTH),
.PRBS_WIDTH(KS_PRBS_WIDTH),
.EXTN_BITS(KS_EXTN_BITS),
.FRAC_BITS(KS_FRAC_BITS)
) ks_string_0 (
.clk_i(ks_clk),
.rst_ni(rst_n && rst_n_ks_string),
.freeze_i(ks_freeze),
.pluck_i(pluck),
.round_en_i(round_en),
.toggle_pattern_prbs_ni(toggle_pattern_prbs_n),
.drum_string_ni(drum_string_n),
.fine_tune_en_i(fine_tune_en),
.fine_tune_C_i(fine_tune_C),
.dynamics_en_i(dynamics_en),
.dynamics_R_i(dynamics_R),
.clip_noise_i(clip_noise),
.prbs_data_i(prbs_data),
.period_i(ks_period),
.ks_sample_o(ks_sample)
);
endmodule
|
tt06-finale_0094
|
tt06-finale
|
tommythorn-tt06-tommythorn-4b-cpu
|
task_tt_um_tommythorn_4b_cpu_v2
|
tt_um_tommythorn_4b_cpu_v2
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Tommy Thorn
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
`default_nettype none
// Instructions
`define Load 0
`define Store 1
`define Add 2
`define Bz 3
// Commands
`define Reset 0
`define LoadCode 1
`define LoadData 2
`define Run 3
module tt_um_tommythorn_4b_cpu_v2 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
`ifdef TB
module tb;
wire [7:0] ui_in; // Dedicated inputs
wire [7:0] uo_out; // Dedicated outputs
wire [7:0] uio_in; // IOs: Input path
wire [7:0] uio_out; // IOs: Output path
wire [7:0] uio_oe = 0;// IOs: Enable path (active high: 0=input; 1=output)
wire ena = 1; // will go high when the design is enabled
reg clk = 1; // clock
wire rst_n = 1;// reset_n - low to reset
always #5 clk = !clk;
reg [1:0] cmd;
reg [3:0] cmdarg;
assign ui_in = {cmdarg, 1'b0, cmd, clk};
tt_um_tommythorn_4b_cpu_v2 inst_4b_cpu_v2
(ui_in, // Dedicated inputs
uo_out, // Dedicated outputs
uio_in, // IOs: Input path
uio_out, // IOs: Output path
uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
ena, // will go high when the design is enabled
clk, // clk
rst_n); // reset_n - low to reset
initial begin
//$monitor("%05d pc %d acc %d", $time, inst_4b_cpu_v2.pc, inst_4b_cpu_v2.acc);
cmd = `Reset; cmdarg = 0;
@(negedge clk)
cmd = `LoadCode;
cmdarg = `Load; @(negedge clk)
cmdarg = `Store; @(negedge clk)
cmdarg = `Add; @(negedge clk)
cmdarg = `Store; @(negedge clk)
cmdarg = `Load; @(negedge clk)
cmdarg = `Store; @(negedge clk)
cmdarg = `Add; @(negedge clk)
cmdarg = `Bz; @(negedge clk)
cmd = `LoadData;
cmdarg = 1; @(negedge clk)
cmdarg = 4; @(negedge clk)
cmdarg = 1; @(negedge clk)
cmdarg = 0; @(negedge clk)
cmdarg = 9; @(negedge clk)
cmdarg = 2; @(negedge clk)
cmdarg = 8; @(negedge clk)
cmdarg = 7; @(negedge clk)
cmd = `Reset; cmdarg = 0;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
@(negedge clk) cmd = `Run;
#100 $display("The End");
$finish;
end
endmodule
`endif
|
module tt_um_tommythorn_4b_cpu_v2 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
assign uio_out = 0;
assign uio_oe = 0;
// State
reg [1:0] code[7:0];
reg [3:0] data[7:0];
reg [2:0] pc;
reg [3:0] acc;
wire [2:0] npc = pc + 1;
assign uo_out = {1'd0, pc, acc};
wire [3:0] arg = data[pc];
always @(posedge clk)
if (rst_n == 0) begin
$display(" Reset");
pc <= ui_in[6:4];
acc <= 0;
end else case (ui_in[2:1])
`Reset: begin // XXX This is now redundant
$display(" Reset");
$display("%d %d %d", ui_in, ui_in[7:4], ui_in[7:4]);
pc <= ui_in[6:4];
acc <= 0;
end
`LoadCode: begin
$display(" LoadCode %d: Insn %d", pc, ui_in[7:4]);
code[pc] <= ui_in[5:4];
pc <= npc;
end
`LoadData: begin
$display(" LoadData %d: Data %d", pc, ui_in[7:4]);
data[pc] <= ui_in[7:4];
pc <= npc;
end
`Run: begin
case (code[pc])
`Load: begin
$display(" Exec %d: Load acc = %d", pc, arg);
acc <= arg; pc <= npc;
end
`Store: begin
$display(" Exec %d: Store [%d]=%d", pc, arg[2:0], acc);
data[arg[2:0]] <= acc; pc <= npc;
end
`Add: begin
$display(" Exec %d: Add acc=%d,%d", pc, acc, arg);
acc <= acc + arg; pc <= npc;
end
`Bz: begin
if (acc == 0)
$display(" Exec %d: Bz %d taken", pc, arg);
else
$display(" Exec %d: Bz %d skipped", pc, arg);
pc <= acc == 0 ? arg[2:0] : npc;
end
endcase
end
endcase
endmodule
|
tt06-finale_0095
|
tt06-finale
|
wmk7fe-tt06-otp-encryptor
|
task_LFSR_PRNG
|
tt_um_otp_encryptor
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
`default_nettype none
module tt_um_otp_encryptor (
input [7:0] ui_in, // Dedicated inputs
output [7:0] uo_out, // Dedicated outputs
/* verilator lint_off UNUSEDSIGNAL */
input [7:0] uio_in, // IOs: Input path
/* verilator lint_on UNUSEDSIGNAL */
output [7:0] uio_out, // IOs: Output path
output [7:0] uio_oe,
input ena, // will go high when the design is enabled
input clk, // clock
input rst_n // reset_n - low to reset
);
wire [7:0] data;
wire [7:0] pad_gen;
wire [2:0] r_num;
reg[2:0] count;
wire decrypt;
wire reset;
reg [7:0] out;
reg [2:0] index_out;
// io
assign data = ui_in[7:0];
assign decrypt = uio_in[0];
assign r_num = uio_in[3:1];
assign reset = ~rst_n;
assign uo_out[7:0] = out[7:0];
assign uio_out[6:4] = index_out[2:0];
assign uio_out[7] = 1'b0;
assign uio_out[3:0] = 4'h0;
assign uio_oe = 8'b11110000;
// registers
reg[7:0] mem[0:7];
integer i;
LFSR_PRNG rng(
.clk(clk),
.rst(reset),
.prn(pad_gen));
//assign out = ena ? (decrypt ? (pad_read ^ data) : (pad_gen ^ data)) : 8'h00;
always @ (posedge clk, posedge reset) begin
if (reset) begin
count <= 3'h0;
out <= 8'h00;
index_out <= 3'h0;
for(i = 0; i < 8; i = i + 1) begin
mem[i] <= 8'h00;
end
end
else if (ena) begin
if (decrypt) begin
index_out <= 3'h0;
out <= mem[r_num] ^ data;
end
else begin // encrypt
if(count == 3'b111) begin
count <= 3'b000;
end
else begin
count <= count + 3'h1;
end
out <= pad_gen ^ data;
mem[count] <= pad_gen;
index_out <= count;
end
end
else out <= 8'h00;
end
endmodule
module LFSR_PRNG (
clk,
rst,
prn);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
|
module LFSR_PRNG (
clk,
rst,
prn);
input clk;
input rst;
output [7:0] prn;
reg [31:0] D32 = 32'hbdca2c92; //NEVER 000000
assign prn[0] = D32[23];
assign prn[1] = D32[17];
assign prn[2] = D32[13];
assign prn[3] = D32[11];
assign prn[4] = D32[7];
assign prn[5] = D32[5];
assign prn[6] = D32[3];
assign prn[7] = D32[2];
always @ (posedge rst or posedge clk)
if (rst)
begin
D32 <= 32'hbdca2c92;
end
else
begin
D32[1] <= D32[0];
D32[2] <= D32[1];
D32[3] <= D32[2];
D32[4] <= D32[3];
D32[5] <= D32[4];
D32[6] <= D32[5];
D32[7] <= D32[6];
D32[8] <= D32[7];
D32[9] <= D32[8];
D32[10] <= D32[9];
D32[11] <= D32[10];
D32[12] <= D32[11];
D32[13] <= D32[12];
D32[14] <= D32[13];
D32[15] <= D32[14];
D32[16] <= D32[15];
D32[17] <= D32[16];
D32[18] <= D32[17];
D32[19] <= D32[18];
D32[20] <= D32[19];
D32[21] <= D32[20];
D32[22] <= D32[21];
D32[23] <= D32[22];
D32[24] <= D32[23];
D32[25] <= D32[24];
D32[26] <= D32[25];
D32[27] <= D32[26];
D32[28] <= D32[27];
D32[29] <= D32[28];
D32[30] <= D32[29];
D32[31] <= D32[30];
D32[0] <= ~(~(~(D32[31] ^ D32[21]) ^ D32[1]) ^ D32[0]);
end
endmodule
|
tt06-finale_0096
|
tt06-finale
|
wmk7fe-tt06-otp-encryptor
|
task_tt_um_otp_encryptor
|
tt_um_otp_encryptor
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
`default_nettype none
module tt_um_otp_encryptor (
input [7:0] ui_in, // Dedicated inputs
output [7:0] uo_out, // Dedicated outputs
/* verilator lint_off UNUSEDSIGNAL */
input [7:0] uio_in, // IOs: Input path
/* verilator lint_on UNUSEDSIGNAL */
output [7:0] uio_out, // IOs: Output path
output [7:0] uio_oe,
input ena, // will go high when the design is enabled
input clk, // clock
input rst_n // reset_n - low to reset
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module LFSR_PRNG (
clk,
rst,
prn);
input clk;
input rst;
output [7:0] prn;
reg [31:0] D32 = 32'hbdca2c92; //NEVER 000000
assign prn[0] = D32[23];
assign prn[1] = D32[17];
assign prn[2] = D32[13];
assign prn[3] = D32[11];
assign prn[4] = D32[7];
assign prn[5] = D32[5];
assign prn[6] = D32[3];
assign prn[7] = D32[2];
always @ (posedge rst or posedge clk)
if (rst)
begin
D32 <= 32'hbdca2c92;
end
else
begin
D32[1] <= D32[0];
D32[2] <= D32[1];
D32[3] <= D32[2];
D32[4] <= D32[3];
D32[5] <= D32[4];
D32[6] <= D32[5];
D32[7] <= D32[6];
D32[8] <= D32[7];
D32[9] <= D32[8];
D32[10] <= D32[9];
D32[11] <= D32[10];
D32[12] <= D32[11];
D32[13] <= D32[12];
D32[14] <= D32[13];
D32[15] <= D32[14];
D32[16] <= D32[15];
D32[17] <= D32[16];
D32[18] <= D32[17];
D32[19] <= D32[18];
D32[20] <= D32[19];
D32[21] <= D32[20];
D32[22] <= D32[21];
D32[23] <= D32[22];
D32[24] <= D32[23];
D32[25] <= D32[24];
D32[26] <= D32[25];
D32[27] <= D32[26];
D32[28] <= D32[27];
D32[29] <= D32[28];
D32[30] <= D32[29];
D32[31] <= D32[30];
D32[0] <= ~(~(~(D32[31] ^ D32[21]) ^ D32[1]) ^ D32[0]);
end
endmodule
|
module tt_um_otp_encryptor (
input [7:0] ui_in, // Dedicated inputs
output [7:0] uo_out, // Dedicated outputs
/* verilator lint_off UNUSEDSIGNAL */
input [7:0] uio_in, // IOs: Input path
/* verilator lint_on UNUSEDSIGNAL */
output [7:0] uio_out, // IOs: Output path
output [7:0] uio_oe,
input ena, // will go high when the design is enabled
input clk, // clock
input rst_n // reset_n - low to reset
);
wire [7:0] data;
wire [7:0] pad_gen;
wire [2:0] r_num;
reg[2:0] count;
wire decrypt;
wire reset;
reg [7:0] out;
reg [2:0] index_out;
// io
assign data = ui_in[7:0];
assign decrypt = uio_in[0];
assign r_num = uio_in[3:1];
assign reset = ~rst_n;
assign uo_out[7:0] = out[7:0];
assign uio_out[6:4] = index_out[2:0];
assign uio_out[7] = 1'b0;
assign uio_out[3:0] = 4'h0;
assign uio_oe = 8'b11110000;
// registers
reg[7:0] mem[0:7];
integer i;
LFSR_PRNG rng(
.clk(clk),
.rst(reset),
.prn(pad_gen));
//assign out = ena ? (decrypt ? (pad_read ^ data) : (pad_gen ^ data)) : 8'h00;
always @ (posedge clk, posedge reset) begin
if (reset) begin
count <= 3'h0;
out <= 8'h00;
index_out <= 3'h0;
for(i = 0; i < 8; i = i + 1) begin
mem[i] <= 8'h00;
end
end
else if (ena) begin
if (decrypt) begin
index_out <= 3'h0;
out <= mem[r_num] ^ data;
end
else begin // encrypt
if(count == 3'b111) begin
count <= 3'b000;
end
else begin
count <= count + 3'h1;
end
out <= pad_gen ^ data;
mem[count] <= pad_gen;
index_out <= count;
end
end
else out <= 8'h00;
end
endmodule
|
tt06-finale_0097
|
tt06-finale
|
zacharysfrazee-tt06-minibyte-cpu
|
task_demo_rom_64B
|
tt_um_minibyte
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//---------------------------------
//Top Level Project Module
//---------------------------------
module tt_um_minibyte (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
//---------------------------------
//Top Level Singal Notes
//---------------------------------
//ui_in => Test and Configuration bits
//uo_out => WE and 7-bit Address Buss
//uio_in/uio_out => 8-bit Bidirectional Data Buss
//uio_oe => Output Enable for Data Buss
//---------------------------------
//ui_in (Test)
// bit[7] => ENABLE ONBOARD REG RAM
// bit[6:5] => UNUSED
// bit[4] => ENABLE DEMO ROM
// bit[3] => HALT CONTROL UNIT
// bit[2:0] => DEBUG OUTPUT SIGNAL CONTROL
// 0 -> Normal output
// 1 -> A output
// 2 -> A (UPPER BIT) output
// 3 -> M output
// 4 -> PC output
// 5 -> IR output
// 6 -> CCR output
// 7 -> CU STATE output
//---------------------------------
//uio_in/uio_out
// bit[7] => WE (Write Enable)
// bit[6:0] => Address Buss
//---------------------------------
//---------------------------------
//Wires
//---------------------------------
wire [6:0] address_buss;
wire we_signal;
wire [7:0] tm_control_bits;
wire [7:0] data_buss_in;
wire [7:0] data_buss_out;
wire [7:0] data_buss_oe;
wire [7:0] data_buss_rom;
wire [7:0] data_buss_ram;
wire [7:0] data_buss_muxed_in;
wire drive_enable_sig;
wire nc_addr_buss_bit_7;
//---------------------------------
//Assignments
//---------------------------------
assign uo_out[6:0] = address_buss;
assign uo_out[7] = we_signal;
assign tm_control_bits = ui_in;
assign data_buss_in = uio_in;
assign uio_out = data_buss_out;
assign uio_oe = data_buss_oe;
//---------------------------------
//Minibyte CPU
//---------------------------------
minibyte_cpu cpu(
//Basic Inputs
.clk_in(clk), .ena_in(ena), .rst_in(rst_n),
.halt_in(tm_control_bits[3]),
//Memory and IO Inputs
.data_in(data_buss_muxed_in),
//DFT Inputs
.tm_control({tm_control_bits[2:0]}),
//Memory and IO Outputs
.addr_out ({nc_addr_buss_bit_7,address_buss}), //Only 7 bits get connected as we need to save one output for WE below:(
.data_out (data_buss_out),
.we_out (we_signal), //Dedicated output bit 7 gets used for WE
.drive_out (drive_enable_sig)
);
//---------------------------------
//Input Device MUX
//---------------------------------
reg [1:0] input_mux_control;
always @ (tm_control_bits, reg_ram_active) begin
//Enable Onboard RAM
if(tm_control_bits[7] == 1 && reg_ram_active)
input_mux_control = 2'b11;
//Enable Demo ROM
else if(tm_control_bits[4] == 1)
input_mux_control = 2'b01;
//Enable Normal Input
else
input_mux_control = 2'b00;
end
minibyte_genmux_4x input_mux(
//Mux Inputs
.a_in(data_buss_in),
.b_in(data_buss_rom),
.c_in(8'h00),
.d_in(data_buss_ram),
//Mux Select
.sel_in(input_mux_control),
//Mux Output
.mux_out(data_buss_muxed_in)
);
//---------------------------------
//Demo ROM
//---------------------------------
demo_rom_64B rom(
//Input Addr and Enable
.address(address_buss[5:0]), //Lower 6 addr buss bits
//Output Data
.data_out(data_buss_rom)
);
//---------------------------------
//Onboard REG RAM
//---------------------------------
reg reg_ram_active;
//Register ram is only active for addresses
//0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f
always @ (address_buss) begin
if(address_buss >= 7'h78)
reg_ram_active = 1;
else
reg_ram_active = 0;
end
reg_ram_8B ram(
//Input CLK and RST
.clk_in(clk),
.rst_in(rst_n),
//Input Addr
.address(address_buss[2:0]),
//Input Data
.data_in(data_buss_out),
//Input WE
.we_in(we_signal),
.en_in(reg_ram_active),
//Output Data
.data_out(data_buss_ram)
);
//---------------------------------
//Output enable control
//---------------------------------
drive_enable_fanout oe_driver(
//Drive enable input signal
.drive_en(drive_enable_sig),
//Output drive signals
.drive(data_buss_oe)
);
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//---------------------------------
//Top Level CPU Module
//---------------------------------
module minibyte_cpu (
//Basic Inputs
input wire clk_in, ena_in, rst_in,
input wire halt_in,
//Memory and IO Inputs
input wire [7:0] data_in,
//DFT Testmode Inputs
input wire [2:0] tm_control,
//Memory and IO Outputs
output wire [7:0] addr_out,
output wire [7:0] data_out,
output wire we_out,
output wire drive_out
);
//Main Data Buss
//--------------------------------
wire [7:0] main_buss;
//Data out comes from the main buss
assign data_out = main_buss;
//ALU A-Side Input Data Buss
//--------------------------------
wire [7:0] alu_a_buss;
//Address Busses
//--------------------------------
wire [7:0] m_addr_buss;
wire [7:0] pc_addr_buss;
wire [7:0] ir_op_buss;
wire [7:0] normal_addr_out;
//DFT Wires
//--------------------------------
wire [7:0] dft_cu_state;
//Control Signals
//--------------------------------
//Set register signals
wire ctrl_set_a;
wire ctrl_set_m;
wire ctrl_set_pc;
wire ctrl_set_ir;
wire ctrl_set_ccr;
//Inc register signals
wire ctrl_inc_pc;
//Addr mux signals
wire ctrl_addr_mux;
//Alu control signals
wire [3:0] ctrl_alu_op;
//Data direction control
wire ctrl_we_out;
wire ctrl_drive_out;
assign we_out=ctrl_we_out;
assign drive_out=ctrl_drive_out;
//Branch Signals
//--------------------------------
wire [1:0] flags_zn_buss;
wire [1:0] ccr_zn_buss;
//A Register
//--------------------------------
minibyte_genreg reg_a(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(main_buss),
.set_in(ctrl_set_a),
//Register Outputs
.reg_out(alu_a_buss)
);
//M Register
//--------------------------------
minibyte_genreg reg_m(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(main_buss),
.set_in(ctrl_set_m),
//Register Outputs
.reg_out(m_addr_buss)
);
//PC Register
//--------------------------------
minibyte_pcreg reg_pc(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(main_buss),
.set_in(ctrl_set_pc),
.inc_in(ctrl_inc_pc),
//Register Outputs
.reg_out(pc_addr_buss)
);
//IR Register
//--------------------------------
minibyte_genreg reg_ir(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(main_buss),
.set_in(ctrl_set_ir),
//Register Outputs
.reg_out(ir_op_buss)
);
//CCR Register
//--------------------------------
minibyte_ccrreg reg_ccr(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(flags_zn_buss),
.set_in(ctrl_set_ccr),
//Register Outputs
.reg_out(ccr_zn_buss)
);
//Addr Out Mux
//--------------------------------
minibyte_genmux_2x addr_mux(
//Mux Inputs
.a_in(pc_addr_buss),
.b_in(m_addr_buss),
//Mux Select
.sel_in(ctrl_addr_mux),
//Mux Output
.mux_out(normal_addr_out)
);
//Debug Out Mux
//--------------------------------
minibyte_genmux_8x tm_debug_out_mux(
//Mux Inputs
.a_in(normal_addr_out), //0 -> Normal output
.b_in(alu_a_buss), //1 -> A output
.c_in({7'h0, alu_a_buss[7]}), //2 -> A (UPPER BIT) output
.d_in(m_addr_buss), //3 -> M output
.e_in(pc_addr_buss), //4 -> PC output
.f_in(ir_op_buss), //5 -> IR output
.g_in({6'h0,ccr_zn_buss}), //6 -> CCR output
.h_in(dft_cu_state), //7 -> CU STATE output
//Mux Select
.sel_in(tm_control[2:0]),
//Mux Output
.mux_out(addr_out)
);
//ALU
//--------------------------------
minibyte_alu alu(
//ALU Inputs
.a_in(alu_a_buss),
.b_in(data_in),
.alu_op_in(ctrl_alu_op),
.res_out(main_buss),
.flags_zn_out(flags_zn_buss)
);
//Control Unit
//--------------------------------
minibyte_cu cu(
//Basic Inputs
.clk_in(clk_in), .ena_in(ena_in), .rst_in(rst_in),
.halt_in(halt_in),
//IR Input
.ir_op_buss_in(ir_op_buss),
//ALU Flags Input
.ccr_flag_zn_in(ccr_zn_buss),
//Control signal outputs
.set_a_out(ctrl_set_a),
.set_m_out(ctrl_set_m),
.set_pc_out(ctrl_set_pc),
.set_ir_out(ctrl_set_ir),
.set_ccr_out(ctrl_set_ccr),
.inc_pc_out(ctrl_inc_pc),
//Addr select signals
.addr_mux_out(ctrl_addr_mux),
//Alu control signals
.alu_op_out(ctrl_alu_op),
//Write to memory
.we_out(ctrl_we_out),
//Drive enable on data bus
.drive_out(ctrl_drive_out),
//DFT Output
.dft_curr_state(dft_cu_state)
);
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//---------------------------------
//Control Unit
//---------------------------------
module minibyte_cu(
//Basic Inputs
input wire clk_in, ena_in, rst_in,
input wire halt_in,
//IR Input
input wire [7:0] ir_op_buss_in,
//ALU Flags Input
input wire [1:0] ccr_flag_zn_in,
//Control signal outputs
output reg set_a_out,
output reg set_m_out,
output reg set_pc_out,
output reg set_ir_out,
output reg set_ccr_out,
output reg inc_pc_out,
//Addr select signals
output reg addr_mux_out,
//Alu control signals
output reg [3:0] alu_op_out,
//Write to memory
output reg we_out,
//Drive enable on data bus
output reg drive_out,
//DFT Output
output reg [7:0] dft_curr_state
);
//State machine memory
//--------------------------
reg [7:0] curr_state, next_state;
//CPU IR opcodes
//--------------------------
parameter IR_NOP = 8'h00;
parameter IR_LDA_IMM = 8'h01;
parameter IR_LDA_DIR = 8'h02;
parameter IR_STA_DIR = 8'h03;
parameter IR_STA_IND = 8'h04;
parameter IR_ADD_IMM = 8'h05;
parameter IR_ADD_DIR = 8'h06;
parameter IR_SUB_IMM = 8'h07;
parameter IR_SUB_DIR = 8'h08;
parameter IR_AND_IMM = 8'h09;
parameter IR_AND_DIR = 8'h0A;
parameter IR_OR_IMM = 8'h0B;
parameter IR_OR_DIR = 8'h0C;
parameter IR_XOR_IMM = 8'h0D;
parameter IR_XOR_DIR = 8'h0E;
parameter IR_LSL_IMM = 8'h0F;
parameter IR_LSL_DIR = 8'h10;
parameter IR_LSR_IMM = 8'h11;
parameter IR_LSR_DIR = 8'h12;
parameter IR_ASL_IMM = 8'h13;
parameter IR_ASL_DIR = 8'h14;
parameter IR_ASR_IMM = 8'h15;
parameter IR_ASR_DIR = 8'h16;
parameter IR_RSL_IMM = 8'h17;
parameter IR_RSL_DIR = 8'h18;
parameter IR_RSR_IMM = 8'h19;
parameter IR_RSR_DIR = 8'h1A;
parameter IR_JMP_DIR = 8'h1B;
parameter IR_JMP_IND = 8'h1C;
parameter IR_BNE_DIR = 8'h1D;
parameter IR_BNE_IND = 8'h1E;
parameter IR_BEQ_DIR = 8'h1F;
parameter IR_BEQ_IND = 8'h20;
parameter IR_BPL_DIR = 8'h21;
parameter IR_BPL_IND = 8'h22;
parameter IR_BMI_DIR = 8'h23;
parameter IR_BMI_IND = 8'h24;
//State machine opcodes
//--------------------------
parameter S_RESET_0 = 8'h00;
parameter S_PC_INC_0 = 8'h01;
parameter S_FETCH_0 = 8'h02;
parameter S_FETCH_1 = 8'h03;
parameter S_FETCH_2 = 8'h04;
parameter S_DECODE_0 = 8'h05;
parameter S_LDA_IMM_0 = 8'h06;
parameter S_LDA_IMM_1 = 8'h07;
parameter S_LDA_DIR_0 = 8'h08;
parameter S_LDA_DIR_1 = 8'h09;
parameter S_LDA_DIR_2 = 8'h0A;
parameter S_LDA_DIR_3 = 8'h0B;
parameter S_STA_DIR_0 = 8'h0C;
parameter S_STA_DIR_1 = 8'h0D;
parameter S_STA_DIR_2 = 8'h0E;
parameter S_STA_DIR_3 = 8'h0F;
parameter S_STA_IND_0 = 8'h10;
parameter S_STA_IND_1 = 8'h11;
parameter S_STA_IND_2 = 8'h12;
parameter S_STA_IND_3 = 8'h13;
parameter S_STA_IND_4 = 8'h14;
parameter S_STA_IND_5 = 8'h15;
parameter S_ADD_IMM_0 = 8'h16;
parameter S_ADD_IMM_1 = 8'h17;
parameter S_ADD_DIR_0 = 8'h18;
parameter S_ADD_DIR_1 = 8'h19;
parameter S_ADD_DIR_2 = 8'h1A;
parameter S_ADD_DIR_3 = 8'h1B;
parameter S_SUB_IMM_0 = 8'h1C;
parameter S_SUB_IMM_1 = 8'h1D;
parameter S_SUB_DIR_0 = 8'h1E;
parameter S_SUB_DIR_1 = 8'h1F;
parameter S_SUB_DIR_2 = 8'h20;
parameter S_SUB_DIR_3 = 8'h21;
parameter S_AND_IMM_0 = 8'h22;
parameter S_AND_IMM_1 = 8'h23;
parameter S_AND_DIR_0 = 8'h24;
parameter S_AND_DIR_1 = 8'h25;
parameter S_AND_DIR_2 = 8'h26;
parameter S_AND_DIR_3 = 8'h27;
parameter S_OR_IMM_0 = 8'h28;
parameter S_OR_IMM_1 = 8'h29;
parameter S_OR_DIR_0 = 8'h2A;
parameter S_OR_DIR_1 = 8'h2B;
parameter S_OR_DIR_2 = 8'h2C;
parameter S_OR_DIR_3 = 8'h2D;
parameter S_XOR_IMM_0 = 8'h2E;
parameter S_XOR_IMM_1 = 8'h2F;
parameter S_XOR_DIR_0 = 8'h30;
parameter S_XOR_DIR_1 = 8'h31;
parameter S_XOR_DIR_2 = 8'h32;
parameter S_XOR_DIR_3 = 8'h33;
parameter S_LSL_IMM_0 = 8'h34;
parameter S_LSL_IMM_1 = 8'h35;
parameter S_LSL_DIR_0 = 8'h36;
parameter S_LSL_DIR_1 = 8'h37;
parameter S_LSL_DIR_2 = 8'h38;
parameter S_LSL_DIR_3 = 8'h39;
parameter S_LSR_IMM_0 = 8'h3A;
parameter S_LSR_IMM_1 = 8'h3B;
parameter S_LSR_DIR_0 = 8'h3C;
parameter S_LSR_DIR_1 = 8'h3D;
parameter S_LSR_DIR_2 = 8'h3E;
parameter S_LSR_DIR_3 = 8'h3F;
parameter S_ASL_IMM_0 = 8'h40;
parameter S_ASL_IMM_1 = 8'h41;
parameter S_ASL_DIR_0 = 8'h42;
parameter S_ASL_DIR_1 = 8'h43;
parameter S_ASL_DIR_2 = 8'h44;
parameter S_ASL_DIR_3 = 8'h45;
parameter S_ASR_IMM_0 = 8'h46;
parameter S_ASR_IMM_1 = 8'h47;
parameter S_ASR_DIR_0 = 8'h48;
parameter S_ASR_DIR_1 = 8'h49;
parameter S_ASR_DIR_2 = 8'h4A;
parameter S_ASR_DIR_3 = 8'h4B;
parameter S_RSL_IMM_0 = 8'h4C;
parameter S_RSL_IMM_1 = 8'h4D;
parameter S_RSL_DIR_0 = 8'h4E;
parameter S_RSL_DIR_1 = 8'h4F;
parameter S_RSL_DIR_2 = 8'h50;
parameter S_RSL_DIR_3 = 8'h51;
parameter S_RSR_IMM_0 = 8'h52;
parameter S_RSR_IMM_1 = 8'h53;
parameter S_RSR_DIR_0 = 8'h54;
parameter S_RSR_DIR_1 = 8'h55;
parameter S_RSR_DIR_2 = 8'h56;
parameter S_RSR_DIR_3 = 8'h57;
parameter S_JMP_DIR_0 = 8'h58;
parameter S_JMP_DIR_1 = 8'h59;
parameter S_JMP_IND_0 = 8'h5A;
parameter S_JMP_IND_1 = 8'h5B;
parameter S_JMP_IND_2 = 8'h5C;
parameter S_JMP_IND_3 = 8'h5D;
//--------------------------
//ALU OPS
//--------------------------
parameter OP_ALU_PASSA = 4'b0000;
parameter OP_ALU_PASSB = 4'b0001;
parameter OP_ALU_ADD = 4'b0010;
parameter OP_ALU_SUB = 4'b0011;
parameter OP_ALU_AND = 4'b0100;
parameter OP_ALU_OR = 4'b0101;
parameter OP_ALU_XOR = 4'b0110;
parameter OP_ALU_LSL = 4'b0111;
parameter OP_ALU_LSR = 4'b1000;
parameter OP_ALU_ASL = 4'b1001;
parameter OP_ALU_ASR = 4'b1010;
parameter OP_ALU_RSL = 4'b1011;
parameter OP_ALU_RSR = 4'b1100;
//State memory block
//--------------------------
always @ (posedge clk_in or negedge rst_in) begin
//Reset to S_RESET_0 on reset
if(!rst_in)
curr_state <= S_RESET_0;
//Dont move states if enable is low
else if(!ena_in)
curr_state <= curr_state;
//Otherwise go to next state on every clk
else
curr_state <= next_state;
end
//Output logic
//--------------------------
always @ (curr_state) begin
case(curr_state)
//Reset sequence
//-----
//Do nothing until the next state
S_RESET_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU dont care
alu_op_out = 0;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//PC Increment
//-----
//Increment PC
S_PC_INC_0: begin
//Increment program counter
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 1;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU dont care
alu_op_out = 0;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Fetch sequence
//-----
//Send PC addr out
S_FETCH_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Load IR from memory
S_FETCH_1: begin
//Set IR Reg
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 1;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Inc PC now that IR is loaded
S_FETCH_2: begin
//Inc PC
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 1;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Decode sequence
//-----
//Do nothing until the next state
S_DECODE_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU dont care
alu_op_out = 0;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//LDA_IMM sequence
//-----
//Pass incoming data from memory to the main buss
S_LDA_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A
S_LDA_IMM_1: begin
//Latch A
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//LDA_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_LDA_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_LDA_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M
S_LDA_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A
S_LDA_DIR_3: begin
//Latch A
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//STA_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_STA_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_STA_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set address and WE, also prepare A data on the main buss
S_STA_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//A (A input) passthrough to main bus
alu_op_out = OP_ALU_PASSA;
//Set WE so that the receiving device is ready for us to drive data
we_out = 1;
drive_out = 0;
end
//Drive the data out
S_STA_DIR_3: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//A (A input) passthrough to main bus
alu_op_out = OP_ALU_PASSA;
//Drive out A data
we_out = 1;
drive_out = 1;
end
//STA_IND sequence
//-----
//Pass incoming data from memory to the main buss
S_STA_IND_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_STA_IND_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Fetch data located at this address
S_STA_IND_2: begin
//Latch M
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_STA_IND_3: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set address and WE, also prepare A data on the main buss
S_STA_IND_4: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//A (A input) passthrough to main bus
alu_op_out = OP_ALU_PASSA;
//Set WE so that the receiving device is ready for us to drive data
we_out = 1;
drive_out = 0;
end
//Drive the data out
S_STA_IND_5: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//A (A input) passthrough to main bus
alu_op_out = OP_ALU_PASSA;
//Drive out A data
we_out = 1;
drive_out = 1;
end
//ADD_IMM sequence
//-----
//Add the incoming data from the operand that the PC is pointing to
S_ADD_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Addition
alu_op_out = OP_ALU_ADD;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_ADD_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Addition
alu_op_out = OP_ALU_ADD;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//ADD_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_ADD_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_ADD_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to add incoming data
S_ADD_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Addition
alu_op_out = OP_ALU_ADD;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_ADD_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Addition
alu_op_out = OP_ALU_ADD;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//SUB_IMM sequence
//-----
//Subtract the incoming data from the operand that the PC is pointing to
S_SUB_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Subtraction
alu_op_out = OP_ALU_SUB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_SUB_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Subtraction
alu_op_out = OP_ALU_SUB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//SUB_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_SUB_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_SUB_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to subtract incoming data
S_SUB_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Subtraction
alu_op_out = OP_ALU_SUB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_SUB_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Subtraction
alu_op_out = OP_ALU_SUB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//AND_IMM sequence
//-----
//And the incoming data from the operand that the PC is pointing to
S_AND_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Logical AND
alu_op_out = OP_ALU_AND;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_AND_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Logical AND
alu_op_out = OP_ALU_AND;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//AND_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_AND_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_AND_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to AND incoming data
S_AND_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Logical AND
alu_op_out = OP_ALU_AND;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_AND_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Logical AND
alu_op_out = OP_ALU_AND;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//OR_IMM sequence
//-----
//And the incoming data from the operand that the PC is pointing to
S_OR_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Logical OR
alu_op_out = OP_ALU_OR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_OR_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Logical OR
alu_op_out = OP_ALU_OR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//OR_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_OR_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_OR_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to OR incoming data
S_OR_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Logical OR
alu_op_out = OP_ALU_OR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_OR_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Logical OR
alu_op_out = OP_ALU_OR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//XOR_IMM sequence
//-----
//And the incoming data from the operand that the PC is pointing to
S_XOR_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Logical XOR
alu_op_out = OP_ALU_XOR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_XOR_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Logical XOR
alu_op_out = OP_ALU_XOR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//XOR_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_XOR_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_XOR_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to XOR incoming data
S_XOR_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Logical XOR
alu_op_out = OP_ALU_XOR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_XOR_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Logical XOR
alu_op_out = OP_ALU_XOR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//LSL_IMM sequence
//-----
//Add the incoming data from the operand that the PC is pointing to
S_LSL_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Logical Shift Left
alu_op_out = OP_ALU_LSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_LSL_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Logical Shift Left
alu_op_out = OP_ALU_LSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//LSL_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_LSL_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_LSL_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to add incoming data
S_LSL_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Logical Shift Left
alu_op_out = OP_ALU_LSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_LSL_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Logical Shift Left
alu_op_out = OP_ALU_LSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//LSR_IMM sequence
//-----
//Add the incoming data from the operand that the PC is pointing to
S_LSR_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Logical Shift Right
alu_op_out = OP_ALU_LSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_LSR_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Logical Shift Right
alu_op_out = OP_ALU_LSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//LSR_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_LSR_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_LSR_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to add incoming data
S_LSR_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Logical Shift Right
alu_op_out = OP_ALU_LSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_LSR_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Logical Shift Right
alu_op_out = OP_ALU_LSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//ASL_IMM sequence
//-----
//Add the incoming data from the operand that the PC is pointing to
S_ASL_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Arithmetic Shift Left
alu_op_out = OP_ALU_ASL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_ASL_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Arithmetic Shift Left
alu_op_out = OP_ALU_ASL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//ASL_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_ASL_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_ASL_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to add incoming data
S_ASL_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Arithmetic Shift Left
alu_op_out = OP_ALU_ASL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_ASL_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Arithmetic Shift Left
alu_op_out = OP_ALU_ASL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//ASR_IMM sequence
//-----
//Add the incoming data from the operand that the PC is pointing to
S_ASR_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Arithmetic Shift Right
alu_op_out = OP_ALU_ASR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_ASR_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Arithmetic Shift Right
alu_op_out = OP_ALU_ASR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//ASR_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_ASR_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_ASR_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to add incoming data
S_ASR_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Arithmetic Shift Right
alu_op_out = OP_ALU_ASR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_ASR_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Arithmetic Shift Right
alu_op_out = OP_ALU_ASR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//RSL_IMM sequence
//-----
//Add the incoming data from the operand that the PC is pointing to
S_RSL_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Rotary Shift Left
alu_op_out = OP_ALU_RSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_RSL_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Rotary Shift Left
alu_op_out = OP_ALU_RSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//RSL_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_RSL_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_RSL_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to add incoming data
S_RSL_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Rotary Shift Left
alu_op_out = OP_ALU_RSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_RSL_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Rotary Shift Left
alu_op_out = OP_ALU_RSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//RSR_IMM sequence
//-----
//Add the incoming data from the operand that the PC is pointing to
S_RSR_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Rotary Shift Right
alu_op_out = OP_ALU_RSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_RSR_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Rotary Shift Right
alu_op_out = OP_ALU_RSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//RSR_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_RSR_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_RSR_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to add incoming data
S_RSR_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Rotary Shift Right
alu_op_out = OP_ALU_RSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_RSR_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Rotary Shift Right
alu_op_out = OP_ALU_RSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//JMP_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_JMP_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to PC
S_JMP_DIR_1: begin
//Latch PC
set_a_out = 0;
set_m_out = 0;
set_pc_out = 1;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//JMP_IND sequence
//-----
//Pass incoming data from memory to the main buss
S_JMP_IND_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_JMP_IND_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M
S_JMP_IND_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to PC
S_JMP_IND_3: begin
//Latch PC
set_a_out = 0;
set_m_out = 0;
set_pc_out = 1;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Default (INVALID) sequence
//-----
default: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU dont care
alu_op_out = 0;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
endcase
end
//Next state logic
//--------------------------
always @ (curr_state, ir_op_buss_in, ccr_flag_zn_in, halt_in) begin
//DFT Output
dft_curr_state = curr_state;
//Next state logic
case(curr_state)
//Reset sequence (skips PC increment on boot)
S_RESET_0: next_state = S_FETCH_0;
//PC Increment
S_PC_INC_0: next_state = S_FETCH_0;
//Fetch sequence
S_FETCH_0: begin
if(halt_in == 1)
next_state = S_FETCH_0; //Remain in S_FETCH_0 forever if halt is asserted
else
next_state = S_FETCH_1; //Otherwise continue fetching this instruction
end
S_FETCH_1: next_state = S_FETCH_2;
S_FETCH_2: next_state = S_DECODE_0;
//Decode IR Opcode
S_DECODE_0: begin
case(ir_op_buss_in)
//IR_NOP (does nothing)
IR_NOP: next_state = S_FETCH_0;
//IR_LDA_IMM (load immediate value to A)
IR_LDA_IMM: next_state = S_LDA_IMM_0;
//IR_LDA_DIR (load direct value to A)
IR_LDA_DIR: next_state = S_LDA_DIR_0;
//IR_STA_DIR (store A at direct address)
IR_STA_DIR: next_state = S_STA_DIR_0;
//IR_STA_IND (store A at indirect address)
IR_STA_IND: next_state = S_STA_IND_0;
//IR_ADD_IMM (add immediate value to A)
IR_ADD_IMM: next_state = S_ADD_IMM_0;
//IR_ADD_DIR (add direct value to A)
IR_ADD_DIR: next_state = S_ADD_DIR_0;
//IR_SUB_IMM (subtract immediate value from A)
IR_SUB_IMM: next_state = S_SUB_IMM_0;
//IR_SUB_DIR (subtract direct value from A)
IR_SUB_DIR: next_state = S_SUB_DIR_0;
//IR_AND_IMM (logical AND immediate value with A)
IR_AND_IMM: next_state = S_AND_IMM_0;
//IR_AND_DIR (logical AND direct value with A)
IR_AND_DIR: next_state = S_AND_DIR_0;
//IR_OR_IMM (logical OR immediate value with A)
IR_OR_IMM: next_state = S_OR_IMM_0;
//IR_OR_DIR (logical OR direct value with A)
IR_OR_DIR: next_state = S_OR_DIR_0;
//IR_XOR_IMM (logical XOR immediate value with A)
IR_XOR_IMM: next_state = S_XOR_IMM_0;
//IR_XOR_DIR (logical XOR direct value with A)
IR_XOR_DIR: next_state = S_XOR_DIR_0;
//IR_LSL_IMM (logical left shift immediate value with A)
IR_LSL_IMM: next_state = S_LSL_IMM_0;
//IR_LSL_DIR (logical left shift direct value with A)
IR_LSL_DIR: next_state = S_LSL_DIR_0;
//IR_LSR_IMM (logical right shift immediate value with A)
IR_LSR_IMM: next_state = S_LSR_IMM_0;
//IR_LSR_DIR (logical right shift direct value with A)
IR_LSR_DIR: next_state = S_LSR_DIR_0;
//IR_ASL_IMM (arithmetic left shift immediate value with A)
IR_ASL_IMM: next_state = S_ASL_IMM_0;
//IR_ASL_DIR (arithmetic left shift direct value with A)
IR_ASL_DIR: next_state = S_ASL_DIR_0;
//IR_ASR_IMM (arithmetic right shift immediate value with A)
IR_ASR_IMM: next_state = S_ASR_IMM_0;
//IR_ASR_DIR (arithmetic right shift direct value with A)
IR_ASR_DIR: next_state = S_ASR_DIR_0;
//IR_RSL_IMM (rotary left shift immediate value with A)
IR_RSL_IMM: next_state = S_RSL_IMM_0;
//IR_RSL_DIR (rotary left shift direct value with A)
IR_RSL_DIR: next_state = S_RSL_DIR_0;
//IR_RSR_IMM (rotary right shift immediate value with A)
IR_RSR_IMM: next_state = S_RSR_IMM_0;
//IR_RSR_DIR (rotary right shift direct value with A)
IR_RSR_DIR: next_state = S_RSR_DIR_0;
//IR_JMP_DIR (load direct value to PC)
IR_JMP_DIR: next_state = S_JMP_DIR_0;
//IR_LDA_DIR (load indirect value to PC)
IR_JMP_IND: next_state = S_JMP_IND_0;
//IR_BNE_DIR (banch if z clear direct)
IR_BNE_DIR: begin
if(ccr_flag_zn_in[1] == 0)
next_state = S_JMP_DIR_0;
else
next_state = S_PC_INC_0;
end
//IR_BNE_IND (banch if z clear indirect)
IR_BNE_IND: begin
if(ccr_flag_zn_in[1] == 0)
next_state = S_JMP_IND_0;
else
next_state = S_PC_INC_0;
end
//IR_BEQ_DIR (banch if z set direct)
IR_BEQ_DIR: begin
if(ccr_flag_zn_in[1] == 1)
next_state = S_JMP_DIR_0;
else
next_state = S_PC_INC_0;
end
//IR_BEQ_IND (banch if z set indirect)
IR_BEQ_IND: begin
if(ccr_flag_zn_in[1] == 1)
next_state = S_JMP_IND_0;
else
next_state = S_PC_INC_0;
end
//IR_BPL_DIR (banch if n clear direct)
IR_BPL_DIR: begin
if(ccr_flag_zn_in[0] == 0)
next_state = S_JMP_DIR_0;
else
next_state = S_PC_INC_0;
end
//IR_BPL_IND (banch if n clear indirect)
IR_BPL_IND: begin
if(ccr_flag_zn_in[0] == 0)
next_state = S_JMP_IND_0;
else
next_state = S_PC_INC_0;
end
//IR_BMI_DIR (banch if n set direct)
IR_BMI_DIR: begin
if(ccr_flag_zn_in[0] == 1)
next_state = S_JMP_DIR_0;
else
next_state = S_PC_INC_0;
end
//IR_BMI_IND (banch if n set indirect)
IR_BMI_IND: begin
if(ccr_flag_zn_in[0] == 1)
next_state = S_JMP_IND_0;
else
next_state = S_PC_INC_0;
end
//Invalid IR, goto fetch_0
default: next_state = S_FETCH_0;
endcase
end
//LDA_IMM sequence
S_LDA_IMM_0: next_state = S_LDA_IMM_1;
S_LDA_IMM_1: next_state = S_PC_INC_0;
//LDA_DIR sequence
S_LDA_DIR_0: next_state = S_LDA_DIR_1;
S_LDA_DIR_1: next_state = S_LDA_DIR_2;
S_LDA_DIR_2: next_state = S_LDA_DIR_3;
S_LDA_DIR_3: next_state = S_PC_INC_0;
//STA_DIR sequence
S_STA_DIR_0: next_state = S_STA_DIR_1;
S_STA_DIR_1: next_state = S_STA_DIR_2;
S_STA_DIR_2: next_state = S_STA_DIR_3;
S_STA_DIR_3: next_state = S_PC_INC_0;
//STA_IND sequence
S_STA_IND_0: next_state = S_STA_IND_1;
S_STA_IND_1: next_state = S_STA_IND_2;
S_STA_IND_2: next_state = S_STA_IND_3;
S_STA_IND_3: next_state = S_STA_IND_4;
S_STA_IND_4: next_state = S_STA_IND_5;
S_STA_IND_5: next_state = S_PC_INC_0;
//ADD_IMM sequence
S_ADD_IMM_0: next_state = S_ADD_IMM_1;
S_ADD_IMM_1: next_state = S_PC_INC_0;
//ADD_DIR sequence
S_ADD_DIR_0: next_state = S_ADD_DIR_1;
S_ADD_DIR_1: next_state = S_ADD_DIR_2;
S_ADD_DIR_2: next_state = S_ADD_DIR_3;
S_ADD_DIR_3: next_state = S_PC_INC_0;
//SUB_IMM sequence
S_SUB_IMM_0: next_state = S_SUB_IMM_1;
S_SUB_IMM_1: next_state = S_PC_INC_0;
//SUB_DIR sequence
S_SUB_DIR_0: next_state = S_SUB_DIR_1;
S_SUB_DIR_1: next_state = S_SUB_DIR_2;
S_SUB_DIR_2: next_state = S_SUB_DIR_3;
S_SUB_DIR_3: next_state = S_PC_INC_0;
//AND_IMM sequence
S_AND_IMM_0: next_state = S_AND_IMM_1;
S_AND_IMM_1: next_state = S_PC_INC_0;
//AND_DIR sequence
S_AND_DIR_0: next_state = S_AND_DIR_1;
S_AND_DIR_1: next_state = S_AND_DIR_2;
S_AND_DIR_2: next_state = S_AND_DIR_3;
S_AND_DIR_3: next_state = S_PC_INC_0;
//OR_IMM sequence
S_OR_IMM_0: next_state = S_OR_IMM_1;
S_OR_IMM_1: next_state = S_PC_INC_0;
//OR_DIR sequence
S_OR_DIR_0: next_state = S_OR_DIR_1;
S_OR_DIR_1: next_state = S_OR_DIR_2;
S_OR_DIR_2: next_state = S_OR_DIR_3;
S_OR_DIR_3: next_state = S_PC_INC_0;
//XOR_IMM sequence
S_XOR_IMM_0: next_state = S_XOR_IMM_1;
S_XOR_IMM_1: next_state = S_PC_INC_0;
//XOR_DIR sequence
S_XOR_DIR_0: next_state = S_XOR_DIR_1;
S_XOR_DIR_1: next_state = S_XOR_DIR_2;
S_XOR_DIR_2: next_state = S_XOR_DIR_3;
S_XOR_DIR_3: next_state = S_PC_INC_0;
//LSL_IMM sequence
S_LSL_IMM_0: next_state = S_LSL_IMM_1;
S_LSL_IMM_1: next_state = S_PC_INC_0;
//LSL_DIR sequence
S_LSL_DIR_0: next_state = S_LSL_DIR_1;
S_LSL_DIR_1: next_state = S_LSL_DIR_2;
S_LSL_DIR_2: next_state = S_LSL_DIR_3;
S_LSL_DIR_3: next_state = S_PC_INC_0;
//LSR_IMM sequence
S_LSR_IMM_0: next_state = S_LSR_IMM_1;
S_LSR_IMM_1: next_state = S_PC_INC_0;
//LSR_DIR sequence
S_LSR_DIR_0: next_state = S_LSR_DIR_1;
S_LSR_DIR_1: next_state = S_LSR_DIR_2;
S_LSR_DIR_2: next_state = S_LSR_DIR_3;
S_LSR_DIR_3: next_state = S_PC_INC_0;
//ASL_IMM sequence
S_ASL_IMM_0: next_state = S_ASL_IMM_1;
S_ASL_IMM_1: next_state = S_PC_INC_0;
//ASL_DIR sequence
S_ASL_DIR_0: next_state = S_ASL_DIR_1;
S_ASL_DIR_1: next_state = S_ASL_DIR_2;
S_ASL_DIR_2: next_state = S_ASL_DIR_3;
S_ASL_DIR_3: next_state = S_PC_INC_0;
//ASR_IMM sequence
S_ASR_IMM_0: next_state = S_ASR_IMM_1;
S_ASR_IMM_1: next_state = S_PC_INC_0;
//ASR_DIR sequence
S_ASR_DIR_0: next_state = S_ASR_DIR_1;
S_ASR_DIR_1: next_state = S_ASR_DIR_2;
S_ASR_DIR_2: next_state = S_ASR_DIR_3;
S_ASR_DIR_3: next_state = S_PC_INC_0;
//RSL_IMM sequence
S_RSL_IMM_0: next_state = S_RSL_IMM_1;
S_RSL_IMM_1: next_state = S_PC_INC_0;
//RSL_DIR sequence
S_RSL_DIR_0: next_state = S_RSL_DIR_1;
S_RSL_DIR_1: next_state = S_RSL_DIR_2;
S_RSL_DIR_2: next_state = S_RSL_DIR_3;
S_RSL_DIR_3: next_state = S_PC_INC_0;
//RSR_IMM sequence
S_RSR_IMM_0: next_state = S_RSR_IMM_1;
S_RSR_IMM_1: next_state = S_PC_INC_0;
//RSR_DIR sequence
S_RSR_DIR_0: next_state = S_RSR_DIR_1;
S_RSR_DIR_1: next_state = S_RSR_DIR_2;
S_RSR_DIR_2: next_state = S_RSR_DIR_3;
S_RSR_DIR_3: next_state = S_PC_INC_0;
//JMP_DIR sequence
S_JMP_DIR_0: next_state = S_JMP_DIR_1;
S_JMP_DIR_1: next_state = S_FETCH_0;
//JMP_IND sequence
S_JMP_IND_0: next_state = S_JMP_IND_1;
S_JMP_IND_1: next_state = S_JMP_IND_2;
S_JMP_IND_2: next_state = S_JMP_IND_3;
S_JMP_IND_3: next_state = S_FETCH_0;
//Should never get here
default:
next_state = S_PC_INC_0;
endcase
end
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//---------------------------------------------------------------------------------------------------------
// MINIBYTE ALU
//---------------------------------------------------------------------------------------------------------
// OPERATION | ALU_OP | MEANING
//---------------------------------------------------------------------------------------------------------
// PASSA | 0b0000 | Passthrough input A
// PASSB | 0b0001 | Passthrough input B
// ADD | 0b0010 | Add A and B
// SUB | 0b0011 | Subtract B from A
// AND | 0b0100 | Logical and of A, B
// OR | 0b0101 | Logical or of A, B
// XOR | 0b0110 | Logical xor of A, B
// LSL | 0b0111 | Logical shift A left by B
// LSR | 0b1000 | Logical shift A right by B
// ASL | 0b1001 | Arithmetic shift A left by B
// ASR | 0b1010 | Arithmetic shift A right by B
// RSL | 0b1011 | Rotary shift A left by B
// RSR | 0b1100 | Rotary shift A right by B
//---------------------------------------------------------------------------------------------------------
//--------------------------
//Params
//--------------------------
parameter ALU_PASSA = 4'b0000;
parameter ALU_PASSB = 4'b0001;
parameter ALU_ADD = 4'b0010;
parameter ALU_SUB = 4'b0011;
parameter ALU_AND = 4'b0100;
parameter ALU_OR = 4'b0101;
parameter ALU_XOR = 4'b0110;
parameter ALU_LSL = 4'b0111;
parameter ALU_LSR = 4'b1000;
parameter ALU_ASL = 4'b1001;
parameter ALU_ASR = 4'b1010;
parameter ALU_RSL = 4'b1011;
parameter ALU_RSR = 4'b1100;
//--------------------------
//ALU Module
//--------------------------
module minibyte_alu (
//ALU Inputs
input wire signed [7:0] a_in,
input wire signed [7:0] b_in,
input wire [3:0] alu_op_in,
//ALU Outputs
output reg signed [7:0] res_out,
output reg [1:0] flags_zn_out
);
//Main Procedural Block
//--------------------------
always @(*) begin
//Assign ALU result
//---------------------
case(alu_op_in)
//A Passthrough
//--------------
ALU_PASSA:
res_out = a_in;
//B Passthrough
//--------------
ALU_PASSB:
res_out = b_in;
//Addition
//--------------
ALU_ADD:
res_out = a_in + b_in;
//Subtraction
//--------------
ALU_SUB:
res_out = a_in - b_in;
//Logical AND
//--------------
ALU_AND:
res_out = a_in & b_in;
//Logical OR
//--------------
ALU_OR:
res_out = a_in | b_in;
//Logical XOR
//--------------
ALU_XOR:
res_out = a_in ^ b_in;
//Logical Shift Left
//--------------
ALU_LSL:
res_out = a_in << b_in;
//Logical Shift Right
//--------------
ALU_LSR:
res_out = a_in >> b_in;
//Arithmetic Shift Left
//--------------
ALU_ASL:
res_out = a_in <<< b_in;
//Arithmetic Shift Right
//--------------
ALU_ASR:
res_out = a_in >>> b_in;
//Rotary Shift Left
//--------------
ALU_RSL:
case(b_in[2:0])
//Hardcoded concatenations of all possible inputs
3'b000:
res_out = a_in;
3'b001:
res_out = {a_in[6:0], a_in[7]};
3'b010:
res_out = {a_in[5:0], a_in[7:6]};
3'b011:
res_out = {a_in[4:0], a_in[7:5]};
3'b100:
res_out = {a_in[3:0], a_in[7:4]};
3'b101:
res_out = {a_in[2:0], a_in[7:3]};
3'b110:
res_out = {a_in[1:0], a_in[7:2]};
3'b111:
res_out = {a_in[0], a_in[7:1]};
endcase
//Rotary Shift Right
//--------------
ALU_RSR:
case(b_in[2:0])
//Hardcoded concatenations of all possible inputs
3'b000:
res_out = a_in;
3'b001:
res_out = {a_in[0], a_in[7:1]};
3'b010:
res_out = {a_in[1:0], a_in[7:2]};
3'b011:
res_out = {a_in[2:0], a_in[7:3]};
3'b100:
res_out = {a_in[3:0], a_in[7:4]};
3'b101:
res_out = {a_in[4:0], a_in[7:5]};
3'b110:
res_out = {a_in[5:0], a_in[7:6]};
3'b111:
res_out = {a_in[6:0], a_in[7]};
endcase
//Default (SHOULD NEVER GET HERE)
//--------------
default:
res_out = 0;
endcase
//Assign Zero flag
//---------------------
if(res_out == 0)
flags_zn_out[1] = 1;
else
flags_zn_out[1] = 0;
//Assign Negative flag
//---------------------
flags_zn_out[0] = res_out[7];
end
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//--------------------------
//General Register Module
//--------------------------
module minibyte_genreg (
//Basic Inputs
input wire clk_in, rst_in,
//Register Inputs
input wire [7:0] reg_in,
input wire set_in,
//Register Outputs
output reg [7:0] reg_out
);
//Main Procedural Block
//--------------------------
always @(posedge clk_in or negedge rst_in) begin
//Reset if rst goes low
if(!rst_in)
reg_out <= 0;
else
//Set register to input if set signal goes high on a clk
if(set_in)
reg_out <= reg_in;
end
endmodule
//--------------------------
//CCR Register Module
//--------------------------
module minibyte_ccrreg (
//Basic Inputs
input wire clk_in, rst_in,
//Register Inputs
input wire [1:0] reg_in,
input wire set_in,
//Register Outputs
output reg [1:0] reg_out
);
//Main Procedural Block
//--------------------------
always @(posedge clk_in or negedge rst_in) begin
//Reset if rst goes low
if(!rst_in)
reg_out <= 0;
else
//Set register to input if set signal goes high on a clk
if(set_in)
reg_out <= reg_in;
end
endmodule
//---------------------------------
//Program Counter Register Module
//---------------------------------
module minibyte_pcreg (
//Basic Inputs
input wire clk_in, rst_in,
//Register Inputs
input wire [7:0] reg_in,
input wire set_in,
input wire inc_in,
//Register Outputs
output reg [7:0] reg_out
);
//Main Procedural Block
//--------------------------
always @(posedge clk_in or negedge rst_in) begin
//Reset if rst goes low
if(!rst_in)
reg_out <= 0;
else
//Set register to input if set signal goes high
if(set_in)
reg_out <= reg_in;
//Increment register if inc signal goes high on a clk
else if(inc_in)
reg_out <= reg_out + 1;
end
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//---------------------------------
//Generic 2->1 Mux Module
//---------------------------------
module minibyte_genmux_2x(
//Mux Inputs
input wire [7:0] a_in,
input wire [7:0] b_in,
//Mux Select
input wire sel_in,
//Mux Output
output reg [7:0] mux_out
);
//Main Procedural Block
//--------------------------
always @(*) begin
//A out if sel is 0
if(sel_in == 0)
mux_out = a_in;
//B out if sel is 1
else
mux_out = b_in;
end
endmodule
//---------------------------------
//Generic 4->1 Mux Module
//---------------------------------
module minibyte_genmux_4x(
//Mux Inputs
input wire [7:0] a_in,
input wire [7:0] b_in,
input wire [7:0] c_in,
input wire [7:0] d_in,
//Mux Select
input wire [1:0] sel_in,
//Mux Output
output reg [7:0] mux_out
);
//Main Procedural Block
//--------------------------
always @(*) begin
//A out if sel is 00
if(sel_in == 2'b00)
mux_out = a_in;
//B out if sel is 01
else if(sel_in == 2'b01)
mux_out = b_in;
//C out if sel is 10
else if(sel_in == 2'b10)
mux_out = c_in;
//D out if sel is 11
else
mux_out = d_in;
end
endmodule
//---------------------------------
//Generic 8->1 Mux Module
//---------------------------------
module minibyte_genmux_8x(
//Mux Inputs
input wire [7:0] a_in,
input wire [7:0] b_in,
input wire [7:0] c_in,
input wire [7:0] d_in,
input wire [7:0] e_in,
input wire [7:0] f_in,
input wire [7:0] g_in,
input wire [7:0] h_in,
//Mux Select
input wire [2:0] sel_in,
//Mux Output
output reg [7:0] mux_out
);
//Main Procedural Block
//--------------------------
always @(*) begin
//A out if sel is 000
if(sel_in == 3'b000)
mux_out = a_in;
//B out if sel is 001
else if(sel_in == 3'b001)
mux_out = b_in;
//C out if sel is 010
else if(sel_in == 3'b010)
mux_out = c_in;
//D out if sel is 011
else if(sel_in == 3'b011)
mux_out = d_in;
//E out if sel is 100
else if(sel_in == 3'b100)
mux_out = e_in;
//F out if sel is 101
else if(sel_in == 3'b101)
mux_out = f_in;
//G out if sel is 110
else if(sel_in == 3'b110)
mux_out = g_in;
//H out if sel is 111
else
mux_out = h_in;
end
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//---------------------------------
//Drive enable device
//---------------------------------
module drive_enable_fanout(
//Drive enable input signal
input wire drive_en,
//Output drive signals
output reg [7:0] drive
);
//Main Procedural Block
//--------------------------
always @(*) begin
if(drive_en == 0)
drive = 0;
else
drive = 8'hff;
end
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//CPU IR opcodes
//--------------------------
parameter _NOP = 8'h00;
parameter _LDA_IMM = 8'h01;
parameter _LDA_DIR = 8'h02;
parameter _STA_DIR = 8'h03;
//parameter _STA_IND = 8'h04;
parameter _ADD_IMM = 8'h05;
//parameter _ADD_DIR = 8'h06;
//parameter _SUB_IMM = 8'h07;
//parameter _SUB_DIR = 8'h08;
//parameter _AND_IMM = 8'h09;
//parameter _AND_DIR = 8'h0A;
//parameter _OR_IMM = 8'h0B;
//parameter _OR_DIR = 8'h0C;
//parameter _XOR_IMM = 8'h0D;
//parameter _XOR_DIR = 8'h0E;
parameter _LSL_IMM = 8'h0F;
//parameter _LSL_DIR = 8'h10;
//parameter _LSR_IMM = 8'h11;
//parameter _LSR_DIR = 8'h12;
//parameter _ASL_IMM = 8'h13;
//parameter _ASL_DIR = 8'h14;
//parameter _ASR_IMM = 8'h15;
//parameter _ASR_DIR = 8'h16;
//parameter _RSL_IMM = 8'h17;
//parameter _RSL_DIR = 8'h18;
//parameter _RSR_IMM = 8'h19;
//parameter _RSR_DIR = 8'h1A;
parameter _JMP_DIR = 8'h1B;
//parameter _JMP_IND = 8'h1C;
parameter _BNE_DIR = 8'h1D;
//parameter _BNE_IND = 8'h1E;
//parameter _BEQ_DIR = 8'h1F;
//parameter _BEQ_IND = 8'h20;
parameter _BPL_DIR = 8'h21;
//parameter _BPL_IND = 8'h22;
//parameter _BMI_DIR = 8'h23;
//parameter _BMI_IND = 8'h24;
//--------------------------
//Demo ROM Program
//--------------------------
module demo_rom_64B(
//Input Addr
input wire [5:0] address,
//Output Data
output reg [7:0] data_out
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//--------------------------
//REGISTER RAM
//--------------------------
module reg_ram_8B(
//Input CLK and RST
input wire clk_in,
input wire rst_in,
//Input Addr
input wire [2:0] address,
//Input Data
input wire [7:0] data_in,
//Input WE and EN
input wire we_in,
input wire en_in,
//Output Data
output reg [7:0] data_out
);
//Data busses
//------------------------------------
reg [7:0] r_we;
reg [7:0] r0_out_data;
reg [7:0] r1_out_data;
reg [7:0] r2_out_data;
reg [7:0] r3_out_data;
reg [7:0] r4_out_data;
reg [7:0] r5_out_data;
reg [7:0] r6_out_data;
reg [7:0] r7_out_data;
//Data registers
//------------------------------------
minibyte_genreg r0(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[0]),
//Register Outputs
.reg_out(r0_out_data)
);
minibyte_genreg r1(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[1]),
//Register Outputs
.reg_out(r1_out_data)
);
minibyte_genreg r2(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[2]),
//Register Outputs
.reg_out(r2_out_data)
);
minibyte_genreg r3(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[3]),
//Register Outputs
.reg_out(r3_out_data)
);
minibyte_genreg r4(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[4]),
//Register Outputs
.reg_out(r4_out_data)
);
minibyte_genreg r5(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[5]),
//Register Outputs
.reg_out(r5_out_data)
);
minibyte_genreg r6(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[6]),
//Register Outputs
.reg_out(r6_out_data)
);
minibyte_genreg r7(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[7]),
//Register Outputs
.reg_out(r7_out_data)
);
//Register control logic
//------------------------------------
always @ (*) begin
if (!en_in) begin
data_out = 8'h00;
r_we = 8'h00;
end
else if (we_in) begin
case(address)
3'b000:
r_we = 8'b00000001;
3'b001:
r_we = 8'b00000010;
3'b010:
r_we = 8'b00000100;
3'b011:
r_we = 8'b00001000;
3'b100:
r_we = 8'b00010000;
3'b101:
r_we = 8'b00100000;
3'b110:
r_we = 8'b01000000;
3'b111:
r_we = 8'b10000000;
default:
r_we = 8'b00000000;
endcase
data_out = 8'h00;
end
else begin
case(address)
3'b000:
data_out = r0_out_data;
3'b001:
data_out = r1_out_data;
3'b010:
data_out = r2_out_data;
3'b011:
data_out = r3_out_data;
3'b100:
data_out = r4_out_data;
3'b101:
data_out = r5_out_data;
3'b110:
data_out = r6_out_data;
3'b111:
data_out = r7_out_data;
endcase
r_we = 8'h00;
end
end
endmodule
|
module demo_rom_64B(
//Input Addr
input wire [5:0] address,
//Output Data
output reg [7:0] data_out
);
always @(address)
case(address)
6'h00: data_out = _NOP; //First istr is a NOP
6'h01: data_out = _LDA_IMM; //Make sure A is zero
6'h02: data_out = 0;
6'h03: data_out = _NOP; //NOP is the START of the LOOP0
6'h04: data_out = _ADD_IMM; //ADD 1 to A
6'h05: data_out = 1;
6'h06: data_out = _STA_DIR; //Write this value to 0x40
6'h07: data_out = 8'h40;
6'h08: data_out = _BNE_DIR; //Keep branching to LOOP0 until we roll over to 0
6'h09: data_out = 8'h03;
6'h0A: data_out = _LDA_IMM; //Load a 1 into A
6'h0B: data_out = 1;
6'h0C: data_out = _STA_DIR; //Write this value to 0x40
6'h0D: data_out = 8'h40;
6'h0E: data_out = _NOP; //NOP is the START of the LOOP1
6'h0F: data_out = _LSL_IMM; //Shift A left by 1
6'h10: data_out = 1;
6'h11: data_out = _STA_DIR; //Write this value to 0x40
6'h12: data_out = 8'h40;
6'h13: data_out = _BPL_DIR; //Keep branching to LOOP1 until we hit 0b10000000
6'h14: data_out = 8'h0E;
6'h15: data_out = _LDA_IMM; //Load DEADBEEF into RAM
6'h16: data_out = 8'hDE;
6'h17: data_out = _STA_DIR;
6'h18: data_out = 8'h78;
6'h19: data_out = _LDA_IMM;
6'h1A: data_out = 8'hAD;
6'h1B: data_out = _STA_DIR;
6'h1C: data_out = 8'h79;
6'h1D: data_out = _LDA_IMM;
6'h1E: data_out = 8'hBE;
6'h1F: data_out = _STA_DIR;
6'h20: data_out = 8'h7A;
6'h21: data_out = _LDA_IMM;
6'h22: data_out = 8'hEF;
6'h23: data_out = _STA_DIR;
6'h24: data_out = 8'h7B;
6'h25: data_out = _LDA_DIR; //READ out the contents of RAM
6'h26: data_out = 8'h78;
6'h27: data_out = _STA_DIR; //Write this value to 0x40
6'h28: data_out = 8'h40;
6'h29: data_out = _LDA_DIR; //READ out the contents of RAM
6'h2A: data_out = 8'h79;
6'h2B: data_out = _STA_DIR; //Write this value to 0x40
6'h2C: data_out = 8'h40;
6'h2D: data_out = _LDA_DIR; //READ out the contents of RAM
6'h2E: data_out = 8'h7A;
6'h2F: data_out = _STA_DIR; //Write this value to 0x40
6'h30: data_out = 8'h40;
6'h31: data_out = _LDA_DIR; //READ out the contents of RAM
6'h32: data_out = 8'h7B;
6'h33: data_out = _STA_DIR; //Write this value to 0x40
6'h34: data_out = 8'h40;
6'h35: data_out = _JMP_DIR; //Start the whole thing over!
6'h36: data_out = 8'h00;
default: data_out = 0; //Unused space
endcase
endmodule
|
tt06-finale_0098
|
tt06-finale
|
zacharysfrazee-tt06-minibyte-cpu
|
task_drive_enable_fanout
|
tt_um_minibyte
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//---------------------------------
//Top Level Project Module
//---------------------------------
module tt_um_minibyte (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
//---------------------------------
//Top Level Singal Notes
//---------------------------------
//ui_in => Test and Configuration bits
//uo_out => WE and 7-bit Address Buss
//uio_in/uio_out => 8-bit Bidirectional Data Buss
//uio_oe => Output Enable for Data Buss
//---------------------------------
//ui_in (Test)
// bit[7] => ENABLE ONBOARD REG RAM
// bit[6:5] => UNUSED
// bit[4] => ENABLE DEMO ROM
// bit[3] => HALT CONTROL UNIT
// bit[2:0] => DEBUG OUTPUT SIGNAL CONTROL
// 0 -> Normal output
// 1 -> A output
// 2 -> A (UPPER BIT) output
// 3 -> M output
// 4 -> PC output
// 5 -> IR output
// 6 -> CCR output
// 7 -> CU STATE output
//---------------------------------
//uio_in/uio_out
// bit[7] => WE (Write Enable)
// bit[6:0] => Address Buss
//---------------------------------
//---------------------------------
//Wires
//---------------------------------
wire [6:0] address_buss;
wire we_signal;
wire [7:0] tm_control_bits;
wire [7:0] data_buss_in;
wire [7:0] data_buss_out;
wire [7:0] data_buss_oe;
wire [7:0] data_buss_rom;
wire [7:0] data_buss_ram;
wire [7:0] data_buss_muxed_in;
wire drive_enable_sig;
wire nc_addr_buss_bit_7;
//---------------------------------
//Assignments
//---------------------------------
assign uo_out[6:0] = address_buss;
assign uo_out[7] = we_signal;
assign tm_control_bits = ui_in;
assign data_buss_in = uio_in;
assign uio_out = data_buss_out;
assign uio_oe = data_buss_oe;
//---------------------------------
//Minibyte CPU
//---------------------------------
minibyte_cpu cpu(
//Basic Inputs
.clk_in(clk), .ena_in(ena), .rst_in(rst_n),
.halt_in(tm_control_bits[3]),
//Memory and IO Inputs
.data_in(data_buss_muxed_in),
//DFT Inputs
.tm_control({tm_control_bits[2:0]}),
//Memory and IO Outputs
.addr_out ({nc_addr_buss_bit_7,address_buss}), //Only 7 bits get connected as we need to save one output for WE below:(
.data_out (data_buss_out),
.we_out (we_signal), //Dedicated output bit 7 gets used for WE
.drive_out (drive_enable_sig)
);
//---------------------------------
//Input Device MUX
//---------------------------------
reg [1:0] input_mux_control;
always @ (tm_control_bits, reg_ram_active) begin
//Enable Onboard RAM
if(tm_control_bits[7] == 1 && reg_ram_active)
input_mux_control = 2'b11;
//Enable Demo ROM
else if(tm_control_bits[4] == 1)
input_mux_control = 2'b01;
//Enable Normal Input
else
input_mux_control = 2'b00;
end
minibyte_genmux_4x input_mux(
//Mux Inputs
.a_in(data_buss_in),
.b_in(data_buss_rom),
.c_in(8'h00),
.d_in(data_buss_ram),
//Mux Select
.sel_in(input_mux_control),
//Mux Output
.mux_out(data_buss_muxed_in)
);
//---------------------------------
//Demo ROM
//---------------------------------
demo_rom_64B rom(
//Input Addr and Enable
.address(address_buss[5:0]), //Lower 6 addr buss bits
//Output Data
.data_out(data_buss_rom)
);
//---------------------------------
//Onboard REG RAM
//---------------------------------
reg reg_ram_active;
//Register ram is only active for addresses
//0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f
always @ (address_buss) begin
if(address_buss >= 7'h78)
reg_ram_active = 1;
else
reg_ram_active = 0;
end
reg_ram_8B ram(
//Input CLK and RST
.clk_in(clk),
.rst_in(rst_n),
//Input Addr
.address(address_buss[2:0]),
//Input Data
.data_in(data_buss_out),
//Input WE
.we_in(we_signal),
.en_in(reg_ram_active),
//Output Data
.data_out(data_buss_ram)
);
//---------------------------------
//Output enable control
//---------------------------------
drive_enable_fanout oe_driver(
//Drive enable input signal
.drive_en(drive_enable_sig),
//Output drive signals
.drive(data_buss_oe)
);
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//---------------------------------
//Top Level CPU Module
//---------------------------------
module minibyte_cpu (
//Basic Inputs
input wire clk_in, ena_in, rst_in,
input wire halt_in,
//Memory and IO Inputs
input wire [7:0] data_in,
//DFT Testmode Inputs
input wire [2:0] tm_control,
//Memory and IO Outputs
output wire [7:0] addr_out,
output wire [7:0] data_out,
output wire we_out,
output wire drive_out
);
//Main Data Buss
//--------------------------------
wire [7:0] main_buss;
//Data out comes from the main buss
assign data_out = main_buss;
//ALU A-Side Input Data Buss
//--------------------------------
wire [7:0] alu_a_buss;
//Address Busses
//--------------------------------
wire [7:0] m_addr_buss;
wire [7:0] pc_addr_buss;
wire [7:0] ir_op_buss;
wire [7:0] normal_addr_out;
//DFT Wires
//--------------------------------
wire [7:0] dft_cu_state;
//Control Signals
//--------------------------------
//Set register signals
wire ctrl_set_a;
wire ctrl_set_m;
wire ctrl_set_pc;
wire ctrl_set_ir;
wire ctrl_set_ccr;
//Inc register signals
wire ctrl_inc_pc;
//Addr mux signals
wire ctrl_addr_mux;
//Alu control signals
wire [3:0] ctrl_alu_op;
//Data direction control
wire ctrl_we_out;
wire ctrl_drive_out;
assign we_out=ctrl_we_out;
assign drive_out=ctrl_drive_out;
//Branch Signals
//--------------------------------
wire [1:0] flags_zn_buss;
wire [1:0] ccr_zn_buss;
//A Register
//--------------------------------
minibyte_genreg reg_a(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(main_buss),
.set_in(ctrl_set_a),
//Register Outputs
.reg_out(alu_a_buss)
);
//M Register
//--------------------------------
minibyte_genreg reg_m(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(main_buss),
.set_in(ctrl_set_m),
//Register Outputs
.reg_out(m_addr_buss)
);
//PC Register
//--------------------------------
minibyte_pcreg reg_pc(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(main_buss),
.set_in(ctrl_set_pc),
.inc_in(ctrl_inc_pc),
//Register Outputs
.reg_out(pc_addr_buss)
);
//IR Register
//--------------------------------
minibyte_genreg reg_ir(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(main_buss),
.set_in(ctrl_set_ir),
//Register Outputs
.reg_out(ir_op_buss)
);
//CCR Register
//--------------------------------
minibyte_ccrreg reg_ccr(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(flags_zn_buss),
.set_in(ctrl_set_ccr),
//Register Outputs
.reg_out(ccr_zn_buss)
);
//Addr Out Mux
//--------------------------------
minibyte_genmux_2x addr_mux(
//Mux Inputs
.a_in(pc_addr_buss),
.b_in(m_addr_buss),
//Mux Select
.sel_in(ctrl_addr_mux),
//Mux Output
.mux_out(normal_addr_out)
);
//Debug Out Mux
//--------------------------------
minibyte_genmux_8x tm_debug_out_mux(
//Mux Inputs
.a_in(normal_addr_out), //0 -> Normal output
.b_in(alu_a_buss), //1 -> A output
.c_in({7'h0, alu_a_buss[7]}), //2 -> A (UPPER BIT) output
.d_in(m_addr_buss), //3 -> M output
.e_in(pc_addr_buss), //4 -> PC output
.f_in(ir_op_buss), //5 -> IR output
.g_in({6'h0,ccr_zn_buss}), //6 -> CCR output
.h_in(dft_cu_state), //7 -> CU STATE output
//Mux Select
.sel_in(tm_control[2:0]),
//Mux Output
.mux_out(addr_out)
);
//ALU
//--------------------------------
minibyte_alu alu(
//ALU Inputs
.a_in(alu_a_buss),
.b_in(data_in),
.alu_op_in(ctrl_alu_op),
.res_out(main_buss),
.flags_zn_out(flags_zn_buss)
);
//Control Unit
//--------------------------------
minibyte_cu cu(
//Basic Inputs
.clk_in(clk_in), .ena_in(ena_in), .rst_in(rst_in),
.halt_in(halt_in),
//IR Input
.ir_op_buss_in(ir_op_buss),
//ALU Flags Input
.ccr_flag_zn_in(ccr_zn_buss),
//Control signal outputs
.set_a_out(ctrl_set_a),
.set_m_out(ctrl_set_m),
.set_pc_out(ctrl_set_pc),
.set_ir_out(ctrl_set_ir),
.set_ccr_out(ctrl_set_ccr),
.inc_pc_out(ctrl_inc_pc),
//Addr select signals
.addr_mux_out(ctrl_addr_mux),
//Alu control signals
.alu_op_out(ctrl_alu_op),
//Write to memory
.we_out(ctrl_we_out),
//Drive enable on data bus
.drive_out(ctrl_drive_out),
//DFT Output
.dft_curr_state(dft_cu_state)
);
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//---------------------------------
//Control Unit
//---------------------------------
module minibyte_cu(
//Basic Inputs
input wire clk_in, ena_in, rst_in,
input wire halt_in,
//IR Input
input wire [7:0] ir_op_buss_in,
//ALU Flags Input
input wire [1:0] ccr_flag_zn_in,
//Control signal outputs
output reg set_a_out,
output reg set_m_out,
output reg set_pc_out,
output reg set_ir_out,
output reg set_ccr_out,
output reg inc_pc_out,
//Addr select signals
output reg addr_mux_out,
//Alu control signals
output reg [3:0] alu_op_out,
//Write to memory
output reg we_out,
//Drive enable on data bus
output reg drive_out,
//DFT Output
output reg [7:0] dft_curr_state
);
//State machine memory
//--------------------------
reg [7:0] curr_state, next_state;
//CPU IR opcodes
//--------------------------
parameter IR_NOP = 8'h00;
parameter IR_LDA_IMM = 8'h01;
parameter IR_LDA_DIR = 8'h02;
parameter IR_STA_DIR = 8'h03;
parameter IR_STA_IND = 8'h04;
parameter IR_ADD_IMM = 8'h05;
parameter IR_ADD_DIR = 8'h06;
parameter IR_SUB_IMM = 8'h07;
parameter IR_SUB_DIR = 8'h08;
parameter IR_AND_IMM = 8'h09;
parameter IR_AND_DIR = 8'h0A;
parameter IR_OR_IMM = 8'h0B;
parameter IR_OR_DIR = 8'h0C;
parameter IR_XOR_IMM = 8'h0D;
parameter IR_XOR_DIR = 8'h0E;
parameter IR_LSL_IMM = 8'h0F;
parameter IR_LSL_DIR = 8'h10;
parameter IR_LSR_IMM = 8'h11;
parameter IR_LSR_DIR = 8'h12;
parameter IR_ASL_IMM = 8'h13;
parameter IR_ASL_DIR = 8'h14;
parameter IR_ASR_IMM = 8'h15;
parameter IR_ASR_DIR = 8'h16;
parameter IR_RSL_IMM = 8'h17;
parameter IR_RSL_DIR = 8'h18;
parameter IR_RSR_IMM = 8'h19;
parameter IR_RSR_DIR = 8'h1A;
parameter IR_JMP_DIR = 8'h1B;
parameter IR_JMP_IND = 8'h1C;
parameter IR_BNE_DIR = 8'h1D;
parameter IR_BNE_IND = 8'h1E;
parameter IR_BEQ_DIR = 8'h1F;
parameter IR_BEQ_IND = 8'h20;
parameter IR_BPL_DIR = 8'h21;
parameter IR_BPL_IND = 8'h22;
parameter IR_BMI_DIR = 8'h23;
parameter IR_BMI_IND = 8'h24;
//State machine opcodes
//--------------------------
parameter S_RESET_0 = 8'h00;
parameter S_PC_INC_0 = 8'h01;
parameter S_FETCH_0 = 8'h02;
parameter S_FETCH_1 = 8'h03;
parameter S_FETCH_2 = 8'h04;
parameter S_DECODE_0 = 8'h05;
parameter S_LDA_IMM_0 = 8'h06;
parameter S_LDA_IMM_1 = 8'h07;
parameter S_LDA_DIR_0 = 8'h08;
parameter S_LDA_DIR_1 = 8'h09;
parameter S_LDA_DIR_2 = 8'h0A;
parameter S_LDA_DIR_3 = 8'h0B;
parameter S_STA_DIR_0 = 8'h0C;
parameter S_STA_DIR_1 = 8'h0D;
parameter S_STA_DIR_2 = 8'h0E;
parameter S_STA_DIR_3 = 8'h0F;
parameter S_STA_IND_0 = 8'h10;
parameter S_STA_IND_1 = 8'h11;
parameter S_STA_IND_2 = 8'h12;
parameter S_STA_IND_3 = 8'h13;
parameter S_STA_IND_4 = 8'h14;
parameter S_STA_IND_5 = 8'h15;
parameter S_ADD_IMM_0 = 8'h16;
parameter S_ADD_IMM_1 = 8'h17;
parameter S_ADD_DIR_0 = 8'h18;
parameter S_ADD_DIR_1 = 8'h19;
parameter S_ADD_DIR_2 = 8'h1A;
parameter S_ADD_DIR_3 = 8'h1B;
parameter S_SUB_IMM_0 = 8'h1C;
parameter S_SUB_IMM_1 = 8'h1D;
parameter S_SUB_DIR_0 = 8'h1E;
parameter S_SUB_DIR_1 = 8'h1F;
parameter S_SUB_DIR_2 = 8'h20;
parameter S_SUB_DIR_3 = 8'h21;
parameter S_AND_IMM_0 = 8'h22;
parameter S_AND_IMM_1 = 8'h23;
parameter S_AND_DIR_0 = 8'h24;
parameter S_AND_DIR_1 = 8'h25;
parameter S_AND_DIR_2 = 8'h26;
parameter S_AND_DIR_3 = 8'h27;
parameter S_OR_IMM_0 = 8'h28;
parameter S_OR_IMM_1 = 8'h29;
parameter S_OR_DIR_0 = 8'h2A;
parameter S_OR_DIR_1 = 8'h2B;
parameter S_OR_DIR_2 = 8'h2C;
parameter S_OR_DIR_3 = 8'h2D;
parameter S_XOR_IMM_0 = 8'h2E;
parameter S_XOR_IMM_1 = 8'h2F;
parameter S_XOR_DIR_0 = 8'h30;
parameter S_XOR_DIR_1 = 8'h31;
parameter S_XOR_DIR_2 = 8'h32;
parameter S_XOR_DIR_3 = 8'h33;
parameter S_LSL_IMM_0 = 8'h34;
parameter S_LSL_IMM_1 = 8'h35;
parameter S_LSL_DIR_0 = 8'h36;
parameter S_LSL_DIR_1 = 8'h37;
parameter S_LSL_DIR_2 = 8'h38;
parameter S_LSL_DIR_3 = 8'h39;
parameter S_LSR_IMM_0 = 8'h3A;
parameter S_LSR_IMM_1 = 8'h3B;
parameter S_LSR_DIR_0 = 8'h3C;
parameter S_LSR_DIR_1 = 8'h3D;
parameter S_LSR_DIR_2 = 8'h3E;
parameter S_LSR_DIR_3 = 8'h3F;
parameter S_ASL_IMM_0 = 8'h40;
parameter S_ASL_IMM_1 = 8'h41;
parameter S_ASL_DIR_0 = 8'h42;
parameter S_ASL_DIR_1 = 8'h43;
parameter S_ASL_DIR_2 = 8'h44;
parameter S_ASL_DIR_3 = 8'h45;
parameter S_ASR_IMM_0 = 8'h46;
parameter S_ASR_IMM_1 = 8'h47;
parameter S_ASR_DIR_0 = 8'h48;
parameter S_ASR_DIR_1 = 8'h49;
parameter S_ASR_DIR_2 = 8'h4A;
parameter S_ASR_DIR_3 = 8'h4B;
parameter S_RSL_IMM_0 = 8'h4C;
parameter S_RSL_IMM_1 = 8'h4D;
parameter S_RSL_DIR_0 = 8'h4E;
parameter S_RSL_DIR_1 = 8'h4F;
parameter S_RSL_DIR_2 = 8'h50;
parameter S_RSL_DIR_3 = 8'h51;
parameter S_RSR_IMM_0 = 8'h52;
parameter S_RSR_IMM_1 = 8'h53;
parameter S_RSR_DIR_0 = 8'h54;
parameter S_RSR_DIR_1 = 8'h55;
parameter S_RSR_DIR_2 = 8'h56;
parameter S_RSR_DIR_3 = 8'h57;
parameter S_JMP_DIR_0 = 8'h58;
parameter S_JMP_DIR_1 = 8'h59;
parameter S_JMP_IND_0 = 8'h5A;
parameter S_JMP_IND_1 = 8'h5B;
parameter S_JMP_IND_2 = 8'h5C;
parameter S_JMP_IND_3 = 8'h5D;
//--------------------------
//ALU OPS
//--------------------------
parameter OP_ALU_PASSA = 4'b0000;
parameter OP_ALU_PASSB = 4'b0001;
parameter OP_ALU_ADD = 4'b0010;
parameter OP_ALU_SUB = 4'b0011;
parameter OP_ALU_AND = 4'b0100;
parameter OP_ALU_OR = 4'b0101;
parameter OP_ALU_XOR = 4'b0110;
parameter OP_ALU_LSL = 4'b0111;
parameter OP_ALU_LSR = 4'b1000;
parameter OP_ALU_ASL = 4'b1001;
parameter OP_ALU_ASR = 4'b1010;
parameter OP_ALU_RSL = 4'b1011;
parameter OP_ALU_RSR = 4'b1100;
//State memory block
//--------------------------
always @ (posedge clk_in or negedge rst_in) begin
//Reset to S_RESET_0 on reset
if(!rst_in)
curr_state <= S_RESET_0;
//Dont move states if enable is low
else if(!ena_in)
curr_state <= curr_state;
//Otherwise go to next state on every clk
else
curr_state <= next_state;
end
//Output logic
//--------------------------
always @ (curr_state) begin
case(curr_state)
//Reset sequence
//-----
//Do nothing until the next state
S_RESET_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU dont care
alu_op_out = 0;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//PC Increment
//-----
//Increment PC
S_PC_INC_0: begin
//Increment program counter
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 1;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU dont care
alu_op_out = 0;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Fetch sequence
//-----
//Send PC addr out
S_FETCH_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Load IR from memory
S_FETCH_1: begin
//Set IR Reg
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 1;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Inc PC now that IR is loaded
S_FETCH_2: begin
//Inc PC
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 1;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Decode sequence
//-----
//Do nothing until the next state
S_DECODE_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU dont care
alu_op_out = 0;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//LDA_IMM sequence
//-----
//Pass incoming data from memory to the main buss
S_LDA_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A
S_LDA_IMM_1: begin
//Latch A
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//LDA_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_LDA_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_LDA_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M
S_LDA_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A
S_LDA_DIR_3: begin
//Latch A
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//STA_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_STA_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_STA_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set address and WE, also prepare A data on the main buss
S_STA_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//A (A input) passthrough to main bus
alu_op_out = OP_ALU_PASSA;
//Set WE so that the receiving device is ready for us to drive data
we_out = 1;
drive_out = 0;
end
//Drive the data out
S_STA_DIR_3: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//A (A input) passthrough to main bus
alu_op_out = OP_ALU_PASSA;
//Drive out A data
we_out = 1;
drive_out = 1;
end
//STA_IND sequence
//-----
//Pass incoming data from memory to the main buss
S_STA_IND_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_STA_IND_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Fetch data located at this address
S_STA_IND_2: begin
//Latch M
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_STA_IND_3: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set address and WE, also prepare A data on the main buss
S_STA_IND_4: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//A (A input) passthrough to main bus
alu_op_out = OP_ALU_PASSA;
//Set WE so that the receiving device is ready for us to drive data
we_out = 1;
drive_out = 0;
end
//Drive the data out
S_STA_IND_5: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//A (A input) passthrough to main bus
alu_op_out = OP_ALU_PASSA;
//Drive out A data
we_out = 1;
drive_out = 1;
end
//ADD_IMM sequence
//-----
//Add the incoming data from the operand that the PC is pointing to
S_ADD_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Addition
alu_op_out = OP_ALU_ADD;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_ADD_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Addition
alu_op_out = OP_ALU_ADD;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//ADD_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_ADD_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_ADD_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to add incoming data
S_ADD_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Addition
alu_op_out = OP_ALU_ADD;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_ADD_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Addition
alu_op_out = OP_ALU_ADD;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//SUB_IMM sequence
//-----
//Subtract the incoming data from the operand that the PC is pointing to
S_SUB_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Subtraction
alu_op_out = OP_ALU_SUB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_SUB_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Subtraction
alu_op_out = OP_ALU_SUB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//SUB_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_SUB_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_SUB_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to subtract incoming data
S_SUB_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Subtraction
alu_op_out = OP_ALU_SUB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_SUB_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Subtraction
alu_op_out = OP_ALU_SUB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//AND_IMM sequence
//-----
//And the incoming data from the operand that the PC is pointing to
S_AND_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Logical AND
alu_op_out = OP_ALU_AND;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_AND_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Logical AND
alu_op_out = OP_ALU_AND;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//AND_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_AND_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_AND_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to AND incoming data
S_AND_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Logical AND
alu_op_out = OP_ALU_AND;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_AND_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Logical AND
alu_op_out = OP_ALU_AND;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//OR_IMM sequence
//-----
//And the incoming data from the operand that the PC is pointing to
S_OR_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Logical OR
alu_op_out = OP_ALU_OR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_OR_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Logical OR
alu_op_out = OP_ALU_OR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//OR_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_OR_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_OR_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to OR incoming data
S_OR_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Logical OR
alu_op_out = OP_ALU_OR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_OR_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Logical OR
alu_op_out = OP_ALU_OR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//XOR_IMM sequence
//-----
//And the incoming data from the operand that the PC is pointing to
S_XOR_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Logical XOR
alu_op_out = OP_ALU_XOR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_XOR_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Logical XOR
alu_op_out = OP_ALU_XOR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//XOR_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_XOR_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_XOR_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to XOR incoming data
S_XOR_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Logical XOR
alu_op_out = OP_ALU_XOR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_XOR_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Logical XOR
alu_op_out = OP_ALU_XOR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//LSL_IMM sequence
//-----
//Add the incoming data from the operand that the PC is pointing to
S_LSL_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Logical Shift Left
alu_op_out = OP_ALU_LSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_LSL_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Logical Shift Left
alu_op_out = OP_ALU_LSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//LSL_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_LSL_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_LSL_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to add incoming data
S_LSL_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Logical Shift Left
alu_op_out = OP_ALU_LSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_LSL_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Logical Shift Left
alu_op_out = OP_ALU_LSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//LSR_IMM sequence
//-----
//Add the incoming data from the operand that the PC is pointing to
S_LSR_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Logical Shift Right
alu_op_out = OP_ALU_LSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_LSR_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Logical Shift Right
alu_op_out = OP_ALU_LSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//LSR_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_LSR_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_LSR_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to add incoming data
S_LSR_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Logical Shift Right
alu_op_out = OP_ALU_LSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_LSR_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Logical Shift Right
alu_op_out = OP_ALU_LSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//ASL_IMM sequence
//-----
//Add the incoming data from the operand that the PC is pointing to
S_ASL_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Arithmetic Shift Left
alu_op_out = OP_ALU_ASL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_ASL_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Arithmetic Shift Left
alu_op_out = OP_ALU_ASL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//ASL_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_ASL_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_ASL_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to add incoming data
S_ASL_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Arithmetic Shift Left
alu_op_out = OP_ALU_ASL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_ASL_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Arithmetic Shift Left
alu_op_out = OP_ALU_ASL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//ASR_IMM sequence
//-----
//Add the incoming data from the operand that the PC is pointing to
S_ASR_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Arithmetic Shift Right
alu_op_out = OP_ALU_ASR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_ASR_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Arithmetic Shift Right
alu_op_out = OP_ALU_ASR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//ASR_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_ASR_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_ASR_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to add incoming data
S_ASR_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Arithmetic Shift Right
alu_op_out = OP_ALU_ASR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_ASR_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Arithmetic Shift Right
alu_op_out = OP_ALU_ASR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//RSL_IMM sequence
//-----
//Add the incoming data from the operand that the PC is pointing to
S_RSL_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Rotary Shift Left
alu_op_out = OP_ALU_RSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_RSL_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Rotary Shift Left
alu_op_out = OP_ALU_RSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//RSL_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_RSL_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_RSL_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to add incoming data
S_RSL_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Rotary Shift Left
alu_op_out = OP_ALU_RSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_RSL_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Rotary Shift Left
alu_op_out = OP_ALU_RSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//RSR_IMM sequence
//-----
//Add the incoming data from the operand that the PC is pointing to
S_RSR_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Rotary Shift Right
alu_op_out = OP_ALU_RSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_RSR_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Rotary Shift Right
alu_op_out = OP_ALU_RSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//RSR_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_RSR_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_RSR_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to add incoming data
S_RSR_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Rotary Shift Right
alu_op_out = OP_ALU_RSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_RSR_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Rotary Shift Right
alu_op_out = OP_ALU_RSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//JMP_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_JMP_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to PC
S_JMP_DIR_1: begin
//Latch PC
set_a_out = 0;
set_m_out = 0;
set_pc_out = 1;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//JMP_IND sequence
//-----
//Pass incoming data from memory to the main buss
S_JMP_IND_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_JMP_IND_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M
S_JMP_IND_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to PC
S_JMP_IND_3: begin
//Latch PC
set_a_out = 0;
set_m_out = 0;
set_pc_out = 1;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Default (INVALID) sequence
//-----
default: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU dont care
alu_op_out = 0;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
endcase
end
//Next state logic
//--------------------------
always @ (curr_state, ir_op_buss_in, ccr_flag_zn_in, halt_in) begin
//DFT Output
dft_curr_state = curr_state;
//Next state logic
case(curr_state)
//Reset sequence (skips PC increment on boot)
S_RESET_0: next_state = S_FETCH_0;
//PC Increment
S_PC_INC_0: next_state = S_FETCH_0;
//Fetch sequence
S_FETCH_0: begin
if(halt_in == 1)
next_state = S_FETCH_0; //Remain in S_FETCH_0 forever if halt is asserted
else
next_state = S_FETCH_1; //Otherwise continue fetching this instruction
end
S_FETCH_1: next_state = S_FETCH_2;
S_FETCH_2: next_state = S_DECODE_0;
//Decode IR Opcode
S_DECODE_0: begin
case(ir_op_buss_in)
//IR_NOP (does nothing)
IR_NOP: next_state = S_FETCH_0;
//IR_LDA_IMM (load immediate value to A)
IR_LDA_IMM: next_state = S_LDA_IMM_0;
//IR_LDA_DIR (load direct value to A)
IR_LDA_DIR: next_state = S_LDA_DIR_0;
//IR_STA_DIR (store A at direct address)
IR_STA_DIR: next_state = S_STA_DIR_0;
//IR_STA_IND (store A at indirect address)
IR_STA_IND: next_state = S_STA_IND_0;
//IR_ADD_IMM (add immediate value to A)
IR_ADD_IMM: next_state = S_ADD_IMM_0;
//IR_ADD_DIR (add direct value to A)
IR_ADD_DIR: next_state = S_ADD_DIR_0;
//IR_SUB_IMM (subtract immediate value from A)
IR_SUB_IMM: next_state = S_SUB_IMM_0;
//IR_SUB_DIR (subtract direct value from A)
IR_SUB_DIR: next_state = S_SUB_DIR_0;
//IR_AND_IMM (logical AND immediate value with A)
IR_AND_IMM: next_state = S_AND_IMM_0;
//IR_AND_DIR (logical AND direct value with A)
IR_AND_DIR: next_state = S_AND_DIR_0;
//IR_OR_IMM (logical OR immediate value with A)
IR_OR_IMM: next_state = S_OR_IMM_0;
//IR_OR_DIR (logical OR direct value with A)
IR_OR_DIR: next_state = S_OR_DIR_0;
//IR_XOR_IMM (logical XOR immediate value with A)
IR_XOR_IMM: next_state = S_XOR_IMM_0;
//IR_XOR_DIR (logical XOR direct value with A)
IR_XOR_DIR: next_state = S_XOR_DIR_0;
//IR_LSL_IMM (logical left shift immediate value with A)
IR_LSL_IMM: next_state = S_LSL_IMM_0;
//IR_LSL_DIR (logical left shift direct value with A)
IR_LSL_DIR: next_state = S_LSL_DIR_0;
//IR_LSR_IMM (logical right shift immediate value with A)
IR_LSR_IMM: next_state = S_LSR_IMM_0;
//IR_LSR_DIR (logical right shift direct value with A)
IR_LSR_DIR: next_state = S_LSR_DIR_0;
//IR_ASL_IMM (arithmetic left shift immediate value with A)
IR_ASL_IMM: next_state = S_ASL_IMM_0;
//IR_ASL_DIR (arithmetic left shift direct value with A)
IR_ASL_DIR: next_state = S_ASL_DIR_0;
//IR_ASR_IMM (arithmetic right shift immediate value with A)
IR_ASR_IMM: next_state = S_ASR_IMM_0;
//IR_ASR_DIR (arithmetic right shift direct value with A)
IR_ASR_DIR: next_state = S_ASR_DIR_0;
//IR_RSL_IMM (rotary left shift immediate value with A)
IR_RSL_IMM: next_state = S_RSL_IMM_0;
//IR_RSL_DIR (rotary left shift direct value with A)
IR_RSL_DIR: next_state = S_RSL_DIR_0;
//IR_RSR_IMM (rotary right shift immediate value with A)
IR_RSR_IMM: next_state = S_RSR_IMM_0;
//IR_RSR_DIR (rotary right shift direct value with A)
IR_RSR_DIR: next_state = S_RSR_DIR_0;
//IR_JMP_DIR (load direct value to PC)
IR_JMP_DIR: next_state = S_JMP_DIR_0;
//IR_LDA_DIR (load indirect value to PC)
IR_JMP_IND: next_state = S_JMP_IND_0;
//IR_BNE_DIR (banch if z clear direct)
IR_BNE_DIR: begin
if(ccr_flag_zn_in[1] == 0)
next_state = S_JMP_DIR_0;
else
next_state = S_PC_INC_0;
end
//IR_BNE_IND (banch if z clear indirect)
IR_BNE_IND: begin
if(ccr_flag_zn_in[1] == 0)
next_state = S_JMP_IND_0;
else
next_state = S_PC_INC_0;
end
//IR_BEQ_DIR (banch if z set direct)
IR_BEQ_DIR: begin
if(ccr_flag_zn_in[1] == 1)
next_state = S_JMP_DIR_0;
else
next_state = S_PC_INC_0;
end
//IR_BEQ_IND (banch if z set indirect)
IR_BEQ_IND: begin
if(ccr_flag_zn_in[1] == 1)
next_state = S_JMP_IND_0;
else
next_state = S_PC_INC_0;
end
//IR_BPL_DIR (banch if n clear direct)
IR_BPL_DIR: begin
if(ccr_flag_zn_in[0] == 0)
next_state = S_JMP_DIR_0;
else
next_state = S_PC_INC_0;
end
//IR_BPL_IND (banch if n clear indirect)
IR_BPL_IND: begin
if(ccr_flag_zn_in[0] == 0)
next_state = S_JMP_IND_0;
else
next_state = S_PC_INC_0;
end
//IR_BMI_DIR (banch if n set direct)
IR_BMI_DIR: begin
if(ccr_flag_zn_in[0] == 1)
next_state = S_JMP_DIR_0;
else
next_state = S_PC_INC_0;
end
//IR_BMI_IND (banch if n set indirect)
IR_BMI_IND: begin
if(ccr_flag_zn_in[0] == 1)
next_state = S_JMP_IND_0;
else
next_state = S_PC_INC_0;
end
//Invalid IR, goto fetch_0
default: next_state = S_FETCH_0;
endcase
end
//LDA_IMM sequence
S_LDA_IMM_0: next_state = S_LDA_IMM_1;
S_LDA_IMM_1: next_state = S_PC_INC_0;
//LDA_DIR sequence
S_LDA_DIR_0: next_state = S_LDA_DIR_1;
S_LDA_DIR_1: next_state = S_LDA_DIR_2;
S_LDA_DIR_2: next_state = S_LDA_DIR_3;
S_LDA_DIR_3: next_state = S_PC_INC_0;
//STA_DIR sequence
S_STA_DIR_0: next_state = S_STA_DIR_1;
S_STA_DIR_1: next_state = S_STA_DIR_2;
S_STA_DIR_2: next_state = S_STA_DIR_3;
S_STA_DIR_3: next_state = S_PC_INC_0;
//STA_IND sequence
S_STA_IND_0: next_state = S_STA_IND_1;
S_STA_IND_1: next_state = S_STA_IND_2;
S_STA_IND_2: next_state = S_STA_IND_3;
S_STA_IND_3: next_state = S_STA_IND_4;
S_STA_IND_4: next_state = S_STA_IND_5;
S_STA_IND_5: next_state = S_PC_INC_0;
//ADD_IMM sequence
S_ADD_IMM_0: next_state = S_ADD_IMM_1;
S_ADD_IMM_1: next_state = S_PC_INC_0;
//ADD_DIR sequence
S_ADD_DIR_0: next_state = S_ADD_DIR_1;
S_ADD_DIR_1: next_state = S_ADD_DIR_2;
S_ADD_DIR_2: next_state = S_ADD_DIR_3;
S_ADD_DIR_3: next_state = S_PC_INC_0;
//SUB_IMM sequence
S_SUB_IMM_0: next_state = S_SUB_IMM_1;
S_SUB_IMM_1: next_state = S_PC_INC_0;
//SUB_DIR sequence
S_SUB_DIR_0: next_state = S_SUB_DIR_1;
S_SUB_DIR_1: next_state = S_SUB_DIR_2;
S_SUB_DIR_2: next_state = S_SUB_DIR_3;
S_SUB_DIR_3: next_state = S_PC_INC_0;
//AND_IMM sequence
S_AND_IMM_0: next_state = S_AND_IMM_1;
S_AND_IMM_1: next_state = S_PC_INC_0;
//AND_DIR sequence
S_AND_DIR_0: next_state = S_AND_DIR_1;
S_AND_DIR_1: next_state = S_AND_DIR_2;
S_AND_DIR_2: next_state = S_AND_DIR_3;
S_AND_DIR_3: next_state = S_PC_INC_0;
//OR_IMM sequence
S_OR_IMM_0: next_state = S_OR_IMM_1;
S_OR_IMM_1: next_state = S_PC_INC_0;
//OR_DIR sequence
S_OR_DIR_0: next_state = S_OR_DIR_1;
S_OR_DIR_1: next_state = S_OR_DIR_2;
S_OR_DIR_2: next_state = S_OR_DIR_3;
S_OR_DIR_3: next_state = S_PC_INC_0;
//XOR_IMM sequence
S_XOR_IMM_0: next_state = S_XOR_IMM_1;
S_XOR_IMM_1: next_state = S_PC_INC_0;
//XOR_DIR sequence
S_XOR_DIR_0: next_state = S_XOR_DIR_1;
S_XOR_DIR_1: next_state = S_XOR_DIR_2;
S_XOR_DIR_2: next_state = S_XOR_DIR_3;
S_XOR_DIR_3: next_state = S_PC_INC_0;
//LSL_IMM sequence
S_LSL_IMM_0: next_state = S_LSL_IMM_1;
S_LSL_IMM_1: next_state = S_PC_INC_0;
//LSL_DIR sequence
S_LSL_DIR_0: next_state = S_LSL_DIR_1;
S_LSL_DIR_1: next_state = S_LSL_DIR_2;
S_LSL_DIR_2: next_state = S_LSL_DIR_3;
S_LSL_DIR_3: next_state = S_PC_INC_0;
//LSR_IMM sequence
S_LSR_IMM_0: next_state = S_LSR_IMM_1;
S_LSR_IMM_1: next_state = S_PC_INC_0;
//LSR_DIR sequence
S_LSR_DIR_0: next_state = S_LSR_DIR_1;
S_LSR_DIR_1: next_state = S_LSR_DIR_2;
S_LSR_DIR_2: next_state = S_LSR_DIR_3;
S_LSR_DIR_3: next_state = S_PC_INC_0;
//ASL_IMM sequence
S_ASL_IMM_0: next_state = S_ASL_IMM_1;
S_ASL_IMM_1: next_state = S_PC_INC_0;
//ASL_DIR sequence
S_ASL_DIR_0: next_state = S_ASL_DIR_1;
S_ASL_DIR_1: next_state = S_ASL_DIR_2;
S_ASL_DIR_2: next_state = S_ASL_DIR_3;
S_ASL_DIR_3: next_state = S_PC_INC_0;
//ASR_IMM sequence
S_ASR_IMM_0: next_state = S_ASR_IMM_1;
S_ASR_IMM_1: next_state = S_PC_INC_0;
//ASR_DIR sequence
S_ASR_DIR_0: next_state = S_ASR_DIR_1;
S_ASR_DIR_1: next_state = S_ASR_DIR_2;
S_ASR_DIR_2: next_state = S_ASR_DIR_3;
S_ASR_DIR_3: next_state = S_PC_INC_0;
//RSL_IMM sequence
S_RSL_IMM_0: next_state = S_RSL_IMM_1;
S_RSL_IMM_1: next_state = S_PC_INC_0;
//RSL_DIR sequence
S_RSL_DIR_0: next_state = S_RSL_DIR_1;
S_RSL_DIR_1: next_state = S_RSL_DIR_2;
S_RSL_DIR_2: next_state = S_RSL_DIR_3;
S_RSL_DIR_3: next_state = S_PC_INC_0;
//RSR_IMM sequence
S_RSR_IMM_0: next_state = S_RSR_IMM_1;
S_RSR_IMM_1: next_state = S_PC_INC_0;
//RSR_DIR sequence
S_RSR_DIR_0: next_state = S_RSR_DIR_1;
S_RSR_DIR_1: next_state = S_RSR_DIR_2;
S_RSR_DIR_2: next_state = S_RSR_DIR_3;
S_RSR_DIR_3: next_state = S_PC_INC_0;
//JMP_DIR sequence
S_JMP_DIR_0: next_state = S_JMP_DIR_1;
S_JMP_DIR_1: next_state = S_FETCH_0;
//JMP_IND sequence
S_JMP_IND_0: next_state = S_JMP_IND_1;
S_JMP_IND_1: next_state = S_JMP_IND_2;
S_JMP_IND_2: next_state = S_JMP_IND_3;
S_JMP_IND_3: next_state = S_FETCH_0;
//Should never get here
default:
next_state = S_PC_INC_0;
endcase
end
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//---------------------------------------------------------------------------------------------------------
// MINIBYTE ALU
//---------------------------------------------------------------------------------------------------------
// OPERATION | ALU_OP | MEANING
//---------------------------------------------------------------------------------------------------------
// PASSA | 0b0000 | Passthrough input A
// PASSB | 0b0001 | Passthrough input B
// ADD | 0b0010 | Add A and B
// SUB | 0b0011 | Subtract B from A
// AND | 0b0100 | Logical and of A, B
// OR | 0b0101 | Logical or of A, B
// XOR | 0b0110 | Logical xor of A, B
// LSL | 0b0111 | Logical shift A left by B
// LSR | 0b1000 | Logical shift A right by B
// ASL | 0b1001 | Arithmetic shift A left by B
// ASR | 0b1010 | Arithmetic shift A right by B
// RSL | 0b1011 | Rotary shift A left by B
// RSR | 0b1100 | Rotary shift A right by B
//---------------------------------------------------------------------------------------------------------
//--------------------------
//Params
//--------------------------
parameter ALU_PASSA = 4'b0000;
parameter ALU_PASSB = 4'b0001;
parameter ALU_ADD = 4'b0010;
parameter ALU_SUB = 4'b0011;
parameter ALU_AND = 4'b0100;
parameter ALU_OR = 4'b0101;
parameter ALU_XOR = 4'b0110;
parameter ALU_LSL = 4'b0111;
parameter ALU_LSR = 4'b1000;
parameter ALU_ASL = 4'b1001;
parameter ALU_ASR = 4'b1010;
parameter ALU_RSL = 4'b1011;
parameter ALU_RSR = 4'b1100;
//--------------------------
//ALU Module
//--------------------------
module minibyte_alu (
//ALU Inputs
input wire signed [7:0] a_in,
input wire signed [7:0] b_in,
input wire [3:0] alu_op_in,
//ALU Outputs
output reg signed [7:0] res_out,
output reg [1:0] flags_zn_out
);
//Main Procedural Block
//--------------------------
always @(*) begin
//Assign ALU result
//---------------------
case(alu_op_in)
//A Passthrough
//--------------
ALU_PASSA:
res_out = a_in;
//B Passthrough
//--------------
ALU_PASSB:
res_out = b_in;
//Addition
//--------------
ALU_ADD:
res_out = a_in + b_in;
//Subtraction
//--------------
ALU_SUB:
res_out = a_in - b_in;
//Logical AND
//--------------
ALU_AND:
res_out = a_in & b_in;
//Logical OR
//--------------
ALU_OR:
res_out = a_in | b_in;
//Logical XOR
//--------------
ALU_XOR:
res_out = a_in ^ b_in;
//Logical Shift Left
//--------------
ALU_LSL:
res_out = a_in << b_in;
//Logical Shift Right
//--------------
ALU_LSR:
res_out = a_in >> b_in;
//Arithmetic Shift Left
//--------------
ALU_ASL:
res_out = a_in <<< b_in;
//Arithmetic Shift Right
//--------------
ALU_ASR:
res_out = a_in >>> b_in;
//Rotary Shift Left
//--------------
ALU_RSL:
case(b_in[2:0])
//Hardcoded concatenations of all possible inputs
3'b000:
res_out = a_in;
3'b001:
res_out = {a_in[6:0], a_in[7]};
3'b010:
res_out = {a_in[5:0], a_in[7:6]};
3'b011:
res_out = {a_in[4:0], a_in[7:5]};
3'b100:
res_out = {a_in[3:0], a_in[7:4]};
3'b101:
res_out = {a_in[2:0], a_in[7:3]};
3'b110:
res_out = {a_in[1:0], a_in[7:2]};
3'b111:
res_out = {a_in[0], a_in[7:1]};
endcase
//Rotary Shift Right
//--------------
ALU_RSR:
case(b_in[2:0])
//Hardcoded concatenations of all possible inputs
3'b000:
res_out = a_in;
3'b001:
res_out = {a_in[0], a_in[7:1]};
3'b010:
res_out = {a_in[1:0], a_in[7:2]};
3'b011:
res_out = {a_in[2:0], a_in[7:3]};
3'b100:
res_out = {a_in[3:0], a_in[7:4]};
3'b101:
res_out = {a_in[4:0], a_in[7:5]};
3'b110:
res_out = {a_in[5:0], a_in[7:6]};
3'b111:
res_out = {a_in[6:0], a_in[7]};
endcase
//Default (SHOULD NEVER GET HERE)
//--------------
default:
res_out = 0;
endcase
//Assign Zero flag
//---------------------
if(res_out == 0)
flags_zn_out[1] = 1;
else
flags_zn_out[1] = 0;
//Assign Negative flag
//---------------------
flags_zn_out[0] = res_out[7];
end
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//--------------------------
//General Register Module
//--------------------------
module minibyte_genreg (
//Basic Inputs
input wire clk_in, rst_in,
//Register Inputs
input wire [7:0] reg_in,
input wire set_in,
//Register Outputs
output reg [7:0] reg_out
);
//Main Procedural Block
//--------------------------
always @(posedge clk_in or negedge rst_in) begin
//Reset if rst goes low
if(!rst_in)
reg_out <= 0;
else
//Set register to input if set signal goes high on a clk
if(set_in)
reg_out <= reg_in;
end
endmodule
//--------------------------
//CCR Register Module
//--------------------------
module minibyte_ccrreg (
//Basic Inputs
input wire clk_in, rst_in,
//Register Inputs
input wire [1:0] reg_in,
input wire set_in,
//Register Outputs
output reg [1:0] reg_out
);
//Main Procedural Block
//--------------------------
always @(posedge clk_in or negedge rst_in) begin
//Reset if rst goes low
if(!rst_in)
reg_out <= 0;
else
//Set register to input if set signal goes high on a clk
if(set_in)
reg_out <= reg_in;
end
endmodule
//---------------------------------
//Program Counter Register Module
//---------------------------------
module minibyte_pcreg (
//Basic Inputs
input wire clk_in, rst_in,
//Register Inputs
input wire [7:0] reg_in,
input wire set_in,
input wire inc_in,
//Register Outputs
output reg [7:0] reg_out
);
//Main Procedural Block
//--------------------------
always @(posedge clk_in or negedge rst_in) begin
//Reset if rst goes low
if(!rst_in)
reg_out <= 0;
else
//Set register to input if set signal goes high
if(set_in)
reg_out <= reg_in;
//Increment register if inc signal goes high on a clk
else if(inc_in)
reg_out <= reg_out + 1;
end
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//---------------------------------
//Generic 2->1 Mux Module
//---------------------------------
module minibyte_genmux_2x(
//Mux Inputs
input wire [7:0] a_in,
input wire [7:0] b_in,
//Mux Select
input wire sel_in,
//Mux Output
output reg [7:0] mux_out
);
//Main Procedural Block
//--------------------------
always @(*) begin
//A out if sel is 0
if(sel_in == 0)
mux_out = a_in;
//B out if sel is 1
else
mux_out = b_in;
end
endmodule
//---------------------------------
//Generic 4->1 Mux Module
//---------------------------------
module minibyte_genmux_4x(
//Mux Inputs
input wire [7:0] a_in,
input wire [7:0] b_in,
input wire [7:0] c_in,
input wire [7:0] d_in,
//Mux Select
input wire [1:0] sel_in,
//Mux Output
output reg [7:0] mux_out
);
//Main Procedural Block
//--------------------------
always @(*) begin
//A out if sel is 00
if(sel_in == 2'b00)
mux_out = a_in;
//B out if sel is 01
else if(sel_in == 2'b01)
mux_out = b_in;
//C out if sel is 10
else if(sel_in == 2'b10)
mux_out = c_in;
//D out if sel is 11
else
mux_out = d_in;
end
endmodule
//---------------------------------
//Generic 8->1 Mux Module
//---------------------------------
module minibyte_genmux_8x(
//Mux Inputs
input wire [7:0] a_in,
input wire [7:0] b_in,
input wire [7:0] c_in,
input wire [7:0] d_in,
input wire [7:0] e_in,
input wire [7:0] f_in,
input wire [7:0] g_in,
input wire [7:0] h_in,
//Mux Select
input wire [2:0] sel_in,
//Mux Output
output reg [7:0] mux_out
);
//Main Procedural Block
//--------------------------
always @(*) begin
//A out if sel is 000
if(sel_in == 3'b000)
mux_out = a_in;
//B out if sel is 001
else if(sel_in == 3'b001)
mux_out = b_in;
//C out if sel is 010
else if(sel_in == 3'b010)
mux_out = c_in;
//D out if sel is 011
else if(sel_in == 3'b011)
mux_out = d_in;
//E out if sel is 100
else if(sel_in == 3'b100)
mux_out = e_in;
//F out if sel is 101
else if(sel_in == 3'b101)
mux_out = f_in;
//G out if sel is 110
else if(sel_in == 3'b110)
mux_out = g_in;
//H out if sel is 111
else
mux_out = h_in;
end
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//---------------------------------
//Drive enable device
//---------------------------------
module drive_enable_fanout(
//Drive enable input signal
input wire drive_en,
//Output drive signals
output reg [7:0] drive
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//CPU IR opcodes
//--------------------------
parameter _NOP = 8'h00;
parameter _LDA_IMM = 8'h01;
parameter _LDA_DIR = 8'h02;
parameter _STA_DIR = 8'h03;
//parameter _STA_IND = 8'h04;
parameter _ADD_IMM = 8'h05;
//parameter _ADD_DIR = 8'h06;
//parameter _SUB_IMM = 8'h07;
//parameter _SUB_DIR = 8'h08;
//parameter _AND_IMM = 8'h09;
//parameter _AND_DIR = 8'h0A;
//parameter _OR_IMM = 8'h0B;
//parameter _OR_DIR = 8'h0C;
//parameter _XOR_IMM = 8'h0D;
//parameter _XOR_DIR = 8'h0E;
parameter _LSL_IMM = 8'h0F;
//parameter _LSL_DIR = 8'h10;
//parameter _LSR_IMM = 8'h11;
//parameter _LSR_DIR = 8'h12;
//parameter _ASL_IMM = 8'h13;
//parameter _ASL_DIR = 8'h14;
//parameter _ASR_IMM = 8'h15;
//parameter _ASR_DIR = 8'h16;
//parameter _RSL_IMM = 8'h17;
//parameter _RSL_DIR = 8'h18;
//parameter _RSR_IMM = 8'h19;
//parameter _RSR_DIR = 8'h1A;
parameter _JMP_DIR = 8'h1B;
//parameter _JMP_IND = 8'h1C;
parameter _BNE_DIR = 8'h1D;
//parameter _BNE_IND = 8'h1E;
//parameter _BEQ_DIR = 8'h1F;
//parameter _BEQ_IND = 8'h20;
parameter _BPL_DIR = 8'h21;
//parameter _BPL_IND = 8'h22;
//parameter _BMI_DIR = 8'h23;
//parameter _BMI_IND = 8'h24;
//--------------------------
//Demo ROM Program
//--------------------------
module demo_rom_64B(
//Input Addr
input wire [5:0] address,
//Output Data
output reg [7:0] data_out
);
always @(address)
case(address)
6'h00: data_out = _NOP; //First istr is a NOP
6'h01: data_out = _LDA_IMM; //Make sure A is zero
6'h02: data_out = 0;
6'h03: data_out = _NOP; //NOP is the START of the LOOP0
6'h04: data_out = _ADD_IMM; //ADD 1 to A
6'h05: data_out = 1;
6'h06: data_out = _STA_DIR; //Write this value to 0x40
6'h07: data_out = 8'h40;
6'h08: data_out = _BNE_DIR; //Keep branching to LOOP0 until we roll over to 0
6'h09: data_out = 8'h03;
6'h0A: data_out = _LDA_IMM; //Load a 1 into A
6'h0B: data_out = 1;
6'h0C: data_out = _STA_DIR; //Write this value to 0x40
6'h0D: data_out = 8'h40;
6'h0E: data_out = _NOP; //NOP is the START of the LOOP1
6'h0F: data_out = _LSL_IMM; //Shift A left by 1
6'h10: data_out = 1;
6'h11: data_out = _STA_DIR; //Write this value to 0x40
6'h12: data_out = 8'h40;
6'h13: data_out = _BPL_DIR; //Keep branching to LOOP1 until we hit 0b10000000
6'h14: data_out = 8'h0E;
6'h15: data_out = _LDA_IMM; //Load DEADBEEF into RAM
6'h16: data_out = 8'hDE;
6'h17: data_out = _STA_DIR;
6'h18: data_out = 8'h78;
6'h19: data_out = _LDA_IMM;
6'h1A: data_out = 8'hAD;
6'h1B: data_out = _STA_DIR;
6'h1C: data_out = 8'h79;
6'h1D: data_out = _LDA_IMM;
6'h1E: data_out = 8'hBE;
6'h1F: data_out = _STA_DIR;
6'h20: data_out = 8'h7A;
6'h21: data_out = _LDA_IMM;
6'h22: data_out = 8'hEF;
6'h23: data_out = _STA_DIR;
6'h24: data_out = 8'h7B;
6'h25: data_out = _LDA_DIR; //READ out the contents of RAM
6'h26: data_out = 8'h78;
6'h27: data_out = _STA_DIR; //Write this value to 0x40
6'h28: data_out = 8'h40;
6'h29: data_out = _LDA_DIR; //READ out the contents of RAM
6'h2A: data_out = 8'h79;
6'h2B: data_out = _STA_DIR; //Write this value to 0x40
6'h2C: data_out = 8'h40;
6'h2D: data_out = _LDA_DIR; //READ out the contents of RAM
6'h2E: data_out = 8'h7A;
6'h2F: data_out = _STA_DIR; //Write this value to 0x40
6'h30: data_out = 8'h40;
6'h31: data_out = _LDA_DIR; //READ out the contents of RAM
6'h32: data_out = 8'h7B;
6'h33: data_out = _STA_DIR; //Write this value to 0x40
6'h34: data_out = 8'h40;
6'h35: data_out = _JMP_DIR; //Start the whole thing over!
6'h36: data_out = 8'h00;
default: data_out = 0; //Unused space
endcase
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//--------------------------
//REGISTER RAM
//--------------------------
module reg_ram_8B(
//Input CLK and RST
input wire clk_in,
input wire rst_in,
//Input Addr
input wire [2:0] address,
//Input Data
input wire [7:0] data_in,
//Input WE and EN
input wire we_in,
input wire en_in,
//Output Data
output reg [7:0] data_out
);
//Data busses
//------------------------------------
reg [7:0] r_we;
reg [7:0] r0_out_data;
reg [7:0] r1_out_data;
reg [7:0] r2_out_data;
reg [7:0] r3_out_data;
reg [7:0] r4_out_data;
reg [7:0] r5_out_data;
reg [7:0] r6_out_data;
reg [7:0] r7_out_data;
//Data registers
//------------------------------------
minibyte_genreg r0(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[0]),
//Register Outputs
.reg_out(r0_out_data)
);
minibyte_genreg r1(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[1]),
//Register Outputs
.reg_out(r1_out_data)
);
minibyte_genreg r2(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[2]),
//Register Outputs
.reg_out(r2_out_data)
);
minibyte_genreg r3(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[3]),
//Register Outputs
.reg_out(r3_out_data)
);
minibyte_genreg r4(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[4]),
//Register Outputs
.reg_out(r4_out_data)
);
minibyte_genreg r5(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[5]),
//Register Outputs
.reg_out(r5_out_data)
);
minibyte_genreg r6(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[6]),
//Register Outputs
.reg_out(r6_out_data)
);
minibyte_genreg r7(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[7]),
//Register Outputs
.reg_out(r7_out_data)
);
//Register control logic
//------------------------------------
always @ (*) begin
if (!en_in) begin
data_out = 8'h00;
r_we = 8'h00;
end
else if (we_in) begin
case(address)
3'b000:
r_we = 8'b00000001;
3'b001:
r_we = 8'b00000010;
3'b010:
r_we = 8'b00000100;
3'b011:
r_we = 8'b00001000;
3'b100:
r_we = 8'b00010000;
3'b101:
r_we = 8'b00100000;
3'b110:
r_we = 8'b01000000;
3'b111:
r_we = 8'b10000000;
default:
r_we = 8'b00000000;
endcase
data_out = 8'h00;
end
else begin
case(address)
3'b000:
data_out = r0_out_data;
3'b001:
data_out = r1_out_data;
3'b010:
data_out = r2_out_data;
3'b011:
data_out = r3_out_data;
3'b100:
data_out = r4_out_data;
3'b101:
data_out = r5_out_data;
3'b110:
data_out = r6_out_data;
3'b111:
data_out = r7_out_data;
endcase
r_we = 8'h00;
end
end
endmodule
|
module drive_enable_fanout(
//Drive enable input signal
input wire drive_en,
//Output drive signals
output reg [7:0] drive
);
//Main Procedural Block
//--------------------------
always @(*) begin
if(drive_en == 0)
drive = 0;
else
drive = 8'hff;
end
endmodule
|
tt06-finale_0099
|
tt06-finale
|
zacharysfrazee-tt06-minibyte-cpu
|
task_minibyte_alu
|
tt_um_minibyte
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//---------------------------------
//Top Level Project Module
//---------------------------------
module tt_um_minibyte (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
//---------------------------------
//Top Level Singal Notes
//---------------------------------
//ui_in => Test and Configuration bits
//uo_out => WE and 7-bit Address Buss
//uio_in/uio_out => 8-bit Bidirectional Data Buss
//uio_oe => Output Enable for Data Buss
//---------------------------------
//ui_in (Test)
// bit[7] => ENABLE ONBOARD REG RAM
// bit[6:5] => UNUSED
// bit[4] => ENABLE DEMO ROM
// bit[3] => HALT CONTROL UNIT
// bit[2:0] => DEBUG OUTPUT SIGNAL CONTROL
// 0 -> Normal output
// 1 -> A output
// 2 -> A (UPPER BIT) output
// 3 -> M output
// 4 -> PC output
// 5 -> IR output
// 6 -> CCR output
// 7 -> CU STATE output
//---------------------------------
//uio_in/uio_out
// bit[7] => WE (Write Enable)
// bit[6:0] => Address Buss
//---------------------------------
//---------------------------------
//Wires
//---------------------------------
wire [6:0] address_buss;
wire we_signal;
wire [7:0] tm_control_bits;
wire [7:0] data_buss_in;
wire [7:0] data_buss_out;
wire [7:0] data_buss_oe;
wire [7:0] data_buss_rom;
wire [7:0] data_buss_ram;
wire [7:0] data_buss_muxed_in;
wire drive_enable_sig;
wire nc_addr_buss_bit_7;
//---------------------------------
//Assignments
//---------------------------------
assign uo_out[6:0] = address_buss;
assign uo_out[7] = we_signal;
assign tm_control_bits = ui_in;
assign data_buss_in = uio_in;
assign uio_out = data_buss_out;
assign uio_oe = data_buss_oe;
//---------------------------------
//Minibyte CPU
//---------------------------------
minibyte_cpu cpu(
//Basic Inputs
.clk_in(clk), .ena_in(ena), .rst_in(rst_n),
.halt_in(tm_control_bits[3]),
//Memory and IO Inputs
.data_in(data_buss_muxed_in),
//DFT Inputs
.tm_control({tm_control_bits[2:0]}),
//Memory and IO Outputs
.addr_out ({nc_addr_buss_bit_7,address_buss}), //Only 7 bits get connected as we need to save one output for WE below:(
.data_out (data_buss_out),
.we_out (we_signal), //Dedicated output bit 7 gets used for WE
.drive_out (drive_enable_sig)
);
//---------------------------------
//Input Device MUX
//---------------------------------
reg [1:0] input_mux_control;
always @ (tm_control_bits, reg_ram_active) begin
//Enable Onboard RAM
if(tm_control_bits[7] == 1 && reg_ram_active)
input_mux_control = 2'b11;
//Enable Demo ROM
else if(tm_control_bits[4] == 1)
input_mux_control = 2'b01;
//Enable Normal Input
else
input_mux_control = 2'b00;
end
minibyte_genmux_4x input_mux(
//Mux Inputs
.a_in(data_buss_in),
.b_in(data_buss_rom),
.c_in(8'h00),
.d_in(data_buss_ram),
//Mux Select
.sel_in(input_mux_control),
//Mux Output
.mux_out(data_buss_muxed_in)
);
//---------------------------------
//Demo ROM
//---------------------------------
demo_rom_64B rom(
//Input Addr and Enable
.address(address_buss[5:0]), //Lower 6 addr buss bits
//Output Data
.data_out(data_buss_rom)
);
//---------------------------------
//Onboard REG RAM
//---------------------------------
reg reg_ram_active;
//Register ram is only active for addresses
//0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f
always @ (address_buss) begin
if(address_buss >= 7'h78)
reg_ram_active = 1;
else
reg_ram_active = 0;
end
reg_ram_8B ram(
//Input CLK and RST
.clk_in(clk),
.rst_in(rst_n),
//Input Addr
.address(address_buss[2:0]),
//Input Data
.data_in(data_buss_out),
//Input WE
.we_in(we_signal),
.en_in(reg_ram_active),
//Output Data
.data_out(data_buss_ram)
);
//---------------------------------
//Output enable control
//---------------------------------
drive_enable_fanout oe_driver(
//Drive enable input signal
.drive_en(drive_enable_sig),
//Output drive signals
.drive(data_buss_oe)
);
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//---------------------------------
//Top Level CPU Module
//---------------------------------
module minibyte_cpu (
//Basic Inputs
input wire clk_in, ena_in, rst_in,
input wire halt_in,
//Memory and IO Inputs
input wire [7:0] data_in,
//DFT Testmode Inputs
input wire [2:0] tm_control,
//Memory and IO Outputs
output wire [7:0] addr_out,
output wire [7:0] data_out,
output wire we_out,
output wire drive_out
);
//Main Data Buss
//--------------------------------
wire [7:0] main_buss;
//Data out comes from the main buss
assign data_out = main_buss;
//ALU A-Side Input Data Buss
//--------------------------------
wire [7:0] alu_a_buss;
//Address Busses
//--------------------------------
wire [7:0] m_addr_buss;
wire [7:0] pc_addr_buss;
wire [7:0] ir_op_buss;
wire [7:0] normal_addr_out;
//DFT Wires
//--------------------------------
wire [7:0] dft_cu_state;
//Control Signals
//--------------------------------
//Set register signals
wire ctrl_set_a;
wire ctrl_set_m;
wire ctrl_set_pc;
wire ctrl_set_ir;
wire ctrl_set_ccr;
//Inc register signals
wire ctrl_inc_pc;
//Addr mux signals
wire ctrl_addr_mux;
//Alu control signals
wire [3:0] ctrl_alu_op;
//Data direction control
wire ctrl_we_out;
wire ctrl_drive_out;
assign we_out=ctrl_we_out;
assign drive_out=ctrl_drive_out;
//Branch Signals
//--------------------------------
wire [1:0] flags_zn_buss;
wire [1:0] ccr_zn_buss;
//A Register
//--------------------------------
minibyte_genreg reg_a(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(main_buss),
.set_in(ctrl_set_a),
//Register Outputs
.reg_out(alu_a_buss)
);
//M Register
//--------------------------------
minibyte_genreg reg_m(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(main_buss),
.set_in(ctrl_set_m),
//Register Outputs
.reg_out(m_addr_buss)
);
//PC Register
//--------------------------------
minibyte_pcreg reg_pc(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(main_buss),
.set_in(ctrl_set_pc),
.inc_in(ctrl_inc_pc),
//Register Outputs
.reg_out(pc_addr_buss)
);
//IR Register
//--------------------------------
minibyte_genreg reg_ir(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(main_buss),
.set_in(ctrl_set_ir),
//Register Outputs
.reg_out(ir_op_buss)
);
//CCR Register
//--------------------------------
minibyte_ccrreg reg_ccr(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(flags_zn_buss),
.set_in(ctrl_set_ccr),
//Register Outputs
.reg_out(ccr_zn_buss)
);
//Addr Out Mux
//--------------------------------
minibyte_genmux_2x addr_mux(
//Mux Inputs
.a_in(pc_addr_buss),
.b_in(m_addr_buss),
//Mux Select
.sel_in(ctrl_addr_mux),
//Mux Output
.mux_out(normal_addr_out)
);
//Debug Out Mux
//--------------------------------
minibyte_genmux_8x tm_debug_out_mux(
//Mux Inputs
.a_in(normal_addr_out), //0 -> Normal output
.b_in(alu_a_buss), //1 -> A output
.c_in({7'h0, alu_a_buss[7]}), //2 -> A (UPPER BIT) output
.d_in(m_addr_buss), //3 -> M output
.e_in(pc_addr_buss), //4 -> PC output
.f_in(ir_op_buss), //5 -> IR output
.g_in({6'h0,ccr_zn_buss}), //6 -> CCR output
.h_in(dft_cu_state), //7 -> CU STATE output
//Mux Select
.sel_in(tm_control[2:0]),
//Mux Output
.mux_out(addr_out)
);
//ALU
//--------------------------------
minibyte_alu alu(
//ALU Inputs
.a_in(alu_a_buss),
.b_in(data_in),
.alu_op_in(ctrl_alu_op),
.res_out(main_buss),
.flags_zn_out(flags_zn_buss)
);
//Control Unit
//--------------------------------
minibyte_cu cu(
//Basic Inputs
.clk_in(clk_in), .ena_in(ena_in), .rst_in(rst_in),
.halt_in(halt_in),
//IR Input
.ir_op_buss_in(ir_op_buss),
//ALU Flags Input
.ccr_flag_zn_in(ccr_zn_buss),
//Control signal outputs
.set_a_out(ctrl_set_a),
.set_m_out(ctrl_set_m),
.set_pc_out(ctrl_set_pc),
.set_ir_out(ctrl_set_ir),
.set_ccr_out(ctrl_set_ccr),
.inc_pc_out(ctrl_inc_pc),
//Addr select signals
.addr_mux_out(ctrl_addr_mux),
//Alu control signals
.alu_op_out(ctrl_alu_op),
//Write to memory
.we_out(ctrl_we_out),
//Drive enable on data bus
.drive_out(ctrl_drive_out),
//DFT Output
.dft_curr_state(dft_cu_state)
);
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//---------------------------------
//Control Unit
//---------------------------------
module minibyte_cu(
//Basic Inputs
input wire clk_in, ena_in, rst_in,
input wire halt_in,
//IR Input
input wire [7:0] ir_op_buss_in,
//ALU Flags Input
input wire [1:0] ccr_flag_zn_in,
//Control signal outputs
output reg set_a_out,
output reg set_m_out,
output reg set_pc_out,
output reg set_ir_out,
output reg set_ccr_out,
output reg inc_pc_out,
//Addr select signals
output reg addr_mux_out,
//Alu control signals
output reg [3:0] alu_op_out,
//Write to memory
output reg we_out,
//Drive enable on data bus
output reg drive_out,
//DFT Output
output reg [7:0] dft_curr_state
);
//State machine memory
//--------------------------
reg [7:0] curr_state, next_state;
//CPU IR opcodes
//--------------------------
parameter IR_NOP = 8'h00;
parameter IR_LDA_IMM = 8'h01;
parameter IR_LDA_DIR = 8'h02;
parameter IR_STA_DIR = 8'h03;
parameter IR_STA_IND = 8'h04;
parameter IR_ADD_IMM = 8'h05;
parameter IR_ADD_DIR = 8'h06;
parameter IR_SUB_IMM = 8'h07;
parameter IR_SUB_DIR = 8'h08;
parameter IR_AND_IMM = 8'h09;
parameter IR_AND_DIR = 8'h0A;
parameter IR_OR_IMM = 8'h0B;
parameter IR_OR_DIR = 8'h0C;
parameter IR_XOR_IMM = 8'h0D;
parameter IR_XOR_DIR = 8'h0E;
parameter IR_LSL_IMM = 8'h0F;
parameter IR_LSL_DIR = 8'h10;
parameter IR_LSR_IMM = 8'h11;
parameter IR_LSR_DIR = 8'h12;
parameter IR_ASL_IMM = 8'h13;
parameter IR_ASL_DIR = 8'h14;
parameter IR_ASR_IMM = 8'h15;
parameter IR_ASR_DIR = 8'h16;
parameter IR_RSL_IMM = 8'h17;
parameter IR_RSL_DIR = 8'h18;
parameter IR_RSR_IMM = 8'h19;
parameter IR_RSR_DIR = 8'h1A;
parameter IR_JMP_DIR = 8'h1B;
parameter IR_JMP_IND = 8'h1C;
parameter IR_BNE_DIR = 8'h1D;
parameter IR_BNE_IND = 8'h1E;
parameter IR_BEQ_DIR = 8'h1F;
parameter IR_BEQ_IND = 8'h20;
parameter IR_BPL_DIR = 8'h21;
parameter IR_BPL_IND = 8'h22;
parameter IR_BMI_DIR = 8'h23;
parameter IR_BMI_IND = 8'h24;
//State machine opcodes
//--------------------------
parameter S_RESET_0 = 8'h00;
parameter S_PC_INC_0 = 8'h01;
parameter S_FETCH_0 = 8'h02;
parameter S_FETCH_1 = 8'h03;
parameter S_FETCH_2 = 8'h04;
parameter S_DECODE_0 = 8'h05;
parameter S_LDA_IMM_0 = 8'h06;
parameter S_LDA_IMM_1 = 8'h07;
parameter S_LDA_DIR_0 = 8'h08;
parameter S_LDA_DIR_1 = 8'h09;
parameter S_LDA_DIR_2 = 8'h0A;
parameter S_LDA_DIR_3 = 8'h0B;
parameter S_STA_DIR_0 = 8'h0C;
parameter S_STA_DIR_1 = 8'h0D;
parameter S_STA_DIR_2 = 8'h0E;
parameter S_STA_DIR_3 = 8'h0F;
parameter S_STA_IND_0 = 8'h10;
parameter S_STA_IND_1 = 8'h11;
parameter S_STA_IND_2 = 8'h12;
parameter S_STA_IND_3 = 8'h13;
parameter S_STA_IND_4 = 8'h14;
parameter S_STA_IND_5 = 8'h15;
parameter S_ADD_IMM_0 = 8'h16;
parameter S_ADD_IMM_1 = 8'h17;
parameter S_ADD_DIR_0 = 8'h18;
parameter S_ADD_DIR_1 = 8'h19;
parameter S_ADD_DIR_2 = 8'h1A;
parameter S_ADD_DIR_3 = 8'h1B;
parameter S_SUB_IMM_0 = 8'h1C;
parameter S_SUB_IMM_1 = 8'h1D;
parameter S_SUB_DIR_0 = 8'h1E;
parameter S_SUB_DIR_1 = 8'h1F;
parameter S_SUB_DIR_2 = 8'h20;
parameter S_SUB_DIR_3 = 8'h21;
parameter S_AND_IMM_0 = 8'h22;
parameter S_AND_IMM_1 = 8'h23;
parameter S_AND_DIR_0 = 8'h24;
parameter S_AND_DIR_1 = 8'h25;
parameter S_AND_DIR_2 = 8'h26;
parameter S_AND_DIR_3 = 8'h27;
parameter S_OR_IMM_0 = 8'h28;
parameter S_OR_IMM_1 = 8'h29;
parameter S_OR_DIR_0 = 8'h2A;
parameter S_OR_DIR_1 = 8'h2B;
parameter S_OR_DIR_2 = 8'h2C;
parameter S_OR_DIR_3 = 8'h2D;
parameter S_XOR_IMM_0 = 8'h2E;
parameter S_XOR_IMM_1 = 8'h2F;
parameter S_XOR_DIR_0 = 8'h30;
parameter S_XOR_DIR_1 = 8'h31;
parameter S_XOR_DIR_2 = 8'h32;
parameter S_XOR_DIR_3 = 8'h33;
parameter S_LSL_IMM_0 = 8'h34;
parameter S_LSL_IMM_1 = 8'h35;
parameter S_LSL_DIR_0 = 8'h36;
parameter S_LSL_DIR_1 = 8'h37;
parameter S_LSL_DIR_2 = 8'h38;
parameter S_LSL_DIR_3 = 8'h39;
parameter S_LSR_IMM_0 = 8'h3A;
parameter S_LSR_IMM_1 = 8'h3B;
parameter S_LSR_DIR_0 = 8'h3C;
parameter S_LSR_DIR_1 = 8'h3D;
parameter S_LSR_DIR_2 = 8'h3E;
parameter S_LSR_DIR_3 = 8'h3F;
parameter S_ASL_IMM_0 = 8'h40;
parameter S_ASL_IMM_1 = 8'h41;
parameter S_ASL_DIR_0 = 8'h42;
parameter S_ASL_DIR_1 = 8'h43;
parameter S_ASL_DIR_2 = 8'h44;
parameter S_ASL_DIR_3 = 8'h45;
parameter S_ASR_IMM_0 = 8'h46;
parameter S_ASR_IMM_1 = 8'h47;
parameter S_ASR_DIR_0 = 8'h48;
parameter S_ASR_DIR_1 = 8'h49;
parameter S_ASR_DIR_2 = 8'h4A;
parameter S_ASR_DIR_3 = 8'h4B;
parameter S_RSL_IMM_0 = 8'h4C;
parameter S_RSL_IMM_1 = 8'h4D;
parameter S_RSL_DIR_0 = 8'h4E;
parameter S_RSL_DIR_1 = 8'h4F;
parameter S_RSL_DIR_2 = 8'h50;
parameter S_RSL_DIR_3 = 8'h51;
parameter S_RSR_IMM_0 = 8'h52;
parameter S_RSR_IMM_1 = 8'h53;
parameter S_RSR_DIR_0 = 8'h54;
parameter S_RSR_DIR_1 = 8'h55;
parameter S_RSR_DIR_2 = 8'h56;
parameter S_RSR_DIR_3 = 8'h57;
parameter S_JMP_DIR_0 = 8'h58;
parameter S_JMP_DIR_1 = 8'h59;
parameter S_JMP_IND_0 = 8'h5A;
parameter S_JMP_IND_1 = 8'h5B;
parameter S_JMP_IND_2 = 8'h5C;
parameter S_JMP_IND_3 = 8'h5D;
//--------------------------
//ALU OPS
//--------------------------
parameter OP_ALU_PASSA = 4'b0000;
parameter OP_ALU_PASSB = 4'b0001;
parameter OP_ALU_ADD = 4'b0010;
parameter OP_ALU_SUB = 4'b0011;
parameter OP_ALU_AND = 4'b0100;
parameter OP_ALU_OR = 4'b0101;
parameter OP_ALU_XOR = 4'b0110;
parameter OP_ALU_LSL = 4'b0111;
parameter OP_ALU_LSR = 4'b1000;
parameter OP_ALU_ASL = 4'b1001;
parameter OP_ALU_ASR = 4'b1010;
parameter OP_ALU_RSL = 4'b1011;
parameter OP_ALU_RSR = 4'b1100;
//State memory block
//--------------------------
always @ (posedge clk_in or negedge rst_in) begin
//Reset to S_RESET_0 on reset
if(!rst_in)
curr_state <= S_RESET_0;
//Dont move states if enable is low
else if(!ena_in)
curr_state <= curr_state;
//Otherwise go to next state on every clk
else
curr_state <= next_state;
end
//Output logic
//--------------------------
always @ (curr_state) begin
case(curr_state)
//Reset sequence
//-----
//Do nothing until the next state
S_RESET_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU dont care
alu_op_out = 0;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//PC Increment
//-----
//Increment PC
S_PC_INC_0: begin
//Increment program counter
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 1;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU dont care
alu_op_out = 0;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Fetch sequence
//-----
//Send PC addr out
S_FETCH_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Load IR from memory
S_FETCH_1: begin
//Set IR Reg
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 1;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Inc PC now that IR is loaded
S_FETCH_2: begin
//Inc PC
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 1;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Decode sequence
//-----
//Do nothing until the next state
S_DECODE_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU dont care
alu_op_out = 0;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//LDA_IMM sequence
//-----
//Pass incoming data from memory to the main buss
S_LDA_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A
S_LDA_IMM_1: begin
//Latch A
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//LDA_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_LDA_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_LDA_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M
S_LDA_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A
S_LDA_DIR_3: begin
//Latch A
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//STA_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_STA_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_STA_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set address and WE, also prepare A data on the main buss
S_STA_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//A (A input) passthrough to main bus
alu_op_out = OP_ALU_PASSA;
//Set WE so that the receiving device is ready for us to drive data
we_out = 1;
drive_out = 0;
end
//Drive the data out
S_STA_DIR_3: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//A (A input) passthrough to main bus
alu_op_out = OP_ALU_PASSA;
//Drive out A data
we_out = 1;
drive_out = 1;
end
//STA_IND sequence
//-----
//Pass incoming data from memory to the main buss
S_STA_IND_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_STA_IND_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Fetch data located at this address
S_STA_IND_2: begin
//Latch M
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_STA_IND_3: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set address and WE, also prepare A data on the main buss
S_STA_IND_4: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//A (A input) passthrough to main bus
alu_op_out = OP_ALU_PASSA;
//Set WE so that the receiving device is ready for us to drive data
we_out = 1;
drive_out = 0;
end
//Drive the data out
S_STA_IND_5: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//A (A input) passthrough to main bus
alu_op_out = OP_ALU_PASSA;
//Drive out A data
we_out = 1;
drive_out = 1;
end
//ADD_IMM sequence
//-----
//Add the incoming data from the operand that the PC is pointing to
S_ADD_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Addition
alu_op_out = OP_ALU_ADD;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_ADD_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Addition
alu_op_out = OP_ALU_ADD;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//ADD_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_ADD_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_ADD_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to add incoming data
S_ADD_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Addition
alu_op_out = OP_ALU_ADD;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_ADD_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Addition
alu_op_out = OP_ALU_ADD;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//SUB_IMM sequence
//-----
//Subtract the incoming data from the operand that the PC is pointing to
S_SUB_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Subtraction
alu_op_out = OP_ALU_SUB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_SUB_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Subtraction
alu_op_out = OP_ALU_SUB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//SUB_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_SUB_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_SUB_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to subtract incoming data
S_SUB_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Subtraction
alu_op_out = OP_ALU_SUB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_SUB_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Subtraction
alu_op_out = OP_ALU_SUB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//AND_IMM sequence
//-----
//And the incoming data from the operand that the PC is pointing to
S_AND_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Logical AND
alu_op_out = OP_ALU_AND;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_AND_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Logical AND
alu_op_out = OP_ALU_AND;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//AND_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_AND_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_AND_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to AND incoming data
S_AND_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Logical AND
alu_op_out = OP_ALU_AND;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_AND_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Logical AND
alu_op_out = OP_ALU_AND;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//OR_IMM sequence
//-----
//And the incoming data from the operand that the PC is pointing to
S_OR_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Logical OR
alu_op_out = OP_ALU_OR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_OR_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Logical OR
alu_op_out = OP_ALU_OR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//OR_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_OR_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_OR_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to OR incoming data
S_OR_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Logical OR
alu_op_out = OP_ALU_OR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_OR_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Logical OR
alu_op_out = OP_ALU_OR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//XOR_IMM sequence
//-----
//And the incoming data from the operand that the PC is pointing to
S_XOR_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Logical XOR
alu_op_out = OP_ALU_XOR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_XOR_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Logical XOR
alu_op_out = OP_ALU_XOR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//XOR_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_XOR_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_XOR_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to XOR incoming data
S_XOR_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Logical XOR
alu_op_out = OP_ALU_XOR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_XOR_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Logical XOR
alu_op_out = OP_ALU_XOR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//LSL_IMM sequence
//-----
//Add the incoming data from the operand that the PC is pointing to
S_LSL_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Logical Shift Left
alu_op_out = OP_ALU_LSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_LSL_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Logical Shift Left
alu_op_out = OP_ALU_LSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//LSL_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_LSL_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_LSL_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to add incoming data
S_LSL_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Logical Shift Left
alu_op_out = OP_ALU_LSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_LSL_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Logical Shift Left
alu_op_out = OP_ALU_LSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//LSR_IMM sequence
//-----
//Add the incoming data from the operand that the PC is pointing to
S_LSR_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Logical Shift Right
alu_op_out = OP_ALU_LSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_LSR_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Logical Shift Right
alu_op_out = OP_ALU_LSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//LSR_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_LSR_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_LSR_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to add incoming data
S_LSR_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Logical Shift Right
alu_op_out = OP_ALU_LSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_LSR_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Logical Shift Right
alu_op_out = OP_ALU_LSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//ASL_IMM sequence
//-----
//Add the incoming data from the operand that the PC is pointing to
S_ASL_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Arithmetic Shift Left
alu_op_out = OP_ALU_ASL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_ASL_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Arithmetic Shift Left
alu_op_out = OP_ALU_ASL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//ASL_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_ASL_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_ASL_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to add incoming data
S_ASL_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Arithmetic Shift Left
alu_op_out = OP_ALU_ASL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_ASL_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Arithmetic Shift Left
alu_op_out = OP_ALU_ASL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//ASR_IMM sequence
//-----
//Add the incoming data from the operand that the PC is pointing to
S_ASR_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Arithmetic Shift Right
alu_op_out = OP_ALU_ASR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_ASR_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Arithmetic Shift Right
alu_op_out = OP_ALU_ASR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//ASR_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_ASR_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_ASR_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to add incoming data
S_ASR_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Arithmetic Shift Right
alu_op_out = OP_ALU_ASR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_ASR_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Arithmetic Shift Right
alu_op_out = OP_ALU_ASR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//RSL_IMM sequence
//-----
//Add the incoming data from the operand that the PC is pointing to
S_RSL_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Rotary Shift Left
alu_op_out = OP_ALU_RSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_RSL_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Rotary Shift Left
alu_op_out = OP_ALU_RSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//RSL_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_RSL_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_RSL_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to add incoming data
S_RSL_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Rotary Shift Left
alu_op_out = OP_ALU_RSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_RSL_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Rotary Shift Left
alu_op_out = OP_ALU_RSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//RSR_IMM sequence
//-----
//Add the incoming data from the operand that the PC is pointing to
S_RSR_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Rotary Shift Right
alu_op_out = OP_ALU_RSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_RSR_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Rotary Shift Right
alu_op_out = OP_ALU_RSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//RSR_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_RSR_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_RSR_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to add incoming data
S_RSR_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Rotary Shift Right
alu_op_out = OP_ALU_RSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_RSR_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Rotary Shift Right
alu_op_out = OP_ALU_RSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//JMP_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_JMP_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to PC
S_JMP_DIR_1: begin
//Latch PC
set_a_out = 0;
set_m_out = 0;
set_pc_out = 1;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//JMP_IND sequence
//-----
//Pass incoming data from memory to the main buss
S_JMP_IND_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_JMP_IND_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M
S_JMP_IND_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to PC
S_JMP_IND_3: begin
//Latch PC
set_a_out = 0;
set_m_out = 0;
set_pc_out = 1;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Default (INVALID) sequence
//-----
default: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU dont care
alu_op_out = 0;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
endcase
end
//Next state logic
//--------------------------
always @ (curr_state, ir_op_buss_in, ccr_flag_zn_in, halt_in) begin
//DFT Output
dft_curr_state = curr_state;
//Next state logic
case(curr_state)
//Reset sequence (skips PC increment on boot)
S_RESET_0: next_state = S_FETCH_0;
//PC Increment
S_PC_INC_0: next_state = S_FETCH_0;
//Fetch sequence
S_FETCH_0: begin
if(halt_in == 1)
next_state = S_FETCH_0; //Remain in S_FETCH_0 forever if halt is asserted
else
next_state = S_FETCH_1; //Otherwise continue fetching this instruction
end
S_FETCH_1: next_state = S_FETCH_2;
S_FETCH_2: next_state = S_DECODE_0;
//Decode IR Opcode
S_DECODE_0: begin
case(ir_op_buss_in)
//IR_NOP (does nothing)
IR_NOP: next_state = S_FETCH_0;
//IR_LDA_IMM (load immediate value to A)
IR_LDA_IMM: next_state = S_LDA_IMM_0;
//IR_LDA_DIR (load direct value to A)
IR_LDA_DIR: next_state = S_LDA_DIR_0;
//IR_STA_DIR (store A at direct address)
IR_STA_DIR: next_state = S_STA_DIR_0;
//IR_STA_IND (store A at indirect address)
IR_STA_IND: next_state = S_STA_IND_0;
//IR_ADD_IMM (add immediate value to A)
IR_ADD_IMM: next_state = S_ADD_IMM_0;
//IR_ADD_DIR (add direct value to A)
IR_ADD_DIR: next_state = S_ADD_DIR_0;
//IR_SUB_IMM (subtract immediate value from A)
IR_SUB_IMM: next_state = S_SUB_IMM_0;
//IR_SUB_DIR (subtract direct value from A)
IR_SUB_DIR: next_state = S_SUB_DIR_0;
//IR_AND_IMM (logical AND immediate value with A)
IR_AND_IMM: next_state = S_AND_IMM_0;
//IR_AND_DIR (logical AND direct value with A)
IR_AND_DIR: next_state = S_AND_DIR_0;
//IR_OR_IMM (logical OR immediate value with A)
IR_OR_IMM: next_state = S_OR_IMM_0;
//IR_OR_DIR (logical OR direct value with A)
IR_OR_DIR: next_state = S_OR_DIR_0;
//IR_XOR_IMM (logical XOR immediate value with A)
IR_XOR_IMM: next_state = S_XOR_IMM_0;
//IR_XOR_DIR (logical XOR direct value with A)
IR_XOR_DIR: next_state = S_XOR_DIR_0;
//IR_LSL_IMM (logical left shift immediate value with A)
IR_LSL_IMM: next_state = S_LSL_IMM_0;
//IR_LSL_DIR (logical left shift direct value with A)
IR_LSL_DIR: next_state = S_LSL_DIR_0;
//IR_LSR_IMM (logical right shift immediate value with A)
IR_LSR_IMM: next_state = S_LSR_IMM_0;
//IR_LSR_DIR (logical right shift direct value with A)
IR_LSR_DIR: next_state = S_LSR_DIR_0;
//IR_ASL_IMM (arithmetic left shift immediate value with A)
IR_ASL_IMM: next_state = S_ASL_IMM_0;
//IR_ASL_DIR (arithmetic left shift direct value with A)
IR_ASL_DIR: next_state = S_ASL_DIR_0;
//IR_ASR_IMM (arithmetic right shift immediate value with A)
IR_ASR_IMM: next_state = S_ASR_IMM_0;
//IR_ASR_DIR (arithmetic right shift direct value with A)
IR_ASR_DIR: next_state = S_ASR_DIR_0;
//IR_RSL_IMM (rotary left shift immediate value with A)
IR_RSL_IMM: next_state = S_RSL_IMM_0;
//IR_RSL_DIR (rotary left shift direct value with A)
IR_RSL_DIR: next_state = S_RSL_DIR_0;
//IR_RSR_IMM (rotary right shift immediate value with A)
IR_RSR_IMM: next_state = S_RSR_IMM_0;
//IR_RSR_DIR (rotary right shift direct value with A)
IR_RSR_DIR: next_state = S_RSR_DIR_0;
//IR_JMP_DIR (load direct value to PC)
IR_JMP_DIR: next_state = S_JMP_DIR_0;
//IR_LDA_DIR (load indirect value to PC)
IR_JMP_IND: next_state = S_JMP_IND_0;
//IR_BNE_DIR (banch if z clear direct)
IR_BNE_DIR: begin
if(ccr_flag_zn_in[1] == 0)
next_state = S_JMP_DIR_0;
else
next_state = S_PC_INC_0;
end
//IR_BNE_IND (banch if z clear indirect)
IR_BNE_IND: begin
if(ccr_flag_zn_in[1] == 0)
next_state = S_JMP_IND_0;
else
next_state = S_PC_INC_0;
end
//IR_BEQ_DIR (banch if z set direct)
IR_BEQ_DIR: begin
if(ccr_flag_zn_in[1] == 1)
next_state = S_JMP_DIR_0;
else
next_state = S_PC_INC_0;
end
//IR_BEQ_IND (banch if z set indirect)
IR_BEQ_IND: begin
if(ccr_flag_zn_in[1] == 1)
next_state = S_JMP_IND_0;
else
next_state = S_PC_INC_0;
end
//IR_BPL_DIR (banch if n clear direct)
IR_BPL_DIR: begin
if(ccr_flag_zn_in[0] == 0)
next_state = S_JMP_DIR_0;
else
next_state = S_PC_INC_0;
end
//IR_BPL_IND (banch if n clear indirect)
IR_BPL_IND: begin
if(ccr_flag_zn_in[0] == 0)
next_state = S_JMP_IND_0;
else
next_state = S_PC_INC_0;
end
//IR_BMI_DIR (banch if n set direct)
IR_BMI_DIR: begin
if(ccr_flag_zn_in[0] == 1)
next_state = S_JMP_DIR_0;
else
next_state = S_PC_INC_0;
end
//IR_BMI_IND (banch if n set indirect)
IR_BMI_IND: begin
if(ccr_flag_zn_in[0] == 1)
next_state = S_JMP_IND_0;
else
next_state = S_PC_INC_0;
end
//Invalid IR, goto fetch_0
default: next_state = S_FETCH_0;
endcase
end
//LDA_IMM sequence
S_LDA_IMM_0: next_state = S_LDA_IMM_1;
S_LDA_IMM_1: next_state = S_PC_INC_0;
//LDA_DIR sequence
S_LDA_DIR_0: next_state = S_LDA_DIR_1;
S_LDA_DIR_1: next_state = S_LDA_DIR_2;
S_LDA_DIR_2: next_state = S_LDA_DIR_3;
S_LDA_DIR_3: next_state = S_PC_INC_0;
//STA_DIR sequence
S_STA_DIR_0: next_state = S_STA_DIR_1;
S_STA_DIR_1: next_state = S_STA_DIR_2;
S_STA_DIR_2: next_state = S_STA_DIR_3;
S_STA_DIR_3: next_state = S_PC_INC_0;
//STA_IND sequence
S_STA_IND_0: next_state = S_STA_IND_1;
S_STA_IND_1: next_state = S_STA_IND_2;
S_STA_IND_2: next_state = S_STA_IND_3;
S_STA_IND_3: next_state = S_STA_IND_4;
S_STA_IND_4: next_state = S_STA_IND_5;
S_STA_IND_5: next_state = S_PC_INC_0;
//ADD_IMM sequence
S_ADD_IMM_0: next_state = S_ADD_IMM_1;
S_ADD_IMM_1: next_state = S_PC_INC_0;
//ADD_DIR sequence
S_ADD_DIR_0: next_state = S_ADD_DIR_1;
S_ADD_DIR_1: next_state = S_ADD_DIR_2;
S_ADD_DIR_2: next_state = S_ADD_DIR_3;
S_ADD_DIR_3: next_state = S_PC_INC_0;
//SUB_IMM sequence
S_SUB_IMM_0: next_state = S_SUB_IMM_1;
S_SUB_IMM_1: next_state = S_PC_INC_0;
//SUB_DIR sequence
S_SUB_DIR_0: next_state = S_SUB_DIR_1;
S_SUB_DIR_1: next_state = S_SUB_DIR_2;
S_SUB_DIR_2: next_state = S_SUB_DIR_3;
S_SUB_DIR_3: next_state = S_PC_INC_0;
//AND_IMM sequence
S_AND_IMM_0: next_state = S_AND_IMM_1;
S_AND_IMM_1: next_state = S_PC_INC_0;
//AND_DIR sequence
S_AND_DIR_0: next_state = S_AND_DIR_1;
S_AND_DIR_1: next_state = S_AND_DIR_2;
S_AND_DIR_2: next_state = S_AND_DIR_3;
S_AND_DIR_3: next_state = S_PC_INC_0;
//OR_IMM sequence
S_OR_IMM_0: next_state = S_OR_IMM_1;
S_OR_IMM_1: next_state = S_PC_INC_0;
//OR_DIR sequence
S_OR_DIR_0: next_state = S_OR_DIR_1;
S_OR_DIR_1: next_state = S_OR_DIR_2;
S_OR_DIR_2: next_state = S_OR_DIR_3;
S_OR_DIR_3: next_state = S_PC_INC_0;
//XOR_IMM sequence
S_XOR_IMM_0: next_state = S_XOR_IMM_1;
S_XOR_IMM_1: next_state = S_PC_INC_0;
//XOR_DIR sequence
S_XOR_DIR_0: next_state = S_XOR_DIR_1;
S_XOR_DIR_1: next_state = S_XOR_DIR_2;
S_XOR_DIR_2: next_state = S_XOR_DIR_3;
S_XOR_DIR_3: next_state = S_PC_INC_0;
//LSL_IMM sequence
S_LSL_IMM_0: next_state = S_LSL_IMM_1;
S_LSL_IMM_1: next_state = S_PC_INC_0;
//LSL_DIR sequence
S_LSL_DIR_0: next_state = S_LSL_DIR_1;
S_LSL_DIR_1: next_state = S_LSL_DIR_2;
S_LSL_DIR_2: next_state = S_LSL_DIR_3;
S_LSL_DIR_3: next_state = S_PC_INC_0;
//LSR_IMM sequence
S_LSR_IMM_0: next_state = S_LSR_IMM_1;
S_LSR_IMM_1: next_state = S_PC_INC_0;
//LSR_DIR sequence
S_LSR_DIR_0: next_state = S_LSR_DIR_1;
S_LSR_DIR_1: next_state = S_LSR_DIR_2;
S_LSR_DIR_2: next_state = S_LSR_DIR_3;
S_LSR_DIR_3: next_state = S_PC_INC_0;
//ASL_IMM sequence
S_ASL_IMM_0: next_state = S_ASL_IMM_1;
S_ASL_IMM_1: next_state = S_PC_INC_0;
//ASL_DIR sequence
S_ASL_DIR_0: next_state = S_ASL_DIR_1;
S_ASL_DIR_1: next_state = S_ASL_DIR_2;
S_ASL_DIR_2: next_state = S_ASL_DIR_3;
S_ASL_DIR_3: next_state = S_PC_INC_0;
//ASR_IMM sequence
S_ASR_IMM_0: next_state = S_ASR_IMM_1;
S_ASR_IMM_1: next_state = S_PC_INC_0;
//ASR_DIR sequence
S_ASR_DIR_0: next_state = S_ASR_DIR_1;
S_ASR_DIR_1: next_state = S_ASR_DIR_2;
S_ASR_DIR_2: next_state = S_ASR_DIR_3;
S_ASR_DIR_3: next_state = S_PC_INC_0;
//RSL_IMM sequence
S_RSL_IMM_0: next_state = S_RSL_IMM_1;
S_RSL_IMM_1: next_state = S_PC_INC_0;
//RSL_DIR sequence
S_RSL_DIR_0: next_state = S_RSL_DIR_1;
S_RSL_DIR_1: next_state = S_RSL_DIR_2;
S_RSL_DIR_2: next_state = S_RSL_DIR_3;
S_RSL_DIR_3: next_state = S_PC_INC_0;
//RSR_IMM sequence
S_RSR_IMM_0: next_state = S_RSR_IMM_1;
S_RSR_IMM_1: next_state = S_PC_INC_0;
//RSR_DIR sequence
S_RSR_DIR_0: next_state = S_RSR_DIR_1;
S_RSR_DIR_1: next_state = S_RSR_DIR_2;
S_RSR_DIR_2: next_state = S_RSR_DIR_3;
S_RSR_DIR_3: next_state = S_PC_INC_0;
//JMP_DIR sequence
S_JMP_DIR_0: next_state = S_JMP_DIR_1;
S_JMP_DIR_1: next_state = S_FETCH_0;
//JMP_IND sequence
S_JMP_IND_0: next_state = S_JMP_IND_1;
S_JMP_IND_1: next_state = S_JMP_IND_2;
S_JMP_IND_2: next_state = S_JMP_IND_3;
S_JMP_IND_3: next_state = S_FETCH_0;
//Should never get here
default:
next_state = S_PC_INC_0;
endcase
end
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//---------------------------------------------------------------------------------------------------------
// MINIBYTE ALU
//---------------------------------------------------------------------------------------------------------
// OPERATION | ALU_OP | MEANING
//---------------------------------------------------------------------------------------------------------
// PASSA | 0b0000 | Passthrough input A
// PASSB | 0b0001 | Passthrough input B
// ADD | 0b0010 | Add A and B
// SUB | 0b0011 | Subtract B from A
// AND | 0b0100 | Logical and of A, B
// OR | 0b0101 | Logical or of A, B
// XOR | 0b0110 | Logical xor of A, B
// LSL | 0b0111 | Logical shift A left by B
// LSR | 0b1000 | Logical shift A right by B
// ASL | 0b1001 | Arithmetic shift A left by B
// ASR | 0b1010 | Arithmetic shift A right by B
// RSL | 0b1011 | Rotary shift A left by B
// RSR | 0b1100 | Rotary shift A right by B
//---------------------------------------------------------------------------------------------------------
//--------------------------
//Params
//--------------------------
parameter ALU_PASSA = 4'b0000;
parameter ALU_PASSB = 4'b0001;
parameter ALU_ADD = 4'b0010;
parameter ALU_SUB = 4'b0011;
parameter ALU_AND = 4'b0100;
parameter ALU_OR = 4'b0101;
parameter ALU_XOR = 4'b0110;
parameter ALU_LSL = 4'b0111;
parameter ALU_LSR = 4'b1000;
parameter ALU_ASL = 4'b1001;
parameter ALU_ASR = 4'b1010;
parameter ALU_RSL = 4'b1011;
parameter ALU_RSR = 4'b1100;
//--------------------------
//ALU Module
//--------------------------
module minibyte_alu (
//ALU Inputs
input wire signed [7:0] a_in,
input wire signed [7:0] b_in,
input wire [3:0] alu_op_in,
//ALU Outputs
output reg signed [7:0] res_out,
output reg [1:0] flags_zn_out
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//--------------------------
//General Register Module
//--------------------------
module minibyte_genreg (
//Basic Inputs
input wire clk_in, rst_in,
//Register Inputs
input wire [7:0] reg_in,
input wire set_in,
//Register Outputs
output reg [7:0] reg_out
);
//Main Procedural Block
//--------------------------
always @(posedge clk_in or negedge rst_in) begin
//Reset if rst goes low
if(!rst_in)
reg_out <= 0;
else
//Set register to input if set signal goes high on a clk
if(set_in)
reg_out <= reg_in;
end
endmodule
//--------------------------
//CCR Register Module
//--------------------------
module minibyte_ccrreg (
//Basic Inputs
input wire clk_in, rst_in,
//Register Inputs
input wire [1:0] reg_in,
input wire set_in,
//Register Outputs
output reg [1:0] reg_out
);
//Main Procedural Block
//--------------------------
always @(posedge clk_in or negedge rst_in) begin
//Reset if rst goes low
if(!rst_in)
reg_out <= 0;
else
//Set register to input if set signal goes high on a clk
if(set_in)
reg_out <= reg_in;
end
endmodule
//---------------------------------
//Program Counter Register Module
//---------------------------------
module minibyte_pcreg (
//Basic Inputs
input wire clk_in, rst_in,
//Register Inputs
input wire [7:0] reg_in,
input wire set_in,
input wire inc_in,
//Register Outputs
output reg [7:0] reg_out
);
//Main Procedural Block
//--------------------------
always @(posedge clk_in or negedge rst_in) begin
//Reset if rst goes low
if(!rst_in)
reg_out <= 0;
else
//Set register to input if set signal goes high
if(set_in)
reg_out <= reg_in;
//Increment register if inc signal goes high on a clk
else if(inc_in)
reg_out <= reg_out + 1;
end
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//---------------------------------
//Generic 2->1 Mux Module
//---------------------------------
module minibyte_genmux_2x(
//Mux Inputs
input wire [7:0] a_in,
input wire [7:0] b_in,
//Mux Select
input wire sel_in,
//Mux Output
output reg [7:0] mux_out
);
//Main Procedural Block
//--------------------------
always @(*) begin
//A out if sel is 0
if(sel_in == 0)
mux_out = a_in;
//B out if sel is 1
else
mux_out = b_in;
end
endmodule
//---------------------------------
//Generic 4->1 Mux Module
//---------------------------------
module minibyte_genmux_4x(
//Mux Inputs
input wire [7:0] a_in,
input wire [7:0] b_in,
input wire [7:0] c_in,
input wire [7:0] d_in,
//Mux Select
input wire [1:0] sel_in,
//Mux Output
output reg [7:0] mux_out
);
//Main Procedural Block
//--------------------------
always @(*) begin
//A out if sel is 00
if(sel_in == 2'b00)
mux_out = a_in;
//B out if sel is 01
else if(sel_in == 2'b01)
mux_out = b_in;
//C out if sel is 10
else if(sel_in == 2'b10)
mux_out = c_in;
//D out if sel is 11
else
mux_out = d_in;
end
endmodule
//---------------------------------
//Generic 8->1 Mux Module
//---------------------------------
module minibyte_genmux_8x(
//Mux Inputs
input wire [7:0] a_in,
input wire [7:0] b_in,
input wire [7:0] c_in,
input wire [7:0] d_in,
input wire [7:0] e_in,
input wire [7:0] f_in,
input wire [7:0] g_in,
input wire [7:0] h_in,
//Mux Select
input wire [2:0] sel_in,
//Mux Output
output reg [7:0] mux_out
);
//Main Procedural Block
//--------------------------
always @(*) begin
//A out if sel is 000
if(sel_in == 3'b000)
mux_out = a_in;
//B out if sel is 001
else if(sel_in == 3'b001)
mux_out = b_in;
//C out if sel is 010
else if(sel_in == 3'b010)
mux_out = c_in;
//D out if sel is 011
else if(sel_in == 3'b011)
mux_out = d_in;
//E out if sel is 100
else if(sel_in == 3'b100)
mux_out = e_in;
//F out if sel is 101
else if(sel_in == 3'b101)
mux_out = f_in;
//G out if sel is 110
else if(sel_in == 3'b110)
mux_out = g_in;
//H out if sel is 111
else
mux_out = h_in;
end
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//---------------------------------
//Drive enable device
//---------------------------------
module drive_enable_fanout(
//Drive enable input signal
input wire drive_en,
//Output drive signals
output reg [7:0] drive
);
//Main Procedural Block
//--------------------------
always @(*) begin
if(drive_en == 0)
drive = 0;
else
drive = 8'hff;
end
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//CPU IR opcodes
//--------------------------
parameter _NOP = 8'h00;
parameter _LDA_IMM = 8'h01;
parameter _LDA_DIR = 8'h02;
parameter _STA_DIR = 8'h03;
//parameter _STA_IND = 8'h04;
parameter _ADD_IMM = 8'h05;
//parameter _ADD_DIR = 8'h06;
//parameter _SUB_IMM = 8'h07;
//parameter _SUB_DIR = 8'h08;
//parameter _AND_IMM = 8'h09;
//parameter _AND_DIR = 8'h0A;
//parameter _OR_IMM = 8'h0B;
//parameter _OR_DIR = 8'h0C;
//parameter _XOR_IMM = 8'h0D;
//parameter _XOR_DIR = 8'h0E;
parameter _LSL_IMM = 8'h0F;
//parameter _LSL_DIR = 8'h10;
//parameter _LSR_IMM = 8'h11;
//parameter _LSR_DIR = 8'h12;
//parameter _ASL_IMM = 8'h13;
//parameter _ASL_DIR = 8'h14;
//parameter _ASR_IMM = 8'h15;
//parameter _ASR_DIR = 8'h16;
//parameter _RSL_IMM = 8'h17;
//parameter _RSL_DIR = 8'h18;
//parameter _RSR_IMM = 8'h19;
//parameter _RSR_DIR = 8'h1A;
parameter _JMP_DIR = 8'h1B;
//parameter _JMP_IND = 8'h1C;
parameter _BNE_DIR = 8'h1D;
//parameter _BNE_IND = 8'h1E;
//parameter _BEQ_DIR = 8'h1F;
//parameter _BEQ_IND = 8'h20;
parameter _BPL_DIR = 8'h21;
//parameter _BPL_IND = 8'h22;
//parameter _BMI_DIR = 8'h23;
//parameter _BMI_IND = 8'h24;
//--------------------------
//Demo ROM Program
//--------------------------
module demo_rom_64B(
//Input Addr
input wire [5:0] address,
//Output Data
output reg [7:0] data_out
);
always @(address)
case(address)
6'h00: data_out = _NOP; //First istr is a NOP
6'h01: data_out = _LDA_IMM; //Make sure A is zero
6'h02: data_out = 0;
6'h03: data_out = _NOP; //NOP is the START of the LOOP0
6'h04: data_out = _ADD_IMM; //ADD 1 to A
6'h05: data_out = 1;
6'h06: data_out = _STA_DIR; //Write this value to 0x40
6'h07: data_out = 8'h40;
6'h08: data_out = _BNE_DIR; //Keep branching to LOOP0 until we roll over to 0
6'h09: data_out = 8'h03;
6'h0A: data_out = _LDA_IMM; //Load a 1 into A
6'h0B: data_out = 1;
6'h0C: data_out = _STA_DIR; //Write this value to 0x40
6'h0D: data_out = 8'h40;
6'h0E: data_out = _NOP; //NOP is the START of the LOOP1
6'h0F: data_out = _LSL_IMM; //Shift A left by 1
6'h10: data_out = 1;
6'h11: data_out = _STA_DIR; //Write this value to 0x40
6'h12: data_out = 8'h40;
6'h13: data_out = _BPL_DIR; //Keep branching to LOOP1 until we hit 0b10000000
6'h14: data_out = 8'h0E;
6'h15: data_out = _LDA_IMM; //Load DEADBEEF into RAM
6'h16: data_out = 8'hDE;
6'h17: data_out = _STA_DIR;
6'h18: data_out = 8'h78;
6'h19: data_out = _LDA_IMM;
6'h1A: data_out = 8'hAD;
6'h1B: data_out = _STA_DIR;
6'h1C: data_out = 8'h79;
6'h1D: data_out = _LDA_IMM;
6'h1E: data_out = 8'hBE;
6'h1F: data_out = _STA_DIR;
6'h20: data_out = 8'h7A;
6'h21: data_out = _LDA_IMM;
6'h22: data_out = 8'hEF;
6'h23: data_out = _STA_DIR;
6'h24: data_out = 8'h7B;
6'h25: data_out = _LDA_DIR; //READ out the contents of RAM
6'h26: data_out = 8'h78;
6'h27: data_out = _STA_DIR; //Write this value to 0x40
6'h28: data_out = 8'h40;
6'h29: data_out = _LDA_DIR; //READ out the contents of RAM
6'h2A: data_out = 8'h79;
6'h2B: data_out = _STA_DIR; //Write this value to 0x40
6'h2C: data_out = 8'h40;
6'h2D: data_out = _LDA_DIR; //READ out the contents of RAM
6'h2E: data_out = 8'h7A;
6'h2F: data_out = _STA_DIR; //Write this value to 0x40
6'h30: data_out = 8'h40;
6'h31: data_out = _LDA_DIR; //READ out the contents of RAM
6'h32: data_out = 8'h7B;
6'h33: data_out = _STA_DIR; //Write this value to 0x40
6'h34: data_out = 8'h40;
6'h35: data_out = _JMP_DIR; //Start the whole thing over!
6'h36: data_out = 8'h00;
default: data_out = 0; //Unused space
endcase
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//--------------------------
//REGISTER RAM
//--------------------------
module reg_ram_8B(
//Input CLK and RST
input wire clk_in,
input wire rst_in,
//Input Addr
input wire [2:0] address,
//Input Data
input wire [7:0] data_in,
//Input WE and EN
input wire we_in,
input wire en_in,
//Output Data
output reg [7:0] data_out
);
//Data busses
//------------------------------------
reg [7:0] r_we;
reg [7:0] r0_out_data;
reg [7:0] r1_out_data;
reg [7:0] r2_out_data;
reg [7:0] r3_out_data;
reg [7:0] r4_out_data;
reg [7:0] r5_out_data;
reg [7:0] r6_out_data;
reg [7:0] r7_out_data;
//Data registers
//------------------------------------
minibyte_genreg r0(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[0]),
//Register Outputs
.reg_out(r0_out_data)
);
minibyte_genreg r1(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[1]),
//Register Outputs
.reg_out(r1_out_data)
);
minibyte_genreg r2(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[2]),
//Register Outputs
.reg_out(r2_out_data)
);
minibyte_genreg r3(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[3]),
//Register Outputs
.reg_out(r3_out_data)
);
minibyte_genreg r4(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[4]),
//Register Outputs
.reg_out(r4_out_data)
);
minibyte_genreg r5(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[5]),
//Register Outputs
.reg_out(r5_out_data)
);
minibyte_genreg r6(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[6]),
//Register Outputs
.reg_out(r6_out_data)
);
minibyte_genreg r7(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[7]),
//Register Outputs
.reg_out(r7_out_data)
);
//Register control logic
//------------------------------------
always @ (*) begin
if (!en_in) begin
data_out = 8'h00;
r_we = 8'h00;
end
else if (we_in) begin
case(address)
3'b000:
r_we = 8'b00000001;
3'b001:
r_we = 8'b00000010;
3'b010:
r_we = 8'b00000100;
3'b011:
r_we = 8'b00001000;
3'b100:
r_we = 8'b00010000;
3'b101:
r_we = 8'b00100000;
3'b110:
r_we = 8'b01000000;
3'b111:
r_we = 8'b10000000;
default:
r_we = 8'b00000000;
endcase
data_out = 8'h00;
end
else begin
case(address)
3'b000:
data_out = r0_out_data;
3'b001:
data_out = r1_out_data;
3'b010:
data_out = r2_out_data;
3'b011:
data_out = r3_out_data;
3'b100:
data_out = r4_out_data;
3'b101:
data_out = r5_out_data;
3'b110:
data_out = r6_out_data;
3'b111:
data_out = r7_out_data;
endcase
r_we = 8'h00;
end
end
endmodule
|
module minibyte_alu (
//ALU Inputs
input wire signed [7:0] a_in,
input wire signed [7:0] b_in,
input wire [3:0] alu_op_in,
//ALU Outputs
output reg signed [7:0] res_out,
output reg [1:0] flags_zn_out
);
//Main Procedural Block
//--------------------------
always @(*) begin
//Assign ALU result
//---------------------
case(alu_op_in)
//A Passthrough
//--------------
ALU_PASSA:
res_out = a_in;
//B Passthrough
//--------------
ALU_PASSB:
res_out = b_in;
//Addition
//--------------
ALU_ADD:
res_out = a_in + b_in;
//Subtraction
//--------------
ALU_SUB:
res_out = a_in - b_in;
//Logical AND
//--------------
ALU_AND:
res_out = a_in & b_in;
//Logical OR
//--------------
ALU_OR:
res_out = a_in | b_in;
//Logical XOR
//--------------
ALU_XOR:
res_out = a_in ^ b_in;
//Logical Shift Left
//--------------
ALU_LSL:
res_out = a_in << b_in;
//Logical Shift Right
//--------------
ALU_LSR:
res_out = a_in >> b_in;
//Arithmetic Shift Left
//--------------
ALU_ASL:
res_out = a_in <<< b_in;
//Arithmetic Shift Right
//--------------
ALU_ASR:
res_out = a_in >>> b_in;
//Rotary Shift Left
//--------------
ALU_RSL:
case(b_in[2:0])
//Hardcoded concatenations of all possible inputs
3'b000:
res_out = a_in;
3'b001:
res_out = {a_in[6:0], a_in[7]};
3'b010:
res_out = {a_in[5:0], a_in[7:6]};
3'b011:
res_out = {a_in[4:0], a_in[7:5]};
3'b100:
res_out = {a_in[3:0], a_in[7:4]};
3'b101:
res_out = {a_in[2:0], a_in[7:3]};
3'b110:
res_out = {a_in[1:0], a_in[7:2]};
3'b111:
res_out = {a_in[0], a_in[7:1]};
endcase
//Rotary Shift Right
//--------------
ALU_RSR:
case(b_in[2:0])
//Hardcoded concatenations of all possible inputs
3'b000:
res_out = a_in;
3'b001:
res_out = {a_in[0], a_in[7:1]};
3'b010:
res_out = {a_in[1:0], a_in[7:2]};
3'b011:
res_out = {a_in[2:0], a_in[7:3]};
3'b100:
res_out = {a_in[3:0], a_in[7:4]};
3'b101:
res_out = {a_in[4:0], a_in[7:5]};
3'b110:
res_out = {a_in[5:0], a_in[7:6]};
3'b111:
res_out = {a_in[6:0], a_in[7]};
endcase
//Default (SHOULD NEVER GET HERE)
//--------------
default:
res_out = 0;
endcase
//Assign Zero flag
//---------------------
if(res_out == 0)
flags_zn_out[1] = 1;
else
flags_zn_out[1] = 0;
//Assign Negative flag
//---------------------
flags_zn_out[0] = res_out[7];
end
endmodule
|
tt06-finale_0100
|
tt06-finale
|
zacharysfrazee-tt06-minibyte-cpu
|
task_minibyte_cpu
|
tt_um_minibyte
|
You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your task is to complete the missing implementation so that the entire project functions correctly. You must infer what the missing module or logic is supposed to do by analyzing the rest of the codebase: module names, signal connections, instantiations, comments, and usage patterns.
Follow these rules:
1. Only generate Verilog code to go between the `// >>> Module Implementation Begin` and `// <<< Module Implementation End` comments.
2. Use Verilog-2001 syntax. Ensure the code is synthesizable.
3. Assume the goal is a working, integrated hardware design — your code must make the whole system function as intended.
4. Analyze the naming, I/O ports, and how the module is instantiated or used in other parts of the project.
5. Implement correct behavior based on design context. Do not guess randomly — reason it out.
6. Avoid vendor-specific features unless explicitly required.
7. Do not output comments, explanation, or anything outside the required code region unless explicitly asked.
Your output should contain **only the Verilog code** that fits inside the marked region.
|
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
`define default_netname none
//---------------------------------
//Top Level Project Module
//---------------------------------
module tt_um_minibyte (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
//---------------------------------
//Top Level Singal Notes
//---------------------------------
//ui_in => Test and Configuration bits
//uo_out => WE and 7-bit Address Buss
//uio_in/uio_out => 8-bit Bidirectional Data Buss
//uio_oe => Output Enable for Data Buss
//---------------------------------
//ui_in (Test)
// bit[7] => ENABLE ONBOARD REG RAM
// bit[6:5] => UNUSED
// bit[4] => ENABLE DEMO ROM
// bit[3] => HALT CONTROL UNIT
// bit[2:0] => DEBUG OUTPUT SIGNAL CONTROL
// 0 -> Normal output
// 1 -> A output
// 2 -> A (UPPER BIT) output
// 3 -> M output
// 4 -> PC output
// 5 -> IR output
// 6 -> CCR output
// 7 -> CU STATE output
//---------------------------------
//uio_in/uio_out
// bit[7] => WE (Write Enable)
// bit[6:0] => Address Buss
//---------------------------------
//---------------------------------
//Wires
//---------------------------------
wire [6:0] address_buss;
wire we_signal;
wire [7:0] tm_control_bits;
wire [7:0] data_buss_in;
wire [7:0] data_buss_out;
wire [7:0] data_buss_oe;
wire [7:0] data_buss_rom;
wire [7:0] data_buss_ram;
wire [7:0] data_buss_muxed_in;
wire drive_enable_sig;
wire nc_addr_buss_bit_7;
//---------------------------------
//Assignments
//---------------------------------
assign uo_out[6:0] = address_buss;
assign uo_out[7] = we_signal;
assign tm_control_bits = ui_in;
assign data_buss_in = uio_in;
assign uio_out = data_buss_out;
assign uio_oe = data_buss_oe;
//---------------------------------
//Minibyte CPU
//---------------------------------
minibyte_cpu cpu(
//Basic Inputs
.clk_in(clk), .ena_in(ena), .rst_in(rst_n),
.halt_in(tm_control_bits[3]),
//Memory and IO Inputs
.data_in(data_buss_muxed_in),
//DFT Inputs
.tm_control({tm_control_bits[2:0]}),
//Memory and IO Outputs
.addr_out ({nc_addr_buss_bit_7,address_buss}), //Only 7 bits get connected as we need to save one output for WE below:(
.data_out (data_buss_out),
.we_out (we_signal), //Dedicated output bit 7 gets used for WE
.drive_out (drive_enable_sig)
);
//---------------------------------
//Input Device MUX
//---------------------------------
reg [1:0] input_mux_control;
always @ (tm_control_bits, reg_ram_active) begin
//Enable Onboard RAM
if(tm_control_bits[7] == 1 && reg_ram_active)
input_mux_control = 2'b11;
//Enable Demo ROM
else if(tm_control_bits[4] == 1)
input_mux_control = 2'b01;
//Enable Normal Input
else
input_mux_control = 2'b00;
end
minibyte_genmux_4x input_mux(
//Mux Inputs
.a_in(data_buss_in),
.b_in(data_buss_rom),
.c_in(8'h00),
.d_in(data_buss_ram),
//Mux Select
.sel_in(input_mux_control),
//Mux Output
.mux_out(data_buss_muxed_in)
);
//---------------------------------
//Demo ROM
//---------------------------------
demo_rom_64B rom(
//Input Addr and Enable
.address(address_buss[5:0]), //Lower 6 addr buss bits
//Output Data
.data_out(data_buss_rom)
);
//---------------------------------
//Onboard REG RAM
//---------------------------------
reg reg_ram_active;
//Register ram is only active for addresses
//0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f
always @ (address_buss) begin
if(address_buss >= 7'h78)
reg_ram_active = 1;
else
reg_ram_active = 0;
end
reg_ram_8B ram(
//Input CLK and RST
.clk_in(clk),
.rst_in(rst_n),
//Input Addr
.address(address_buss[2:0]),
//Input Data
.data_in(data_buss_out),
//Input WE
.we_in(we_signal),
.en_in(reg_ram_active),
//Output Data
.data_out(data_buss_ram)
);
//---------------------------------
//Output enable control
//---------------------------------
drive_enable_fanout oe_driver(
//Drive enable input signal
.drive_en(drive_enable_sig),
//Output drive signals
.drive(data_buss_oe)
);
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//---------------------------------
//Top Level CPU Module
//---------------------------------
module minibyte_cpu (
//Basic Inputs
input wire clk_in, ena_in, rst_in,
input wire halt_in,
//Memory and IO Inputs
input wire [7:0] data_in,
//DFT Testmode Inputs
input wire [2:0] tm_control,
//Memory and IO Outputs
output wire [7:0] addr_out,
output wire [7:0] data_out,
output wire we_out,
output wire drive_out
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//---------------------------------
//Control Unit
//---------------------------------
module minibyte_cu(
//Basic Inputs
input wire clk_in, ena_in, rst_in,
input wire halt_in,
//IR Input
input wire [7:0] ir_op_buss_in,
//ALU Flags Input
input wire [1:0] ccr_flag_zn_in,
//Control signal outputs
output reg set_a_out,
output reg set_m_out,
output reg set_pc_out,
output reg set_ir_out,
output reg set_ccr_out,
output reg inc_pc_out,
//Addr select signals
output reg addr_mux_out,
//Alu control signals
output reg [3:0] alu_op_out,
//Write to memory
output reg we_out,
//Drive enable on data bus
output reg drive_out,
//DFT Output
output reg [7:0] dft_curr_state
);
//State machine memory
//--------------------------
reg [7:0] curr_state, next_state;
//CPU IR opcodes
//--------------------------
parameter IR_NOP = 8'h00;
parameter IR_LDA_IMM = 8'h01;
parameter IR_LDA_DIR = 8'h02;
parameter IR_STA_DIR = 8'h03;
parameter IR_STA_IND = 8'h04;
parameter IR_ADD_IMM = 8'h05;
parameter IR_ADD_DIR = 8'h06;
parameter IR_SUB_IMM = 8'h07;
parameter IR_SUB_DIR = 8'h08;
parameter IR_AND_IMM = 8'h09;
parameter IR_AND_DIR = 8'h0A;
parameter IR_OR_IMM = 8'h0B;
parameter IR_OR_DIR = 8'h0C;
parameter IR_XOR_IMM = 8'h0D;
parameter IR_XOR_DIR = 8'h0E;
parameter IR_LSL_IMM = 8'h0F;
parameter IR_LSL_DIR = 8'h10;
parameter IR_LSR_IMM = 8'h11;
parameter IR_LSR_DIR = 8'h12;
parameter IR_ASL_IMM = 8'h13;
parameter IR_ASL_DIR = 8'h14;
parameter IR_ASR_IMM = 8'h15;
parameter IR_ASR_DIR = 8'h16;
parameter IR_RSL_IMM = 8'h17;
parameter IR_RSL_DIR = 8'h18;
parameter IR_RSR_IMM = 8'h19;
parameter IR_RSR_DIR = 8'h1A;
parameter IR_JMP_DIR = 8'h1B;
parameter IR_JMP_IND = 8'h1C;
parameter IR_BNE_DIR = 8'h1D;
parameter IR_BNE_IND = 8'h1E;
parameter IR_BEQ_DIR = 8'h1F;
parameter IR_BEQ_IND = 8'h20;
parameter IR_BPL_DIR = 8'h21;
parameter IR_BPL_IND = 8'h22;
parameter IR_BMI_DIR = 8'h23;
parameter IR_BMI_IND = 8'h24;
//State machine opcodes
//--------------------------
parameter S_RESET_0 = 8'h00;
parameter S_PC_INC_0 = 8'h01;
parameter S_FETCH_0 = 8'h02;
parameter S_FETCH_1 = 8'h03;
parameter S_FETCH_2 = 8'h04;
parameter S_DECODE_0 = 8'h05;
parameter S_LDA_IMM_0 = 8'h06;
parameter S_LDA_IMM_1 = 8'h07;
parameter S_LDA_DIR_0 = 8'h08;
parameter S_LDA_DIR_1 = 8'h09;
parameter S_LDA_DIR_2 = 8'h0A;
parameter S_LDA_DIR_3 = 8'h0B;
parameter S_STA_DIR_0 = 8'h0C;
parameter S_STA_DIR_1 = 8'h0D;
parameter S_STA_DIR_2 = 8'h0E;
parameter S_STA_DIR_3 = 8'h0F;
parameter S_STA_IND_0 = 8'h10;
parameter S_STA_IND_1 = 8'h11;
parameter S_STA_IND_2 = 8'h12;
parameter S_STA_IND_3 = 8'h13;
parameter S_STA_IND_4 = 8'h14;
parameter S_STA_IND_5 = 8'h15;
parameter S_ADD_IMM_0 = 8'h16;
parameter S_ADD_IMM_1 = 8'h17;
parameter S_ADD_DIR_0 = 8'h18;
parameter S_ADD_DIR_1 = 8'h19;
parameter S_ADD_DIR_2 = 8'h1A;
parameter S_ADD_DIR_3 = 8'h1B;
parameter S_SUB_IMM_0 = 8'h1C;
parameter S_SUB_IMM_1 = 8'h1D;
parameter S_SUB_DIR_0 = 8'h1E;
parameter S_SUB_DIR_1 = 8'h1F;
parameter S_SUB_DIR_2 = 8'h20;
parameter S_SUB_DIR_3 = 8'h21;
parameter S_AND_IMM_0 = 8'h22;
parameter S_AND_IMM_1 = 8'h23;
parameter S_AND_DIR_0 = 8'h24;
parameter S_AND_DIR_1 = 8'h25;
parameter S_AND_DIR_2 = 8'h26;
parameter S_AND_DIR_3 = 8'h27;
parameter S_OR_IMM_0 = 8'h28;
parameter S_OR_IMM_1 = 8'h29;
parameter S_OR_DIR_0 = 8'h2A;
parameter S_OR_DIR_1 = 8'h2B;
parameter S_OR_DIR_2 = 8'h2C;
parameter S_OR_DIR_3 = 8'h2D;
parameter S_XOR_IMM_0 = 8'h2E;
parameter S_XOR_IMM_1 = 8'h2F;
parameter S_XOR_DIR_0 = 8'h30;
parameter S_XOR_DIR_1 = 8'h31;
parameter S_XOR_DIR_2 = 8'h32;
parameter S_XOR_DIR_3 = 8'h33;
parameter S_LSL_IMM_0 = 8'h34;
parameter S_LSL_IMM_1 = 8'h35;
parameter S_LSL_DIR_0 = 8'h36;
parameter S_LSL_DIR_1 = 8'h37;
parameter S_LSL_DIR_2 = 8'h38;
parameter S_LSL_DIR_3 = 8'h39;
parameter S_LSR_IMM_0 = 8'h3A;
parameter S_LSR_IMM_1 = 8'h3B;
parameter S_LSR_DIR_0 = 8'h3C;
parameter S_LSR_DIR_1 = 8'h3D;
parameter S_LSR_DIR_2 = 8'h3E;
parameter S_LSR_DIR_3 = 8'h3F;
parameter S_ASL_IMM_0 = 8'h40;
parameter S_ASL_IMM_1 = 8'h41;
parameter S_ASL_DIR_0 = 8'h42;
parameter S_ASL_DIR_1 = 8'h43;
parameter S_ASL_DIR_2 = 8'h44;
parameter S_ASL_DIR_3 = 8'h45;
parameter S_ASR_IMM_0 = 8'h46;
parameter S_ASR_IMM_1 = 8'h47;
parameter S_ASR_DIR_0 = 8'h48;
parameter S_ASR_DIR_1 = 8'h49;
parameter S_ASR_DIR_2 = 8'h4A;
parameter S_ASR_DIR_3 = 8'h4B;
parameter S_RSL_IMM_0 = 8'h4C;
parameter S_RSL_IMM_1 = 8'h4D;
parameter S_RSL_DIR_0 = 8'h4E;
parameter S_RSL_DIR_1 = 8'h4F;
parameter S_RSL_DIR_2 = 8'h50;
parameter S_RSL_DIR_3 = 8'h51;
parameter S_RSR_IMM_0 = 8'h52;
parameter S_RSR_IMM_1 = 8'h53;
parameter S_RSR_DIR_0 = 8'h54;
parameter S_RSR_DIR_1 = 8'h55;
parameter S_RSR_DIR_2 = 8'h56;
parameter S_RSR_DIR_3 = 8'h57;
parameter S_JMP_DIR_0 = 8'h58;
parameter S_JMP_DIR_1 = 8'h59;
parameter S_JMP_IND_0 = 8'h5A;
parameter S_JMP_IND_1 = 8'h5B;
parameter S_JMP_IND_2 = 8'h5C;
parameter S_JMP_IND_3 = 8'h5D;
//--------------------------
//ALU OPS
//--------------------------
parameter OP_ALU_PASSA = 4'b0000;
parameter OP_ALU_PASSB = 4'b0001;
parameter OP_ALU_ADD = 4'b0010;
parameter OP_ALU_SUB = 4'b0011;
parameter OP_ALU_AND = 4'b0100;
parameter OP_ALU_OR = 4'b0101;
parameter OP_ALU_XOR = 4'b0110;
parameter OP_ALU_LSL = 4'b0111;
parameter OP_ALU_LSR = 4'b1000;
parameter OP_ALU_ASL = 4'b1001;
parameter OP_ALU_ASR = 4'b1010;
parameter OP_ALU_RSL = 4'b1011;
parameter OP_ALU_RSR = 4'b1100;
//State memory block
//--------------------------
always @ (posedge clk_in or negedge rst_in) begin
//Reset to S_RESET_0 on reset
if(!rst_in)
curr_state <= S_RESET_0;
//Dont move states if enable is low
else if(!ena_in)
curr_state <= curr_state;
//Otherwise go to next state on every clk
else
curr_state <= next_state;
end
//Output logic
//--------------------------
always @ (curr_state) begin
case(curr_state)
//Reset sequence
//-----
//Do nothing until the next state
S_RESET_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU dont care
alu_op_out = 0;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//PC Increment
//-----
//Increment PC
S_PC_INC_0: begin
//Increment program counter
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 1;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU dont care
alu_op_out = 0;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Fetch sequence
//-----
//Send PC addr out
S_FETCH_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Load IR from memory
S_FETCH_1: begin
//Set IR Reg
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 1;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Inc PC now that IR is loaded
S_FETCH_2: begin
//Inc PC
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 1;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Decode sequence
//-----
//Do nothing until the next state
S_DECODE_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU dont care
alu_op_out = 0;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//LDA_IMM sequence
//-----
//Pass incoming data from memory to the main buss
S_LDA_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A
S_LDA_IMM_1: begin
//Latch A
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//LDA_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_LDA_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_LDA_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M
S_LDA_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A
S_LDA_DIR_3: begin
//Latch A
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//STA_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_STA_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_STA_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set address and WE, also prepare A data on the main buss
S_STA_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//A (A input) passthrough to main bus
alu_op_out = OP_ALU_PASSA;
//Set WE so that the receiving device is ready for us to drive data
we_out = 1;
drive_out = 0;
end
//Drive the data out
S_STA_DIR_3: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//A (A input) passthrough to main bus
alu_op_out = OP_ALU_PASSA;
//Drive out A data
we_out = 1;
drive_out = 1;
end
//STA_IND sequence
//-----
//Pass incoming data from memory to the main buss
S_STA_IND_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_STA_IND_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Fetch data located at this address
S_STA_IND_2: begin
//Latch M
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_STA_IND_3: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set address and WE, also prepare A data on the main buss
S_STA_IND_4: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//A (A input) passthrough to main bus
alu_op_out = OP_ALU_PASSA;
//Set WE so that the receiving device is ready for us to drive data
we_out = 1;
drive_out = 0;
end
//Drive the data out
S_STA_IND_5: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//A (A input) passthrough to main bus
alu_op_out = OP_ALU_PASSA;
//Drive out A data
we_out = 1;
drive_out = 1;
end
//ADD_IMM sequence
//-----
//Add the incoming data from the operand that the PC is pointing to
S_ADD_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Addition
alu_op_out = OP_ALU_ADD;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_ADD_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Addition
alu_op_out = OP_ALU_ADD;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//ADD_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_ADD_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_ADD_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to add incoming data
S_ADD_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Addition
alu_op_out = OP_ALU_ADD;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_ADD_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Addition
alu_op_out = OP_ALU_ADD;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//SUB_IMM sequence
//-----
//Subtract the incoming data from the operand that the PC is pointing to
S_SUB_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Subtraction
alu_op_out = OP_ALU_SUB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_SUB_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Subtraction
alu_op_out = OP_ALU_SUB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//SUB_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_SUB_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_SUB_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to subtract incoming data
S_SUB_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Subtraction
alu_op_out = OP_ALU_SUB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_SUB_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Subtraction
alu_op_out = OP_ALU_SUB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//AND_IMM sequence
//-----
//And the incoming data from the operand that the PC is pointing to
S_AND_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Logical AND
alu_op_out = OP_ALU_AND;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_AND_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Logical AND
alu_op_out = OP_ALU_AND;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//AND_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_AND_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_AND_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to AND incoming data
S_AND_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Logical AND
alu_op_out = OP_ALU_AND;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_AND_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Logical AND
alu_op_out = OP_ALU_AND;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//OR_IMM sequence
//-----
//And the incoming data from the operand that the PC is pointing to
S_OR_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Logical OR
alu_op_out = OP_ALU_OR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_OR_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Logical OR
alu_op_out = OP_ALU_OR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//OR_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_OR_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_OR_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to OR incoming data
S_OR_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Logical OR
alu_op_out = OP_ALU_OR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_OR_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Logical OR
alu_op_out = OP_ALU_OR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//XOR_IMM sequence
//-----
//And the incoming data from the operand that the PC is pointing to
S_XOR_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Logical XOR
alu_op_out = OP_ALU_XOR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_XOR_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Logical XOR
alu_op_out = OP_ALU_XOR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//XOR_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_XOR_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_XOR_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to XOR incoming data
S_XOR_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Logical XOR
alu_op_out = OP_ALU_XOR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_XOR_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Logical XOR
alu_op_out = OP_ALU_XOR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//LSL_IMM sequence
//-----
//Add the incoming data from the operand that the PC is pointing to
S_LSL_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Logical Shift Left
alu_op_out = OP_ALU_LSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_LSL_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Logical Shift Left
alu_op_out = OP_ALU_LSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//LSL_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_LSL_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_LSL_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to add incoming data
S_LSL_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Logical Shift Left
alu_op_out = OP_ALU_LSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_LSL_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Logical Shift Left
alu_op_out = OP_ALU_LSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//LSR_IMM sequence
//-----
//Add the incoming data from the operand that the PC is pointing to
S_LSR_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Logical Shift Right
alu_op_out = OP_ALU_LSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_LSR_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Logical Shift Right
alu_op_out = OP_ALU_LSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//LSR_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_LSR_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_LSR_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to add incoming data
S_LSR_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Logical Shift Right
alu_op_out = OP_ALU_LSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_LSR_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Logical Shift Right
alu_op_out = OP_ALU_LSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//ASL_IMM sequence
//-----
//Add the incoming data from the operand that the PC is pointing to
S_ASL_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Arithmetic Shift Left
alu_op_out = OP_ALU_ASL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_ASL_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Arithmetic Shift Left
alu_op_out = OP_ALU_ASL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//ASL_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_ASL_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_ASL_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to add incoming data
S_ASL_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Arithmetic Shift Left
alu_op_out = OP_ALU_ASL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_ASL_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Arithmetic Shift Left
alu_op_out = OP_ALU_ASL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//ASR_IMM sequence
//-----
//Add the incoming data from the operand that the PC is pointing to
S_ASR_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Arithmetic Shift Right
alu_op_out = OP_ALU_ASR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_ASR_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Arithmetic Shift Right
alu_op_out = OP_ALU_ASR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//ASR_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_ASR_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_ASR_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to add incoming data
S_ASR_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Arithmetic Shift Right
alu_op_out = OP_ALU_ASR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_ASR_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Arithmetic Shift Right
alu_op_out = OP_ALU_ASR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//RSL_IMM sequence
//-----
//Add the incoming data from the operand that the PC is pointing to
S_RSL_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Rotary Shift Left
alu_op_out = OP_ALU_RSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_RSL_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Rotary Shift Left
alu_op_out = OP_ALU_RSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//RSL_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_RSL_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_RSL_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to add incoming data
S_RSL_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Rotary Shift Left
alu_op_out = OP_ALU_RSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_RSL_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Rotary Shift Left
alu_op_out = OP_ALU_RSL;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//RSR_IMM sequence
//-----
//Add the incoming data from the operand that the PC is pointing to
S_RSR_IMM_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU->Rotary Shift Right
alu_op_out = OP_ALU_RSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_RSR_IMM_1: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//PC selected
addr_mux_out = 0;
//ALU->Rotary Shift Right
alu_op_out = OP_ALU_RSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//RSR_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_RSR_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_RSR_DIR_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M and prep to add incoming data
S_RSR_DIR_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//ALU->Rotary Shift Right
alu_op_out = OP_ALU_RSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to A/CCR
S_RSR_DIR_3: begin
//Latch A and CCR
set_a_out = 1;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 1;
//M selected
addr_mux_out = 1;
//ALU->Rotary Shift Right
alu_op_out = OP_ALU_RSR;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//JMP_DIR sequence
//-----
//Pass incoming data from memory to the main buss
S_JMP_DIR_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to PC
S_JMP_DIR_1: begin
//Latch PC
set_a_out = 0;
set_m_out = 0;
set_pc_out = 1;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//JMP_IND sequence
//-----
//Pass incoming data from memory to the main buss
S_JMP_IND_0: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to M
S_JMP_IND_1: begin
//Latch M
set_a_out = 0;
set_m_out = 1;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Set addr out to M
S_JMP_IND_2: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Latch data to PC
S_JMP_IND_3: begin
//Latch PC
set_a_out = 0;
set_m_out = 0;
set_pc_out = 1;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//M selected
addr_mux_out = 1;
//B (mem input) passthrough to main bus
alu_op_out = OP_ALU_PASSB;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
//Default (INVALID) sequence
//-----
default: begin
//Dont set or inc any registers
set_a_out = 0;
set_m_out = 0;
set_pc_out = 0;
inc_pc_out = 0;
set_ir_out = 0;
set_ccr_out = 0;
//PC selected
addr_mux_out = 0;
//ALU dont care
alu_op_out = 0;
//Dont write or drive
we_out = 0;
drive_out = 0;
end
endcase
end
//Next state logic
//--------------------------
always @ (curr_state, ir_op_buss_in, ccr_flag_zn_in, halt_in) begin
//DFT Output
dft_curr_state = curr_state;
//Next state logic
case(curr_state)
//Reset sequence (skips PC increment on boot)
S_RESET_0: next_state = S_FETCH_0;
//PC Increment
S_PC_INC_0: next_state = S_FETCH_0;
//Fetch sequence
S_FETCH_0: begin
if(halt_in == 1)
next_state = S_FETCH_0; //Remain in S_FETCH_0 forever if halt is asserted
else
next_state = S_FETCH_1; //Otherwise continue fetching this instruction
end
S_FETCH_1: next_state = S_FETCH_2;
S_FETCH_2: next_state = S_DECODE_0;
//Decode IR Opcode
S_DECODE_0: begin
case(ir_op_buss_in)
//IR_NOP (does nothing)
IR_NOP: next_state = S_FETCH_0;
//IR_LDA_IMM (load immediate value to A)
IR_LDA_IMM: next_state = S_LDA_IMM_0;
//IR_LDA_DIR (load direct value to A)
IR_LDA_DIR: next_state = S_LDA_DIR_0;
//IR_STA_DIR (store A at direct address)
IR_STA_DIR: next_state = S_STA_DIR_0;
//IR_STA_IND (store A at indirect address)
IR_STA_IND: next_state = S_STA_IND_0;
//IR_ADD_IMM (add immediate value to A)
IR_ADD_IMM: next_state = S_ADD_IMM_0;
//IR_ADD_DIR (add direct value to A)
IR_ADD_DIR: next_state = S_ADD_DIR_0;
//IR_SUB_IMM (subtract immediate value from A)
IR_SUB_IMM: next_state = S_SUB_IMM_0;
//IR_SUB_DIR (subtract direct value from A)
IR_SUB_DIR: next_state = S_SUB_DIR_0;
//IR_AND_IMM (logical AND immediate value with A)
IR_AND_IMM: next_state = S_AND_IMM_0;
//IR_AND_DIR (logical AND direct value with A)
IR_AND_DIR: next_state = S_AND_DIR_0;
//IR_OR_IMM (logical OR immediate value with A)
IR_OR_IMM: next_state = S_OR_IMM_0;
//IR_OR_DIR (logical OR direct value with A)
IR_OR_DIR: next_state = S_OR_DIR_0;
//IR_XOR_IMM (logical XOR immediate value with A)
IR_XOR_IMM: next_state = S_XOR_IMM_0;
//IR_XOR_DIR (logical XOR direct value with A)
IR_XOR_DIR: next_state = S_XOR_DIR_0;
//IR_LSL_IMM (logical left shift immediate value with A)
IR_LSL_IMM: next_state = S_LSL_IMM_0;
//IR_LSL_DIR (logical left shift direct value with A)
IR_LSL_DIR: next_state = S_LSL_DIR_0;
//IR_LSR_IMM (logical right shift immediate value with A)
IR_LSR_IMM: next_state = S_LSR_IMM_0;
//IR_LSR_DIR (logical right shift direct value with A)
IR_LSR_DIR: next_state = S_LSR_DIR_0;
//IR_ASL_IMM (arithmetic left shift immediate value with A)
IR_ASL_IMM: next_state = S_ASL_IMM_0;
//IR_ASL_DIR (arithmetic left shift direct value with A)
IR_ASL_DIR: next_state = S_ASL_DIR_0;
//IR_ASR_IMM (arithmetic right shift immediate value with A)
IR_ASR_IMM: next_state = S_ASR_IMM_0;
//IR_ASR_DIR (arithmetic right shift direct value with A)
IR_ASR_DIR: next_state = S_ASR_DIR_0;
//IR_RSL_IMM (rotary left shift immediate value with A)
IR_RSL_IMM: next_state = S_RSL_IMM_0;
//IR_RSL_DIR (rotary left shift direct value with A)
IR_RSL_DIR: next_state = S_RSL_DIR_0;
//IR_RSR_IMM (rotary right shift immediate value with A)
IR_RSR_IMM: next_state = S_RSR_IMM_0;
//IR_RSR_DIR (rotary right shift direct value with A)
IR_RSR_DIR: next_state = S_RSR_DIR_0;
//IR_JMP_DIR (load direct value to PC)
IR_JMP_DIR: next_state = S_JMP_DIR_0;
//IR_LDA_DIR (load indirect value to PC)
IR_JMP_IND: next_state = S_JMP_IND_0;
//IR_BNE_DIR (banch if z clear direct)
IR_BNE_DIR: begin
if(ccr_flag_zn_in[1] == 0)
next_state = S_JMP_DIR_0;
else
next_state = S_PC_INC_0;
end
//IR_BNE_IND (banch if z clear indirect)
IR_BNE_IND: begin
if(ccr_flag_zn_in[1] == 0)
next_state = S_JMP_IND_0;
else
next_state = S_PC_INC_0;
end
//IR_BEQ_DIR (banch if z set direct)
IR_BEQ_DIR: begin
if(ccr_flag_zn_in[1] == 1)
next_state = S_JMP_DIR_0;
else
next_state = S_PC_INC_0;
end
//IR_BEQ_IND (banch if z set indirect)
IR_BEQ_IND: begin
if(ccr_flag_zn_in[1] == 1)
next_state = S_JMP_IND_0;
else
next_state = S_PC_INC_0;
end
//IR_BPL_DIR (banch if n clear direct)
IR_BPL_DIR: begin
if(ccr_flag_zn_in[0] == 0)
next_state = S_JMP_DIR_0;
else
next_state = S_PC_INC_0;
end
//IR_BPL_IND (banch if n clear indirect)
IR_BPL_IND: begin
if(ccr_flag_zn_in[0] == 0)
next_state = S_JMP_IND_0;
else
next_state = S_PC_INC_0;
end
//IR_BMI_DIR (banch if n set direct)
IR_BMI_DIR: begin
if(ccr_flag_zn_in[0] == 1)
next_state = S_JMP_DIR_0;
else
next_state = S_PC_INC_0;
end
//IR_BMI_IND (banch if n set indirect)
IR_BMI_IND: begin
if(ccr_flag_zn_in[0] == 1)
next_state = S_JMP_IND_0;
else
next_state = S_PC_INC_0;
end
//Invalid IR, goto fetch_0
default: next_state = S_FETCH_0;
endcase
end
//LDA_IMM sequence
S_LDA_IMM_0: next_state = S_LDA_IMM_1;
S_LDA_IMM_1: next_state = S_PC_INC_0;
//LDA_DIR sequence
S_LDA_DIR_0: next_state = S_LDA_DIR_1;
S_LDA_DIR_1: next_state = S_LDA_DIR_2;
S_LDA_DIR_2: next_state = S_LDA_DIR_3;
S_LDA_DIR_3: next_state = S_PC_INC_0;
//STA_DIR sequence
S_STA_DIR_0: next_state = S_STA_DIR_1;
S_STA_DIR_1: next_state = S_STA_DIR_2;
S_STA_DIR_2: next_state = S_STA_DIR_3;
S_STA_DIR_3: next_state = S_PC_INC_0;
//STA_IND sequence
S_STA_IND_0: next_state = S_STA_IND_1;
S_STA_IND_1: next_state = S_STA_IND_2;
S_STA_IND_2: next_state = S_STA_IND_3;
S_STA_IND_3: next_state = S_STA_IND_4;
S_STA_IND_4: next_state = S_STA_IND_5;
S_STA_IND_5: next_state = S_PC_INC_0;
//ADD_IMM sequence
S_ADD_IMM_0: next_state = S_ADD_IMM_1;
S_ADD_IMM_1: next_state = S_PC_INC_0;
//ADD_DIR sequence
S_ADD_DIR_0: next_state = S_ADD_DIR_1;
S_ADD_DIR_1: next_state = S_ADD_DIR_2;
S_ADD_DIR_2: next_state = S_ADD_DIR_3;
S_ADD_DIR_3: next_state = S_PC_INC_0;
//SUB_IMM sequence
S_SUB_IMM_0: next_state = S_SUB_IMM_1;
S_SUB_IMM_1: next_state = S_PC_INC_0;
//SUB_DIR sequence
S_SUB_DIR_0: next_state = S_SUB_DIR_1;
S_SUB_DIR_1: next_state = S_SUB_DIR_2;
S_SUB_DIR_2: next_state = S_SUB_DIR_3;
S_SUB_DIR_3: next_state = S_PC_INC_0;
//AND_IMM sequence
S_AND_IMM_0: next_state = S_AND_IMM_1;
S_AND_IMM_1: next_state = S_PC_INC_0;
//AND_DIR sequence
S_AND_DIR_0: next_state = S_AND_DIR_1;
S_AND_DIR_1: next_state = S_AND_DIR_2;
S_AND_DIR_2: next_state = S_AND_DIR_3;
S_AND_DIR_3: next_state = S_PC_INC_0;
//OR_IMM sequence
S_OR_IMM_0: next_state = S_OR_IMM_1;
S_OR_IMM_1: next_state = S_PC_INC_0;
//OR_DIR sequence
S_OR_DIR_0: next_state = S_OR_DIR_1;
S_OR_DIR_1: next_state = S_OR_DIR_2;
S_OR_DIR_2: next_state = S_OR_DIR_3;
S_OR_DIR_3: next_state = S_PC_INC_0;
//XOR_IMM sequence
S_XOR_IMM_0: next_state = S_XOR_IMM_1;
S_XOR_IMM_1: next_state = S_PC_INC_0;
//XOR_DIR sequence
S_XOR_DIR_0: next_state = S_XOR_DIR_1;
S_XOR_DIR_1: next_state = S_XOR_DIR_2;
S_XOR_DIR_2: next_state = S_XOR_DIR_3;
S_XOR_DIR_3: next_state = S_PC_INC_0;
//LSL_IMM sequence
S_LSL_IMM_0: next_state = S_LSL_IMM_1;
S_LSL_IMM_1: next_state = S_PC_INC_0;
//LSL_DIR sequence
S_LSL_DIR_0: next_state = S_LSL_DIR_1;
S_LSL_DIR_1: next_state = S_LSL_DIR_2;
S_LSL_DIR_2: next_state = S_LSL_DIR_3;
S_LSL_DIR_3: next_state = S_PC_INC_0;
//LSR_IMM sequence
S_LSR_IMM_0: next_state = S_LSR_IMM_1;
S_LSR_IMM_1: next_state = S_PC_INC_0;
//LSR_DIR sequence
S_LSR_DIR_0: next_state = S_LSR_DIR_1;
S_LSR_DIR_1: next_state = S_LSR_DIR_2;
S_LSR_DIR_2: next_state = S_LSR_DIR_3;
S_LSR_DIR_3: next_state = S_PC_INC_0;
//ASL_IMM sequence
S_ASL_IMM_0: next_state = S_ASL_IMM_1;
S_ASL_IMM_1: next_state = S_PC_INC_0;
//ASL_DIR sequence
S_ASL_DIR_0: next_state = S_ASL_DIR_1;
S_ASL_DIR_1: next_state = S_ASL_DIR_2;
S_ASL_DIR_2: next_state = S_ASL_DIR_3;
S_ASL_DIR_3: next_state = S_PC_INC_0;
//ASR_IMM sequence
S_ASR_IMM_0: next_state = S_ASR_IMM_1;
S_ASR_IMM_1: next_state = S_PC_INC_0;
//ASR_DIR sequence
S_ASR_DIR_0: next_state = S_ASR_DIR_1;
S_ASR_DIR_1: next_state = S_ASR_DIR_2;
S_ASR_DIR_2: next_state = S_ASR_DIR_3;
S_ASR_DIR_3: next_state = S_PC_INC_0;
//RSL_IMM sequence
S_RSL_IMM_0: next_state = S_RSL_IMM_1;
S_RSL_IMM_1: next_state = S_PC_INC_0;
//RSL_DIR sequence
S_RSL_DIR_0: next_state = S_RSL_DIR_1;
S_RSL_DIR_1: next_state = S_RSL_DIR_2;
S_RSL_DIR_2: next_state = S_RSL_DIR_3;
S_RSL_DIR_3: next_state = S_PC_INC_0;
//RSR_IMM sequence
S_RSR_IMM_0: next_state = S_RSR_IMM_1;
S_RSR_IMM_1: next_state = S_PC_INC_0;
//RSR_DIR sequence
S_RSR_DIR_0: next_state = S_RSR_DIR_1;
S_RSR_DIR_1: next_state = S_RSR_DIR_2;
S_RSR_DIR_2: next_state = S_RSR_DIR_3;
S_RSR_DIR_3: next_state = S_PC_INC_0;
//JMP_DIR sequence
S_JMP_DIR_0: next_state = S_JMP_DIR_1;
S_JMP_DIR_1: next_state = S_FETCH_0;
//JMP_IND sequence
S_JMP_IND_0: next_state = S_JMP_IND_1;
S_JMP_IND_1: next_state = S_JMP_IND_2;
S_JMP_IND_2: next_state = S_JMP_IND_3;
S_JMP_IND_3: next_state = S_FETCH_0;
//Should never get here
default:
next_state = S_PC_INC_0;
endcase
end
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//---------------------------------------------------------------------------------------------------------
// MINIBYTE ALU
//---------------------------------------------------------------------------------------------------------
// OPERATION | ALU_OP | MEANING
//---------------------------------------------------------------------------------------------------------
// PASSA | 0b0000 | Passthrough input A
// PASSB | 0b0001 | Passthrough input B
// ADD | 0b0010 | Add A and B
// SUB | 0b0011 | Subtract B from A
// AND | 0b0100 | Logical and of A, B
// OR | 0b0101 | Logical or of A, B
// XOR | 0b0110 | Logical xor of A, B
// LSL | 0b0111 | Logical shift A left by B
// LSR | 0b1000 | Logical shift A right by B
// ASL | 0b1001 | Arithmetic shift A left by B
// ASR | 0b1010 | Arithmetic shift A right by B
// RSL | 0b1011 | Rotary shift A left by B
// RSR | 0b1100 | Rotary shift A right by B
//---------------------------------------------------------------------------------------------------------
//--------------------------
//Params
//--------------------------
parameter ALU_PASSA = 4'b0000;
parameter ALU_PASSB = 4'b0001;
parameter ALU_ADD = 4'b0010;
parameter ALU_SUB = 4'b0011;
parameter ALU_AND = 4'b0100;
parameter ALU_OR = 4'b0101;
parameter ALU_XOR = 4'b0110;
parameter ALU_LSL = 4'b0111;
parameter ALU_LSR = 4'b1000;
parameter ALU_ASL = 4'b1001;
parameter ALU_ASR = 4'b1010;
parameter ALU_RSL = 4'b1011;
parameter ALU_RSR = 4'b1100;
//--------------------------
//ALU Module
//--------------------------
module minibyte_alu (
//ALU Inputs
input wire signed [7:0] a_in,
input wire signed [7:0] b_in,
input wire [3:0] alu_op_in,
//ALU Outputs
output reg signed [7:0] res_out,
output reg [1:0] flags_zn_out
);
//Main Procedural Block
//--------------------------
always @(*) begin
//Assign ALU result
//---------------------
case(alu_op_in)
//A Passthrough
//--------------
ALU_PASSA:
res_out = a_in;
//B Passthrough
//--------------
ALU_PASSB:
res_out = b_in;
//Addition
//--------------
ALU_ADD:
res_out = a_in + b_in;
//Subtraction
//--------------
ALU_SUB:
res_out = a_in - b_in;
//Logical AND
//--------------
ALU_AND:
res_out = a_in & b_in;
//Logical OR
//--------------
ALU_OR:
res_out = a_in | b_in;
//Logical XOR
//--------------
ALU_XOR:
res_out = a_in ^ b_in;
//Logical Shift Left
//--------------
ALU_LSL:
res_out = a_in << b_in;
//Logical Shift Right
//--------------
ALU_LSR:
res_out = a_in >> b_in;
//Arithmetic Shift Left
//--------------
ALU_ASL:
res_out = a_in <<< b_in;
//Arithmetic Shift Right
//--------------
ALU_ASR:
res_out = a_in >>> b_in;
//Rotary Shift Left
//--------------
ALU_RSL:
case(b_in[2:0])
//Hardcoded concatenations of all possible inputs
3'b000:
res_out = a_in;
3'b001:
res_out = {a_in[6:0], a_in[7]};
3'b010:
res_out = {a_in[5:0], a_in[7:6]};
3'b011:
res_out = {a_in[4:0], a_in[7:5]};
3'b100:
res_out = {a_in[3:0], a_in[7:4]};
3'b101:
res_out = {a_in[2:0], a_in[7:3]};
3'b110:
res_out = {a_in[1:0], a_in[7:2]};
3'b111:
res_out = {a_in[0], a_in[7:1]};
endcase
//Rotary Shift Right
//--------------
ALU_RSR:
case(b_in[2:0])
//Hardcoded concatenations of all possible inputs
3'b000:
res_out = a_in;
3'b001:
res_out = {a_in[0], a_in[7:1]};
3'b010:
res_out = {a_in[1:0], a_in[7:2]};
3'b011:
res_out = {a_in[2:0], a_in[7:3]};
3'b100:
res_out = {a_in[3:0], a_in[7:4]};
3'b101:
res_out = {a_in[4:0], a_in[7:5]};
3'b110:
res_out = {a_in[5:0], a_in[7:6]};
3'b111:
res_out = {a_in[6:0], a_in[7]};
endcase
//Default (SHOULD NEVER GET HERE)
//--------------
default:
res_out = 0;
endcase
//Assign Zero flag
//---------------------
if(res_out == 0)
flags_zn_out[1] = 1;
else
flags_zn_out[1] = 0;
//Assign Negative flag
//---------------------
flags_zn_out[0] = res_out[7];
end
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//--------------------------
//General Register Module
//--------------------------
module minibyte_genreg (
//Basic Inputs
input wire clk_in, rst_in,
//Register Inputs
input wire [7:0] reg_in,
input wire set_in,
//Register Outputs
output reg [7:0] reg_out
);
//Main Procedural Block
//--------------------------
always @(posedge clk_in or negedge rst_in) begin
//Reset if rst goes low
if(!rst_in)
reg_out <= 0;
else
//Set register to input if set signal goes high on a clk
if(set_in)
reg_out <= reg_in;
end
endmodule
//--------------------------
//CCR Register Module
//--------------------------
module minibyte_ccrreg (
//Basic Inputs
input wire clk_in, rst_in,
//Register Inputs
input wire [1:0] reg_in,
input wire set_in,
//Register Outputs
output reg [1:0] reg_out
);
//Main Procedural Block
//--------------------------
always @(posedge clk_in or negedge rst_in) begin
//Reset if rst goes low
if(!rst_in)
reg_out <= 0;
else
//Set register to input if set signal goes high on a clk
if(set_in)
reg_out <= reg_in;
end
endmodule
//---------------------------------
//Program Counter Register Module
//---------------------------------
module minibyte_pcreg (
//Basic Inputs
input wire clk_in, rst_in,
//Register Inputs
input wire [7:0] reg_in,
input wire set_in,
input wire inc_in,
//Register Outputs
output reg [7:0] reg_out
);
//Main Procedural Block
//--------------------------
always @(posedge clk_in or negedge rst_in) begin
//Reset if rst goes low
if(!rst_in)
reg_out <= 0;
else
//Set register to input if set signal goes high
if(set_in)
reg_out <= reg_in;
//Increment register if inc signal goes high on a clk
else if(inc_in)
reg_out <= reg_out + 1;
end
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//---------------------------------
//Generic 2->1 Mux Module
//---------------------------------
module minibyte_genmux_2x(
//Mux Inputs
input wire [7:0] a_in,
input wire [7:0] b_in,
//Mux Select
input wire sel_in,
//Mux Output
output reg [7:0] mux_out
);
//Main Procedural Block
//--------------------------
always @(*) begin
//A out if sel is 0
if(sel_in == 0)
mux_out = a_in;
//B out if sel is 1
else
mux_out = b_in;
end
endmodule
//---------------------------------
//Generic 4->1 Mux Module
//---------------------------------
module minibyte_genmux_4x(
//Mux Inputs
input wire [7:0] a_in,
input wire [7:0] b_in,
input wire [7:0] c_in,
input wire [7:0] d_in,
//Mux Select
input wire [1:0] sel_in,
//Mux Output
output reg [7:0] mux_out
);
//Main Procedural Block
//--------------------------
always @(*) begin
//A out if sel is 00
if(sel_in == 2'b00)
mux_out = a_in;
//B out if sel is 01
else if(sel_in == 2'b01)
mux_out = b_in;
//C out if sel is 10
else if(sel_in == 2'b10)
mux_out = c_in;
//D out if sel is 11
else
mux_out = d_in;
end
endmodule
//---------------------------------
//Generic 8->1 Mux Module
//---------------------------------
module minibyte_genmux_8x(
//Mux Inputs
input wire [7:0] a_in,
input wire [7:0] b_in,
input wire [7:0] c_in,
input wire [7:0] d_in,
input wire [7:0] e_in,
input wire [7:0] f_in,
input wire [7:0] g_in,
input wire [7:0] h_in,
//Mux Select
input wire [2:0] sel_in,
//Mux Output
output reg [7:0] mux_out
);
//Main Procedural Block
//--------------------------
always @(*) begin
//A out if sel is 000
if(sel_in == 3'b000)
mux_out = a_in;
//B out if sel is 001
else if(sel_in == 3'b001)
mux_out = b_in;
//C out if sel is 010
else if(sel_in == 3'b010)
mux_out = c_in;
//D out if sel is 011
else if(sel_in == 3'b011)
mux_out = d_in;
//E out if sel is 100
else if(sel_in == 3'b100)
mux_out = e_in;
//F out if sel is 101
else if(sel_in == 3'b101)
mux_out = f_in;
//G out if sel is 110
else if(sel_in == 3'b110)
mux_out = g_in;
//H out if sel is 111
else
mux_out = h_in;
end
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//---------------------------------
//Drive enable device
//---------------------------------
module drive_enable_fanout(
//Drive enable input signal
input wire drive_en,
//Output drive signals
output reg [7:0] drive
);
//Main Procedural Block
//--------------------------
always @(*) begin
if(drive_en == 0)
drive = 0;
else
drive = 8'hff;
end
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//CPU IR opcodes
//--------------------------
parameter _NOP = 8'h00;
parameter _LDA_IMM = 8'h01;
parameter _LDA_DIR = 8'h02;
parameter _STA_DIR = 8'h03;
//parameter _STA_IND = 8'h04;
parameter _ADD_IMM = 8'h05;
//parameter _ADD_DIR = 8'h06;
//parameter _SUB_IMM = 8'h07;
//parameter _SUB_DIR = 8'h08;
//parameter _AND_IMM = 8'h09;
//parameter _AND_DIR = 8'h0A;
//parameter _OR_IMM = 8'h0B;
//parameter _OR_DIR = 8'h0C;
//parameter _XOR_IMM = 8'h0D;
//parameter _XOR_DIR = 8'h0E;
parameter _LSL_IMM = 8'h0F;
//parameter _LSL_DIR = 8'h10;
//parameter _LSR_IMM = 8'h11;
//parameter _LSR_DIR = 8'h12;
//parameter _ASL_IMM = 8'h13;
//parameter _ASL_DIR = 8'h14;
//parameter _ASR_IMM = 8'h15;
//parameter _ASR_DIR = 8'h16;
//parameter _RSL_IMM = 8'h17;
//parameter _RSL_DIR = 8'h18;
//parameter _RSR_IMM = 8'h19;
//parameter _RSR_DIR = 8'h1A;
parameter _JMP_DIR = 8'h1B;
//parameter _JMP_IND = 8'h1C;
parameter _BNE_DIR = 8'h1D;
//parameter _BNE_IND = 8'h1E;
//parameter _BEQ_DIR = 8'h1F;
//parameter _BEQ_IND = 8'h20;
parameter _BPL_DIR = 8'h21;
//parameter _BPL_IND = 8'h22;
//parameter _BMI_DIR = 8'h23;
//parameter _BMI_IND = 8'h24;
//--------------------------
//Demo ROM Program
//--------------------------
module demo_rom_64B(
//Input Addr
input wire [5:0] address,
//Output Data
output reg [7:0] data_out
);
always @(address)
case(address)
6'h00: data_out = _NOP; //First istr is a NOP
6'h01: data_out = _LDA_IMM; //Make sure A is zero
6'h02: data_out = 0;
6'h03: data_out = _NOP; //NOP is the START of the LOOP0
6'h04: data_out = _ADD_IMM; //ADD 1 to A
6'h05: data_out = 1;
6'h06: data_out = _STA_DIR; //Write this value to 0x40
6'h07: data_out = 8'h40;
6'h08: data_out = _BNE_DIR; //Keep branching to LOOP0 until we roll over to 0
6'h09: data_out = 8'h03;
6'h0A: data_out = _LDA_IMM; //Load a 1 into A
6'h0B: data_out = 1;
6'h0C: data_out = _STA_DIR; //Write this value to 0x40
6'h0D: data_out = 8'h40;
6'h0E: data_out = _NOP; //NOP is the START of the LOOP1
6'h0F: data_out = _LSL_IMM; //Shift A left by 1
6'h10: data_out = 1;
6'h11: data_out = _STA_DIR; //Write this value to 0x40
6'h12: data_out = 8'h40;
6'h13: data_out = _BPL_DIR; //Keep branching to LOOP1 until we hit 0b10000000
6'h14: data_out = 8'h0E;
6'h15: data_out = _LDA_IMM; //Load DEADBEEF into RAM
6'h16: data_out = 8'hDE;
6'h17: data_out = _STA_DIR;
6'h18: data_out = 8'h78;
6'h19: data_out = _LDA_IMM;
6'h1A: data_out = 8'hAD;
6'h1B: data_out = _STA_DIR;
6'h1C: data_out = 8'h79;
6'h1D: data_out = _LDA_IMM;
6'h1E: data_out = 8'hBE;
6'h1F: data_out = _STA_DIR;
6'h20: data_out = 8'h7A;
6'h21: data_out = _LDA_IMM;
6'h22: data_out = 8'hEF;
6'h23: data_out = _STA_DIR;
6'h24: data_out = 8'h7B;
6'h25: data_out = _LDA_DIR; //READ out the contents of RAM
6'h26: data_out = 8'h78;
6'h27: data_out = _STA_DIR; //Write this value to 0x40
6'h28: data_out = 8'h40;
6'h29: data_out = _LDA_DIR; //READ out the contents of RAM
6'h2A: data_out = 8'h79;
6'h2B: data_out = _STA_DIR; //Write this value to 0x40
6'h2C: data_out = 8'h40;
6'h2D: data_out = _LDA_DIR; //READ out the contents of RAM
6'h2E: data_out = 8'h7A;
6'h2F: data_out = _STA_DIR; //Write this value to 0x40
6'h30: data_out = 8'h40;
6'h31: data_out = _LDA_DIR; //READ out the contents of RAM
6'h32: data_out = 8'h7B;
6'h33: data_out = _STA_DIR; //Write this value to 0x40
6'h34: data_out = 8'h40;
6'h35: data_out = _JMP_DIR; //Start the whole thing over!
6'h36: data_out = 8'h00;
default: data_out = 0; //Unused space
endcase
endmodule
/*
* Copyright (c) 2024 Zachary Frazee
* SPDX-License-Identifier: Apache-2.0
*/
//--------------------------
//REGISTER RAM
//--------------------------
module reg_ram_8B(
//Input CLK and RST
input wire clk_in,
input wire rst_in,
//Input Addr
input wire [2:0] address,
//Input Data
input wire [7:0] data_in,
//Input WE and EN
input wire we_in,
input wire en_in,
//Output Data
output reg [7:0] data_out
);
//Data busses
//------------------------------------
reg [7:0] r_we;
reg [7:0] r0_out_data;
reg [7:0] r1_out_data;
reg [7:0] r2_out_data;
reg [7:0] r3_out_data;
reg [7:0] r4_out_data;
reg [7:0] r5_out_data;
reg [7:0] r6_out_data;
reg [7:0] r7_out_data;
//Data registers
//------------------------------------
minibyte_genreg r0(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[0]),
//Register Outputs
.reg_out(r0_out_data)
);
minibyte_genreg r1(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[1]),
//Register Outputs
.reg_out(r1_out_data)
);
minibyte_genreg r2(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[2]),
//Register Outputs
.reg_out(r2_out_data)
);
minibyte_genreg r3(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[3]),
//Register Outputs
.reg_out(r3_out_data)
);
minibyte_genreg r4(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[4]),
//Register Outputs
.reg_out(r4_out_data)
);
minibyte_genreg r5(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[5]),
//Register Outputs
.reg_out(r5_out_data)
);
minibyte_genreg r6(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[6]),
//Register Outputs
.reg_out(r6_out_data)
);
minibyte_genreg r7(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(data_in),
.set_in(r_we[7]),
//Register Outputs
.reg_out(r7_out_data)
);
//Register control logic
//------------------------------------
always @ (*) begin
if (!en_in) begin
data_out = 8'h00;
r_we = 8'h00;
end
else if (we_in) begin
case(address)
3'b000:
r_we = 8'b00000001;
3'b001:
r_we = 8'b00000010;
3'b010:
r_we = 8'b00000100;
3'b011:
r_we = 8'b00001000;
3'b100:
r_we = 8'b00010000;
3'b101:
r_we = 8'b00100000;
3'b110:
r_we = 8'b01000000;
3'b111:
r_we = 8'b10000000;
default:
r_we = 8'b00000000;
endcase
data_out = 8'h00;
end
else begin
case(address)
3'b000:
data_out = r0_out_data;
3'b001:
data_out = r1_out_data;
3'b010:
data_out = r2_out_data;
3'b011:
data_out = r3_out_data;
3'b100:
data_out = r4_out_data;
3'b101:
data_out = r5_out_data;
3'b110:
data_out = r6_out_data;
3'b111:
data_out = r7_out_data;
endcase
r_we = 8'h00;
end
end
endmodule
|
module minibyte_cpu (
//Basic Inputs
input wire clk_in, ena_in, rst_in,
input wire halt_in,
//Memory and IO Inputs
input wire [7:0] data_in,
//DFT Testmode Inputs
input wire [2:0] tm_control,
//Memory and IO Outputs
output wire [7:0] addr_out,
output wire [7:0] data_out,
output wire we_out,
output wire drive_out
);
//Main Data Buss
//--------------------------------
wire [7:0] main_buss;
//Data out comes from the main buss
assign data_out = main_buss;
//ALU A-Side Input Data Buss
//--------------------------------
wire [7:0] alu_a_buss;
//Address Busses
//--------------------------------
wire [7:0] m_addr_buss;
wire [7:0] pc_addr_buss;
wire [7:0] ir_op_buss;
wire [7:0] normal_addr_out;
//DFT Wires
//--------------------------------
wire [7:0] dft_cu_state;
//Control Signals
//--------------------------------
//Set register signals
wire ctrl_set_a;
wire ctrl_set_m;
wire ctrl_set_pc;
wire ctrl_set_ir;
wire ctrl_set_ccr;
//Inc register signals
wire ctrl_inc_pc;
//Addr mux signals
wire ctrl_addr_mux;
//Alu control signals
wire [3:0] ctrl_alu_op;
//Data direction control
wire ctrl_we_out;
wire ctrl_drive_out;
assign we_out=ctrl_we_out;
assign drive_out=ctrl_drive_out;
//Branch Signals
//--------------------------------
wire [1:0] flags_zn_buss;
wire [1:0] ccr_zn_buss;
//A Register
//--------------------------------
minibyte_genreg reg_a(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(main_buss),
.set_in(ctrl_set_a),
//Register Outputs
.reg_out(alu_a_buss)
);
//M Register
//--------------------------------
minibyte_genreg reg_m(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(main_buss),
.set_in(ctrl_set_m),
//Register Outputs
.reg_out(m_addr_buss)
);
//PC Register
//--------------------------------
minibyte_pcreg reg_pc(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(main_buss),
.set_in(ctrl_set_pc),
.inc_in(ctrl_inc_pc),
//Register Outputs
.reg_out(pc_addr_buss)
);
//IR Register
//--------------------------------
minibyte_genreg reg_ir(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(main_buss),
.set_in(ctrl_set_ir),
//Register Outputs
.reg_out(ir_op_buss)
);
//CCR Register
//--------------------------------
minibyte_ccrreg reg_ccr(
//Basic Inputs
.clk_in(clk_in), .rst_in(rst_in),
//Register Inputs
.reg_in(flags_zn_buss),
.set_in(ctrl_set_ccr),
//Register Outputs
.reg_out(ccr_zn_buss)
);
//Addr Out Mux
//--------------------------------
minibyte_genmux_2x addr_mux(
//Mux Inputs
.a_in(pc_addr_buss),
.b_in(m_addr_buss),
//Mux Select
.sel_in(ctrl_addr_mux),
//Mux Output
.mux_out(normal_addr_out)
);
//Debug Out Mux
//--------------------------------
minibyte_genmux_8x tm_debug_out_mux(
//Mux Inputs
.a_in(normal_addr_out), //0 -> Normal output
.b_in(alu_a_buss), //1 -> A output
.c_in({7'h0, alu_a_buss[7]}), //2 -> A (UPPER BIT) output
.d_in(m_addr_buss), //3 -> M output
.e_in(pc_addr_buss), //4 -> PC output
.f_in(ir_op_buss), //5 -> IR output
.g_in({6'h0,ccr_zn_buss}), //6 -> CCR output
.h_in(dft_cu_state), //7 -> CU STATE output
//Mux Select
.sel_in(tm_control[2:0]),
//Mux Output
.mux_out(addr_out)
);
//ALU
//--------------------------------
minibyte_alu alu(
//ALU Inputs
.a_in(alu_a_buss),
.b_in(data_in),
.alu_op_in(ctrl_alu_op),
.res_out(main_buss),
.flags_zn_out(flags_zn_buss)
);
//Control Unit
//--------------------------------
minibyte_cu cu(
//Basic Inputs
.clk_in(clk_in), .ena_in(ena_in), .rst_in(rst_in),
.halt_in(halt_in),
//IR Input
.ir_op_buss_in(ir_op_buss),
//ALU Flags Input
.ccr_flag_zn_in(ccr_zn_buss),
//Control signal outputs
.set_a_out(ctrl_set_a),
.set_m_out(ctrl_set_m),
.set_pc_out(ctrl_set_pc),
.set_ir_out(ctrl_set_ir),
.set_ccr_out(ctrl_set_ccr),
.inc_pc_out(ctrl_inc_pc),
//Addr select signals
.addr_mux_out(ctrl_addr_mux),
//Alu control signals
.alu_op_out(ctrl_alu_op),
//Write to memory
.we_out(ctrl_we_out),
//Drive enable on data bus
.drive_out(ctrl_drive_out),
//DFT Output
.dft_curr_state(dft_cu_state)
);
endmodule
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